WO2018014371A1 - 柔性阵列基板及其制备方法、柔性显示装置 - Google Patents

柔性阵列基板及其制备方法、柔性显示装置 Download PDF

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WO2018014371A1
WO2018014371A1 PCT/CN2016/093004 CN2016093004W WO2018014371A1 WO 2018014371 A1 WO2018014371 A1 WO 2018014371A1 CN 2016093004 W CN2016093004 W CN 2016093004W WO 2018014371 A1 WO2018014371 A1 WO 2018014371A1
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layer
interlayer dielectric
flexible
array substrate
active layer
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French (fr)
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秦芳
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/14—Carrier transporting layers
    • H10K50/15—Hole transporting layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H10K50/14—Carrier transporting layers
    • H10K50/16—Electron transporting layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a flexible array substrate and a method for fabricating the same, and to a flexible display device including the above flexible array substrate.
  • a flexible display device includes a laminated flexible array substrate and an electroluminescent device, and the electroluminescent device is encapsulated with a transparent flexible cover.
  • a flexible array substrate as shown in FIG. 1 includes a flexible substrate 1, a buffer layer 2 formed on the flexible substrate 1, and a plurality of thin film transistors 3 arrayed on the buffer layer 2 (only in FIG. 1 One of the thin film transistors 3) is shown.
  • the thin film transistor 3 includes an active layer 4, a gate electrode 5, a source electrode 6 and a drain electrode 7, a gate insulating layer 8 is disposed between the active layer 4 and the gate electrode 5, and an interlayer dielectric is disposed on the gate electrode 5.
  • An Inter Layer Dielectric (ILD) 9, and an interlayer dielectric layer 9 covers the buffer layer 2 to interconnect the layer structures.
  • the interlayer dielectric layer 9 is also used to isolate the source electrode 6 and the drain electrode 7 from the gate electrode 5, and the source electrode 6 and the drain electrode 7 are electrically connected to the active layer 4 through via holes in the interlayer dielectric layer 9, respectively.
  • the flexible array substrate configured as described above, the buffer layer 2, the material of the gate insulating layer 8 and the interlayer dielectric layer 9 is usually used inorganic oxides such as SiO x, SiN x and the like.
  • the bending of the flexible array substrate has less damage to the organic and metallic materials therein, but the damage to the less flexible inorganic oxide is relatively serious, especially when bending into a small radius of curvature, which is easy to cause Failure of cracking and peeling of the flexible array substrate of the inorganic oxide.
  • the gate insulating layer 8 can be patterned to reduce the coverage area to reduce the stress and reduce the problem of cracking and peeling dislocation, but the interlayer dielectric layer 9 and the buffer layer 2 are combined with each other. The area is large, and the bonding performance of the two is poor.
  • the interlayer dielectric layer 9 is easily detached from the buffer layer 2 or cracked, which affects the quality of the flexible array substrate.
  • the present invention provides a flexible array substrate and a method for fabricating the same, to enhance the bonding performance of the interconnect structure layer in the flexible array substrate, improve the problem of the falling or cracking of the interconnect structure layer, and improve the quality of the flexible array substrate.
  • a flexible array substrate comprising a flexible substrate and a buffer layer on the flexible substrate, the buffer layer is arranged on the array with a plurality of thin film transistors, and the thin film transistor is provided with an interlayer dielectric layer, the interlayer dielectric layer covering the substrate a buffer layer; wherein an interconnect structure is disposed between the interlayer dielectric layer and the buffer layer, and at least one interconnect structure member is disposed on each side of each of the thin film transistors, and the interconnect structure member Extending in a direction parallel to the bending axis of the flexible array substrate.
  • a portion of the interconnecting structural member embedded in the buffer layer has a square cross section, and a portion of the portion embedded in the interlayer dielectric layer has a semicircular cross section or a trapezoid having a circular chamfer.
  • the interconnecting structural member comprises a plurality of first structural portions and a plurality of second structural portions arranged alternately spaced along a length thereof;
  • the first structural portion is a strip-like structure having a length greater than a width
  • the second structural portion is a dot structure having a length equal to or nearly equal to the width.
  • the material of the interconnecting structural member is an organic photoresist material.
  • the thin film transistor includes an active layer, a gate electrode, a source electrode, and a drain electrode; the active layer is formed on the buffer layer, the gate electrode is formed on the active layer, and the active layer a gate insulating layer is disposed between the gate electrode and the gate electrode; the interlayer dielectric layer is disposed on the gate electrode, and the source electrode and the drain electrode are respectively disposed on the interlayer dielectric layer, the source electrode The drain electrode and the drain electrode are electrically connected to the active layer through via holes provided in the interlayer dielectric layer, respectively.
  • the material of the active layer is indium gallium zinc oxide.
  • the gate insulating layer covers an intermediate region of the active layer, and the active layer is exposed on both sides of the gate insulating layer; the exposed active source is applied by an ion implantation process or a plasma bombardment process
  • the layer is converted into a conductor, a source connection portion is formed at one end of the active layer, and a drain connection portion is formed at the other end;
  • the source electrode is connected to the source connection portion, and the drain electrode is connected to the drain connection portion.
  • Another aspect of the present invention provides a flexible display device including a laminated flexible array substrate and an electroluminescent device, the electroluminescent device further having a transparent flexible cover; wherein the flexible array
  • the substrate employs a flexible array substrate as described above.
  • the flexible array substrate and the corresponding flexible display device provided in the embodiments of the present invention by providing interconnecting structural members between the interlayer dielectric layer and the buffer layer, the interconnecting structural members are prepared by materials having good leveling and flexibility. Forming, can effectively release the stress of the interlayer dielectric layer and avoid stress concentration, enhance the bonding performance of the interconnect structure layer (interlayer dielectric layer and buffer layer) in the flexible array substrate, and improve the problem of falling or cracking of the interconnect structure layer, The quality of the flexible array substrate is improved, and the flexibility of the entire flexible display device is also improved.
  • 1 is a schematic structural view of a conventional flexible array substrate
  • FIG. 2 is a schematic structural diagram of a flexible array substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic view showing the distribution of interconnecting structural members on a buffer layer in an embodiment of the present invention
  • Figure 4 is a schematic cross-sectional view of an interconnecting structural member in a preferred embodiment of the present invention.
  • FIG. 5 is a process flow diagram of a method for fabricating a flexible array substrate according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a flexible display device according to an embodiment of the present invention.
  • the flexible array substrate includes a flexible substrate 10 and a buffer layer 20 on the flexible substrate 10.
  • the buffer layer 20 is provided with a plurality of thin film transistors. 30 (only one of the thin film transistors 30 is shown in FIG. 2), on which the interlayer dielectric layer 40 is disposed, the interlayer dielectric layer 40 covering the buffer layer 20.
  • An interconnecting structure 50 is disposed between the interlayer dielectric layer 40 and the buffer layer 20, and at least one interconnect structure 50 is disposed on each side of each of the thin film transistors 30, and the interconnect structure The piece 50 extends in a direction parallel to the bending axis of the flexible array substrate.
  • 3 is a schematic view showing the distribution of the interconnection structure 50 on the buffer layer 20.
  • each of the interconnection structures 50 has a direction along the bending axis of the flexible array substrate in the buffer layer 20 ( Extending in the Y direction in FIG. 3, a plurality of interconnecting structural members 50 are arranged in parallel in a direction perpendicular to the bending axis (in the X direction in FIG. 3), and a line of thin films is distributed between each of the two interconnecting structural members 50.
  • Transistor (not shown in Figure 3).
  • the interconnecting structural member 50 is formed by using a material having good leveling property and flexibility, thereby enhancing the bonding performance of the interlayer dielectric layer 40 and the buffer layer 20 in the flexible array substrate, and effectively releasing the interlayer dielectric layer.
  • the material of the interconnecting structural member 50 may be selected as an organic photoresist material.
  • a part of the interconnecting structural member 50 is embedded in the interlayer dielectric layer 40, and another portion is embedded in the buffer.
  • a portion of the interconnecting structure 50 embedded in the buffer layer 20 has a square cross section, and a portion of the portion embedded in the interlayer dielectric layer 40 has a cross section of The trapezoidal shape having a circular chamfer is used to smooth the contact cross section of the interconnecting structural member 50 and the interlayer dielectric layer 40, and the interconnecting structural member 50 can more effectively release the stress of the interlaminar dielectric layer 40.
  • the cross section of the portion of the interconnect structure 50 embedded in the interlayer dielectric layer 40 may also be designed to be semi-circular, or may have other smooth surfaces. shape.
  • the interconnecting structural member 50 includes a plurality of first structural portions 51 and a plurality of second structural portions 52 arranged alternately spaced along its length direction (in FIG. 3 Only a few first structural portions 51 and second structural portions 52) are shown.
  • the first structural portion 51 is a strip-like structure having a length multiplied by a width
  • the second structural portion 52 is a dot-like structure having a length equal to or nearly equal to the width.
  • the portion of the second structural portion 52 that protrudes from the buffer layer 20 ie, the portion that is embedded in the interlayer dielectric layer 40
  • the spacing arrangement means that the first structural portion 51 and the second structural portion 52 are not integrally connected, but have a distance therebetween.
  • the thin film transistor 30 includes an active layer 31, a gate electrode 32, a source electrode 33, and a drain electrode 34.
  • the thin film transistor 30 is a thin film transistor of a top gate structure.
  • the active layer 31 is formed on the buffer layer 20, and the gate electrode 32 is formed on the gate electrode 32.
  • a gate insulating layer 35 is disposed between the active layer 31 and the gate electrode 32 in the active layer 31.
  • the interlayer dielectric layer 40 is disposed on the gate electrode 32.
  • the source electrode 33 and the drain electrode 34 are respectively disposed on the interlayer dielectric layer 40.
  • the source electrode 33 and the drain electrode 34 are respectively disposed through The via holes 41, 42 in the interlayer dielectric layer 40 are electrically connected to the active layer 31.
  • the material of the active layer 31 is IGZO (indium gallium zinc oxide).
  • the gate insulating layer 35 covers only the intermediate portion of the active layer 31, and the active sides of the gate insulating layer 35 expose the active Layer 31.
  • the exposed active layer 31 is converted into a conductor by applying an ion implantation process or a plasma bombardment process, a source connection portion 31a is formed at one end of the active layer 31, and a drain connection portion 31b is formed at the other end.
  • the source electrode 33 is connected to the source connection portion 31a, and the drain electrode 34 is connected to the drain connection portion 31b.
  • the source connection portion 31a and the drain connection portion 31b are in the same layer and integrated structure as the active layer 31, and the source connection portion 31a and the drain connection portion 31b have good electrical conductivity, whereby The source electrode 33 and the drain electrode 34 are connected to the active layer through the source connection portion 31a and the drain connection portion 31b, respectively.
  • the contact resistance between the source electrode 33 and the drain electrode 34 and the active layer 31 is reduced, further improving the performance of the device.
  • the method includes the steps of:
  • a flexible substrate 10 is provided, and a buffer layer 20 is formed on the flexible substrate 10.
  • the buffer layer 20 may be prepared by a magnetron sputtering process, a plasma enhanced chemical vapor deposition process (PECVD), an atomic deposition process (ALD) or a solution process, and the buffer layer 20 may be organic or inorganic. material.
  • the material of the flexible substrate 10 is selected from Polyimide (PI) or Polyethylene Terephthalate (PET).
  • the step includes:
  • a semiconductor film for forming the active layer 31 on the buffer layer 20 by a deposition process such as a magnetron sputtering process, a plasma enhanced chemical vapor deposition process (PECVD), an atomic deposition process (ALD), or a solution method, In the examples, it is an IGZO semiconductor film.
  • a deposition process such as a magnetron sputtering process, a plasma enhanced chemical vapor deposition process (PECVD), an atomic deposition process (ALD), or a solution method, In the examples, it is an IGZO semiconductor film.
  • the IGZO semiconductor film is etched by a photomask process to form a patterned active layer 31.
  • the material of the gate insulating film layer may be SiO x or SiN x , and the material of the gate electrode film layer is mainly It is a metal conductive material.
  • the gate insulating film layer and the gate electrode film layer can be prepared by a magnetron sputtering process, a plasma enhanced chemical vapor deposition process (PECVD), an atomic deposition process (ALD) or a solution process.
  • PECVD plasma enhanced chemical vapor deposition process
  • ALD atomic deposition process
  • the gate insulating film layer and the gate electrode film layer are etched by a photomask process to form a patterned gate insulating layer 35 and a gate electrode 32.
  • a thin film layer for forming the interconnect structure 50 is first deposited on the buffer layer 20 corresponding to the embedded region.
  • an organic photoresist material is selected, which can be subjected to a magnetron sputtering process and plasma enhanced chemistry.
  • a deposition process such as a vapor deposition process (PECVD), an atomic deposition process (ALD), or a solution process is prepared; then the thin film layer is etched by a photomask process to form a patterned interconnect structure 50.
  • an interlayer dielectric layer 40 is prepared on the gate electrode 32, and the interlayer dielectric layer 40 covers the buffer layer 20, and a portion of the interconnect structure 50 is embedded in the interlayer dielectric layer 40.
  • the material of the interlayer dielectric layer 40 may be SiO x or SiN x , and may be deposited by a magnetron sputtering process, a plasma enhanced chemical vapor deposition process (PECVD), an atomic deposition process (ALD) or a solution process. Preparation is obtained.
  • a source electrode 33 and a drain electrode 34 of the thin film transistor 30 on the interlayer dielectric layer 40 by a photomask process, and the source electrode 33 and the drain electrode 34 are electrically connected to the via hole 41, 42 respectively.
  • the active layer 31 Specifically, a metal conductive thin film layer for forming the source electrode 33 and the drain electrode 34 is first prepared on the interlayer dielectric layer 40; the metal conductive thin film layer may be subjected to a magnetron sputtering process, plasma enhanced chemical vapor deposition Prepared by a deposition process such as a process (PECVD), an atomic deposition process (ALD), or a solution process. The metal conductive thin film layer is then etched by a photomask process to form a patterned source electrode 33 and drain electrode 34.
  • PECVD plasma enhanced chemical vapor deposition Process
  • ALD atomic deposition process
  • each mask process includes a mask, an exposure, a development, an etching, and a stripping process, respectively, wherein the etching process includes dry etching and wet etching.
  • the parameters of the reticle process may vary in each step, but in the field of display manufacturing, the reticle process is already a relatively mature process technology, and will not be described in detail herein.
  • a rigid substrate is generally provided first, and the flexible substrate is placed on the rigid substrate to prepare the structural layers of the layers, and the entire flexible array is completed. The substrate is fabricated even after the fabrication of the entire display device is completed, and then the rigid substrate is removed.
  • step S24 as above specifically includes:
  • the gate insulating layer 35 and the gate electrode 32 are formed by a top gate self-aligned process etching, the gate insulating layer 35 covering only the intermediate region of the active layer 31, the gate insulating layer 35 The active layer 31 is exposed on both sides.
  • the exposed active layer 31 is converted into a conductor by an ion implantation process or a plasma bombardment process, a source connection portion 31a is formed at one end of the active layer 31, and a drain connection portion 31b is formed at the other end.
  • the connection portion 31a is for connecting the source electrode 33
  • the drain connection portion 31b is for connecting the drain electrode 34.
  • an embodiment of the present invention further provides a flexible display device.
  • the flexible display device includes a laminated flexible array substrate 100 and an electroluminescent device 200.
  • a transparent flexible cover 300 is also packaged on the electroluminescent device 200.
  • the flexible array substrate 100 adopts the flexible array substrate provided by the above embodiments of the present invention.
  • the electroluminescent device 200 generally includes an anode formed on the flexible array substrate 100, an organic functional layer formed on the anode, and a cathode formed on the organic functional layer, and the anode and the cathode excite the organic functional layer to realize display.
  • the organic functional layer is generally composed of three functional layers, namely a Hole Transport Layer (HTL), an Emissive Layer (EML), and an Electro Transport Layer (ETL).
  • Each functional layer may be one layer or more than one layer, for example, a hole transport functional layer, and may be subdivided into a hole injection layer and a hole transport layer; an electron transport functional layer may be subdivided into an electron transport layer.
  • the electron injection layer but its function is similar, so it is collectively referred to as a hole transport function layer and an electron transport function layer.
  • the flexible array substrate and the corresponding flexible display device have good leveling property by providing interconnecting structural members between the interlayer dielectric layer and the buffer layer.
  • the flexible material is prepared to effectively release the stress of the interlayer dielectric layer and avoid stress concentration, enhance the bonding performance of the interconnect structure layer (interlayer dielectric layer and buffer layer) in the flexible array substrate, and improve the disconnection of the interconnect structure layer. Or the problem of cracking, improving the quality of the flexible array substrate, and also improving the flexibility of the entire flexible display device.

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  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种柔性阵列基板，包括柔性基底（10）以及柔性基底（10）上的缓冲层（20），缓冲层（20）上阵列设置有多个薄膜晶体管（30），薄膜晶体管（30）上设置有层间介质层（40），层间介质层（40）覆盖缓冲层（20）；其中，层间介质层（40）和缓冲层（20）之间设置有互联结构件（50），每一列薄膜晶体管（30）的两侧分别设置有至少一个互联结构件（50），互联结构件（50）朝向平行于柔性阵列基板的弯曲轴的方向延伸。还公开了柔性阵列基板的制备方法以及包含柔性阵列基板的柔性显示装置。通过设置互联结构件（50），增强了柔性阵列基板中互联结构层的联结性能，改善了互联结构层发生脱落或破裂的问题，提高柔性阵列基板的品质。

Description

柔性阵列基板及其制备方法、柔性显示装置 技术领域
本发明涉及显示器技术领域,尤其涉及一种柔性阵列基板及其制备方法，还涉及一种包含如上柔性阵列基板的柔性显示装置。
背景技术
平板显示技术在近十年有了飞速的发展，无论是屏幕的尺寸还是显示的质量都取得了很大进步。柔性显示装置凭借其能够弯曲的特性可以胜任很多需要曲面显示的领域，如智能卡、电子纸、智能标签、以及传统平板显示装置所能够适用的各个领域，柔性显示装置必将在未来的显示产品市场中凭借其梦幻般的靓丽外观而占领巨大的市场份额。通常地，柔性显示装置包括叠层设置的柔性阵列基板以及电致发光器件，电致发光器件上封装有透明柔性盖板。
如图1所示的现有的一种柔性阵列基板，其包括柔性基板1、形成在柔性基板1上的缓冲层2以及阵列设置在缓冲层2上的多个薄膜晶体管3(图1中仅示出了其中的一个薄膜晶体管3)。其中，薄膜晶体管3包括有源层4、栅电极5、源电极6和漏电极7，有源层4和栅电极5之间设置有栅极绝缘层8，栅电极5上设置有层间介质层(Inter Layer Dielectric，ILD)9，并且层间介质层9覆盖缓冲层2以将各层结构互联为一体。层间介质层9还用于将源电极6和漏电极7与栅电极5相互隔离，源电极6和漏电极7分别通过层间介质层9中的过孔电连接到有源层4。
如上结构的柔性阵列基板中，缓冲层2、栅极绝缘层8以及层间介质层9的材料通常使用无机氧化物如SiOx、SiNx等。柔性阵列基板的弯曲对其中的有机及金属材料的损伤较小，但对柔韧性较差的无机氧化物的损伤相对来说较为严重，尤其是弯曲成较小曲率半径时，易造成包含有上述无机氧化物的柔性阵列基板的破裂及剥离错位等故障。对于栅极绝缘层8，可将栅极绝缘层8图形化，减小其覆盖面积达到减小应力，降低开裂及剥离错位的问题，但是层间介质层9和缓冲层2之间相互结合的面积较大，两者的联结性能较差，在弯曲柔性阵列基板时， 层间介质层9易于从缓冲层2上脱落或发生破裂，影响柔性阵列基板的品质。
发明内容
有鉴于此，本发明提供了一种柔性阵列基板及其制备方法，以增强柔性阵列基板中互联结构层的联结性能，改善互联结构层发生脱落或破裂的问题，提高柔性阵列基板的品质。
为了实现上述目的，本发明采用了如下的技术方案：
一种柔性阵列基板，包括柔性基底以及柔性基底上的缓冲层，所述缓冲层上阵列设置有多个薄膜晶体管，所述薄膜晶体管上设置有层间介质层，所述层间介质层覆盖所述缓冲层；其中，所述层间介质层和所述缓冲层之间设置有互联结构件，每一列所述薄膜晶体管的两侧分别设置有至少一个所述互联结构件，所述互联结构件朝向平行于所述柔性阵列基板的弯曲轴的方向延伸。
其中，所述互联结构件的一部分嵌入到所述层间介质层中，另一部分嵌入到所述缓冲层中。
其中，所述互联结构件嵌入到所述缓冲层的部分的截面为方形，嵌入到所述层间介质层的部分的截面为半圆形或具有圆弧倒角的梯形。
其中，所述互联结构件包括沿其长度方向上交替间隔排布的多个第一结构部和多个第二结构部；所述第一结构部为长度数倍大于宽度的条状结构，所述第二结构部为长度与宽度相等或近于相等的点状结构。
其中，所述互联结构件的材料为有机光阻材料。
其中，所述薄膜晶体管包括有源层、栅电极、源电极和漏电极；所述有源层形成于所述缓冲层上，所述栅电极形成于所述有源层，所述有源层和所述栅电极之间设置有栅极绝缘层；所述层间介质层设置于所述栅电极上，所述源电极和漏电极分别设置于所述层间介质层上，所述源电极和漏电极分别通过设置于所述层间介质层中的过孔电连接到所述有源层。
其中，所述有源层的材料为铟镓锌氧化物。
其中，所述栅极绝缘层覆盖所述有源层的中间区域，所述栅极绝缘层的两侧裸露出所述有源层；应用离子注入工艺或等离子轰击工艺，将裸露出的有源层转化为导体，在所述有源层的一端形成源极连接部，另一端形成漏极连接部； 所述源电极连接到所述源极连接部，所述漏电极连接到所述漏极连接部。
如上所述的柔性阵列基板的制备方法，该方法包括步骤：
S1、提供一柔性基底，在该柔性基底上制备形成缓冲层；
S2、在所述缓冲层上制备形成所述薄膜晶体管的有源层和栅电极；
S3、在所述缓冲层上位于所述有源层的两侧，通过光罩工艺制备形成图案化的互联结构件嵌入区域；
S4、通过光罩工艺在所述嵌入区域上制备形成互联结构件；
S5、在所述栅电极上制备层间介质层，并且所述层间介质层覆盖所述缓冲层，所述互联结构件的一部分嵌入到所述层间介质层中；
S6、在所述层间介质层中刻蚀出连通到所述有源层的过孔；
S7、通过光罩工艺在所述层间介质层上制备形成所述薄膜晶体管的源电极和漏电极，所述源电极和漏电极分别通过所述过孔电连接到所述有源层。
本发明的另一方面是提供一种柔性显示装置，其包括叠层设置的柔性阵列基板以及电致发光器件，所述电致发光器件上还封装有透明柔性盖板；其中，所述柔性阵列基板采用如上所述的柔性阵列基板。
本发明实施例中提供的柔性阵列基板及其相应的柔性显示装置，通过在层间介质层和缓冲层之间设置互联结构件，互联结构件采用具有良好的流平性和柔韧性的材料制备形成，可以有效释放层间介质层的应力以及避免应力集中，增强了柔性阵列基板中互联结构层(层间介质层和缓冲层)的联结性能，改善了互联结构层发生脱落或破裂的问题，提高柔性阵列基板的品质，并且也提升了柔性显示装置整体的柔韧性。
附图说明
图1是现有的一种柔性阵列基板的结构示意图；
图2是本发明实施例提供的柔性阵列基板的结构示意图；
图3是本发明实施例中的互联结构件在缓冲层上的分布示意图；
图4是本发明优选实施例中互联结构件的截面示意图；
图5是本发明实施例提供的柔性阵列基板的制备方法的工艺流程图；
图6是本发明实施例提供的柔性显示装置的结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面结合附图对本发明的具体实施方式进行详细说明。这些优选实施方式的示例在附图中进行了例示。附图中所示和根据附图描述的本发明的实施方式仅仅是示例性的，并且本发明并不限于这些实施方式。
在此，还需要说明的是，为了避免因不必要的细节而模糊了本发明，在附图中仅仅示出了与根据本发明的方案密切相关的结构和/或处理步骤，而省略了与本发明关系不大的其他细节。
本实施例首先提供了一种柔性阵列基板，如图2所示，所述柔性阵列基板包括柔性基底10以及柔性基底10上的缓冲层20，所述缓冲层20上阵列设置有多个薄膜晶体管30(图2中仅示出了其中的一个薄膜晶体管30)，所述薄膜晶体管30上设置有层间介质层40，所述层间介质层40覆盖所述缓冲层20。其中，所述层间介质层40和所述缓冲层20之间设置有互联结构件50，每一列所述薄膜晶体管30的两侧分别设置有至少一个所述互联结构件50，所述互联结构件50朝向平行于所述柔性阵列基板的弯曲轴的方向延伸。图3示出了互联结构件50在缓冲层20上的分布示意图，如图3所示，可以这样理解，每一互联结构件50在缓冲层20均沿着柔性阵列基板的弯曲轴的方向(如图3中的Y方向)上延伸，多个互联结构件50在与弯曲轴垂直的方向(如图3中的X方向)上并行排列，每两个互联结构件50之间分布有一列薄膜晶体管(图3中未示出)。
其中，互联结构件50采用具有良好的流平性和柔韧性的材料制备形成，由此可以增强柔性阵列基板中层间介质层40和缓冲层20的联结性能，并且可以有效释放层间介质层40的应力以及避免应力集中，在弯曲柔性阵列基板时，柔韧性较差的层间介质层40的应力可以通过互联结构件50释放，改善了层间介质层40发生脱落或破裂的问题。具体地，所述互联结构件50的材料可以选择为有机光阻材料。
其中，为了进一步提升层间介质层40和缓冲层20的联结性能，如图2所示，所述互联结构件50的一部分嵌入到所述层间介质层40中，另一部分嵌入到所述缓冲层20中。更具体地，在本实施例中，所述互联结构件50嵌入到所述缓冲层20的部分的截面为方形，嵌入到所述层间介质层40的部分的截面为 具有圆弧倒角的梯形，以使互联结构件50与层间介质层40的接触截面平滑，互联结构件50能够更加有效地释放层间介质层40的应力。
在另外一个优选的实施例方案中，如图4所示，互联结构件50嵌入到所述层间介质层40的部分的截面也可以是设计为半圆形，或者也可以是其它具有平滑表面的形状。
其中，如图3所示，在本实施例中，所述互联结构件50包括沿其长度方向上交替间隔排布的多个第一结构部51和多个第二结构部52(图3中仅示出了若干第一结构部51和第二结构部52)。所述第一结构部51为长度数倍大于宽度的条状结构，所述第二结构部52为长度与宽度相等或近于相等的点状结构。在一个优选的方案中，所述第二结构部52凸起于缓冲层20的部分(即嵌入到所述层间介质层40的部分)呈半球体结构。在此，间隔排布是指第一结构部51和第二结构部52不是连为一体的，而是两者之间具有间隔的距离。通过采用条状结构和点状结构交替间隔排布的互联结构件50，可以更好地分散层间介质层40产生的应力，避免应力集中。
其中，参阅图2，所述薄膜晶体管30包括有源层31、栅电极32、源电极33和漏电极34。在本实施例中，所述薄膜晶体管30为顶栅结构的薄膜晶体管，具体地，如图2所示，所述有源层31形成于所述缓冲层20上，所述栅电极32形成于所述有源层31，所述有源层31和所述栅电极32之间设置有栅极绝缘层35。所述层间介质层40设置于所述栅电极32上，所述源电极33和漏电极34分别设置于所述层间介质层40上，所述源电极33和漏电极34分别通过设置于所述层间介质层40中的过孔41、42电连接到所述有源层31。
其中，在本实施例中，所述有源层31的材料为IGZO(indium gallium zinc oxide，铟镓锌氧化物)。
进一步地，在本实施例中，如图2所示，所述栅极绝缘层35仅覆盖所述有源层31的中间区域，所述栅极绝缘层35的两侧裸露出所述有源层31。通过应用离子注入工艺或等离子轰击工艺，将裸露出的有源层31转化为导体，在所述有源层31的一端形成源极连接部31a，另一端形成漏极连接部31b。所述源电极33连接到所述源极连接部31a，所述漏电极34连接到所述漏极连接部31b。如上结构中，源极连接部31a和漏极连接部31b与有源层31是同层且为一体的结构，并且源极连接部31a和漏极连接部31b具有良好的导电性能，由此，源电极33和漏电极34分别通过源极连接部31a和漏极连接部31b连接到有源层 31时，减小了源电极33和漏电极34与有源层31之间的接触电阻，进一步提高了器件的性能。
下面参阅图5并结合图2和图3，详细介绍如上所述的柔性阵列基板的制备方法。如图3所示，该方法包括步骤：
S1、提供一柔性基底10，该柔性基底10上制备形成缓冲层(Buffer Layer)20。其中，缓冲层20可以通过磁控溅射工艺、等离子体增强化学气相沉积工艺(PECVD)、原子沉积工艺(ALD)或者溶液法等沉积工艺制备获得，缓冲层20的材料可以是有机或无机绝缘材料。所述柔性基底10的材料选择为聚酰亚胺(Polyimide，PI)或聚对苯二甲酸乙二醇酯(Polyethylene Terephthalate，PET)。
S2、在所述缓冲层20上制备形成所述薄膜晶体管30的有源层31和栅电极32。具体地，该步骤包括：
S21、通过磁控溅射工艺、等离子体增强化学气相沉积工艺(PECVD)、原子沉积工艺(ALD)或者溶液法等沉积工艺在缓冲层20上沉积用于形成有源层31的半导体薄膜，本实施例中为IGZO半导体薄膜。
S22、通过光罩工艺将IGZO半导体薄膜刻蚀形成图案化的有源层31。
S23、在具有有源层31的缓冲层20上依次制备栅绝缘薄膜层和栅电极薄膜层，所述栅绝缘薄膜层的材料可以为SiOx或SiNx，所述栅电极薄膜层的材料主要是金属导电材料。其中，栅绝缘薄膜层和栅电极薄膜层可以通过磁控溅射工艺、等离子体增强化学气相沉积工艺(PECVD)、原子沉积工艺(ALD)或者溶液法等沉积工艺制备获得。
S24、通过光罩工艺将所述栅绝缘薄膜层和栅电极薄膜层刻蚀形成图案化的栅绝缘层35和栅电极32。
S3、在所述缓冲层20上位于所述有源层31的两侧，通过光罩工艺制备形成图案化的互联结构件嵌入区域。
S4、通过光罩工艺在所述嵌入区域上制备形成互联结构件50。具体地，首先在对应于嵌入区域的缓冲层20上沉积用于用于形成互联结构件50的薄膜层，本实施例中选用有机光阻材料，可通过磁控溅射工艺、等离子体增强化学气相沉积工艺(PECVD)、原子沉积工艺(ALD)或者溶液法等沉积工艺制备获得；然后通过光罩工艺将薄膜层刻蚀形成图案化的互联结构件50。
S5、在所述栅电极32上制备层间介质层40，并且所述层间介质层40覆盖所述缓冲层20，所述互联结构件50的一部分嵌入到所述层间介质层40中。其中，所述层间介质层40的材料可以为SiOx或SiNx，可以通过磁控溅射工艺、等离子体增强化学气相沉积工艺(PECVD)、原子沉积工艺(ALD)或者溶液法等沉积工艺制备获得。
S6、在所述层间介质层40中刻蚀出连通到所述有源层31的过孔41、42。
S7、通过光罩工艺在所述层间介质层40上制备形成薄膜晶体管30的源电极33和漏电极34，所述源电极33和漏电极34分别通过所述过孔41、42电连接到所述有源层31。具体地，首先在所述层间介质层40上制备用于形成源电极33和漏电极34的金属导电薄膜层；所述金属导电薄膜层可以通过磁控溅射工艺、等离子体增强化学气相沉积工艺(PECVD)、原子沉积工艺(ALD)或者溶液法等沉积工艺制备获得。然后通过光罩工艺将所述金属导电薄膜层刻蚀形成图案化的源电极33和漏电极34。
以上的制备工艺中，每一次光罩工艺中又分别包括掩膜、曝光、显影、刻蚀和剥离等工艺，其中刻蚀工艺包括干法刻蚀和湿法刻蚀。在各个步骤中光罩工艺的参数可能有所不同，但是在显示器的制造领域，光罩工艺已经是现有的比较成熟的工艺技术，在此不再展开详细说明。
需要说明的是，由于柔性阵列基板中使用的柔性基底，其支撑能力较差，因此通常都先提供一刚性基底，将柔性基底放置在刚性基底上再制备各层结构层，在完成整个柔性阵列基板的制作甚至是完成整个显示器件的制作之后，再将刚性基底去除。
进一步地，在本实施例中，如上的步骤S24具体包括：
首先，应用顶栅自对准工艺刻蚀形成所述栅绝缘层35和栅电极32，所述栅极绝缘层35仅覆盖所述有源层31的中间区域，所述栅极绝缘层35的两侧裸露出所述有源层31。
然后，应用离子注入工艺或等离子轰击工艺，将裸露出的有源层31转化为导体，在所述有源层31的一端形成源极连接部31a，另一端形成漏极连接部31b，源极连接部31a用于连接源电极33，漏极连接部31b用于连接漏电极34。
进一步地，本发明实施例还提供了一种柔性显示装置，如图6所示，所述柔性显示装置包括叠层设置的柔性阵列基板100以及电致发光器件200，所述电 致发光器件200上还封装有透明柔性盖板300。其中，所述柔性阵列基板100采用本发明如上实施例所提供的柔性阵列基板。其中，电致发光器件200通常包括形成于柔性阵列基板100上的阳极、形成于阳极上的有机功能层以及形成于有机功能层上的阴极，阳极与阴极激发有机功能层以实现显示。其中，有机功能层一般由三个功能层构成，分别为空穴传输功能层(Hole Transport Layer，HTL)、发光功能层(Emissive Layer，EML)和电子传输功能层(Electron Transport Layer，ETL)。每个功能层可以是一层，也可以是一层以上，例如空穴传输功能层，有时可以细分为空穴注入层和空穴传输层；电子传输功能层，可以细分为电子传输层和电子注入层，但其功能相近，故统称为空穴传输功能层和电子传输功能层。
综上所述，本发明实施例中提供的柔性阵列基板及其相应的柔性显示装置，通过在层间介质层和缓冲层之间设置互联结构件，互联结构件采用具有良好的流平性和柔韧性的材料制备形成，可以有效释放层间介质层的应力以及避免应力集中，增强了柔性阵列基板中互联结构层(层间介质层和缓冲层)的联结性能，改善了互联结构层发生脱落或破裂的问题，提高柔性阵列基板的品质，并且也提升了柔性显示装置整体的柔韧性。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上所述仅是本申请的具体实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (20)

  1. 一种柔性阵列基板，包括柔性基底以及柔性基底上的缓冲层，所述缓冲层上阵列设置有多个薄膜晶体管，所述薄膜晶体管上设置有层间介质层，所述层间介质层覆盖所述缓冲层；其中，所述层间介质层和所述缓冲层之间设置有互联结构件，每一列所述薄膜晶体管的两侧分别设置有至少一个所述互联结构件，所述互联结构件朝向平行于所述柔性阵列基板的弯曲轴的方向延伸。
  2. 根据权利要求1所述的柔性阵列基板，其中，所述互联结构件的一部分嵌入到所述层间介质层中，另一部分嵌入到所述缓冲层中。
  3. 根据权利要求2所述的柔性阵列基板，其中，所述互联结构件嵌入到所述缓冲层的部分的截面为方形，嵌入到所述层间介质层的部分的截面为半圆形或具有圆弧倒角的梯形。
  4. 根据权利要求2所述的柔性阵列基板，其中，所述互联结构件包括沿其长度方向上交替间隔排布的多个第一结构部和多个第二结构部；所述第一结构部为长度数倍大于宽度的条状结构，所述第二结构部为长度与宽度相等或近于相等的点状结构。
  5. 根据权利要求4所述的柔性阵列基板，其中，所述互联结构件的材料为有机光阻材料。
  6. 根据权利要求1所述的柔性阵列基板，其中，所述薄膜晶体管包括有源层、栅电极、源电极和漏电极；所述有源层形成于所述缓冲层上，所述栅电极形成于所述有源层，所述有源层和所述栅电极之间设置有栅极绝缘层；所述层间介质层设置于所述栅电极上，所述源电极和漏电极分别设置于所述层间介质层上，所述源电极和漏电极分别通过设置于所述层间介质层中的过孔电连接到所述有源层。
  7. 根据权利要求6所述的柔性阵列基板，其中，所述有源层的材料为铟镓锌氧化物。
  8. 根据权利要求7所述的柔性阵列基板，其中，所述栅极绝缘层覆盖所述有源层的中间区域，所述栅极绝缘层的两侧裸露出所述有源层；应用离子注入工艺或等离子轰击工艺，将裸露出的有源层转化为导体，在所述有源层的一端形成源极连接部，另一端形成漏极连接部；所述源电极连接到所述源极连接部， 所述漏电极连接到所述漏极连接部。
  9. 一种柔性阵列基板的制备方法，其中，包括步骤：
    S1、提供一柔性基底，在该柔性基底上制备形成缓冲层；
    S2、在所述缓冲层上制备形成所述薄膜晶体管的有源层和栅电极；
    S3、在所述缓冲层上位于所述有源层的两侧，通过光罩工艺制备形成图案化的互联结构件嵌入区域；
    S4、通过光罩工艺在所述嵌入区域上制备形成互联结构件；
    S5、在所述栅电极上制备层间介质层，并且所述层间介质层覆盖所述缓冲层，所述互联结构件的一部分嵌入到所述层间介质层中；
    S6、在所述层间介质层中刻蚀出连通到所述有源层的过孔；
    S7、通过光罩工艺在所述层间介质层上制备形成所述薄膜晶体管的源电极和漏电极，所述源电极和漏电极分别通过所述过孔电连接到所述有源层。
  10. 根据权利要求9所述的柔性阵列基板的制备方法，其中，所述互联结构件嵌入到所述缓冲层的部分的截面为方形，嵌入到所述层间介质层的部分的截面为半圆形或具有圆弧倒角的梯形。
  11. 根据权利要求10所述的柔性阵列基板的制备方法，其中，所述互联结构件包括沿其长度方向上交替间隔排布的多个第一结构部和多个第二结构部；所述第一结构部为长度数倍大于宽度的条状结构，所述第二结构部为长度与宽度相等或近于相等的点状结构。
  12. 根据权利要求11所述的柔性阵列基板的制备方法，其中，所述互联结构件的材料为有机光阻材料。
  13. 根据权利要求9所述的柔性阵列基板的制备方法，其中，所述有源层的材料为铟镓锌氧化物，所述有源层和所述栅电极还制备形成有栅极绝缘层；步骤S2中具体包括：
    应用顶栅自对准工艺刻蚀形成所述栅绝缘层和栅电极，所述栅极绝缘层仅覆盖所述有源层的中间区域，所述栅极绝缘层的两侧裸露出所述有源层；
    应用离子注入工艺或等离子轰击工艺，将裸露出的有源层转化为导体，在 所述有源层的一端形成源极连接部，另一端形成漏极连接部，所述源极连接部用于连接源电极，所述漏极连接部用于连接漏电极。
  14. 一种柔性显示装置，包括叠层设置的柔性阵列基板以及电致发光器件，所述电致发光器件上还封装有透明柔性盖板；其中，所述柔性阵列基板包括柔性基底以及柔性基底上的缓冲层，所述缓冲层上阵列设置有多个薄膜晶体管，所述薄膜晶体管上设置有层间介质层，所述层间介质层覆盖所述缓冲层；其中，所述层间介质层和所述缓冲层之间设置有互联结构件，每一列所述薄膜晶体管的两侧分别设置有至少一个所述互联结构件，所述互联结构件朝向平行于所述柔性阵列基板的弯曲轴的方向延伸。
  15. 根据权利要求14所述的柔性显示装置，其中，所述互联结构件的一部分嵌入到所述层间介质层中，另一部分嵌入到所述缓冲层中。
  16. 根据权利要求15所述的柔性显示装置，其中，所述互联结构件嵌入到所述缓冲层的部分的截面为方形，嵌入到所述层间介质层的部分的截面为半圆形或具有圆弧倒角的梯形。
  17. 根据权利要求15所述的柔性显示装置，其中，所述互联结构件包括沿其长度方向上交替间隔排布的多个第一结构部和多个第二结构部；所述第一结构部为长度数倍大于宽度的条状结构，所述第二结构部为长度与宽度相等或近于相等的点状结构。
  18. 根据权利要求17所述的柔性显示装置，其中，所述互联结构件的材料为有机光阻材料。
  19. 根据权利要求14所述的柔性显示装置，其中，所述薄膜晶体管包括有源层、栅电极、源电极和漏电极；所述有源层形成于所述缓冲层上，所述栅电极形成于所述有源层，所述有源层和所述栅电极之间设置有栅极绝缘层；所述层间介质层设置于所述栅电极上，所述源电极和漏电极分别设置于所述层间介质层上，所述源电极和漏电极分别通过设置于所述层间介质层中的过孔电连接到所述有源层。
  20. 根据权利要求19所述的柔性显示装置，其中，所述有源层的材料为铟镓锌氧化物，所述栅极绝缘层覆盖所述有源层的中间区域，所述栅极绝缘层的两侧裸露出所述有源层；应用离子注入工艺或等离子轰击工艺，将裸露出的有源层转化为导体，在所述有源层的一端形成源极连接部，另一端形成漏极连接 部；所述源电极连接到所述源极连接部，所述漏电极连接到所述漏极连接部。
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