WO2018009145A1 - Boîtier à semi-conducteur et procédés de formation de celui-ci - Google Patents

Boîtier à semi-conducteur et procédés de formation de celui-ci Download PDF

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Publication number
WO2018009145A1
WO2018009145A1 PCT/SG2017/050317 SG2017050317W WO2018009145A1 WO 2018009145 A1 WO2018009145 A1 WO 2018009145A1 SG 2017050317 W SG2017050317 W SG 2017050317W WO 2018009145 A1 WO2018009145 A1 WO 2018009145A1
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Prior art keywords
die
electrical
contact elements
routing layer
semiconductor
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PCT/SG2017/050317
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English (en)
Inventor
Masaya Kawano
Surya Bhattacharya
Vempati Srinivasa Rao
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Agency For Science, Technology And Research
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Publication of WO2018009145A1 publication Critical patent/WO2018009145A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73209—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates

Definitions

  • Various aspects of this disclosure relate to a semiconductor package. Various aspects of this disclosure relate to methods of forming a semiconductor package.
  • Portable computing systems have become one of the major drivers in semiconductor industry.
  • Such electronic systems include basically high performance logic, such as central processing unit (CPU) and graphic processing unit (GPU), and single or multiple memory modules, and carry out massive amount of data processing and transfers between CPU/GPU and memories. Therefore, significant storage capacity in memories and as well as higher data transfer capabilities (bandwidth) between logic and memory is required in order to meet the system demands.
  • CPU central processing unit
  • GPU graphic processing unit
  • single or multiple memory modules single or multiple memory modules
  • High-Bandwidth Memory introduced recently to the market to achieve next generation portable computing systems solves two key problems related to contemporary DRAM: it increases the bandwidth (BW) and reduces the power consumption.
  • HBM Genel
  • HBM contains 3982 micro-bumps with a staggered pitch of 27.5 micrometer and 48 micrometer and the bump size is 25micrometer.
  • the die-to-die input-output (IO) contacts in HBM ( ⁇ 1200) are located towards one edge so that the logic to memory channel length is reduced.
  • existing silicon interposer based packaging technologies can be used but they are prohibitively expensive due to foundry based multi-layer fine-pitch interconnects and large interposer size.
  • Various embodiments may provide a semiconductor package including:
  • a routing layer including one or more dielectric materials
  • first semiconductor die having a first side facing the first side of the routing layer, and a second side opposite the first side of the first semiconductor die; a plurality of first electrical die contact elements on the first side of the first semiconductor die; a plurality of second electrical die contact elements on the first side of the first semiconductor die; a second semiconductor die having a first side facing the first side of the routing layer, and a second side opposite the first side of the second semiconductor die; a plurality of third electrical die contact elements on the first side of the second semiconductor die;
  • an interconnection die having a first side, and a second side opposite the first side; wherein a first portion of the first side faces at least a portion of the first side of the first semiconductor die and a second portion of the first side faces at least a portion of the first side of the second semiconductor die; and wherein the second side faces the first side of the routing layer;
  • a resin encapsulation structure covering at least a portion of the first semiconductor die, at least a portion of the second semiconductor die, and at least a portion of the interconnection die; one or more first resin encapsulated electrical interconnections extending vertically between the plurality of first electrical routing layer contact elements and the plurality of first electrical die contact elements to electrically connect the routing layer and the first semiconductor die; one or more second resin encapsulated electrical interconnections extending vertically between the plurality of second electrical routing layer contact elements and the plurality of third electrical die contact elements to electrically connect the routing layer and the second semiconductor die;
  • the routing layer includes one or more electrically conductive routing layer interconnections electrically coupling one or more of the plurality of third electrical routing layer contact elements with the first electrical routing layer contact elements contact elements, and one or more of the plurality of third electrical routing layer contact elements with the second electrical routing layer contact elements;
  • interconnection die includes one or more electrically conductive interconnection die interconnections electrically connecting the plurality of fifth electrical die eontact elements and the plurality of sixth electrical die contact elements.
  • Various embodiments may provide a method of forming the semiconductor structure, the method including:
  • first semiconductor die having a first side and a second side opposite the first side of the first semiconductor die; a plurality of first electrical die contact elements on the first side of the first semiconductor die; and a plurality of second electrical die contact elements on the first side of the first semiconductor die;
  • a second semiconductor die having a first side and a second side opposite the first side of the second semiconductor die; a plurality of third electrical die contact elements on the first side of the second semiconductor die; and a plurality of fourth electrical die contact elements on the first side of the second semiconductor die;
  • the interconnection die further includes a plurality of fifth electrical die contact elements on the first portion of the first side of the interconnection die; and a plurality of sixth electrical die contact elements on the second portion of the first side of the interconnection die; wherein the interconnection die includes one or more electrically conductive interconnection die interconnections electrically connecting the plurality of fifth electrical die contact elements and the plurality of sixth electrical die contact elements; wherein a first portion of the first side of the interconnection die faces at least a portion of the first side of the first semiconductor die and a second portion of the first side of the interconnection die faces at least a portion of the first side of the second semiconductor die; forming one or more first resin encapsulated electrical interconnections extending from the plurality of first electrical routing layer contact elements; forming one or more second resin encapsulated electrical interconnections extending from the plurality of second electrical routing layer contact elements
  • first electrical routing layer contact elements forming a plurality of first electrical routing layer contact elements and a plurality of second electrical routing layer contact elements on a first side of the routing layer; and a plurality of third electrical routing layer contact elements on a second side of the routing layer opposite the first side;
  • the routing layer is formed so that the first side of the routing layer faces the first side of the first semiconductor die and so that the first side of the routing layer the first side of the second semiconductor die and further so that the first side of the routing layer faces the second side of the interconnection die; wherein the routing layer is formed so to be arranged in relation to the plurality of first electrical die contact elements to electrically connect the routing layer and the first semiconductor die, and in relation to the plurality of third electrical die contact elements to electrically connect the routing layer and the second semiconductor die; wherein the routing layer includes one or more electrically conductive routing layer interconnections electrically coupling one or more of the plurality of third electrical routing layer contact elements with the first electrical routing layer contact elements, and one or more of the plurality of third electrical routing layer contact elements with the second electrical routing layer contact elements.
  • FIG. 1 shows schematic illustration of a semiconductor package 01 according to various embodiments, in the "inverted" position wherein the first semiconductor die 20 and the second semiconductor die 30 are above the routing layer 10.
  • FIG. 2 shows schematic illustration of the semiconductor package 01 according to figure 1 attached to a PCB 03.
  • FIG. 3 shows schematic illustration of another semiconductor package 01 according to various embodiments, wherein in addition to the first semiconductor die and the second semiconductor die a third and a fourth semiconductor dies comprised in the same semiconductor package. Also a second interconnection die is comprised.
  • FIG. 4 is a flow diagram of forming a semiconductor packaging according to various embodiments.
  • FIG. 5A and 5B is a schematic illustrating a method of forming a semiconductor packaging according to various embodiments.
  • Fig. 5B is the continuation of Fig. 5 A.
  • FIG. 6A and 6B is a schematic illustrating a method of forming a semiconductor packaging according to various embodiments, wherein first and second resin encapsulated electrical interconnections 51 and 52 are fabricated after die mounting of the first semiconductor die 20 and the second semiconductor die 30 on a carrier 70.
  • Fig. 6B is the continuation of Fig. 6A.
  • FIG. 7A and 7B is a schematic illustrating a method of forming a semiconductor packaging according to various embodiments, wherein part, e.g. the substrate 49, of the interconnection die 40 is etched away enabling connection paths on the second side 42 of the interconnection die 40.
  • Fig. 7B is the continuation of Fig. 7A.
  • FIG. 8 is a schematic repeated from Fig. 7B step 7.g to show the plane 61, first plane 63, and second plane 64. The lines indicating the planes are not shown in the other figures to improve visibility. DETAILED DESCRIPTION
  • Embodiments described in the context of one of the methods or memory cells/devices are analogously valid for the other methods or memory cells/devices. Similarly, embodiments described in the context of a method are analogously valid for a memory cell/device, and vice versa.
  • the word “over” used with regards to a deposited material formed “over” a side or surface may be used herein to mean that the deposited material may be formed “directly on”, e.g. in direct contact with, the implied side or surface.
  • the word “over” used with regards to a deposited material formed “over” a side or surface may also be used herein to mean that the deposited material may be formed "indirectly on” the implied side or surface with one or more additional layers being arranged between the implied side or surface and the deposited material.
  • a first layer "over" a second layer may refer to the first layer directly on the second layer, or that the first layer and the second layer are separated by one or more intervening layers.
  • the word "inverted” or “flipped” is used with regards to the orientation of a semiconductor die.
  • a semiconductor die is non-inverted or non-flipped if the substrate, or carrier, is facing downwards.
  • the largest carrier is usually drawn at the bottom, because that also corresponds to the usual position in a manufacturing process.
  • the device arrangement as described herein may be operable in various orientations, and thus it should be understood that the terms “top”, “bottom”, etc., when used in the following description are used for convenience and to aid understanding of relative positions or directions, and not intended to limit the orientation of the device arrangement.
  • connections as in resin encapsulated electrical interconnections, refers that there is a plurality.
  • connection of such elements it means that one or more, e.g. a plurality, is being connected, also written as coupled.
  • suitable connection will be chosen according to the envisaged application, so that not necessarily all of a plurality of "elements” or “interconnections” need to be connected.
  • the "routing layer includes electrically conductive routing layer interconnections electrically coupling the third electrical routing layer contact elements with the first electrical routing layer contact elements " means "the routing layer includes one or more electrically conductive routing layer interconnections electrically coupling one or more of the plurality of third electrical routing layer contact elements with one or more of the first electrical routing layer contact elements". Obviously it is not necessary that all of the plurality are connected. The skilled in the art will understand that it means that those contact elements that provide the desired electronic function are connected. There could be other contact elements that are not required for a desired function, that are left unconnected.
  • the figures are of schematic nature, the proportion and the number of connections is modified to improve the visibility and to easier explain the invention. When there is a reference to a plurality of elements, these may in reality be of a different number as shown in the figure, e.g. of a larger number.
  • the figures are mainly schematic illustrations of cross- sections, wherein some connections are shown in two dimensions as exemplary only.
  • the contact elements e.g. as shown in the figures, elements 23, 33, 24, 43, 34, 44, are e.g. metallized.
  • the figures show the respective contact elements of the dies being flush with the die surface, however it the contact elements can also be provided non-flush, thus at least partially out of the surface plane of the respective die. It is preferred that the contact elements inelude under bump metallization (UBM).
  • UBM under bump metallization
  • Various embodiments provide novel packaging technologies which may reduce the system cost and footprint in par with the performance improvements.
  • the presently proposed fan-out packaging technology uses fewer thick metallization layers with an embedded fine pitch interconnect (EFI) die and wafer level assembly process. There is also proposed a process for producing such package.
  • EFI embedded fine pitch interconnect
  • the present invention allows for increased bandwidth of high-speed electronic systems with novel techniques to meet fine-pitch IO requirements.
  • the invention also provides a greater flexibility for signal and power/IO routing.
  • FIG. 1 shows a semiconductor package 01 according to various embodiments.
  • the semiconductor package 01 includes a routing layer 10 including one or more dielectric materials 02, a first semiconductor die 20, a second semiconductor die 30, and an interconnection die 40.
  • the semiconductor package further includes a plurality of first electrical routing layer contact elements 13 and a plurality of second electrical routing layer contact elements 14 on a first side 11 of the routing layer 10; and a plurality of third electrical routing layer contact elements 15 on a second side 12 of the routing layer 10 opposite the first side 11.
  • the semiconductor package further includes a first semiconductor die 20 having a first side 21 facing the first side 11 of the routing layer 10, and a second side 22 opposite the first side 21 of the first semiconductor die 20; a plurality of first electrical die contact elements 23 on the first side 21 of the first semiconductor die 20; and a plurality of second electrical die contact elements 24 on the first side 21 of the first semiconductor die 20.
  • the semiconductor package further includes a second semiconductor die 30 having a first side 31 facing the first side 11 of the routing layer 10, and a second side 32 opposite the first side 31 of the second semiconductor die 30; a plurality of third electrical die contact elements 33 on the first side 31 of the second semiconductor die 30; and a plurality of fourth electrical die contact elements 34 on the first side 31 of the second semiconductor die 30.
  • the semiconductor package further includes an interconnection die 40 having a first side 41, and a second side 42 opposite the first side 41; wherein a first portion 47 of the first side 41 faces at least a portion 25 of the first side 21 of the first semiconductor die 20 and a second portion 48 of the first side 41 faces at least a portion 35 of the first side 31 of the second semiconductor die 30; and wherein the second side 42 faces the first side 11 of the routing layer 10; a plurality of fifth electrical die contact elements 43 on the first portion 47 of the first side 41 of the interconnection die 40; and a plurality of sixth electrical die contact elements 44 on the second portion 48 of the first side 41 of the interconnection die 40;
  • Figure 1 shows the semiconductor packaging 1 further includes a resin encapsulation structure 50 covering at least a portion of the first semiconductor die 20, at least a portion of the second semiconductor die 30, and at least a portion of the interconnection die 40.
  • Figure 1 shows the semiconductor packaging 1 further includes one or more first resin encapsulated electrical interconnections 51 extending vertically between the plurality of first electrical routing layer contact elements 13 and the plurality of first electrical die contact elements 23 to electrically connect the routing layer 10 and the first semiconductor die 20.
  • Figure 1 shows the semiconductor packaging 1 further includes one or more second resin encapsulated electrical interconnections 52 extending vertically between the plurality of second electrical routing layer contact elements 14 and the plurality of third electrical die contact elements 33 to electrically connect the routing layer 10 and the second semiconductor die 30;
  • one or more third resin encapsulated electrical interconnections 53 extending vertically between the plurality of second electrical die contact elements 24 and the plurality of fifth electrical die contact elements 43 to electrically connect the interconnection die 40 and the first semiconductor die 20; and one or more fourth resin encapsulated electrical interconnections 54 extending vertically between the plurality of fourth electrical die contact elements 34 and the plurality of sixth electrical die contact elements 44 to electrically connect the interconnection die 40 and the second semiconductor die 30.
  • figure 1 shows that the routing layer 10 includes one or more electrically conductive routing layer interconnections 17 electrically coupling one or more of the plurality of third electrical routing layer contact elements 15 with the first electrical routing layer contact elements 13, and one or more of the plurality of third electrical routing layer contact elements 15 with the second electrical routing layer contact elements 14.
  • the interconnection die 40 includes one or more electrically conductive interconnection die interconnections 46 electrically connecting the plurality of fifth electrical die contact elements 43 and the plurality of sixth electrical die contact elements 44.
  • the semiconductor structure 01 includes a plurality of seventh electrical die contact elements 45 on the second side 42 of the interconnection die 40, and a plurality of fourth electrical routing layer contact elements 16 on the first side 11 of the routing layer 10.
  • a plurality of seventh electrical die contact elements 45 on the second side 42 of the interconnection die 40 and a plurality of fourth electrical routing layer contact elements 16 on the first side 11 of the routing layer 10.
  • the semiconductor structure 01 includes one or more backside interconnections 60 extending between the plurality of fourth electrical routing layer contact elements 16 and the plurality of seventh electrical die contact elements 45 to electrically connect the interconnection die 40 and the routing layer 10.
  • backside interconnections 60 extending between the plurality of fourth electrical routing layer contact elements 16 and the plurality of seventh electrical die contact elements 45 to electrically connect the interconnection die 40 and the routing layer 10.
  • the plurality of first electrical routing layer contact elements 13, the plurality of second electrical routing layer contact elements 14, and the plurality of fourth electrical routing layer contact elements 16 are substantially along a common plane 61.
  • the interconnection die 40 is an embedded fine-pitch interconnect (EFI) die.
  • EFI embedded fine-pitch interconnect
  • the EFI includes single or multiple metal layers on a front side of a Si substrate.
  • the metal layers can be fabricated by standard BEOL (backend of line) process which is commonly used for most advanced CMOS devices. This allows to make interconnects with fine line and space (L/S) pitch less than 1 micrometer or even below. Through silicon vias (TSV) are not required.
  • the interconnection die 40 includes an active device.
  • the invention also provides a semiconductor package containing embedded fine- pitch interconnect(s) (EFI), and/or active devices, attached to two dies as a bridge.
  • EFI embedded fine- pitch interconnect
  • the interconnection die 40 includes a silicon substrate 49.
  • each of the one or more first resin encapsulated electrical interconnections 51 or each of the one or more second resin encapsulated electrical interconnections 52 is longer than each of the one or more third resin encapsulated electrical interconnections 43 or each of the one or more fourth resin encapsulated electrical interconnections 54.
  • the interconnection die 40 is between the routing layer 10 and a plane including a lateral arrangement including the first semiconductor die 20 and the second semiconductor die 30.
  • the plurality of first electrical die contact elements 23 and the plurality of third electrical die contact elements 33 are along a first plane 63; and wherein the plurality of second electrical die contact elements 24 and the plurality of fourth electrical die contact elements 34 are along a second plane 64.
  • the first plane 63 and the second plane 64 are preferably each independently lower than plane 61. Such planes can be seen, for example, in figure 8.
  • a minimum pitch of the one or more electrically conductive routing layer interconnections 17 is equal or less than 5 micrometer / 5 micrometer line/space (L/S). It means that the minimum distance between two lines can be less than 5 micrometers, it also means that the width of a line can be less than 5 micrometers.
  • FIG. 2 shows a schematic illustrating the semiconductor package 01 according to figure 1 attached to a PCB 03. It is shown that third electrical routing layer contact elements 15 of the routing layer 10 are electrically connected to the PCB 70 via solder bumps 66.
  • the solder bumps 66 are e.g. placed on the second side 12 of the routing layer 10 before placing the semiconductor package 01 on the PCB 70.
  • FIG. 3 shows a schematic illustrating another semiconductor package 01 according to various embodiments. It is shown a semiconductor package 01 on a PCB 70.
  • the semiconductor package 01 includes a first semiconductor die 20 and a second semiconductor die 30.
  • the first and second semiconductor dies are each electrically connected to the routing layer 10, and also electrically connected to each other via the interconnection die 40.
  • the package 01 of figure 3 further includes a third semiconductor die 68 and a fourth semiconductor die 69. These third and fourth semiconductor dies can arranged and electrically connected in analogous manner as described for the first semiconductor die and the second semiconductor die throughout of the invention.
  • the third semiconductor die may be a further first semiconductor die.
  • the fourth semiconductor die may be a further second semiconductor die.
  • a further interconnection die 67 can be arranged and function in an analogous manner as described for the interconnection die 40 throughout of the invention.
  • Figure 3 shows in an exemplary manner, that the third semiconductor die is electrically connected to the routing layer 10.
  • Figure 3 also shows in exemplary manner, that the second semiconductor die 30 and the fourth semiconductor die 69 are electrically connected to each other via the further interconnection die 67.
  • the skilled in the art would understand that the appropriate electrical contact elements and resin encapsulated electrical interconnections are provided for such arrangement.
  • connections 71-76 With the use of the interconnection dies and the routing layer, it is possible to provide for various different electrical paths, as exemplary shown by connections 71-76.
  • connections For 71-76, the term “connections" is meant that the end points communicate electronically via such connections.
  • connections are selected from: semiconductor die to PCB (71, 72, 73), semiconductor die to semiconductor die (74), interconnection die to interconnection die (75), interconnection die to semiconductor die (76), interconnection die to PCB (77), and combinations thereof. [054] Examples of purpose for such connections are:
  • the semiconductor package and the method of fabricating the same according to figure 3 has a greater flexibility on electrical routing and provides many possible electrical connections which utmost important in multi-die system design.
  • the invention also concerns a method for forming a semiconductor package.
  • Figure 4 shows a flow diagram illustrating a method for forming a semiconductor package.
  • the method includes the processes as explained in the following.
  • the method includes providing a first semiconductor die 20 having a first side 21, and a second side 22 opposite the first side 21; the first semiconductor die 20 including a plurality of first electrical die contact elements 23 on the first side 21, and a plurality of second electrical die contact elements 24 on the first side 21.
  • the method also includes providing a second semiconductor die 30 having a first side 31, and a second side 32 opposite the first side 31; the second semiconductor die 30 including a plurality of third electrical die contact elements 33 on the first side 31, and a plurality of fourth electrical die contact elements 34 on the first side 31.
  • interconnection die 40 can be provided with the required configuration, for example it can be pre-fabricated and stored, or it can be formed in the same manufacturing site to then be provided in the semiconductor package 01.
  • the method also includes providing an interconnection die 40 having a first side 41, and a second side 42 opposite the first side 41, and wherein the interconnection die 40 further includes a plurality of fifth electrical die contact elements 43 on the first portion 47 of the first side 41 ; and a plurality of sixth electrical die contact elements 44 on the second portion 48 of the first side 41; and wherein the interconnection die 40 further includes one or more electrically conductive interconnection die interconnections 46 electrically connecting the plurality of fifth electrical die contact elements 43 and the plurality of sixth electrical die contact elements 44; wherein a first portion 47 of the first side 41 faces at least a portion 25 of the first side 21 of the first semiconductor die 20 and a second portion 48 of the first side 41 faces at least a portion 35 of the first side 31 of the second semiconductor die 30.
  • the method also includes forming one or more first resin encapsulated electrical interconnections 51 extending from the plurality of first electrical die contact elements 23.
  • the method also includes forming one or more second resin encapsulated electrical interconnections 52 extending from the plurality of third electrical die contact elements 33.
  • the method also includes forming one or more third resin encapsulated electrical interconnections 53 extending vertically between the plurality of second electrical die contact elements 24 and the plurality of fifth electrical die contact elements 43 to electrically connect the interconnection die 40 and the first semiconductor die 20; and forming one or more fourth resin encapsulated electrical interconnections 54 extending vertically between the plurality of fourth electrical die contact elements 34 and the plurality of sixth electrical die contact elements 44 to electrically connect the interconnection die 40 and the second semiconductor die 30;
  • the method also includes forming a resin encapsulation structure 50 covering at least a portion of the first semiconductor die 20, at least a portion of the second semiconductor die 30, and at least a portion of the interconnection die 40.
  • the method includes forming a routing layer including one or more dielectric materials, a plurality of first electrical routing layer contact elements 13 and a plurality of second electrical routing layer contact elements 14 on a first side 11 of the routing layer 10, and a plurality of third electrical routing layer contact elements 15 on a second side 12 of the routing layer 10 opposite the first side 11.
  • the routing layer 10 is formed so that the first side 11 faces the first side 21 of the first semiconductor die 20, and so that the first side of the routing layer 10 faces the first side 31 of the second semiconductor die 30, and further so that the first side 11 of the routing layer 10 faces the second side 42 of the interconnection die 40.
  • routing layer is formed so to be arranged in relation to the plurality of first electrical die contact elements 23 of the first semiconductor die 20 to electrically connect the routing layer 10 and the first semiconductor die 20, and in relation to the plurality of third electrical die contact elements 33 of the second semiconductor die 30 to electrically connect the routing layer 10 and the second semiconductor die 30.
  • the routing layer includes one or more electrically conductive routing layer interconnections 17 electrically coupling one or more of the plurality of third electrical routing layer contact elements 15 with the first electrical routing layer contact elements 13. and one or more of the plurality of third electrical routing layer contact elements 15 with the second electrical routing layer contact elements 14;
  • the routing layer 10 is fabricated over the grinded resin layer.
  • the routing layer 10 may be formed by forming a plurality of metallization layers 17 separated by dielectric layers.
  • the plurality of metallization layers 17 are e.g. patterned into conductive traces that are vertically connected by vertical interconnections, such as through mold vias, Cu or Au pillars, Cu or Au wires.
  • An exemplary pitch of a metal layer segment of the plurality of metallization layers segment could be 6um
  • the first side 21 of the first semiconductor 20 and the first side 31 of the second semiconductor die are e.g. coplanar. Additionally, the second side 22 of the first semiconductor 20 and the second side 32 of the second semiconductor die are e.g. coplanar. [072] In various embodiments, the one or more first resin encapsulated electrical interconnections 51 and the one or more second resin encapsulated electrical interconnections 52 are e.g. selected from at least one of stud bumps or through any other mold interconnects.
  • Through mold interconnects - can be any other suitable means of electrical connection, such as stud bumping by wire bonder, solder balls, Cu pillars by electroplating, laser drilled through mold vias with metallization by electroplating etc.
  • first semiconductor die 20 and the second semiconductor die 30 are provided on a carrier 70 and the second side of the first semiconductor die 20 and the second side of the second semiconductor die 30 face the carrier. In various embodiments, it is preferred that the first semiconductor die 20 and the second semiconductor die 30 are provided on a carrier 70 before, the one or more first resin encapsulated electrical interconnections 51 are formed on the first semiconductor die 20 and the one or more second resin encapsulated electrical interconnections 52 are formed on the second semiconductor die 30.
  • the semiconductor structure e.g. includes at least one further first semiconductor die, at least one further second semiconductor die and at least one further interconnection die.
  • the forming the resin encapsulation structure 50 e.g. include depositing a mold compound material, and back grinding the encapsulation material to expose one or more first resin encapsulated electrical interconnections 51, and one or more second resin encapsulated electrical interconnections 52. Additionally, in various embodiments, the forming the resin encapsulation structure 50 e.g. includes depositing a mold compound material, and back grinding the encapsulation material to expose the second side 42 of the interconnection die 40.
  • the method e.g. further includes forming a plurality of seventh electrical die contact elements 45 on the second side 42 of the interconnection die 40 before forming the routing layer 10, and forming one or more backside interconnections on the plurality of seventh electrical die contact elements. Additionally, the method e.g. includes forming a plurality of fourth electrical routing layer contact elements 16 on the first side 11 of the routing layer 10 to connect the one or more backside interconnections.
  • FIG. 5A and 5B is a schematic illustrating a method of forming a semiconductor packaging according to various embodiments.
  • a (not shown) the first semiconductor die 20 and the second semiconductor die 30 are provided.
  • a first semiconductor die 20 with a first side 21 and a second side 22 is provided, wherein the first side includes first electrical die contact elements 23 and second electrical die contact elements 24.
  • the second electrical die contact elements 24 are comprised on portion 25 of the first side 21.
  • a second semiconductor die 30 with a first side 301 and a second side 32 is provided, wherein the first side includes third electrical die contact elements 33 and fourth electrical die contact elements 34.
  • the fourth electrical die contact elements 34 are comprised on portion 35 of the first side 31.
  • the first resin encapsulated electrical interconnections 51 are provided on first side
  • the interconnections 51 and 52 can be fabricated on the dies 20 and 30 or the dies can be provided with the finished interconnections.
  • the second side 22 of the second semiconductor die 20 and the second side 32 of the second semiconductor die 30 are attached to the same side of the carrier 70.
  • a portion 35 of the first side 31 of the second semiconductor die 30 includes fourth electrical die contact elements 34.
  • a portion 25 of the first side 21 of the second semiconductor die 22 includes second electrical die contact elements 24.
  • an interconnection die 40 with a first side 41 and a second side 42 is provided wherein the first side 41 is facing the portion 35 of the first side 31 of the second semiconductor die 30 and the portion 25 of the first side 21 of the second semiconductor die 22.
  • the first side 41 of the interconnection die 40 includes a first portion 47 including fifth electrical die contact elements 43, and a second portion 48 including the sixth electrical die contact elements 44.
  • the second electrical die contact elements 24 on the first side 21 of the first semiconductor die 20 are electrically contacted to the fifth electrical die contact elements 43 on the first portion 47 of the first side 41 of the interconnection die 40 e.g. by the third resin encapsulated electrical interconnections 53.
  • the fourth electrical die contact elements 34 on the first side 31 of the second semiconductor die 32 are electrically connected to the sixth electrical die contact elements 44 on the second portion 48 of the first side 41 of the interconnection die 40 e.g. by the fourth resin encapsulated electrical interconnections 54.
  • the third resin encapsulated electrical interconnections 53 are solder bumps.
  • the fourth resin encapsulated electrical interconnections 54 are solder bumps.
  • the electrical connection for example solder joints, can be performed at the same time of positioning the die, or at a later stage, preferably by solder reflow, but is performed, e.g. before the encapsulation step 5.d.
  • a resin layer 55 is formed covering at least a portion of the first die 20, the second die 30, and the interconnection die 40, e.g. encapsulating the first die 20, the second die 30, and the interconnection die 40 into an intermediate product.
  • a preferred method for the encapsulation is molding. In this process, the resin encapsulated electrical interconnections, e.g. first 51, second 52, are encapsulated, hence the name "encapsulated” electrical interconnections as used throughout this specification.
  • the overmold of the resin layer 55 is partially removed, for example by grinding so as to expose part of the first resin encapsulated electrical interconnections 51 and part of the second resin encapsulated electrical interconnections 52, so that these can be electrically connected in the next processes.
  • the term "overmold” means an excess of resin that is not required in the final product, and is only available in the intermediate product of 5.d (or equivalent process in other embodiments), and removed in 5.e (or equivalent process in other embodiments).
  • the routing layer includes redistribution layers (RDLs), the redistribution layers have a fine L/S as low as ⁇ 2micrometers. Such fine-pitch RDL cannot be fabricated on conventional organic substrate.
  • this invention can achieve low-cost assembly process for 2.5D/3D package, since organic substrate underfill and through-silicon vias are not necessary at this side of the semiconductor package.
  • the routing layer 10 is formed.
  • the routing layer 10 includes a first side 11 and a second side 12 opposite the first side 11.
  • the routing layer 10 is formed to include first electrical routing layer contact elements 13 on the first side 12 of the routing layer 10 and a second electrical routing layer contact elements 14 on the first side 12 of the routing layer 10.
  • the routing layer 10 is formed to further include third electrical routing layer contact elements 15 on the second side 12.
  • the routing layer 10 further includes routing-layer interconnections 17 electrically coupling of the of third electrical routing layer contact elements 15 with the first electrical routing layer contact elements 13 contact elements, and one or more of the third electrical routing layer contact elements 15 with the second electrical routing layer contact elements 14.
  • the routing layer 10 may be formed by forming a plurality of metallization layers 17 separated by dielectric layers.
  • the plurality of metallization layers 17 are e.g. patterned into conductive traces that are vertically connected by vertical interconnections, such as through mold vias, Cu or Au pillars, Cu or Au wires.
  • An exemplary pitch of a metal layer segment of the plurality of metallization layers segment could be 6 micrometers.
  • solder bumps 66 are placed on the third electrical routing layer contact elements 15.
  • the carrier 70 may be removed before or after, e.g. after, placing the solder bumps.
  • FIG. 6A and 6B is a schematic illustrating a method of forming a semiconductor packaging according to various embodiments.
  • a first semiconductor die 20 with a first side 21 and a second side 22 is provided, wherein the first side includes first electrical die contact elements 23 and second electrical die contact elements 24.
  • the second electrical die contact elements 24 are comprised on portion 25 of the first side 21.
  • a second semiconductor die 30 with a first side 301 and a second side 32 is provided, wherein the first side includes third electrical die contact elements 33 and fourth electrical die contact elements 34.
  • the fourth electrical die contact elements 34 are comprised on portion 35 of the first side 31.
  • the first resin encapsulated electrical interconnections 51 are fabricated on first side 21 of the first semiconductor die 20 and the second resin encapsulated electrical interconnections 51 and 52 are fabricated on the first side 31 of the second semiconductor die 30.
  • the interconnections 51 and 52 are made after the first semiconductor die 20 and the second semiconductor die 30 are attached to carrier 70.
  • a portion 35 of the first side 31 of the second semiconductor die 30 includes fourth electrical die contact elements 34.
  • a portion 25 of the first side 21 of the second semiconductor die 22 includes second electrical die contact elements 24.
  • the interconnections 51 and 52 are not formed on these portions 35 and 34. These portions will be needed in a following process for other connections.
  • an interconnection die 40 with a first side 41 and a second side 42 is provided wherein the first side 41 is facing the portion 35 of the first side 31 of the second semiconductor die 30 and the portion 25 of the first side 21 of the second semiconductor die 22.
  • the first side 41 of the interconnection die 40 includes a first portion 47 including fifth electrical die contact elements 43, and a second portion 48 including the sixth electrical die contact elements 44.
  • the second electrical die contact elements 24 on the first side 21 of the first semiconductor die 20 are electrically contacted to the fifth electrical die contact elements 43 on the first portion 47 of the first side 41 of the interconnection die 40 e.g. by the third resin encapsulated electrical interconnections 53.
  • the fourth electrical die contact elements 34 on the first side 31 of the second semiconductor die 32 are electrically connected to the sixth electrical die contact elements 44 on the second portion 48 of the first side 41 of the interconnection die 40 e.g. by the fourth resin encapsulated electrical interconnections 54.
  • the third resin encapsulated electrical interconnections 53 are solder bumps.
  • the fourth resin encapsulated electrical interconnections 54 are solder bumps.
  • the electrical connection for example solder joints, can be performed at the same time of positioning the die, or at a later stage, preferably by solder reflow, but is performed, e.g. before the encapsulation step 5.d.
  • a resin layer 55 is formed covering at least a portion of the first die 20, the second die 30, and the interconnection die 40, e.g. encapsulating the first die 20, the second die 30, and the interconnection die 40 into an intermediate product.
  • a preferred method for the encapsulation is molding.
  • the overmold of the resin layer 55 is partially removed, for example by grinding, so as to expose part of the first resin encapsulated electrical interconnections 51 and part of the second resin encapsulated electrical interconnections 52, so that these can be electrically connected in the next processes.
  • the routing layer includes redistribution layers (RDLs), the redistribution layers have a fine L/S as low as ⁇ 2micrometers. Such fine-pitch RDL cannot be fabricated on conventional organic substrate.
  • this invention can achieve low-cost assembly process for 2.5D/3D package, since organic substrate underfill and through-silicon vias are not necessary at this side of the semiconductor package.
  • the resin also provides advantages such as environmental protection for ten embedded interconnection die 40, the fourth resin encapsulated electrical interconnections 54 between sixth electrical die contact elements 44 and fourth electrical die contact elements 34, and the third resin encapsulated electrical interconnections 53 between fifth electrical die contact elements 43 and second electrical die contact elements 24.
  • the routing layer 10 is formed.
  • the routing layer 10 includes a first side 11 and a second side 12 opposite the first side 11.
  • the routing layer 10 is formed to include first electrical routing layer contact elements 13 on the first side 12 of the routing layer 10 and a second electrical routing layer contact elements 14 on the first side 12 of the routing layer 10.
  • the routing layer 10 is formed to further include third electrical routing layer contact elements 15 on the second side 12.
  • the routing layer 10 further includes routing-layer interconnections 17 electrically coupling of the of third electrical routing layer contact elements 15 with the first electrical routing layer contact elements 13 contact elements, and one or more of the third electrical routing layer contact elements 15 with the second electrical routing layer contact elements 14.
  • the routing layer 10 may be formed by forming a plurality of metallization layers 17 separated by dielectric layers.
  • the plurality of metallization layers 17 are e.g. patterned into conductive traces that are vertically connected by vertical interconnections, such as through mold vias, Cu or Au pillars, Cu or Au wires.
  • An exemplary pitch of a metal layer segment of the plurality of metallization layers segment could be 6 micrometers.
  • solder bumps 66 are placed on the third electrical routing layer contact elements 15.
  • the carrier 70 may be removed before or after, e.g. after, placing the solder bumps.
  • FIG. 7A and 7B is a schematic illustrating a method of forming a semiconductor packaging according to various embodiments.
  • a first semiconductor die 20 with a first side 21 and a second side 22 is provided, wherein the first side includes first electrical die contact elements 23 and second electrical die contact elements 24.
  • the second electrical die contact elements 24 are comprised on portion 25 of the first side 21.
  • a second semiconductor die 30 with a first side 301 and a second side 32 is provided, wherein the first side includes third electrical die contact elements 33 and fourth electrical die contact elements 34.
  • the fourth electrical die contact elements 34 are comprised on portion 35 of the first side 31.
  • the first resin encapsulated electrical interconnections 51 are fabricated on first side 21 of the first semiconductor die 20 and the second resin encapsulated electrical interconnections 51 and 52 are fabricated on the first side 31 of the second semiconductor die 30.
  • the interconnections 51 and 52 are made after the first semiconductor die 20 and the second semiconductor die 30 are attached to carrier 70.
  • a portion 35 of the first side 31 of the second semiconductor die 30 includes fourth electrical die contaet elements 34.
  • a portion 25 of the first side 21 of the second semiconductor die 22 includes second electrical die contact elements 24.
  • the interconnections 51 and 52 are not formed on these portions 35 and 34. These portions will be needed in a following process for other connections.
  • an interconnection die 40 with a first side 41 and a second side 42 is provided wherein the first side 41 is facing the portion 35 of the first side 31 of the second semiconductor die 30 and the portion 25 of the first side 21 of the second semiconductor die 22.
  • the first side 41 of the interconnection die 40 includes a first portion 47 including fifth electrical die contact elements 43, and a second portion 48 including the sixth electrical die contact elements 44.
  • the second electrical die contact elements 24 on the first side 21 of the first semiconductor die 20 are electrically contacted to the fifth electrical die contact elements 43 on the first portion 47 of the first side 41 of the interconnection die 40 e.g. by the third resin encapsulated electrical interconnections 53.
  • any, including the interconnection die 40 is e.g. made on s substrate 49, which is e.g. Si. e.g. the interconnection die is attached to the semiconductor dies (20, 30, or other) with the substrate facing away from the semiconductor dies.
  • the fourth electrical die contact elements 34 on the first side 31 of the second semiconductor die 32 are electrically connected to the sixth electrical die contact elements 44 on the second portion 48 of the first side 41 of the interconnection die 40 e.g. by the fourth resin encapsulated electrical interconnections 54.
  • the third resin encapsulated electrical interconnections 53 are solder bumps.
  • the fourth resin encapsulated electrical interconnections 54 are solder bumps.
  • the electrical connection for example solder joints, can be performed at the same time of positioning the die, or at a later stage, preferably by solder reflow, but is performed, e.g. before the encapsulation step 5.d.
  • a resin layer 55 is formed covering at least a portion of the first die 20, the second die 30, and the interconnection die 40, e.g. encapsulating the first die 20, the second die 30, and the interconnection die 40 into an intermediate product.
  • a preferred method for the encapsulation is molding.
  • the overmold of the resin layer 55 is partially removed, for example by grinding.
  • removing part of the resin layer has at least two functions. One function is to expose part of the first resin encapsulated electrical interconnections 51 and part of the second resin encapsulated electrical interconnections 52, so that these can be electrically connected in the next processes. Another function is to expose the substrate 49 of the interconnection die 40.
  • the substrate After exposing the substrate 49 of the interconnection die 40, the substrate may be completely etched away, thus exposing the second side 42 of the interconnection die 40 and the seventh electrical die contact elements 45 on the second side 42 of the interconnection die 40.
  • This enables additional connection paths through the interconnection die 40 (or another interconnection die) resulting design flexibility.
  • Part of I/Os and/or power & ground from the first semiconductor die 20 can be connected via interconnection die 40 (or another respective interconnection die).
  • backside interconnections 60 are provided, extending from the seventh electrical die contact elements 45 for contacting with the fourth electrical routing layer contact elements 16 to electrically connect the interconnection die 40 and the routing layer 10, when the routing layer 10 is formed.
  • the routing layer 10 is formed.
  • the routing layer 10 includes a first side 11 and a second side 12 opposite the first side 11.
  • the routing layer 10 is formed to include first electrical routing layer contact elements 13 on the first side 12 of the routing layer 10 and a second electrical routing layer contact elements 14 on the first side 12 of the routing layer 10.
  • the routing layer 10 is formed to further include third electrical routing layer contact elements 15 on the second side 12.
  • the routing layer 10 further includes routing-layer interconnections 17 electrically coupling the of third electrical routing layer contact elements 15 with the first electrical routing layer contact elements 13, and one or more of the third electrical routing layer contact elements 15 with the second electrical routing layer contact elements 14.
  • the routing layer 10 includes fourth electrical routing layer contact elements 16, and the routing-layer interconnections 17 electrically couple the electrical routing layer contact elements 16 with the third electrical routing layer contact elements 15, the first electrical routing layer contact elements 13, and/or the second electrical routing layer contact elements 14.
  • the routing layer 10 may be formed by forming a plurality of metallization layers 17 separated by dielectric layers.
  • the plurality of metallization layers 17 are e.g. patterned into conductive traces that are vertically connected by vertical interconnections, such as through mold vias, Cu or Au pillars, Cu or Au wires.
  • An exemplary pitch of a metal layer segment of the plurality of metallization layers segment could be 6 micrometers.
  • solder bumps 66 are formed on placed on the third electrical routing layer contact elements 15.
  • the carrier 70 may be removed before or after, e.g. after, placing the solder bumps.
  • the method of figure 7A can be further modified by replacing 7.a and 7.b by 5.b of figure 5 A, thus wherein the first semiconductor die 20 and the second semiconductor die 30 are provided with the electrical interconnections 51, instead of fabricating the electrical interconnections 51 on the first semiconductor die 20 and the second semiconductor die 30 after their attachment to the substrate.
  • the substrate 49 of the interconnection die 40 is removed, e.g. by etching). This reduces the overall thickness of the semiconductor package, in particular the thickness of the interconnection die. It is therefore possible to use resin encapsulated electrical interconnections (such as first resin encapsulated electrical interconnections 51, and second resin encapsulated electrical interconnections 52) with less height, e.g. the resin encapsulated electrical interconnections have a height of below 50 micrometers. Additionally or alternative, the resin encapsulated electrical interconnections are metal pillars including mainly Cu. Such are especially suitable for high I/O counts more than 1000 pins for example.
  • the term semiconductor die has the common meaning in the art.
  • the first semiconductor e.g. die includes a processing using, such as a central processing unit (CPU) or a graphic processing unit (GPU), and the second semiconductor die e.g. includes a memory.
  • the second semiconductor die e.g. includes a memory.
  • HBM high band width
  • memory herein means that a die that includes the storage circuit and e.g. includes the auxiliary circuit such as the memory controller on the same die.
  • the present invention is especially advantageous for semiconductor die(s) that require high density inter-chip connections, such as HBM, which requires high density inter-chip connections between CPU/GPU and HBM of over 1000 lines per several millimeters.
  • the present invention enables this high density inter-chip connections without using expensive additional components such as Si interposer with TSVs.
  • the material of the carrier 70 is e.g. selected from Si, glass or ceramics.
  • the any of the semiconductor dies, at least the first die 20 and the second die 30, are e.g. attached to the carrier with an adhesive material, such as a die attach film.
  • connection pitch can be reduced such as ⁇ 50micrometer range, providing much higher connection density as compared with boding on to organic substrate.
  • connection die refers to a die, including a substrate, which substrate includes single or multiple metal layers on at least one side of the substrate.
  • the die is preferably a Si die and the substrate a Si substrate.
  • the interconnection die(s) is(are) e.g. an embedded fine-pitch interconnect (EFI).
  • EFI embedded fine-pitch interconnect
  • the metal layers can be fabricated by standard BEOL (backend of line) process which is commonly used for most advanced CMOS devices. This allows to make interconnects with fine line and space (L/S) pitch less than 1 micrometer or even below. Through silicon vias (TSV) are not required.
  • the encapsulated electrical interconnections are e.g. through mold interconnections (TMIs).
  • the interconnections 51 and 52 are stud bumps, e.g. including mainly: Cu, Au, Al, or a suitable combination thereof.
  • the interconnections 51 and 52 are metal pillars, such as Cu-pillars. Such pillars can have a high aspect ratio and fine-pitch. This also applies to other interconnections in semiconductor packages having additional semiconductor dies according to the invention.
  • solder dots are provided on the metallized contact elements of the interconnection die, the die 40 is positioned so that the solder dots face the electrical contacts of the dies 20 and 30. Thereafter the solder dots are remelted, joining the electrical contacts of the die 40 with die 20 or 30.
  • sixth electrical die contact elements on the second portion of the first side of the interconnection die

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Abstract

Divers modes de réalisation concernent un boîtier à semi-conducteur comprenant une couche de routage, une première matrice de semi-conducteur, une seconde matrice de semi-conducteur, une matrice d'interconnexion. La matrice d'interconnexion comprend une ou plusieurs interconnexions de matrices d'interconnexion électriquement conductrices connectant électriquement une pluralité d'éléments de contact de matrices électriques de la première matrice et une pluralité d'éléments de contact de matrices électriques de la seconde matrice. La couche de routage comprend une ou plusieurs interconnexions de couche de routage électriquement conductrices couplant électriquement des éléments de contact de la première matrice de semi-conducteur à la couche de routage, et des éléments de contact de la seconde matrice de semi-conducteur à la couche de routage. La couche de routage comprend en outre des éléments de contact sur sa face arrière, qui sont appropriés pour être mis en contact avec une carte de circuit imprimé. Divers modes de réalisation de l'invention concernent également un procédé de production d'un tel boîtier de semi-conducteur.
PCT/SG2017/050317 2016-07-08 2017-06-28 Boîtier à semi-conducteur et procédés de formation de celui-ci WO2018009145A1 (fr)

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SG10201605613S 2016-07-08

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EP3696852A1 (fr) * 2019-02-12 2020-08-19 INTEL Corporation Première architecture de micropuces pour des applications de pavage de puce
US11114410B2 (en) 2019-11-27 2021-09-07 International Business Machines Corporation Multi-chip package structures formed by joining chips to pre-positioned chip interconnect bridge devices
US11164817B2 (en) 2019-11-01 2021-11-02 International Business Machines Corporation Multi-chip package structures with discrete redistribution layers
EP3803973A4 (fr) * 2018-06-04 2022-06-29 Intel Corporation Encapsulation multi-puce
EP4325565A3 (fr) * 2020-12-22 2024-07-03 INTEL Corporation Assemblage de module 2xd utilisant des ponts d'interconnexion à haute densité

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