WO2018006686A1 - Procédé, appareil et dispositif pour optimiser la synchronisation temporelle entre des dispositifs de réseau de communication - Google Patents

Procédé, appareil et dispositif pour optimiser la synchronisation temporelle entre des dispositifs de réseau de communication Download PDF

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Publication number
WO2018006686A1
WO2018006686A1 PCT/CN2017/087862 CN2017087862W WO2018006686A1 WO 2018006686 A1 WO2018006686 A1 WO 2018006686A1 CN 2017087862 W CN2017087862 W CN 2017087862W WO 2018006686 A1 WO2018006686 A1 WO 2018006686A1
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Prior art keywords
line card
packet
time
message
processing chip
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PCT/CN2017/087862
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English (en)
Chinese (zh)
Inventor
蒋海辉
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中兴通讯股份有限公司
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Publication of WO2018006686A1 publication Critical patent/WO2018006686A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements

Definitions

  • the present disclosure relates to the field of network communication technologies, and in particular, to a method, an apparatus, and a device for optimizing time synchronization between communication network devices.
  • PTP Precision Time Protocol
  • PTP Precision Time Protocol
  • the master clock periodically issues the PTP time synchronization protocol and time information, and receives the timestamp information sent by the master clock port from the clock port, and the system calculates the time delay of the master-slave line and the master-slave time difference, and The time difference is used to adjust the local time so that the slave time is kept at the same frequency and phase as the master time.
  • the delay may occur due to the transmission of the signal on the line, and the device may not be able to measure the delay of the line, and the delay compensation needs to be manually performed.
  • the device needs to support the delay compensation function of various interfaces.
  • the device needs to support the automatic tracking of the standby time source when the primary time source fails.
  • the device needs to support tracking the time source from different line directions, and can automatically switch to other directions when the current tracking direction fails. For example, 16 device switching requires a phase jitter requirement of less than +/- 200 ns.
  • the technical problem to be solved by the present disclosure is to provide a method, a device and a device for optimizing time synchronization between communication network devices, which are used to solve the problem that the device cannot meet the delay jitter requirement of time synchronization switching in a complex networking environment in the related art. .
  • an embodiment of the present disclosure provides a method for optimizing time synchronization between communication network devices, which is applied to a first device, including:
  • the second time difference compensation value is a time difference compensation value that is transmitted from the line card port of the second device to the line card processing chip, where the second message added in the second message is sent;
  • the third time difference compensation value is the line card processing chip added from the second device in the response message fed back after the second control device obtains the second message by the second device.
  • the time difference offset value transmitted to the line card port is the line card processing chip added from the second device in the response message fed back after the second control device obtains the second message by the second device.
  • the first time information includes: a first timestamp of the main control board and a first physical clock frequency when the first packet for frequency synchronization is created on the main control board of the first device;
  • the third physical clock of the line card processing chip is recorded a second timestamp and a fourth physical clock frequency of the main control board when the second message is transmitted from the line card processing chip of the second device to the main control board of the second device;
  • the third message is also recorded in the third time of the main control board when the main control board of the second device creates the response message generated by the second message on the main control board.
  • a fifth physical clock frequency when the response message is transmitted from the main control board of the second device to the line card processing chip of the second device, the line card processes the sixth physical clock frequency of the chip;
  • the fourth message is further recorded when the third message is transmitted from the line card port of the first device to the line card processing chip of the first device, and the seventh physical clock of the line card processing chip a frequency; a fourth timestamp of the main control board and an eighth physical clock frequency when the fourth message is transmitted from the line card processing chip to the main control board of the first device.
  • the step of calculating a delay time of packet transmission between the first device and the second device according to the fourth packet includes:
  • the two-time difference compensation value, the third time difference compensation value, and the fourth time difference compensation value are calculated by a preset algorithm to obtain a delay time of message transmission between the first device and the second device.
  • the step of calculating the delay time of the message transmission between the first device and the second device by using a preset algorithm includes: a compensation value, a second time difference compensation value, a third time difference compensation value, and a fourth time difference compensation value; :
  • Delay [((T 4 -N 4 -t 4 )-(T 1 +N 1 +t 1 ))+((T 3 +N 3 +t 3 )-(T 2 -N 2 -t 2 ))] ⁇ 2, calculating a delay time of message transmission between the first device and the second device;
  • Delay represents a delay time for the message to be transmitted between the first device and the second device; T 1 is represented as the first timestamp; and T 2 is represented as the second timestamp ; T 3 is represented as a third time stamp; T 4 represents said fourth time stamp; N 1 is expressed as the first transmission time; N 2 of the second transmission time is represented; N 3 is represented by a third transmission time; N 4 is represented as the fourth transmission time; t 1 is represented as the first time difference compensation value; t 2 is represented as the second time difference compensation value; t 3 is represented as the third time difference The compensation value; t 4 is expressed as the fourth time difference compensation value.
  • the embodiment of the present disclosure further provides an apparatus for optimizing time synchronization between communication network devices, including:
  • a first acquiring module configured to acquire a first packet that is transmitted by the main control board of the first device to the second device, where the first packet is recorded with the first time information when the first packet is created;
  • the first processing module is configured to add, in the first packet, a first time difference compensation value that is sent from the line card processing chip of the first device to the line card port, to obtain a second message;
  • a sending module configured to send the second packet to the second device
  • a second acquiring module configured to obtain a third packet that is returned after the second device receives the second packet, where the second packet records that the second device receives the second packet a second time difference compensation value and a third time difference compensation value transmitted between the line card processing chip of the second device and the line card port;
  • a second processing module configured to add, in the third packet, a fourth time difference compensation value that is sent from the line card port of the first device to the line card processing chip, to obtain a fourth message;
  • the calculating module is configured to calculate, according to the fourth packet, a delay time for packet transmission between the first device and the second device.
  • the embodiment of the present disclosure further provides a first device, including: an apparatus for optimizing time synchronization between communication network devices as described in the foregoing embodiments.
  • the embodiment of the present disclosure further provides an optimization method for time synchronization between communication network devices, which is applied to a second device, and the method includes:
  • the first packet of the first device After the first packet of the first device is recorded in the second packet, the first packet is added to the line of the first device in the first packet.
  • the embodiment of the present disclosure further provides an apparatus for optimizing time synchronization between communication network devices, including:
  • the first receiving module is configured to receive the second packet sent by the first device
  • a third processing module configured to add, in the second packet, a second time difference compensation value that is sent from the line card port of the second device to the line card processing chip, and the second report is Transmitting to the main control board of the second device;
  • a second receiving module configured to receive a response message that is received by the main control board after obtaining the second packet
  • the fourth processing module is configured to add a third time difference compensation value that is sent from the line card processing chip of the second device to the line card port in the response message, to obtain a third message;
  • a transmission module configured to transmit the third packet to the first device by using a line card port of the second device.
  • the embodiment of the present disclosure further provides a second device, including: an apparatus for optimizing time synchronization between communication network devices as described in the foregoing embodiments.
  • the embodiment of the present disclosure further provides a storage medium, configured to store program code, where the program code is used to perform an optimization method for time synchronization between communication network devices provided by any of the above embodiments.
  • the time difference compensation value is added in the message, and the message is reduced.
  • the delay error during transmission between communication network devices can realize accurate time synchronization between communication network devices and meet the delay jitter requirements of time synchronization switching of devices in complex networking environments.
  • FIG. 1 is a flow chart showing the basic steps of a method for optimizing time synchronization between communication network devices according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a device for optimizing time synchronization between communication network devices according to an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a packet sending and receiving path of a single device
  • 4 is a schematic diagram of a packet transmission delay between devices
  • FIG. 5 is a flowchart of basic steps of a method for optimizing time synchronization between communication network devices according to an embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of another apparatus for optimizing time synchronization between communication network devices according to an embodiment of the present disclosure
  • FIG. 7 is a timing diagram of packet time delay optimization according to an embodiment of the present disclosure.
  • the present disclosure is directed to the problem that the device in the related art cannot meet the delay jitter requirement of time synchronization switching in a complex networking environment, and provides an optimization method for time synchronization between communication network devices, which reduces the transmission of packets between communication network devices.
  • the delay error enables accurate time synchronization between communication network devices and meets the delay jitter requirements of time synchronization switching of devices in complex networking environments.
  • an embodiment of the present disclosure provides a method for optimizing time synchronization between communication network devices, including:
  • Step 11 Acquire a first packet that is sent by the main control board of the first device to the second device, where the first packet is recorded with the first time information when the first packet is created.
  • the central processing unit CPU on the main control board of the first device is responsible for maintaining the 1588 state machine, running the 1588 protocol and the 1588 loop algorithm, and reading the side-mounted FPGA (Field-Programmable Gate Array). ) The timestamp of the collection.
  • the timestamp is usually a sequence of characters that uniquely identifies the time of a certain moment.
  • the counter is not time-stamped, and there is no requirement for the start time. That is, when the device is powered on, the default time issued by the timestamp counter can be uniformly used. When the frequency is restored, the clock provided by the timestamp counter is counted.
  • the 1588 protocol is an accurate time synchronization protocol.
  • Two types of packets, event packets and general messages are defined in the 1588 protocol.
  • the event packet time concept packet is marked with an accurate timestamp when it enters and exits the device port.
  • the PTP calculates the link delay based on the timestamp carried in the event packet.
  • the event message contains the following four types: Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp.
  • the first packet is an event packet.
  • the 1588 loop algorithm enables high-precision time synchronization calculations.
  • Step 12 Add a first time difference compensation value that is transmitted from the line card processing chip of the first device to the line card port in the first packet, to obtain a second packet.
  • the time difference compensation value described in the embodiment of the present disclosure can be obtained by manual compensation, and the time difference compensation value is added to the corresponding field of the message.
  • the manual compensation obtains the time difference compensation value, that is, the oscilloscope measures the transmission time of the message from the line card processing chip of the device to the line card port or from the line card port of the device to the line card processing chip, and the measured time is measured. A large amount of time data is averaged to obtain a time difference compensation value.
  • time difference compensation value can also be obtained in real time through the PTP system.
  • Step 13 the second packet is sent to the second device
  • the second message includes time information recorded in the first message.
  • the second message is sent from the line card port of the first device to the line card port of the second device.
  • Step 14 Obtain a third packet returned by the second device after receiving the second packet, where the third packet records that the second device receives the second packet, where Line card processing chip and line card end of the second device a second time difference compensation value and a third time difference compensation value transmitted between the ports;
  • the third packet includes time information recorded in the first packet and the second packet.
  • Step 15 Add a fourth time difference compensation value that is transmitted from the line card port of the first device to the line card processing chip in the third message, to obtain a fourth message;
  • the line card processing chip may be a PHY (Physical Layer) chip
  • the PHY chip generally refers to a chip that interfaces with an external signal.
  • Step 16 Calculate, according to the fourth packet, a delay time for packet transmission between the first device and the second device.
  • the fourth packet includes time information in the first packet, the second packet, and the third packet.
  • the second time difference compensation value is a time difference compensation value that is sent from the line card port of the second device to the line card processing chip, where the second message added in the second message is sent;
  • the third time difference compensation value is the line card processing chip added from the second device in the response message fed back after the second control device obtains the second message by the second device.
  • the time difference offset value transmitted to the line card port is the line card processing chip added from the second device in the response message fed back after the second control device obtains the second message by the second device.
  • the first time information includes: a first timestamp of the main control board and a first physical clock when the first message for frequency synchronization is created on the main control board of the first device frequency.
  • the third physical clock of the line card processing chip is recorded a second timestamp and a fourth physical clock frequency of the main control board when the second message is transmitted from the line card processing chip of the second device to the main control board of the second device;
  • the third message is also recorded in the third time of the main control board when the main control board of the second device creates the response message generated by the second message on the main control board.
  • a fifth physical clock frequency when the response message is transmitted from the main control board of the second device to the line card processing chip of the second device, the line card processes the sixth physical clock frequency of the chip;
  • the fourth message is further recorded when the third message is transmitted from the line card port of the first device to the line card processing chip of the first device, and the seventh physical clock of the line card processing chip a frequency; a fourth timestamp of the main control board and an eighth physical clock frequency when the fourth message is transmitted from the line card processing chip to the main control board of the first device.
  • timestamps on different devices are different because the default time of the device's timestamp counter is different. Therefore, the timestamps on different devices cannot be calculated. The time stamp of the same device can be calculated.
  • the time information of the packet passing through the internal components of the device is filled in the corresponding field of the packet. That is, the message in the embodiment of the present disclosure may have a fixed format.
  • the step 16 described in the embodiment of the present disclosure may further include:
  • Step 161 Obtain the first report according to the first physical clock frequency and the second physical clock frequency. Transmitting from the main control board of the first device to the first transfer time of the line card processing chip of the first device;
  • the second physical clock frequency of the line card processing chip of the first device is subtracted from the first physical clock frequency of the main control board of the first device, and the first packet is transmitted from the main control board of the first device to The physical clock frequency difference of the line card processing chip of the first device.
  • the jitter time of each clock frequency offset is 1/125 ms, that is, the time interval of 8 ns
  • the transmission time difference from the main control board to the line card processing chip is a CF domain difference, that is, the first message is from the first
  • the first transmission time of the main control board of the device transmitted to the line card processing chip of the first device is that the first message is transmitted from the main control board of the first device to the line card processing chip of the first device
  • the physical clock frequency difference is multiplied by the beat time of each clock offset.
  • Step 162 According to the third physical clock frequency and the fourth physical clock frequency, the second packet is transmitted from the line card processing chip of the second device to the main control board of the second device. Second transfer time;
  • the second transmission time is the difference between the fourth physical clock frequency of the line card processing chip of the second device minus the third physical clock frequency of the main control board of the second device multiplied by the frequency offset of each clock. The result of the beating time.
  • Step 163 According to the fifth physical clock frequency and the sixth physical clock frequency, obtain a third transmission of the response message from the main control board of the second device to the line card processing chip of the second device. time;
  • the third transmission time is the sixth physical clock frequency of the main control board of the second device minus the difference of the fifth physical clock frequency of the line card processing chip of the second device multiplied by the frequency offset of each clock. The result of the beating time.
  • Step 164 According to the seven physical clock frequencies and the eighth physical clock frequency, obtain the fourth packet from the line card processing chip of the first device to the fourth control panel of the first device. Transfer time
  • the fourth transmission time is the eighth physical clock frequency of the line card processing chip of the first device minus the difference of the seven physical clock frequencies of the main control board of the first device multiplied by the jitter of each clock frequency offset. The result of time.
  • Step 165 According to the first timestamp, the second timestamp, the third timestamp, the fourth timestamp, the first transmission time, the second transmission time, the third transmission time, the fourth transmission time, and the first time difference compensation
  • the value, the second time difference compensation value, the third time difference compensation value, and the fourth time difference compensation value are calculated by a preset algorithm to obtain a delay time of message transmission between the first device and the second device.
  • the step 165 may further include:
  • Delay [((T 4 -N 4 -t 4 )-(T 1 +N 1 +t 1 ))+((T 3 +N 3 +t 3 )-(T 2 -N 2 -t 2 ))] ⁇ 2, calculating a delay time of message transmission between the first device and the second device;
  • Delay represents a delay time for the message to be transmitted between the first device and the second device; T 1 is represented as the first timestamp; and T 2 is represented as the second timestamp ; T 3 is represented as the third time stamp; T 4 is represented as the fourth time stamp; N 1 is represented as the first transmission time; N 2 is represented as the second transmission time; N 3 is represented as a third transmission time; N 4 is represented as the fourth transmission time; t 1 is represented as the first time difference compensation value; t 2 is represented as the second time difference compensation value; t 3 is represented as the third time difference The compensation value; t 4 is expressed as the fourth time difference compensation value.
  • the method for optimizing time synchronization between communication network devices is used in a message when a message is transmitted from a line card processing chip of the device to a line card port or from a line card port of the device to a line card processing chip.
  • the time difference compensation value is added to reduce the delay error when the message is transmitted between the communication network devices, so that accurate time synchronization between the communication network devices can be realized, and the delay jitter requirement of the time synchronization switching of the device in the complex networking environment can be met.
  • an embodiment of the present disclosure further provides an apparatus for optimizing time synchronization between communication network devices, including:
  • the first obtaining module 21 is configured to acquire a first packet that is sent by the main control board of the first device to the second device, where the first packet is recorded with the first time information when the first packet is created. ;
  • FIG. 3 it is a schematic diagram of a packet transmission and reception path of a single device.
  • the central processing unit CPU on the main control board of the first device is responsible for maintaining the 1588 state machine, running the 1588 protocol and the 1588 loop algorithm, and reading the time stamp collected by the Field-Programmable Gate Array (Field-Programmable Gate Array). .
  • the timestamp is usually a sequence of characters that uniquely identifies the time of a certain moment.
  • the counter is not time-stamped, and there is no requirement for the start time. That is, when the device is powered on, the default time issued by the timestamp counter can be uniformly used. When the frequency is restored, the clock provided by the timestamp counter is counted.
  • the 1588 protocol is an accurate time synchronization protocol.
  • Two types of packets, event packets and general messages are defined in the 1588 protocol.
  • the event packet time concept packet is marked with an accurate timestamp when it enters and exits the device port.
  • the PTP calculates the link delay based on the timestamp carried in the event packet.
  • the event message contains the following four types: Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp.
  • the first packet is an event packet.
  • the 1588 loop algorithm enables high-precision time synchronization calculations.
  • the first processing module 22 is configured to add, in the first packet, a first time difference compensation value that is sent from the line card processing chip of the first device to the line card port, to obtain a second message;
  • the time difference compensation value described in the embodiment of the present disclosure can be obtained by manual compensation, and the time difference compensation value is added to the corresponding field of the message.
  • the manual compensation obtains the time difference compensation value, that is, the oscilloscope measures the transmission time of the message from the line card processing chip of the device to the line card port or from the line card port of the device to the line card processing chip, and the measured time is measured. A large amount of time data is averaged to obtain a time difference compensation value.
  • time difference compensation value can also be obtained in real time through the PTP system.
  • the sending module 23 is configured to send the second packet to the second device
  • the second message includes time information recorded in the first message.
  • the second message is sent from the line card port of the first device to the line card port of the second device.
  • the second obtaining module 24 is configured to obtain a third packet that is returned after the second device receives the second packet, where the second packet records that the second device receives the second packet a second time difference compensation value and a third time difference compensation value transmitted between the line card processing chip of the second device and the line card port;
  • the third packet includes time information recorded in the first packet and the second packet.
  • the second processing module 25 is configured to add, in the third packet, a fourth time difference compensation value that is sent from the line card port of the first device to the line card processing chip, to obtain a fourth message;
  • the line card processing chip may be a PHY (Physical Layer) chip
  • the PHY chip generally refers to a chip that interfaces with an external signal.
  • the calculating module 26 is configured to calculate, according to the fourth packet, a delay time of message transmission between the first device and the second device.
  • the fourth packet includes time information in the first packet, the second packet, and the third packet.
  • the calculation module 26 calculates the single link delay time of the line card port of the first device to the line card port of the second device.
  • the second time difference compensation value is a time difference compensation value that is sent from the line card port of the second device to the line card processing chip, where the second message added in the second message is sent;
  • the third time difference compensation value is the line card processing chip added from the second device in the response message fed back after the second control device obtains the second message by the second device.
  • the time difference offset value transmitted to the line card port is the line card processing chip added from the second device in the response message fed back after the second control device obtains the second message by the second device.
  • the first time information includes: a first timestamp of the main control board and a first physical clock when the first message for frequency synchronization is created on the main control board of the first device frequency.
  • the third physical clock of the line card processing chip is recorded a second timestamp and a fourth physical clock frequency of the main control board when the second message is transmitted from the line card processing chip of the second device to the main control board of the second device;
  • the third message is also recorded in the third time of the main control board when the main control board of the second device creates the response message generated by the second message on the main control board.
  • a fifth physical clock frequency when the response message is transmitted from the main control board of the second device to the line card processing chip of the second device, the line card processes the sixth physical clock frequency of the chip;
  • the fourth message is further recorded when the third message is transmitted from the line card port of the first device to the line card processing chip of the first device, and the seventh physical clock of the line card processing chip a frequency; a fourth timestamp of the main control board and an eighth physical clock frequency when the fourth message is transmitted from the line card processing chip to the main control board of the first device.
  • timestamps on different devices are different because the default time of the device's timestamp counter is different. Therefore, the timestamps on different devices cannot be calculated. The time stamp of the same device can be calculated.
  • the time information of the packet passing through the internal components of the device is filled in the corresponding field of the packet. That is, the message in the embodiment of the present disclosure may have a fixed format.
  • calculation module 26 in the embodiment of the present disclosure may further include:
  • a first calculating unit configured to obtain according to the first physical clock frequency and the second physical clock frequency Transmitting, by the first control device of the first device, a first transmission time of the line card processing chip of the first device;
  • the second physical clock frequency of the line card processing chip of the first device is subtracted from the first physical clock frequency of the main control board of the first device, and the first packet is transmitted from the main control board of the first device to The physical clock frequency difference of the line card processing chip of the first device.
  • the jitter time of each clock frequency offset is 1/125 ms, that is, the time interval of 8 ns
  • the transmission time difference from the main control board to the line card processing chip is a CF domain difference, that is, the first message is from the first
  • the first transmission time of the main control board of the device transmitted to the line card processing chip of the first device is that the first message is transmitted from the main control board of the first device to the line card processing chip of the first device
  • the physical clock frequency difference is multiplied by the beat time of each clock offset.
  • a second calculating unit configured to transmit, according to the third physical clock frequency and the fourth physical clock frequency, the second packet from the line card processing chip of the second device to the second device The second transmission time of the main control board;
  • the second transmission time is the difference between the fourth physical clock frequency of the line card processing chip of the second device minus the third physical clock frequency of the main control board of the second device multiplied by the frequency offset of each clock. The result of the beating time.
  • a third calculating unit configured to: according to the fifth physical clock frequency and the sixth physical clock frequency, obtain the line card processing chip that is sent from the main control board of the second device to the second device Third transmission time;
  • the third transmission time is the sixth physical clock frequency of the main control board of the second device minus the difference of the fifth physical clock frequency of the line card processing chip of the second device multiplied by the frequency offset of each clock. The result of the beating time.
  • a fourth calculating unit configured to obtain, according to the seven physical clock frequencies and the eighth physical clock frequency, the fourth packet from the line card processing chip of the first device to the master of the first device The fourth transfer time of the board;
  • the fourth transmission time is the eighth physical clock frequency of the line card processing chip of the first device minus the difference of the seven physical clock frequencies of the main control board of the first device multiplied by the jitter of each clock frequency offset. The result of time.
  • a fifth calculating unit configured to be according to the first timestamp, the second timestamp, the third timestamp, the fourth timestamp, the first transmission time, the second transmission time, the third transmission time, the fourth transmission time, a first time difference compensation value, a second time difference compensation value, a third time difference compensation value, and a fourth time difference compensation value, and calculating, by using a preset algorithm, a delay time of message transmission between the first device and the second device .
  • Delay represents a delay time for the message to be transmitted between the first device and the second device; T 1 is represented as the first timestamp; and T 2 is represented as the second timestamp ; T 3 is represented as the third time stamp; T 4 is represented as the fourth time stamp; N 1 is represented as the first transmission time; N 2 is represented as the second transmission time; N 3 is represented as a third transmission time; N 4 is represented as the fourth transmission time; t 1 is represented as the first time difference compensation value; t 2 is represented as the second time difference compensation value; t 3 is represented as the third time difference The compensation value; t 4 is expressed as the fourth time difference compensation value.
  • the embodiment of the present disclosure further provides a first device, which is a communication network device, and includes: an apparatus for optimizing time synchronization between communication network devices as described in the foregoing embodiments.
  • the device for optimizing time synchronization between communication network devices is used in a message when a message is transmitted from a line card processing chip of the device to a line card port or from a line card port of the device to a line card processing chip.
  • the time difference compensation value is added to reduce the delay error when the message is transmitted between the communication network devices, so that accurate time synchronization between the communication network devices can be realized, and the delay jitter requirement of the time synchronization switching of the device in the complex networking environment can be met.
  • an embodiment of the present disclosure further provides an optimization method for time synchronization between communication network devices, which is applied to a second device, including:
  • Step 31 Receive a second packet sent by the first device.
  • the second message records the time information of the message when it is transmitted internally by the first device.
  • the first message created by the main control board of the first device is transmitted at a first time difference offset value from the line card processing chip of the first device to the line card port.
  • Step 32 Add, in the second packet, a second time difference compensation value that is sent from the line card port of the second device to the line card processing chip, and transmit the second message. To the main control board of the second device;
  • the time difference compensation value described in the embodiment of the present disclosure can be obtained by manual compensation, and the time difference compensation value is added to the corresponding field of the message.
  • the manual compensation obtains the time difference compensation value, that is, the oscilloscope measures the transmission time of the message from the line card processing chip of the device to the line card port or from the line card port of the device to the line card processing chip, and the measured time is measured. A large amount of time data is averaged to obtain a time difference compensation value.
  • time difference compensation value can also be obtained in real time through the PTP system.
  • Step 33 Receive a response message that is sent back by the main control board after obtaining the second packet.
  • response message is generated by the main control board according to the second message, and the response message includes the time information recorded in the second message.
  • Step 34 Add a third time difference compensation value that is sent from the line card processing chip of the second device to the line card port in the response message, to obtain a third message.
  • the third packet includes a third time difference compensation value that is sent from the line card processing chip of the second device to the line card port, and includes a response message. Other time information recorded in .
  • Step 35 The third packet is transmitted to the first device by using a line card port of the second device.
  • the first packet of the first device is configured to create the first packet
  • the first packet is added to the first packet from the first device.
  • the line card handles the first time difference offset value transmitted by the chip to the line card port.
  • the method for optimizing time synchronization between communication network devices is used in a message when a message is transmitted from a line card processing chip of the device to a line card port or from a line card port of the device to a line card processing chip.
  • the time difference compensation value is added to provide a calculation parameter, so that the delay error rate of the message transmitted between the communication network devices is reduced, thereby achieving accurate time synchronization between the communication network devices, and meeting the time synchronization switching of the device in a complex networking environment. Delay Jitter requirements.
  • the embodiment of the present disclosure further provides an apparatus for optimizing time synchronization between communication network devices, including:
  • the first receiving module 41 is configured to receive the second packet sent by the first device
  • the second message records the time information of the message when it is transmitted internally by the first device.
  • the first message created by the main control board of the first device is transmitted at a first time difference offset value from the line card processing chip of the first device to the line card port.
  • the third processing module 42 is configured to add, in the second packet, a second time difference compensation value that is sent from the line card port of the second device to the line card processing chip, and the second Transmitting the message to the main control board of the second device;
  • the time difference compensation value described in the embodiment of the present disclosure can be obtained by manual compensation, and the time difference compensation value is added to the corresponding field of the message.
  • the manual compensation obtains the time difference compensation value, that is, the oscilloscope measures the transmission time of the message from the line card processing chip of the device to the line card port or from the line card port of the device to the line card processing chip, and the measured time is measured. A large amount of time data is averaged to obtain a time difference compensation value.
  • time difference compensation value can also be obtained in real time through the PTP system.
  • the second receiving module 43 is configured to receive a response message that is sent back by the main control board after obtaining the second packet;
  • response message is generated by the main control board according to the second message, and the response message includes the time information recorded in the second message.
  • the fourth processing module 44 is configured to add a third time difference compensation value that is sent from the line card processing chip of the second device to the line card port in the response message, to obtain a third message;
  • the third packet includes a third time difference compensation value that is sent from the line card processing chip of the second device to the line card port, and includes a response message. Other time information recorded in .
  • the transmitting module 45 is configured to transmit the third packet to the first device by using a line card port of the second device.
  • the first packet of the first device is configured to create the first packet
  • the first packet is added to the first packet from the first device.
  • the line card handles the first time difference offset value transmitted by the chip to the line card port.
  • the embodiment of the present disclosure further provides a second device, which is a communication network device, and includes: an apparatus for optimizing time synchronization between communication network devices as described in the foregoing embodiment.
  • the device for optimizing time synchronization between communication network devices is used in a message when a message is transmitted from a line card processing chip of the device to a line card port or from a line card port of the device to a line card processing chip.
  • the time difference compensation value is added to provide a calculation parameter, so that the delay error rate of the message transmitted between the communication network devices is reduced, thereby achieving accurate time synchronization between the communication network devices, and meeting the time synchronization switching of the device in a complex networking environment. Delay jitter requirements.
  • the message time delay optimization map of the embodiment of the present disclosure illustrates the flow of messages as they travel between communication network devices.
  • Step 101 Perform frequency synchronization on the main control board and the line card of the same device.
  • the embodiment of the present disclosure takes the first device and the second device as an example.
  • the first device sends the request as a delay
  • the second device acts as the delay responder.
  • Step 102 The first packet of the first device is configured to form a first packet on the main control board, and the timestamp T1 and the first physical clock frequency of the moment are recorded in the first packet.
  • the first packet is also a PTP packet, that is, an event packet.
  • the first packet is configured on the 1588 related module of the main control board.
  • Step 103 After forwarding the first packet from the main control board to the line card processing chip, record the second physical clock frequency of the line card processing chip at the moment in the first message.
  • the first packet is forwarded from the main control board to the line card processing chip, the line card processing chip is a line card FPGA module; and the second physical clock frequency of the line card processing chip is acquired, the line card
  • the processing chip is a PHY chip.
  • Step 104 Add a first time difference compensation value t1 to the line card port after processing the first message by the line card processing chip, to obtain a second message.
  • Step 105 Send the second message to the second device.
  • the second packet includes time information of the first packet.
  • Step 106 Add a second time difference compensation value t2 that the line card processing chip receives the second message after receiving the second packet by the line card port of the second device.
  • Step 107 Record the third physical clock frequency of the line card processing chip at the time when the line card processing chip of the second device receives the second message.
  • Step 108 When the second packet is transmitted to the main control board by the line card processing chip of the second device, the second device acquires the second timestamp T2 and the fourth physical clock frequency of the main control board at the moment, and records the In the second message.
  • the second message passes through the line card FPGA module of the second device to the 1588 related module of the main control board.
  • Step 109 The main control board of the second device forms a response packet, and records the timestamp T3 and the fifth physical clock frequency of the main control board at the moment in the response message.
  • the 1588 related module of the main control board of the second device forms a response message according to the second message.
  • response message includes time information recorded in the second message.
  • Step 110 After the response packet is forwarded from the main control board to the line card processing chip, the sixth physical clock frequency of the line card processing chip acquired at the moment is recorded in the response message.
  • the response message is forwarded from the main control board to the line card FPGA module, and the sixth physical clock frequency of the line card processing chip is obtained, and the line card processing chip is a PHY chip.
  • Step 111 Add a third time difference compensation to the line card port after the line card processing chip of the second device processes the response message.
  • the value t3 gives a third message.
  • Step 112 Return the third message to the first device.
  • the third message includes time information recorded in the response message.
  • Step 113 Add a fourth packet to the line card processing chip of the first device to receive a fourth time difference compensation value t4 of the third packet, to obtain a fourth packet.
  • Step 114 Record the seventh physical clock frequency of the line card processing chip at the time when the line card processing chip of the first device receives the third message.
  • Step 115 When the fourth packet passes the line card processing chip of the first device to the main control board, the first device acquires the fourth timestamp T4 and the eighth physical clock frequency of the main control board at the moment, and records the Four messages.
  • the exemplary fourth message passes through the line card FPGA module of the first device to the 1588 related module of the main control board.
  • the fourth message includes the first message, the second message, and the time information recorded in the third message.
  • Step 116 Calculate the delay correction value.
  • the delay correction value is the CF domain difference between the main control board and the line card processing chip plus the time difference compensation of the line card processing chip to the line card port, that is, N+t.
  • CF domain difference between the main control board and the line card processing chip can be calculated by using the physical clock frequency recorded in the above steps. The calculation process is shown in the first embodiment, and is not described here.
  • the calculated delay time is a single link delay time.
  • Delay represents a delay time for the message to be transmitted between the first device and the second device; T 1 is represented as the first timestamp; and T 2 is represented as the second timestamp ; T 3 is represented as the third time stamp; T 4 is represented as the fourth time stamp; N 1 is represented as the first transmission time; N 2 is represented as the second transmission time; N 3 is represented as said third transmission time; N 4 is represented by said fourth transfer time; t 1 represents a compensation value for said first time difference; t 2 represents a compensation value for said second time difference; t 3 represents said third time difference The compensation value; t 4 is expressed as the fourth time difference compensation value.
  • the method and device for optimizing time synchronization between communication network devices are reported when the message is transmitted from the line card processing chip of the device to the line card port or from the line card port of the device to the line card processing chip.
  • the time difference compensation value is added to reduce the delay error when the message is transmitted between communication network devices, so that accurate time synchronization between communication network devices can be realized, and the delay jitter requirement of time synchronization switching of the device in a complex networking environment can be met. .

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

La présente invention concerne un procédé, un appareil et un dispositif permettant d'optimiser la synchronisation temporelle entre des dispositifs de réseau de communication. Le procédé consiste à : acquérir un premier message transmis à un deuxième dispositif par une carte de commande principale d'un premier dispositif ; ajouter, dans le premier message, une première valeur de compensation de différence de temps pour le premier message à transmettre d'une puce de traitement de carte de ligne du premier dispositif à un port de carte de ligne de façon à obtenir un deuxième message ; envoyer le deuxième message au deuxième dispositif ; obtenir un troisième message renvoyé par le deuxième dispositif après réception du deuxième message, le troisième message enregistrant une valeur de compensation de différence de temps pour le deuxième message à transmettre entre une puce de traitement de carte de ligne du deuxième dispositif à un port de carte de ligne après que le deuxième dispositif a reçu le deuxième message ; ajouter, dans le troisième message, une quatrième valeur de compensation de différence de temps pour le troisième message à transmettre du port de carte de ligne du premier dispositif à la puce de traitement de carte de ligne de façon à obtenir un quatrième message ; et selon le quatrième message, calculer un temps de retard de transmission de message entre le premier dispositif et le deuxième dispositif. L'invention réalise une synchronisation temporelle précise entre des dispositifs de réseau de communication, et satisfait aux exigences de gigue de retard des dispositifs pour une commutation de synchronisation temporelle dans un environnement de réseau complexe.
PCT/CN2017/087862 2016-07-04 2017-06-12 Procédé, appareil et dispositif pour optimiser la synchronisation temporelle entre des dispositifs de réseau de communication WO2018006686A1 (fr)

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CN112737724A (zh) * 2020-12-24 2021-04-30 盛科网络（苏州）有限公司 时间信息的同步方法及装置、存储介质、电子装置
CN112737724B (zh) * 2020-12-24 2022-09-23 苏州盛科通信股份有限公司 时间信息的同步方法及装置、存储介质、电子装置
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CN112994824B (zh) * 2021-03-03 2023-03-21 山东山大电力技术股份有限公司 一种irig-b码无延迟传输的时间同步方法、装置及系统

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