WO2018000703A1 - 一种整流电路和具有该整流电路的特高频标签 - Google Patents

一种整流电路和具有该整流电路的特高频标签 Download PDF

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Publication number
WO2018000703A1
WO2018000703A1 PCT/CN2016/107160 CN2016107160W WO2018000703A1 WO 2018000703 A1 WO2018000703 A1 WO 2018000703A1 CN 2016107160 W CN2016107160 W CN 2016107160W WO 2018000703 A1 WO2018000703 A1 WO 2018000703A1
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Prior art keywords
circuit
voltage
output
stages
charge pump
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PCT/CN2016/107160
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English (en)
French (fr)
Inventor
杜鹏程
郄利波
胡毅
王于波
何洋
赵东艳
张海峰
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北京智芯微电子科技有限公司
国网信息通信产业集团有限公司
国家电网公司
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Priority to BR112018077441-3A priority Critical patent/BR112018077441B1/pt
Publication of WO2018000703A1 publication Critical patent/WO2018000703A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M7/25—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only arranged for operation in series, e.g. for multiplication of voltage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/07773—Antenna details
    • G06K19/07786—Antenna details the antenna being of the HF type, such as a dipole

Definitions

  • the invention belongs to the field of integrated circuit design, and relates to a rectifier circuit and an ultra high frequency tag having a rectifier circuit.
  • the embodiments of the present invention provide a rectifying circuit and a UHF tag having a rectifying circuit, which can improve the efficiency of the rectifying circuit.
  • An embodiment of the present invention provides a rectifier circuit including a multi-stage charge pump in a first aspect
  • the high voltage output terminal being a first predetermined number of stages in the multi-stage charge pump The output of the charge pump;
  • the low voltage output being an output of a second predetermined number of charge pumps in the multi-stage charge pump.
  • the second predetermined number of stages is less than the first predetermined number of stages, and the first predetermined number of stages is less than or equal to a total number of stages of the charge pump.
  • the output voltage of the high voltage output is higher than the output voltage of the low voltage output.
  • An embodiment of the present invention provides, in a second aspect, a UHF tag having a rectifying circuit, including:
  • a rectifier circuit according to any of the first aspects of the invention above;
  • An electrostatic discharge circuit connected to the rectifier circuit, the modulation circuit, and the demodulation circuit, wherein the RF voltage VRF output by the electrostatic discharge circuit is used as an input of the rectifier circuit, the modulation circuit, and the demodulation circuit;
  • a high voltage output end of the rectifier circuit is connected to the current limiting circuit, and a DC high voltage VDDH_RECT outputted by the high voltage output terminal is used as an input of the current limiting circuit;
  • the low voltage output terminal of the rectifier circuit is connected to the voltage stabilizing circuit and the reset circuit, and the DC low voltage VDD_RECT outputted by the low voltage output terminal is used as an input of the voltage stabilizing circuit and the reset circuit.
  • the rectifier circuit includes a multi-stage charge pump
  • the DC high voltage VDDH_RECT outputted by the rectifier circuit is an output voltage of a first predetermined number of stages in the multi-stage charge pump
  • the rectification The DC low voltage VDD_RECT outputted by the circuit is a second predetermined number of output voltages in the multi-stage charge pump, the second predetermined number of stages is less than the first predetermined number of stages, and the first predetermined number of stages is less than Or equal to the total number of stages of the charge pump.
  • the UHF tag further includes:
  • the current limiting circuit is connected to a reference circuit and a multipath transmission circuit, and the voltage VDDH output by the current limiting circuit is used as an input of the reference circuit and the multipath transmission circuit.
  • the UHF tag further includes:
  • the voltage stabilizing circuit is connected to a clock circuit, a random number circuit, a flag bit circuit and a digital circuit, and the voltage VDD output by the voltage stabilizing circuit is used as the clock circuit, the random number circuit, the flag bit circuit and the The input to the digital circuit.
  • the peak absolute value of the VRF is less than or equal to the diode threshold voltage.
  • the absolute value of the peak value of the VRF is less than or equal to 0.7V; the absolute value of the peak value of the VDD is greater than or equal to 0.7V; and the absolute value of the peak value of the VDDH and the VDDH_RECT is less than or equal to 2V; VDD_RECT is greater than 0.7V and less than 2V.
  • a rectifying circuit provided by an embodiment of the present invention includes a multi-stage charge pump, and a high-voltage output terminal is an output end of a first predetermined number of charge pumps in the multi-stage charge pump; And a low voltage output terminal, wherein the low voltage output terminal is an output end of a second predetermined number of charge pumps in the multi-stage charge pump, and the high voltage output terminal and the low voltage output terminal can be respectively used for different modules
  • the power supply makes full use of the characteristics that the number of charge pump stages is less and the efficiency is higher, and the efficiency of the rectifier circuit can be improved.
  • An ultra high frequency tag having the rectification circuit provided by the embodiment of the present invention, through VRF as an input of a rectification circuit, a modulation circuit and a demodulation circuit, VDDH_RECT is used as an input of a current limiting circuit, and VDD_RECT is used as a voltage stabilization circuit and a reset circuit.
  • Input according to the different power supply voltage requirements of different load modules, adjust the UHF architecture, configure it on the rectifier output of different stages, reasonably configure the voltage, improve the efficiency of the rectifier and the sensitivity of UHG.
  • An ultra high frequency tag having the rectification circuit provided by the embodiment of the present invention, through VDDH as an input of the reference circuit and the multipath transmission circuit, VDD as the clock circuit, the random number circuit, and the
  • the input of the flag circuit and the digital circuit adjusts the UHF architecture according to different power supply voltage requirements of different load modules, and is configured on the rectifier output of different stages, and the voltage is reasonably configured to improve the efficiency of the rectifier and the sensitivity of the UHG.
  • Figure 1 shows a more common N-stage Dickson charge pump RECT structure
  • FIG. 2 is a circuit diagram showing a multi-stage rectifier circuit of a MOS transistor
  • Figure 3 shows the power architecture of the current UHF tag
  • FIG. 4 is a schematic diagram showing an analysis circuit of a current UHF tag
  • FIG. 5 is a schematic structural diagram of a rectifier circuit according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a UHF tag with a rectifier circuit according to an embodiment of the present invention.
  • Fig. 7 is a view showing a comparison of output powers of the embodiment of the present invention and related art.
  • the rectification circuit is mainly used to form impedance matching with the antenna to obtain the largest possible energy for the subsequent load.
  • the principle is that the small amplitude sinusoidal voltage signal on the antenna is converted into direct current, and the amplitude is boosted and converted by the charge pump to obtain a suitable voltage value of the load.
  • Its key performance indicators include rectification efficiency, that is, rectification boost while minimizing its own consumption. When the load is constant, increasing the efficiency of the rectifier circuit can effectively improve the receiving sensitivity of the UHF tag.
  • Figure 1 shows a more common N-stage Dickson charge pump RECT structure. At present, basically all RECTs of UHF tags adopt this structure or an optimized variant on this structure.
  • ⁇ represents the efficiency value of the entire circuit
  • P out represents the output power of the rectifier circuit
  • P in represents the input power of the rectifier circuit.
  • ⁇ represents the efficiency value of the entire circuit
  • P out represents the output power of the rectifier circuit
  • P in represents the input power of the rectifier circuit.
  • the efficiency value ⁇ there are many factors affecting the efficiency value ⁇ , such as the number of stages of the charge pump, process parameters, diode device threshold (or metal oxide semiconductor (MOS) device threshold), load current, input voltage Amplitude and so on.
  • MOS metal oxide semiconductor
  • P d represents the power consumption of the single-stage charge pump
  • N represents the number of charge pump stages in the rectifier circuit. It can be seen from the formula (2) that reducing the number of stages of the rectifier circuit and reducing the power consumption per stage are the key to improving the rectification efficiency in the case where the input power is constant.
  • Fig. 2 is a circuit diagram showing a multi-stage rectifier circuit of a MOS transistor.
  • Figure 3 shows the power architecture of the current UHF tag.
  • the VRF is a radio frequency voltage after passing through an Electro-Static Discharge (ESD) circuit, which is used as a rectification (abbreviation: RECT), modulation (abbreviation: MOD), and demodulation (abbreviation: DEM) circuit.
  • ESD Electro-Static Discharge
  • RECT rectification
  • MOD modulation
  • DEM demodulation
  • VRECT is the rectified output DC power supply, which is only used as the input of the current limiting (abbreviation: LIM) circuit. Due to the current limiting circuit, the VRECT peak is about 2V.
  • VDDH is the current-limit circuit output. It is used as the input to the reset (abbreviation: PDR) and voltage regulator (abbreviation: REG) circuits.
  • PDR reset
  • REG voltage regulator
  • the voltage is similar to VRECT and has a peak value of approximately 2V.
  • VDD is the regulator circuit output, which is the input to the reference (REF), clock (OSC), random number (RNG), and flag (FLAG) circuits, and has a voltage of approximately 1V.
  • FIG. 4 is a schematic diagram showing an analysis circuit of a current UHF tag, by which different rectifier circuit devices are analyzed, including NMOS transistors, PMOS transistors, and Schottky diodes. (Schottky) and the effect of the series on efficiency, the data in Table 1 can be obtained.
  • the rectifier circuit is cascaded in multiple stages. From the data analysis in Table 1 above, it can be seen that the more the number of cascaded stages, the lower the efficiency of the rectifier circuit.
  • FIG. 5 is a schematic structural diagram of a rectifier circuit according to an embodiment of the present invention. As shown in FIG. 5, the rectifier circuit includes a multi-level charge pump, and includes: a high voltage output terminal and a low voltage output terminal.
  • the high voltage output terminal being an output of a first predetermined number of charge pumps in the multi-stage charge pump for providing a DC high voltage VDDH_RECT, and a low voltage output terminal, the low voltage output
  • the output of the second predetermined number of charge pumps in the multi-stage charge pump is used to provide a DC low voltage VDD_RECT, and the DC high voltage VDDH_RECT is greater than the DC low voltage VDD_RECT.
  • the second predetermined number of stages is less than the first predetermined number of stages, and the first predetermined number of stages is less than or equal to a total number of stages of charge pumps in the rectifier circuit.
  • the second predetermined number of stages is 3, and the first predetermined number of stages is an example of the total number of stages of the charge pump.
  • the high voltage output terminal is shown.
  • the output of the last stage is used to provide a DC high voltage VDDH_RECT; and the output of the low voltage output is a third stage for providing a DC low voltage VDD_RECT.
  • the embodiment of the present invention recognizes that the lower the number of charge pump stages in the rectifier, the higher the efficiency, and makes full use of this characteristic, adjusting the output voltage node of the rectifier to provide a high voltage output terminal and a low voltage output terminal, the high voltage output terminal And the low voltage output can be used to supply power to different modules, which can improve the efficiency of the rectifier circuit.
  • FIG. 6 shows a UHF tag with a rectifying circuit according to an embodiment of the present invention.
  • the UHF tag includes: a RECT circuit 11, an ESD circuit 12, a MOD circuit 13, a DEM circuit 14, and a LIM circuit 15.
  • REG circuit 16, PDR circuit 17, REF circuit 18 and MTP circuit 19, OSC circuit 21, RNG circuit 22, FLAG circuit 23, and DIGITAL circuit 24.
  • the RECT circuit 11 is a RECT circuit provided in accordance with Embodiment 1 of the present invention.
  • the RECT circuit can be used to convert the received RF signal to the desired rectified voltage.
  • the ESD circuit 12 is connected to the RECT circuit 11, the MOD circuit 13, and the DEM circuit 14, and the RF voltage VRF output from the ESD circuit 12 is input to the RECT circuit 11, the MOD circuit 13, and the DEM circuit 14.
  • the DEM circuit 14 restores the data carried in the radio frequency voltage to demodulated data that the digital system can process.
  • the MOD circuit 13 modulates the data in the digital system and transmits the signal through the antenna port.
  • the high voltage output of the RECT circuit 11 is connected to the LIM circuit 15 to the DC high voltage VDDH_RECT outputted from the high voltage output of the RECT circuit 11 as an input to the LIM circuit 15.
  • the low voltage output terminal of the RECT circuit 11 is connected to the regulated REG circuit 16 and the reset PDR circuit 17, and the DC low voltage VDD_RECT outputted from the low voltage output terminal of the RECT circuit 11 is input to the REG circuit 16 and the PDR circuit 17.
  • the REG circuit 16 regulates the rectified voltage to provide an operating voltage to the tag.
  • the PDR circuit 17 provides the required reset signal for the digital system and performs a power-down detection of the VDD_RECT and VDDH voltages to ensure that the circuit operates at a minimum voltage.
  • the RECT circuit 11 includes a multi-stage charge pump, the DC high voltage VDDH_RECT outputted by the RECT circuit 11 is an output voltage of a first predetermined number of stages in the multi-stage charge pump, and the DC low voltage VDD_RECT outputted by the RECT circuit 11 is the multi-stage a second predetermined number of output voltages in the charge pump, the second predetermined number of stages being less than the first predetermined number of stages, and the first predetermined number of stages being less than or equal to a total number of stages of the charge pump. As shown in FIG. 5, the second predetermined number of stages is 3, and the first predetermined number of stages is the total number of stages of the charge pump.
  • the output voltage of the rectifier is not limited to being output only in the third stage and the last stage. It is used to supply power to other modules depending on the load voltage.
  • the LIM circuit 15 is connected to the reference REF circuit 18 and the multipath transmission MTP circuit 19, and the voltage VDDH output from the LIM circuit 15 serves as an input of the REF circuit 18 and the MTP circuit 19.
  • the REG circuit 16 is connected to a clock OSC circuit 21, a random number RNG circuit 22, a flag FLAG circuit 23, and a digital DIGITAL circuit 24, and the voltage VDD output by the REG circuit 16 is used as the OSC circuit 21 and the RNG circuit. 22. Input of FLAG circuit 23 and DIGITAL circuit 24.
  • the OSC circuit 21 provides a stable clock signal for the digital system.
  • the absolute value of the peak value of the VRF is less than or equal to the threshold voltage of the diode
  • the absolute value of the peak value of the VRF is less than or equal to 0.7V
  • the absolute value of the peak value of VDD is greater than or equal to 0.7V
  • the absolute value of the peak value of VDDH, VDDH_RECT is less than or equal to 2V
  • VDD_RECT is greater than 0.7. V and less than 2V.
  • FIG. 7 is a comparison diagram of output power of an embodiment of the present invention and related art. As shown in FIG. 7, ESD, RECT, and LIM are regarded as a whole, and the input power is the same, the antenna network is completely matched, and the rectification efficiency of the overall architecture is analyzed. .
  • the related art needs to improve the efficiency of the rectifier RECT in the structure of the rectifier circuit, or to improve the process.
  • the technical level of the circuit structure has been basically fixed, it is difficult to greatly improve, and the process improvement requires the optimization of the process plant, and the circuit design is far away, and it is not a method that can easily improve the efficiency.
  • the embodiment of the invention recognizes that the lower the number of charge pump stages in the rectifier, the higher the efficiency, and makes full use of the characteristics, adjusts the output voltage node of the rectifier, respectively supplies power to different modules, and achieves the effect of improving the efficiency of the rectifier circuit.
  • the related technology does not take into account the different requirements of different modules for the supply voltage, unifying the voltage of all loads, wasting power consumption, and reducing the efficiency of the rectifier.
  • the UHF architecture is adjusted according to different power supply voltage requirements of different load modules, and is configured on the rectifier output of different stages, and the voltage is reasonably configured, thereby improving the efficiency of the rectifier and the sensitivity of the UHG.
  • the device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, ie may be located A place, or it can be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the embodiment. Those of ordinary skill in the art can understand and implement without deliberate labor.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) including computer usable program code.
  • the rectifier circuit includes: a high voltage output terminal, wherein the high voltage output terminal is an output end of the first predetermined number of charge pumps in the multi-stage charge pump; and a low voltage output terminal, the low The voltage output is an output of a second predetermined number of charge pumps in the multi-stage charge pump.
  • the invention fully utilizes the characteristics that the less the number of charge pump stages is, the higher the efficiency is, the output voltage node of the rectifier is adjusted to provide a high voltage output end and a low voltage output end, and the high voltage output end and the low voltage output end can be respectively used for Different modules supply power, which achieves the effect of improving the efficiency of the rectifier circuit.

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Abstract

一种整流电路（11）和具有该整流电路（11）的特高频标签，包括多级电荷泵，所述整流电路（11）包括：高电压输出端，所述高电压输出端为所述多级电荷泵中第一预定级数的电荷泵的输出端；以及低电压输出端，所述低电压输出端为所述多级电荷泵中第二预定级数的电荷泵的输出端。该整流电路（11）能够提高整流效率。

Description

一种整流电路和具有该整流电路的特高频标签 技术领域
本发明属于集成电路设计领域，涉及一种整流电路和具有整流电路的特高频标签。
背景技术
目前，900兆赫兹(MHz)的特高频(Ultra High Frequency，UHF)标签的发展迅速，接收灵敏度已经接近-20分贝毫(dBm)。功率的绝对值越高说明接收灵敏度越高。提高电路的接收灵敏度要求标签实现模拟和数字电路的低功耗设计：模拟电路的静态功耗需要不断消减；数字电路的功耗消减的同时不断降低工作电压以及降低系统的时钟频率。这些都是节流的措施，但是因为整流(RECT)电路的效率不高，导致无法开源，这仍然无法满足现在不断提高的接收灵敏度要求。因此，为了提高UHF标签的灵敏度，如何提高整流器的效率是现有技术中存在的问题。
公开于该背景技术部分的信息仅仅旨在增加对本发明的总体背景的理解，而不应当被视为承认或以任何形式暗示该信息构成已为本领域一般技术人员所公知的现有技术。
发明内容
有鉴于此，本发明实施例提供一种整流电路和具有整流电路的UHF标签，能够提高整流电路的效率。
本发明实施例的技术方案如下：
本发明实施例在第一方面提供一种整流电路，包括多级电荷泵；
高电压输出端，所述高电压输出端为所述多级电荷泵中第一预定级数 的电荷泵的输出端；以及
低电压输出端，所述低电压输出端为所述多级电荷泵中第二预定级数的电荷泵的输出端。
在本发明的其他实施例中，所述第二预定级数小于所述第一预定级数，并且所述第一预定级数小于或等于所述电荷泵的总级数。
在本发明的其他实施例中，所述高电压输出端的输出电压高于所述低电压输出端的输出电压。
本发明实施例在第二方面提供一种具有整流电路的特高频标签，包括：
根据以上本发明的第一方面中任一项所述的整流电路；
静电放电电路，与所述整流电路、调制电路和解调电路连接，所述静电放电电路输出的射频电压VRF作为所述整流电路、所述调制电路和所述解调电路的输入；
所述整流电路的高电压输出端与限流电路连接，所述高电压输出端输出的直流高电压VDDH_RECT作为所述限流电路的输入；
所述整流电路的低电压输出端与稳压电路和复位电路连接，所述低电压输出端输出的直流低电压VDD_RECT作为所述稳压电路和所述复位电路的输入。
在本发明的其他实施例中，所述整流电路包括多级电荷泵，所述整流电路输出的直流高电压VDDH_RECT为所述多级电荷泵中的第一预定级数的输出电压，所述整流电路输出的直流低电压VDD_RECT为所述多级电荷泵中的第二预定级数的输出电压，所述第二预定级数小于所述第一预定级数，并且所述第一预定级数小于或等于所述电荷泵的总级数。
在本发明的其他实施例中，所述的特高频标签，还包括：
所述限流电路，与基准电路和多路径传输电路连接，所述限流电路输出的电压VDDH作为所述基准电路和所述多路径传输电路的输入。
在本发明的其他实施例中，所述的特高频标签，还包括：
所述稳压电路，与时钟电路、随机数电路、标志位电路和数字电路连接，所述稳压电路输出的电压VDD作为所述时钟电路、所述随机数电路、所述标志位电路和所述数字电路的输入。
在本发明的其他实施例中，所述VRF的峰值绝对值小于等于二极管阈值电压。
在本发明的其他实施例中，所述VRF的峰值绝对值小于等于0.7V；所述VDD的峰值绝对值大于等于0.7V；所述VDDH、所述VDDH_RECT的峰值绝对值小于等于2V；所述VDD_RECT大于0.7V并且小于2V。
本发明实施例提供的一种整流电路，包括多级电荷泵，通过设置高电压输出端，所述高电压输出端为所述多级电荷泵中第一预定级数的电荷泵的输出端；以及低电压输出端，所述低电压输出端为所述多级电荷泵中第二预定级数的电荷泵的输出端，该高电压输出端和低电压输出端可以分别用于给不同的模块供电，充分利用了电荷泵级数越少效率越高的特性，能够提高整流电路效率的效果。
本发明实施例提供的一种具有该整流电路的特高频标签，通过VRF作为整流电路、调制电路和解调电路的输入，VDDH_RECT作为限流电路的输入，VDD_RECT作为稳压电路和复位电路的输入，根据不同负载模块的不同电源电压需求，调整UHF架构，将其配置在不同级的整流器输出上，合理配置了电压，提高了整流器效率和UHG的灵敏度。
本发明实施例提供的一种具有该整流电路的特高频标签，通过VDDH作为所述基准电路和所述多路径传输电路的输入，VDD作为所述时钟电路、所述随机数电路、所述标志位电路和所述数字电路的输入，根据不同负载模块的不同电源电压需求，调整UHF架构，将其配置在不同级的整流器输出上，合理配置了电压，提高了整流器效率和UHG的灵敏度。
根据下面参考附图对示例性实施例的详细说明，本发明的其它特征及方面将变得清楚。
附图说明
包含在说明书中并且构成说明书的一部分的附图与说明书一起示出了本发明的示例性实施例、特征和方面，并且用于解释本发明的原理。
图1示出较为常用的N级Dickson电荷泵RECT结构；
图2示出MOS管的多级整流电路的电路图；
图3示出当前UHF标签的电源架构；
图4示出当前UHF标签的分析电路示意图；
图5示出本发明实施例提供的一种整流电路的结构示意图；
图6示出本发明实施例提供的一种具有整流电路的UHF标签的示意图；
图7示出本发明实施例与相关技术的输出功率对比图。
具体实施方式
下面结合附图，对本发明的具体实施方式进行详细描述，但应当理解本发明的保护范围并不受具体实施方式的限制。
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。除非另有其它明确表示，否则在整个说明书和权利要求书中，术语“包括”或其变换如“包含”或“包括有”等等将被理解为包括所陈述的元件或组成部分，而并未排除其它元件或其它组成部分。
在这里专用的词“示例性”意为“用作例子、实施例或说明性”。这里作为“示例性”所说明的任何实施例不必解释为优于或好于其它实施例。
另外，为了更好的说明本发明，在下文的具体实施方式中给出了众多的具体细节。本领域技术人员应当理解，没有某些具体细节，本发明同样可以实施。在一些实例中，对于本领域技术人员熟知的方法、手段、元件未作详细描述，以便于凸显本发明的主旨。
整流电路作为整个UHF的关键模块，主要的作用是和天线形成阻抗匹配，得到尽可能大的能量提供给后续的负载。其原理是将天线上的小幅度正弦电压信号转换成直流的同时，将幅度经过电荷泵进行升压转化，得到负载适合的电压值。其关键性能指标包括整流效率，即整流升压的同时尽量减小自身的消耗。在负载不变的情况下，提高整流电路的效率能够有效提高UHF标签的接收灵敏度。
图1示出较为常用的N级Dickson电荷泵RECT结构。目前基本上所有的UHF标签的RECT都是采用此结构或者在此结构上的优化变型。
整个电路的效率值η可以简单的表示为公式(1)：
η＝Pout/Pin          (1)；
公式(1)中，η表示整个电路的效率值，Pout表示整流电路的输出功率，Pin表示整流电路的输入功率。在公式(1)中，影响效率值η的因素很多，如电荷泵的级数、工艺参数、二极管器件阈值(或者金属氧化物半导体(Metal Oxide Semiconductor，MOS)器件阈值)、负载电流、输入电压幅度等。其中，与整流电路设计直接相关的内容为整流电路本身器件的采用和整流电路的级数。
根据公式(1)，变型可得到公式(2)：
η＝(Pin-N*Pd)/Pin               (2)；
公式(2)中，Pd表示单级电荷泵的功率消耗，N表示整流电路中电荷 泵级数。由公式(2)可知，在输入功率恒定的情况下，减小整流电路的级数和减小每级的功率消耗是提高整流效率的关键。
传统的Dickson整流电路都是采用肖特基二极管作为整流电路件的，但是二极管有阈值损失，效率不高。所以当前针对Dickson的整流电路进行了很多的变型。有本征晶体管(Native MOS，NMOS，N-Metal-Oxide-Semiconductor，又称为N沟道MOS)晶体管，P沟道MOS(PMOS，P-Metal Oxide Semiconductor，Positive Channel Metal Oxide Semiconductor)晶体管等。
图2示出MOS管的多级整流电路的电路图。图3示出当前UHF标签的电源架构。
如图3所示，VRF为通过静电放电(Electro-Static discharge，ESD)电路后的射频电压，其作为整流(缩写：RECT)、调制(缩写：MOD)和解调(缩写：DEM)电路的输入，由于ESD的存在，VRF的峰值绝对值不超过二极管阈值，约为0.7V。
VRECT为整流输出的直流电源，其只作为限流(缩写：LIM)电路的输入，由于限流电路存在，VRECT峰值约为2V。
VDDH为限流电路输出，作为复位(缩写：PDR)和稳压(缩写：REG)电路的输入，其电压与VRECT类似，峰值约为2V。
VDD为稳压电路输出，作为基准(REF)、时钟(OSC)、随机数(RNG)和标志位(FLAG)电路的输入，其电压约为1V。
如图3所示，假设输入功率相同，天线网络完全匹配且输出的负载电流相同，将ESD、RECT、LIM看作一个整体，可以得到输出能量与输入能量的比，即整流效率。
图4示出当前UHF标签的分析电路示意图，利用该分析电路，分析不同整流电路器件包括NMOS晶体管、PMOS晶体管、肖特基二极管 (Schottky)和级数对于效率的影响，可以得到表1的数据。
表1
级数 Schottky nativeMOS NMOS PMOS
2 52％ 60％ 55％ 45％
3 46％ 56％ 35％ 22％
4 36％ 49％ 14％ 1％
5 25％ 40％ 3％ 0
从表1分析可知：不同的整流器件得到的整流效率不同，最重要的是当级数增加时，整流电路的效率在不断下降。
如图4所示，所有的负载模块都和整理器的输出直接连接，那么整流电路的输出电压将是所有负载模块中电源电压需求最大的，这增加了负载的能量消耗，效率下降。
此外，整流电路是多级级联，从之前表1中的数据分析可知，级联的级数越多，整流电路效率就会下降。
图5示出本发明实施例提供的一种整流电路的结构示意图，如图5所示，该整流电路包括多级电荷泵，并且包括：高电压输出端和低电压输出端。
高电压输出端，所述高电压输出端为所述多级电荷泵中第一预定级数的电荷泵的输出端，用于提供直流高电压VDDH_RECT，以及低电压输出端，所述低电压输出端为所述多级电荷泵中第二预定级数的电荷泵的输出端用于提供直流低电压VDD_RECT，直流高电压VDDH_RECT大于直流低电压VDD_RECT。
所述第二预定级数小于所述第一预定级数，并且所述第一预定级数小于或等于整流电路中电荷泵的总级数。图5中以第二预定级数为3，第一预定级数为电荷泵的总级数为例进行说明，在图5的示例中，高电压输出端 为整流最后一级的输出端，用于提供直流高电压VDDH_RECT；以及低电压输出端为第三级的输出端用于提供直流低电压VDD_RECT。
本发明实施例认识到了整流器中电荷泵级数越少效率越高的特性，并充分利用了该特性，调整整流器的输出电压节点以提供高电压输出端和低电压输出端，该高电压输出端和低电压输出端可以分别用于给不同的模块供电，实现了提高整流电路效率的效果。
图6示出本发明实施例提供的一种具有整流电路的UHF标签，如图6所示，该UHF标签包括：RECT电路11、ESD电路12、MOD电路13、DEM电路14、LIM电路15、REG电路16、PDR电路17、REF电路18和MTP电路19、OSC电路21、RNG电路22、FLAG电路23和DIGITAL电路24。
RECT电路11为根据本发明实施例1提供的RECT电路。RECT电路可以用于将接收下来的射频信号转化为所需要的整流电压。
ESD电路12，与RECT电路11、MOD电路13和DEM电路14连接，ESD电路12输出的射频电压VRF作为RECT电路11、MOD电路13和DEM电路14的输入。DEM电路14将射频电压中携带的数据恢复为数字系统可以处理的解调数据，MOD电路13对数字系统中的数据进行调制，通过天线端口传输信号。
RECT电路11的高电压输出端与LIM电路15连接RECT电路11的高电压输出端输出的直流高电压VDDH_RECT作为所述LIM电路15的输入。RECT电路11的低电压输出端与稳压REG电路16和复位PDR电路17连接，RECT电路11的低电压输出端输出的直流低电压VDD_RECT作为REG电路16和PDR电路17的输入。REG电路16是对整流电压进行稳压，为标签提供工作电压，PDR电路17为数字系统提供所需的复位信号，并对VDD_RECT和VDDH电压进行下电检测，确保电路工作在最小的电压的范 围内。
RECT电路11包括多级电荷泵，RECT电路11输出的直流高电压VDDH_RECT为所述多级电荷泵中的第一预定级数的输出电压，RECT电路11输出的直流低电压VDD_RECT为所述多级电荷泵中的第二预定级数的输出电压，所述第二预定级数小于所述第一预定级数，并且所述第一预定级数小于或等于所述电荷泵的总级数。结合图5所示，以第二预定级数为3，第一预定级数为电荷泵的总级数为例进行说明，整流器的输出电压不限于仅仅在第三级和最后一级输出，可以根据负载电压的不同在其他级间引出用于给其他模块供电。
LIM电路15，与基准REF电路18和多路径传输MTP电路19连接，LIM电路15输出的电压VDDH作为所述REF电路18和所述MTP电路19的输入。
所述REG电路16，与时钟OSC电路21、随机数RNG电路22、标志位FLAG电路23和数字DIGITAL电路24连接，所述REG电路16输出的电压VDD作为所述OSC电路21、所述RNG电路22、FLAG电路23和DIGITAL电路24的输入。OSC电路21为数字系统提供稳定的时钟信号，
其中，VRF的峰值绝对值小于等于二极管阈值电压，VRF的峰值绝对值小于或等于0.7V，VDD的峰值绝对值大于或等于0.7V，VDDH、VDDH_RECT的峰值绝对值小于或等于2V，VDD_RECT大于0.7V并且小于2V。
图7示出本发明实施例与相关技术的输出功率对比图，如图7所示，将ESD、RECT、LIM看做一个整体，假设输入功率相同，天线网络完全匹配，分析整体架构的整流效率。
从图7可以看出，随着负载电流的增加，本发明实施例的整体输出功率提高。那么可以假设当负载电流不变时，本发明图6的输入功率可以比 之前图4的结构低更多，那么也就提高了UHF标签的效率和激活灵敏度。
相关技术(图4)提高整流器RECT的效率必须在整流电路的结构上进行深化，或者工艺上进行改善。但是电路结构相关技术水平已经基本定型，很难有很大的提高，且工艺改善需要工艺厂进行优化，和电路设计相去甚远，都不是能很容易提高效率的方法。
本发明实施例认识到了整流器中电荷泵级数越少效率越高的特性并充分利用了该特性，调整整流器的输出电压节点，分别给不同的模块供电，实现了提高整流电路效率的效果。
相关技术(图4)并没有考虑到不同模块对于电源电压的需求不同的特点，将所有负载的电压统一，浪费功耗，降低了整流器的效率。本发明实施例根据不同负载模块的不同电源电压需求，调整UHF架构，将其配置在不同级的整流器输出上，合理配置了电压，提高了整流器效率和UHG的灵敏度。
以上所描述的装置实施例仅仅是示意性的，其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。本领域普通技术人员在不付出创造性的劳动的情况下，即可以理解并实施。
本领域内的技术人员应明白，本发明的实施例可提供为方法、系统、或计算机程序产品。因此，本发明可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器和光学存储器等)上实施的计算机程序产品的形式。
前述对本发明的具体示例性实施方案的描述是为了说明和例证的目 的。这些描述并非想将本发明限定为所公开的精确形式，并且很显然，根据上述教导，可以进行很多改变和变化。对示例性实施例进行选择和描述的目的在于解释本发明的特定原理及其实际应用，从而使得本领域的技术人员能够实现并利用本发明的各种不同的示例性实施方案以及各种不同的选择和改变。本发明的范围意在由权利要求书及其等同形式所限定。
工业实用性
本发明实施例中，整流电路包括：高电压输出端，所述高电压输出端为所述多级电荷泵中第一预定级数的电荷泵的输出端；以及低电压输出端，所述低电压输出端为所述多级电荷泵中第二预定级数的电荷泵的输出端。本发明充分利用了电荷泵级数越少效率越高的特性，调整整流器的输出电压节点以提供高电压输出端和低电压输出端，该高电压输出端和低电压输出端可以分别用于给不同的模块供电，实现了提高整流电路效率的效果。

Claims (9)

  1. 一种整流电路，包括：
    多级电荷泵；
    高电压输出端，所述高电压输出端为所述多级电荷泵中第一预定级数的电荷泵的输出端；以及
    低电压输出端，所述低电压输出端为所述多级电荷泵中第二预定级数的电荷泵的输出端。
  2. 根据权利要求1所述的整流电路，其中，所述第二预定级数小于所述第一预定级数，并且所述第一预定级数小于或等于所述电荷泵的总级数。
  3. 根据权利要求2所述的整流电路，其中，所述高电压输出端的输出电压高于所述低电压输出端的输出电压。
  4. 一种具有整流电路的特高频标签，包括：
    根据权利要求1至3中任一项所述的整流电路；
    静电放电电路，与所述整流电路、调制电路和解调电路连接，所述静电放电电路输出的射频电压VRF作为所述整流电路、所述调制电路和所述解调电路的输入；
    所述整流电路的高电压输出端与限流电路连接，所述高电压输出端输出的直流高电压VDDH_RECT作为所述限流电路的输入；
    所述整流电路的低电压输出端与稳压电路和复位电路连接，所述低电压输出端输出的直流低电压VDD_RECT作为所述稳压电路和所述复位电路的输入。
  5. 根据权利要求4所述的特高频标签，其中，所述整流电路包括多级电荷泵，所述整流电路输出的直流高电压VDDH_RECT为所述多级电荷泵中的第一预定级数的输出电压，所述整流电路输出的直流低电压 VDD_RECT为所述多级电荷泵中的第二预定级数的输出电压，所述第二预定级数小于所述第一预定级数，并且所述第一预定级数小于或等于所述电荷泵的总级数。
  6. 根据权利要求4或5所述的特高频标签，其中，还包括：
    所述限流电路，与基准电路和多路径传输电路连接，所述限流电路输出的电压VDDH作为所述基准电路和所述多路径传输电路的输入。
  7. 根据权利要求6所述的特高频标签，其中，还包括：
    所述稳压电路，与时钟电路、随机数电路、标志位电路和数字电路连接，所述稳压电路输出的电压VDD作为所述时钟电路、所述随机数电路、所述标志位电路和所述数字电路的输入。
  8. 根据权利要求7所述的特高频标签，其中，所述VRF的峰值绝对值小于等于二极管阈值电压。
  9. 根据权利要求8所述的特高频标签，其中，所述VRF的峰值绝对值小于等于0.7V；所述VDD的峰值绝对值大于等于0.7V；所述VDDH、所述VDDH_RECT的峰值绝对值小于等于2V；所述VDD_RECT大于0.7V并且小于2V。
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