WO2015103958A1 - 一种开关信号控制的整流与限幅电路与无源射频标签 - Google Patents

一种开关信号控制的整流与限幅电路与无源射频标签 Download PDF

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Publication number
WO2015103958A1
WO2015103958A1 PCT/CN2015/070142 CN2015070142W WO2015103958A1 WO 2015103958 A1 WO2015103958 A1 WO 2015103958A1 CN 2015070142 W CN2015070142 W CN 2015070142W WO 2015103958 A1 WO2015103958 A1 WO 2015103958A1
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type mos
mos transistor
unit
circuit
voltage dividing
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PCT/CN2015/070142
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English (en)
French (fr)
Inventor
吴边
漆射虎
罗远明
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卓捷创芯科技（深圳）有限公司
无锡智速科技有限公司
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Publication of WO2015103958A1 publication Critical patent/WO2015103958A1/zh
Priority to US15/202,573 priority Critical patent/US10387760B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/0701—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips at least one of the integrated circuit chips comprising an arrangement for power management
    • G06K19/0707—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips at least one of the integrated circuit chips comprising an arrangement for power management the arrangement being capable of collecting energy from external energy sources, e.g. thermocouples, vibration, electromagnetic radiation
    • G06K19/0708—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips at least one of the integrated circuit chips comprising an arrangement for power management the arrangement being capable of collecting energy from external energy sources, e.g. thermocouples, vibration, electromagnetic radiation the source being electromagnetic or magnetic
    • G06K19/0709—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips at least one of the integrated circuit chips comprising an arrangement for power management the arrangement being capable of collecting energy from external energy sources, e.g. thermocouples, vibration, electromagnetic radiation the source being electromagnetic or magnetic the source being an interrogation field

Definitions

  • the invention belongs to the technical field of radio frequency identification, and specifically relates to a rectification and limiting circuit controlled by a switching signal, and a passive radio frequency tag including the rectifying and limiting circuit.
  • the Radio Frequency Identification (RFID) tag itself does not have a battery, and it relies on the electromagnetic energy transmitted by the card reader. Because of its simple structure and economical utility, it has been widely used in logistics management, asset tracking and mobile medical.
  • a passive RFID tag When a passive RFID tag is in operation, it absorbs the electromagnetic energy emitted by the reader from the surrounding environment. After absorbing energy, the passive RFID tag rectifies a portion of the energy into a DC power source for operation of the passive RFID tag internal circuit; the passive RFID tag also inputs another portion of the energy into the internal modulation and demodulation circuit. The modem circuit demodulates the amplitude modulated signal carried in the energy and transmits the demodulated signal to the digital baseband portion of the passive RFID tag for processing.
  • the electromagnetic energy absorbed by the passive RFID tag from the surrounding environment also changes as the passive RFID tag operates.
  • the signal strength received by the passive RFID tag is also strong, so that the voltage induced on the coil exceeds the voltage used by the rectifier module in the chip.
  • the voltage withstand voltage of the transistor causes permanent damage to the transistor, causing the RFID tag to fail.
  • the passive RFID tag transmits data to the card reader through load modulation, and the coil at the card reader end detects the impedance change of the RFID tag end coil to acquire data.
  • the load modulation signal capacity coupled back from the RFID tag end It is easy to cause saturation of the reader's receiving end, and the communication fails. This failure is more likely to occur in the RTF communication mode (Reader Talk First) where the reader first issues a command and then waits for an RFID tag to answer.
  • an amplitude limiting processing circuit is required inside the RFID tag chip circuit to ensure that the voltage across the antenna on the RFID tag is limited to a predetermined value.
  • the implementation of the amplitude limit can be performed by leaking current from the rectifier branch to ground, thereby controlling the voltage level of the rectifier output.
  • the most ideal design requires that the leakage current path can be effectively turned off in the case of a very weak field, that is, no leakage at all, and in the case of a gradually increasing field, the leakage current path can control the starting point of the start of leakage and the leakage current at any time. How much to achieve the purpose of dynamic adjustment.
  • the amplitude limit function is through a voltage comparator.
  • the voltage comparator compares the relationship between the envelope signal generated by the envelope detection circuit, that is, the data information, and the average value of the envelope signal itself, so that the inverter outputs high and low logic behind the voltage comparator. Signal, the demodulated signal.
  • the demodulation circuit can adaptively ensure the stability of the averaging circuit, thereby ensuring the demodulation circuit. Normal and stable work.
  • the technique of adaptively adjusting the gate voltage of the first PMOS transistor used in the above patent is a method of indirectly monitoring the intensity of the RF signal.
  • the dynamic adjustment object is a PMOS tube used as an equivalent resistor, so that the channel equivalent resistance of the PMOS tube is stable under different signal strengths, that is, the filter time constant of the capacitor is stable, and finally a stable detection effect is obtained.
  • the present application monitors the magnitude of the RF signal strength for the dynamic adjustment of the voltage amplitude of the rectifier, and adjusts the object.
  • the leakage current path from the antenna port to the ground has different degrees of opening under different signal strength conditions, thereby protecting the transistor of the RF front end from high voltage and avoiding the reader end. Receive saturation occurs.
  • Limiting circuit The limiting circuit is used for limiting the signal strength, and is directed to a circuit having a constant power input, which is different from the rectification control circuit used in the present application, and cannot be used in an RFID circuit. .
  • the application does not relate to the aspect of using the switching signal to adjust the voltage amplitude circuit at the input of the rectifier as described in this patent application, and is not repeatable with the inventive aspects of the present patent application.
  • the limit circuit of Shanghai Huahong is controlled by a high-voltage or low-voltage detection circuit to charge and discharge a capacitor to generate a limiter signal.
  • the limiting signal has a significantly larger time constant in the change of the specific field strength, that is, a change in the voltage amplitude on the slowly reacting antenna.
  • Such a technique does not serve the purpose of the overvoltage protection proposed by the present application because within a limited time constant, the transistors inside the radio frequency tag chip are already in an unreliable state of overvoltage driving. Therefore, the limiting circuit disclosed in the present application has an extremely fast response speed to the change of the voltage on the antenna, and can play a good protection role.
  • the limiter circuit disclosed in the present application controls the path of the limiter circuit by the power supply voltage and the decision circuit output switching signal, regardless of whether the demodulation circuit is present or not, and is independent of the characteristics of the demodulated signal outputted by the demodulation circuit.
  • the techniques disclosed herein have a broader range of applications for high performance RF tags and low cost RF tags.
  • An object of the present invention is to provide a DC signal that is absorbed and rectified by an inductor coil antenna of a passive RFID tag into a high-low level signal, and is input to a control input end of a discharge path of the rectifier circuit, according to the amount of charge Controlling the discharge path to open discharge or in a closed state, by limiting the voltage amplitude of the rectifier to achieve limiting control of the circuit voltage, to meet the reliability requirements of the overvoltage protection of the semiconductor device on the chip, and preventing the reader end Receive saturation occurs.
  • a switching signal controlled rectification and limiting circuit comprising:
  • a resonant capacitor connected in parallel with the resonant inductor between the first antenna end and the second antenna end, for forming a resonant circuit with the resonant inductor, receiving an external electromagnetic field and coupling it to the rectifier circuit;
  • a rectifier circuit having an input end connected to the first antenna end and the second antenna end, configured to convert the AC power coupled by the resonant circuit into a DC power source, and the first output end of the rectifier circuit is output to an external load circuit,
  • the second output is output to a power supply voltage detection and determination circuit for detecting the power supply voltage
  • the determination circuit provides a determination voltage
  • the third output end is grounded through at least two parallel N-type MOS tubes as a discharge path for outputting the charge to the ground when the field strength is too strong;
  • At least two power supply voltage detecting and determining circuits wherein a power input end is connected to the second output end of the rectifying circuit, and an output end thereof is connected to a control input end of at least two discharging paths of the rectifying circuit, for The amount of charge between the antenna end and the second antenna end controls the discharge path of the rectifier circuit to be turned on or off to control the leakage state of the output terminal.
  • Another object of embodiments of the present invention is to provide a passive radio frequency tag including a rectification and limiting circuit controlled by the above switching signals.
  • a rectifying and limiting circuit controlled by a switching signal according to the present invention is provided with x N-type MOS tubes of different width-to-length ratios arranged side by side in the discharge path of the rectifying circuit, and is disposed with the x N-type MOS tubes
  • the same number of power supply voltage detecting and determining circuits are respectively connected to the gates of the N-type MOS transistors for controlling the opening and closing of the respective N-type MOS tubes. Since each power supply voltage detecting and determining circuit has different limiting points, each power supply voltage detecting and determining circuit outputs a high and low level signal when the amount of charge between the first antenna end and the second antenna end is the same.
  • the high and low level signals control the N-type MOS transistor connected thereto to open leakage or turn off. Since the width-to-length ratios of the N-type MOS transistors are different, various combinations of N-type MOS transistors are opened and closed to achieve various degrees of leakage.
  • the discharge path composed of x parallel N-type MOS tubes and x supply voltage detection and determination circuits, the combination form of the discharge paths is 2 x (x is a natural number and greater than or equal to 2), and the larger the value of x, the combination The more the form, the higher the accuracy of the limit discharge.
  • the solution is applied to a limiter circuit module in a passive RFID tag circuit, so that the withstand voltage of the device connected to the inductor coil antenna can be reliably ensured.
  • Another significant feature of this scheme is that the implementation of the x supply voltage detection and decision circuits connected in parallel is an ultra-low power implementation. The typical current consumption sum is on the order of nanoamps (10 -9 ), making the entire scheme suitable for none. Source RFID tag
  • FIG. 1 is a block diagram showing the overall structure of a circuit of the present invention.
  • Embodiment 1 is a structural diagram of Embodiment 1 of a rectifier circuit used in the present invention
  • Embodiment 3 is a structural diagram of Embodiment 2 of a rectifier circuit used in the present invention.
  • FIG. 4 is a block diagram showing the overall structure of a power supply voltage detecting and determining circuit used in the present invention.
  • Embodiment 1 is a structural diagram of Embodiment 1 of a power supply voltage detecting and determining circuit used in the present invention
  • Embodiment 6 is a structural diagram of Embodiment 2 of a power supply voltage detecting and determining circuit used in the present invention
  • Embodiment 7 is a structural diagram of Embodiment 3 of a power supply voltage detecting and determining circuit used in the present invention.
  • FIG. 8 is a structural diagram of a fourth embodiment of a power supply voltage detecting and determining circuit used in the present invention.
  • Embodiment 9 is a structural diagram of Embodiment 5 of a power supply voltage detecting and determining circuit used in the present invention.
  • Fig. 10 is a structural view showing the sixth embodiment of the power supply voltage detecting and determining circuit employed in the present invention.
  • FIG. 1 is a block diagram showing the overall structure of the circuit of the present invention.
  • the switching signal controlled rectification and limiting circuit 1 of the present invention comprises:
  • a resonant capacitor C1 connected in parallel with the resonant inductor L between the first antenna end in1 and the second antenna end in2 for forming a resonant circuit with the resonant inductor L, receiving an external electromagnetic field and coupling it to the rectifier circuit;
  • the rectifier circuit 2 has an input end connected to the first antenna end in1 and the second antenna end in2 for converting the AC power coupled by the resonant circuit into a DC power source, and the first output terminal V dd_out of the rectifier circuit is output to external load circuit which outputs a second output terminal V 1 to the power supply voltage detection circuit 3 to the determination, the determination voltage for providing a power supply voltage detection circuit and the determination that the output of the third N-MOS transistor is grounded through at least two parallel As a discharge path, used to output charge to the ground when the field strength is too strong;
  • At least two power supply voltage detection circuit 3 determines that the power supply input is connected to a second output terminal of the rectifier circuit V 1, V CTRL output terminal of the rectifier circuit connected to the at least two control input of the discharge passage,
  • the method is used for controlling the discharge path of the rectifier circuit to be turned on or off according to the amount of charge between the first antenna end in1 and the second antenna end in2, so as to control the leakage state of the output end.
  • the rectification and limiting circuit controlled by the switching signal of the present invention is provided with x N-type MOS tubes of different width-to-length ratios in parallel in the discharge path of the rectifying circuit, and is disposed in the same number as the N-type MOS tubes. And a power supply voltage detecting and determining circuit, wherein the output terminals of the power voltage detecting and determining circuit are respectively connected to gates of the N-type MOS transistors for respectively controlling opening and closing of the N-type MOS tubes. Since each power supply voltage detecting and determining circuit has different limiting points, each power supply voltage detecting and determining circuit outputs a high and low level signal when the amount of charge between the first antenna end and the second antenna end is the same.
  • the high and low level signals control the N-type MOS tube connected to it to open leakage or off close. Since the width-to-length ratios of the N-type MOS transistors are different, various combinations of N-type MOS transistors are opened and closed to achieve various degrees of leakage.
  • the solution is applied to a limiter circuit module in a passive RFID tag circuit, so that the withstand voltage of the device connected to the inductor coil antenna can be reliably ensured.
  • FIG. 2 is a structural diagram of Embodiment 1 of a rectifier circuit used in the present invention.
  • the rectifier circuit 2 includes a first rectification branch, a second rectification branch, and a third rectification branch connected in parallel between the first antenna end in1 and the second antenna end in2.
  • the first rectifying branch is a bridge rectifying circuit, and an output end thereof is grounded, and the first output end V dd — out is connected to an external load circuit for converting the AC power coupled by the resonant circuit into a DC power source to supply power to the external load circuit. .
  • the second rectifying branch is a fifth diode D5 and a sixth diode D6 connected between the first antenna end in1 and the second antenna end in2, as shown in FIG. 2, the fifth diode D5 And a sixth diode D6 for converting the AC power coupled by the resonant circuit into a DC power source, and outputting from the second output terminal V 1 of the rectifier circuit to the input end of the power voltage detecting and determining circuit 3 for use as a power source
  • the voltage detection and determination circuit 3 provides a determination voltage.
  • the second embodiment of the second rectifying branch is structured as shown in FIG. 3.
  • the second rectifying branch is a fifth N-type connected between the first antenna end in1 and the second antenna end in2.
  • the MOS transistor M5 and the sixth N-type MOS transistor M6, the gate and the drain of the fifth N-type MOS transistor M5 are respectively coupled to the first antenna terminal in1, and the gate and the drain of the sixth N-type MOS transistor M6 are respectively coupled Connected to the second antenna terminal in2, the source of the fifth N-type MOS transistor M5 is coupled to the source of the sixth N-type MOS transistor M6 for converting the AC power coupled by the resonant circuit into a DC power source, and from the rectifier circuit a second output terminal V OUT 1-3 and the input power supply voltage detection determination circuit for detecting the power source voltage decision circuit 3 provided as the determination voltage.
  • the fifth diode D5 and the fifth N-type MOS transistor M5, and the sixth diode D6 and the sixth N-type MOS transistor M6 are all unidirectional electronic components for using the first antenna end in1 and the first
  • the AC power supply between the two antenna terminals in2 is rectified to the DC power supply V 1 , and the voltage value of V 1 is V in1 (positive half cycle AC signal) or V in2 (negative half cycle AC signal) minus the threshold voltage of the diode or MOS transistor.
  • the third rectifying branch is a seventh diode D7 and an eighth diode D8 connected between the first antenna end in1 and the second antenna end in2, as shown in FIG. 2, the seventh diode D7 And a cathode end of the eighth diode D8 is coupled to the drains of the at least two N-type MOS transistors connected in parallel, and the gates of the at least two N-type MOS transistors connected in parallel are respectively connected to the power supply voltage detection and determination
  • the output terminal V CTRL of the circuit 3 and the source of each N-type MOS transistor are grounded for outputting the charge coupled to the resonant circuit to the ground when the field strength is too strong, thereby reducing the first antenna end in1 and the second antenna end The amount of charge between in2.
  • the third rectifying branch is a seventh N-type connected between the first antenna end in1 and the second antenna end in2.
  • the MOS transistor M7 and the eighth N-type MOS transistor M8, the gate and the drain of the seventh N-type MOS transistor M7 are respectively coupled to the first antenna terminal in1, and the gate and the drain of the eighth N-type MOS transistor M8 are respectively coupled.
  • the source of the seventh N-type MOS transistor M7 is coupled to the source of the eighth N-type MOS transistor M8 and coupled to the drain of the at least two N-type MOS transistors connected in parallel.
  • the at least two parallel connected N-type MOS transistor gates are respectively connected to the output terminal V CTRL of the power supply voltage detecting and determining circuit 3, and the sources of the N-type MOS transistors are grounded for resonating when the field strength is too strong.
  • the electric charge coupled by the circuit is output to the ground, thereby reducing the amount of charge between the first antenna end in1 and the second antenna end in2.
  • the seventh diode D7 and the seventh N-type MOS transistor M7, and the eighth diode D8 and the eighth N-type MOS transistor M8 are all unidirectional electronic components for using the first antenna end in1 and the first
  • the AC power between the two antenna ends in2 is rectified to a DC power source and input to the at least two N-type MOS tubes connected in parallel The drain terminal.
  • the unidirectional conductive electronic components in the first rectifying branch, the second rectifying branch, and the third rectifying branch that can be rectified may adopt any combination of diodes or MOS tubes, including but not limited to the drawings.
  • the two combinations shown, and the amplification ratio of the diode or MOS tube can be set by adjusting the size of the diode (ie, the area of the PN junction) or adjusting the channel size ratio of the MOS transistor to achieve power saving. purpose.
  • FIG. 4 is a block diagram showing the overall structure of a power supply voltage detecting and determining circuit used in the present invention.
  • the power supply voltage detecting and determining circuit 3 includes a first voltage dividing unit 31, a second voltage dividing unit 32, a threshold comparing unit 33, a first current limiting unit 34, and a logic signal generating unit 35.
  • the first voltage dividing unit 31 and the second voltage dividing unit 32 are sequentially connected in series between the power supply terminal V 1 and the ground.
  • the control terminal of the threshold comparison unit 33 is connected to the first voltage dividing unit 31 and the second voltage dividing unit 32.
  • the input end is connected to the current source V 1 through the first current limiting unit 34 , and the output end thereof is grounded.
  • the input end of the logic signal generating unit 35 is connected to the input end of the threshold comparing unit 33 and the first current limiting unit 34 . Between, used to generate logic control signals, control the discharge path of the rectifier circuit to open or close.
  • the first voltage dividing unit 31 is at least one resistor, or at least one P-type MOS transistor, or at least one of N-type MOS transistors.
  • the first voltage dividing resistor unit 31 When the first voltage dividing resistor unit 31 at least one time, the structure shown in Figure 5, connected end to end to form a series resistor structure and adjacent said at least one resistor, the first resistor is connected to a power source as a first divided voltage V The input end of the unit 31, the last resistor is connected to the second voltage dividing unit 32 as the output end of the first voltage dividing unit 31;
  • the first voltage dividing unit 31 is at least one P-type MOS transistor
  • the structure thereof is as shown in FIG. 6.
  • the drain terminal of the at least one P-type MOS transistor is connected to the source terminal of the adjacent P-type MOS transistor to form a series structure.
  • the source of a P-MOS transistor 31 is connected to the input terminal of the first power dividing means V 1
  • the drain of the last P-type MOS transistor is connected to a second dividing unit dividing unit 32 as a first 31
  • the output terminal of each P-type MOS transistor is connected to the drain of the last P-type MOS transistor;
  • the first voltage dividing unit 31 is at least one N-type MOS transistor
  • the structure thereof is as shown in FIG. 7.
  • the source terminal of the at least one N-type MOS transistor is connected to the drain terminal of the adjacent N-type MOS transistor to form a series structure.
  • a drain of the N-type MOS transistor 31 is connected to the input terminal of the first power dividing means V 1
  • a source of the last N-type MOS transistor is connected to a second dividing unit dividing unit 32 as a first 31
  • the gates of the respective N-type MOS transistors are connected to the drain of the first N-type MOS transistor.
  • the second voltage dividing unit 32 is at least one resistor, or at least one P-type MOS transistor, or at least one of N-type MOS transistors.
  • the second voltage dividing unit 32 is at least one resistor
  • the structure thereof is as shown in FIG. 5.
  • the at least one resistor is connected in series with the adjacent resistors to form a series structure, and the first resistor is connected to the first voltage dividing unit 31 as a first
  • the input end of the second voltage dividing unit 32, and the last one of the resistors is grounded as the output end of the second voltage dividing unit 32;
  • the second voltage dividing unit 32 is at least one P-type MOS transistor
  • the structure thereof is as shown in FIG. 6.
  • the drain terminal of the at least one P-type MOS transistor is connected to the source terminal of the adjacent P-type MOS transistor to form a series structure.
  • a source of the P-type MOS transistor is connected to the first voltage dividing unit 31 as an input end of the second voltage dividing unit 32, and a drain of the last P-type MOS transistor is grounded as an output end of the second voltage dividing unit 32.
  • Each P-type MOS tube The gates are all connected to the drain of the last P-type MOS transistor;
  • the second voltage dividing unit 32 is at least one N-type MOS transistor
  • the structure thereof is as shown in FIG. 7.
  • the source terminal of the at least one N-type MOS transistor is connected to the drain terminal of the adjacent N-type MOS transistor to form a series structure.
  • the drain of one of the N-type MOS transistors is connected to the first voltage dividing unit 31 as the input end of the second voltage dividing unit 32, and the source of the last N-type MOS transistor is grounded as the output end of the second voltage dividing unit 32.
  • the gates of the respective N-type MOS transistors are connected to the drains of the first N-type MOS transistors.
  • the first current limiting unit 34 is at least one resistor, or at least one P-type MOS transistor, or at least one of the N-type MOS transistors.
  • the first current limiting unit 34 to at least one of resistance, the structure shown in Figure 5, connected end to end to form a series resistor structure and adjacent said at least one resistor, the first resistor is connected to a power source V 1 as a first flow restrictor
  • the input of the unit 34, the last resistor is connected to the threshold comparison unit 33 as the output of the first current limiting unit 34;
  • the first current limiting unit 34 is at least one P-type MOS transistor
  • the structure thereof is as shown in FIG. 6.
  • the drain terminal of the at least one P-type MOS transistor is connected to the source terminal of the adjacent P-type MOS transistor to form a series structure.
  • the source of a P-type MOS transistor is connected to the power supply V 1 as a first input terminal of the current limiting unit 34
  • the drain of the last P-type MOS transistor is connected to the threshold comparison unit 33 as an output of the first current limiting unit 34
  • the gates of the P-type MOS transistors are connected to the drain of the last P-type MOS transistor;
  • the first current limiting unit 34 is at least one N-type MOS transistor
  • the structure thereof is as shown in FIG. 7.
  • the source terminal of the at least one N-type MOS transistor is connected with the drain terminal of the adjacent N-type MOS transistor to form a series structure.
  • a drain of the N-type MOS transistor is connected to the power supply V 1 as a first input terminal of the current limiting unit 34
  • a source of the last N-type MOS transistor is connected to the threshold comparison unit 33 as an output of the first current limiting unit 34
  • the gates of the respective N-type MOS transistors are connected to the drains of the first N-type MOS transistors.
  • the first voltage dividing unit, the second voltage dividing unit and the first current limiting unit may be formed by connecting one or more resistance elements such as resistors or MOS tubes in series, and in each embodiment, the first voltage dividing unit
  • the resistive elements used in the second voltage dividing unit and the first current limiting unit need not maintain symmetry, and one or more kinds of resistive elements may be arbitrarily selected in series in each unit. Since a plurality of series-connected MOS transistor channel lengths become longer, the resistance value thereof becomes larger, and thus the impedance characteristics are better, and the area thereof is much smaller than the resistance of the same impedance. Therefore, a preferred embodiment of the present invention is adopted. A structure in which a plurality of MOS tubes are connected in series.
  • the threshold comparison unit 33 is at least one N-type MOS transistor, and its structure is as shown in FIG. 5-8.
  • the N-type MOS transistor gate is connected between the first voltage dividing unit 31 and the second voltage dividing unit 32. as a control of the threshold comparison unit 33, the drain 1 as a threshold value by the input of the first current limiting unit 34 access comparator unit 33 V source, its source is grounded as a threshold value comparison unit 33 outputs.
  • the threshold comparison unit 33 of the present invention may also be formed by connecting two or more N-type MOS transistors in series, and the source terminals of the N-type MOS transistors are connected in series with the drain terminals of the adjacent N-type MOS transistors to form a series connection.
  • the drain of the first N-MOS transistor as a threshold value by an input of the first current limiting unit 34 the access source V comparing unit 33
  • the last N-type MOS transistor is grounded as a threshold value comparison unit
  • the gates of the respective N-type MOS transistors are connected between the first voltage dividing unit 31 and the second voltage dividing unit 32 as the control terminal of the threshold comparing unit 33, as shown in FIG.
  • the channel size of the MOS transistor is lengthened, and the width-to-length ratio is reduced, so that the turn-over time constant of the MOS transistor is lengthened, and the flipping speed of the threshold unit is delayed, Therefore, the purpose of reducing the ripple of the output power is achieved.
  • the channel size of the MOS transistor is lengthened, the resistance value thereof is increased, and the power consumption and current limiting are also achieved.
  • the threshold comparison unit 33 is a P-type MOS transistor, its structure is as shown in FIG. 10, and the P-type MOS transistor gate is connected between the first voltage dividing unit 31 and the second voltage dividing unit 32 as a threshold comparison.
  • the control terminal unit 33 which is connected to the source as the threshold value comparison unit 33 of the input of the current source V 1, a drain is grounded through a first current limiting unit 34 as a threshold value comparison unit 33 outputs.
  • the threshold comparison unit of the present invention can also change the structure of the single P-type MOS tube shown in FIG. 10 to a structure using a plurality of P-type MOS tubes, and the connection structure and principle thereof are not described herein again.
  • the logic signal generating unit 35 is an odd number of inverters connected in series (when the threshold comparing unit is a P-type MOS transistor, the number of inverters connected in series in the logic signal generating unit is an even number), the first inversion The input stage is connected between the threshold comparison unit and the first current limiting unit as an input of the logic signal generating unit, and the last inverter output stage V CTRL is connected to the control input of the discharge path of the rectifier circuit for generating logic control The signal controls the discharge path of the rectifier circuit to be turned on or off.
  • the rectifier of the radio frequency identification tag converts the DC voltage V 1 from the electromagnetic field energy of the surrounding environment, and the voltage V 1 is input to the power source voltage detecting and determining circuit 3.
  • the impedance of the first voltage dividing unit is set to R 1 and the impedance of the second voltage dividing unit is R 2 , and the current values of the branches of the first and second voltage dividing units are:
  • V A V 1 ⁇ R 2 /(R 1 +R 2 )
  • the voltage value of the control terminal of the threshold comparison unit is
  • control threshold comparison unit control can be achieved by setting the impedance ratios of the first and second voltage dividing units.
  • the voltage value of the terminal is the purpose of controlling the limiting point of each power supply voltage detection and determination circuit.
  • An odd number of inverters connected in series outputs the low level signal as 1 representing a high level logic signal, and inputs the high level logic signal V CTRL1 to the N of the first path discharge path of the rectifier circuit connected thereto a gate of the MOS transistor, the N-type MOS transistor is turned on, and the charge between the first antenna end and the second antenna end is output to the ground through the source thereof, so that the first antenna end and the second antenna end are between When the amount of charge is reduced, the DC power supply V dd — out rectified by the bridge rectifier
  • the threshold comparison unit of the power supply voltage detecting and determining circuit is also turned on, and the logic signal generating unit generates a signal representing a high level logic signal, and the rectifier circuit connected thereto is connected.
  • the N-type MOS transistor of the path discharge path is turned on to start discharging.
  • the threshold turn-on voltage is 0.7V
  • the threshold comparison unit is turned off
  • the logic signal generating unit outputs 0 representing a low-level logic signal
  • the low-level signal V CTRLx is input to the n-type MOS transistor of the x- th discharge path connected to the rectifier circuit connected thereto
  • the gate when the N-type MOS transistor is not turned on, the discharge path of the circuit is turned off and does not discharge.
  • the number of the discharge path and the power supply voltage detecting and determining circuit composed of the parallel N-type MOS transistors according to the present invention is x, and the combination of the opening and closing of the discharge path is 2 x (x is a natural number and greater than or equal to 2)
  • x is a natural number and greater than or equal to 2
  • the rectification and limiting circuit controlled by the switching signal of the present invention can also pass the output ends of the at least two power supply voltage detecting and determining circuits respectively through the delay circuit according to the requirement of the reaction time of the control circuit.
  • the control inputs of the at least two discharge paths are connected.
  • the simplest implementation of the delay circuit can be constructed as a low pass filter composed of a combination of a resistive device and a capacitive device.
  • the output ends of the at least two power supply voltage detecting and determining circuits may be directly connected to the control input ends of the at least two discharge paths, but in actual applications, the control is generally given.
  • the loop has a certain reaction time to avoid repeated jumps of the switching device such as the N-type MOS transistor, so that the output power source generates a large ripple.
  • Another object of embodiments of the present invention is to provide a passive radio frequency tag including a rectification and limiting circuit controlled by the above switching signals.
  • the width-to-length ratio of the N-type MOS transistors of the discharge paths of the rectifier circuit in the RF tag is different, so the discharge capacities of the discharge channels of the respective paths are different, and the discharge channels of the various combinations are turned on and off, so that The discharge capability of the limiter circuit is also different, and the opening and closing of the N-type MOS transistor of each discharge path depends on the input control signal V CTRL connected to its gate terminal.
  • the V GS of each circuit is different, that is, the turn-on voltages of the threshold comparison units of the circuits are different,
  • the power supply voltage detection and determination circuit having a lower threshold turn-on voltage is connected to the N-type MOS transistor having a weaker discharge capability, and the power supply voltage detection and determination circuit having the highest threshold turn-on voltage is connected to the discharge capacity.
  • N type MOS tube is
  • the V 1 value rectified by the rectifier circuit of the tag is too low, all the power supply voltage detection and determination circuit clipping points are higher than the V 1 value, then all the power supply voltage detection and determination circuits are cut off, and the output is low.
  • the level signal causes the N-type MOS transistor of the discharge path to be turned off, and the rectifier circuit rectifies all the charges at the antenna end into a DC power source for use by the load circuit; when the V 1 value is too high, the N-type MOS tube with strong discharge capability is turned on. Achieve fast discharge, realize dynamic rectification control of circulating circuit voltage, prevent excessive voltage from penetrating the load circuit.

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Abstract

一种开关信号控制的整流与限幅电路，以及包含该整流与限幅电路的无源射频标签。所述开关信号控制的整流与限幅电路将无源RFID标签的电感线圈天线所吸收并整流后的直流信号转化为高低电平信号，并输入到整流电路放电通路的控制输入端，根据电荷量的大小控制放电通路打开放电或处于关闭状态，通过对整流器电压幅度进行动态调整实现对电路电压的限幅控制，以满足芯片上半导体器件在过压保护的可靠性方面的要求，并防止读卡器端接收饱和现象的发生。

Description

一种开关信号控制的整流与限幅电路与无源射频标签 技术领域
本发明属于射频识别技术领域，具体是指一种开关信号控制的整流与限幅电路，以及包含该整流与限幅电路的无源射频标签。
背景技术
无源射频识别(Radio Frequency Identification，RFID)标签本身不带电池，其依靠读卡器发送的电磁能量工作。由于它结构简单、经济实用，因而其在物流管理、资产追踪以及移动医疗领域获得了广泛的应用。
无源RFID标签工作时，其会从周围环境中吸收读卡器发送的电磁能量。无源RFID标签在吸收能量之后，将一部分能量整流为直流电源，以供无源RFID标签内部电路工作；无源RFID标签还将另一部分能量输入内部的调制解调电路。调制解调电路会对该能量中携带的幅度调制信号进行解调，并将解调后的信号发送给无源RFID标签的数字基带部分处理。
由于无源RFID标签与读卡器的距离是变化的，因此，当无源RFID标签工作时，其从周围环境中吸收的电磁能量也是变化的。当无源RFID标签离读卡器太近或读卡器发送的电磁能量太强时，无源RFID标签接收到的信号强度也较强，以至线圈上感应的电压超过了芯片中整流器模块所用的晶体管的耐压极限，造成晶体管的永久性损坏，导致RFID标签失效。
无源RFID标签通过负载调制的方式传输数据到读卡器，读卡器端的线圈探测到RFID标签端线圈的阻抗变化从而获取数据。当无源RFID标签离读卡器太近或读卡器发送的电磁能量太强时，从RFID标签端耦合回来的负载调制信号容 易造成读卡器接受端的饱和，以至通讯失败。这种失败在读卡器首先发命令然后等待RFID标签应答的RTF通讯模式(Reader Talk First)下更容易发生。
为了解决上述耐压可靠性以及读卡器接受饱和的问题，RFID标签芯片电路内部需要施加幅度限制处理电路，以确保RFID标签上的天线两端电压被限制在一个预定的数值。幅度限制的实施可采用从整流支路上漏电流到地的方法，从而使整流器输出的电压水平得到控制。最理想化的设计要求漏电流通路在极弱场的情况下能够被有效关断，即完全不漏电，而在逐渐增强的场情况下，漏电流通路能够随时控制开始漏电的起点，以及漏电流的多少，达到动态调整的目的。
电子科技大学以2010年11月30日申请的名称为《一种用于超高频射频识别标签芯片的解调电路》，申请号为201010568305.4的发明专利中，幅度限制功能是通过一个电压比较器实施的，该电压比较器比较了包络检波电路产生的包络信号，即数据信息，和包络信号本身的均值之间的大小对比关系，从而由电压比较器后面的反相器输出高低逻辑信号，即解调后的信号。如此，即使在读卡器与电子标签之间的很近或很远导致的信号强度差异很大的情况下，该解调电路仍能够自适应地保证均值产生电路的稳定性，从而确保了解调电路正常稳定的工作。
上述专利中所用的自适应调整第一PMOS管栅极电压的技术是间接监控射频信号强度的一种方法。其中动态调整的对象是作为等效电阻用的PMOS管，使得在不同信号强度下该PMOS管的沟道等效电阻保持稳定，也即和电容组成的滤波时间常数稳定，最终获得稳定的检波效果，确保了解调电路正常稳定的工作。本申请针对整流器电压幅度的动态调整而监控射频信号强度的大小，调整对象 为整流器的限幅电路，使得从天线端口到地的漏电流通路在不同的信号强度情况下有不同程度的开启程度，从而保护了射频前端的晶体管不受高压影响，也避免了读卡器端的接收饱和现象的发生。
株式会社岛津制作所以2008年6月9日申请的，名称为《限幅电路》，申请号为200880129721.5的PCT专利，提出一种利用晶体管的导通、截止切掉超出上下限阈值信号电压值的限幅电路。该限幅电路是用于对信号强度的限幅，且其针对的是有恒定电源输入的电路，不同于本申请中所采用的整流控制电路，且也无法将该电路转用于RFID电路中。
天津南大强芯半导体芯片设计有限公司以2007年8月20号申请的，名称为《一种射频识别标签电路系统结构及其工作方法与应用》，申请号为200710058875.7的发明专利,唯一的提出的发明点是从整流器输出的供电电源线分了几路给不同的模块,并以此提出提高了能量转换和使用效率的观点。首先，就其电源线分开几路接到不同模块的做法，是芯片设计中的常规做法，但是该申请中未能阐述清楚能量转换和使用效率是如何提高的，提高到什么程度。要达到真正的效率提高，光是该申请中所提到的接法(那本身就是一个普通接法)是不够的，用整流器输出支路直接给存储器控制模块的高压产生电路供电甚至会导致电荷泵所用的振荡器功耗很大的问题。其次，该申请没有涉及本专利申请所述用开关信号来调整整流器输入端电压幅度电路的方面，跟本专利申请的发明点没有重复性。
上海华虹集成电路有限责任公司以2006年03月17日申请的，名称为《用于非接触式IC卡和射频识别标签芯片的限幅保护电路》，申请号为200610024814.4的发明专利中，提出一种在强场范围内将通过天线耦合得到的 能量限制在可以接受的范围内，同时不会影响芯片内部后续解调、稳压、时钟、复位电路的正常工作。该专利与本申请所存在的区别点在于：
1、因为限幅电路的目的不同，所以上海华虹的限幅电路是由高压或者低压的检测电路控制对一个电容的充放电来产生限幅信号。该限幅信号在比场强度的变化有着明显较大的时间常数，即缓慢反应天线上电压幅度的变化。这样的技术不能起到本申请所提出的过压保护的目的，因为在有限的时间常数之内，射频标签芯片内部的晶体管已经处在过压驱动的不可靠状态。所以本申请所公开的限幅电路对天线上电压的变化有着极快的反应速度，能够起到很好的保护作用。
2、上海华虹的限幅电路有两条泄放通路，其中一条慢通路，如前所述，不适合过压保护，另一条由解调信号控制的泄放通路，与本申请所公开的技术有着本质的不同。在很多应用于门禁卡等领域中的低成本射频标签芯片中，读卡器仅仅提供场能量，而标签电路的工作局限于“标签耦合到能量后启动上电，并直接发出自身所存储的信息”的简单模式，不存在该专利中所用到的解调电路，也即不能提供控制泄放通路的信号。本申请所公开的限幅电路由电源电压与判定电路输出开关信号控制限幅电路的通路，与是否存在解调电路无关，与解调电路输出的解调信号本身特性无关。相比之下本申请所公开的技术在高性能射频标签和低成本射频标签均有更广泛的适用范围。
3、上海华虹的高压检测与低压检测信号所控制的开关管有两个恒定电流源作为偏置，在无源射频标签系统中将造成较大的直流功耗，不利于达到低功耗，高灵敏度的目的。本申请所公开的技术利用电源检测和判定电路所输出的开关信号控制若干个不同泄放能力的通路的打开和关断，以达到限幅的目的。泄放 电流在本申请所公开的技术中达到了细分化，有着更好的能量效率。
4、上海华虹的限幅电路在检测天线两端电压上存在两个判断点，即电压过低的临界点和电压过高的临界点。当天线两端的电压低于电压过低的临界点时，电容上的电荷得到泄放。当天线两端电压高于电压过高的临界点时，电容上的电荷得到充电积累。这其中的问题是当天线两端的电压处于两个临界点之间时，上下两个控制开关均处于关断状态，电容上的电压是浮动的，不受任何信号控制。在无源射频标签芯片中这是一个致命的问题，容易造成不可控的泄放电流而损失能量，影响标签的灵敏度。
发明内容
本发明实施例目的在于提供一种将无源RFID标签的电感线圈天线所吸收并整流后的直流信号转化为高低电平信号，并输入到整流电路放电通路的控制输入端，根据电荷量的大小控制放电通路打开放电或处于关闭状态，通过对整流器电压幅度进行动态调整实现对电路电压的限幅控制，以满足芯片上半导体器件在过压保护的可靠性方面的要求，并防止读卡器端接收饱和现象的发生。
为实现上述目的，本发明所采取的技术方案为：
一种开关信号控制的整流与限幅电路，所述该电路包括：
谐振电容，与谐振电感并联连接于第一天线端与第二天线端之间，用于与谐振电感组成谐振电路，接收外部电磁场并将其耦合至整流电路；
整流电路，其输入端连接至第一天线端与第二天线端，用于将所述谐振电路耦合的交流电源转换为直流电源，所述整流电路的第一输出端输出至外部负载电路，其第二输出端输出至电源电压探测与判定电路，用于为电源电压探测 与判定电路提供判定电压，其第三输出端通过至少两个并联的N型MOS管接地作为放电通路，用于在场强过强时将电荷输出至地；
至少两路电源电压探测与判定电路，其电源输入端连接至所述整流电路第二输出端，其输出端连接至所述整流电路的至少两路放电通路的控制输入端，用于根据第一天线端与第二天线端之间的电荷量大小控制所述整流电路的放电通路打开或关闭，实现控制该输出端的漏电状态。
本发明实施例的另一目的在于提供一种包括上述开关信号控制的整流与限幅电路的无源射频标签。
本发明所述一种开关信号控制的整流与限幅电路，在整流电路的放电通路并列设置有x个宽长比各不相同的N型MOS管，并且设置与所述x个N型MOS管数目相同的电源电压探测与判定电路，所述电源电压探测与判定电路输出端分别连接至所述各N型MOS管的栅极，用于分别控制各N型MOS管的打开与关闭。由于各电源电压探测与判定电路限幅点各不相同，因此各电源电压探测与判定电路在第一天线端与第二天线端之间的电荷量大小相同的情况下，输出的高低电平信号各不相同，该高低电平信号控制与其连接的N型MOS管打开漏电或关闭。由于各N型MOS管的宽长比各不相同，因此各种不同的N型MOS管打开和关闭的组合形式便实现了各种不同程度的漏电状态。采用x个并联的N型MOS管组成的放电通路与x个电源电压探测与判定电路，则放电通路的组合形式为2x种(x为自然数且大于等于2)，x的数值越大，组合形式越多，即限幅放电的精度越高。本方案运用于无源RFID标签电路中的限幅电路模块中，使得与电感线圈天线所连接的器件的耐压得以可靠的保证。本方案的另一个显著特点在于并联连接的x个电源电压探测与判定电路的实施是超低功耗的实施，典型的 电流消耗总和为纳安数量级(10-9)，使得整个方案适用于无源RFID标签系统。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明的电路总体结构框图；
图2是本发明采用的整流电路实施例一结构图；
图3是本发明采用的整流电路实施例二结构图；
图4是本发明采用的电源电压探测与判定电路总体结构框图；
图5是本发明采用的电源电压探测与判定电路实施例一结构图；
图6是本发明采用的电源电压探测与判定电路实施例二结构图；
图7是本发明采用的电源电压探测与判定电路实施例三结构图；
图8是本发明采用的电源电压探测与判定电路实施例四结构图；
图9是本发明采用的电源电压探测与判定电路实施例五结构图；
图10是本发明采用的电源电压探测与判定电路实施例六结构图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造 性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
如图1所示为本发明的电路总体结构框图。本发明所述一种开关信号控制的整流与限幅电路1包括：
谐振电容C1，其与谐振电感L并联连接于第一天线端in1与第二天线端in2之间，用于与谐振电感L组成谐振电路，接收外部电磁场并将其耦合至整流电路；
整流电路2，其输入端连接至第一天线端in1与第二天线端in2，用于将所述谐振电路耦合的交流电源转换为直流电源，所述整流电路的第一输出端Vdd_out输出至外部负载电路，其第二输出端V1输出至电源电压探测与判定电路3，用于为电源电压探测与判定电路提供判定电压，其第三输出端通过至少两个并联的N型MOS管接地作为放电通路，用于在场强过强时将电荷输出至地；
至少两路电源电压探测与判定电路3，其电源输入端连接至所述整流电路第二输出端V1，其输出端VCTRL连接至所述整流电路的至少两路放电通路的控制输入端，用于根据第一天线端in1与第二天线端in2之间的电荷量大小控制所述整流电路的放电通路打开或关闭，实现控制该输出端的漏电状态。
本发明所述一种开关信号控制的整流与限幅电路，在整流电路的放电通路并列设置有x个宽长比各不相同的N型MOS管，并且设置与所述N型MOS管数目相同的电源电压探测与判定电路，所述电源电压探测与判定电路输出端分别连接至所述各N型MOS管的栅极，用于分别控制各N型MOS管的打开与关闭。由于各电源电压探测与判定电路限幅点各不相同，因此各电源电压探测与判定电路在第一天线端与第二天线端之间的电荷量大小相同的情况下，输出的高低电平信号各不相同，该高低电平信号控制与其连接的N型MOS管打开漏电或关 闭。由于各N型MOS管的宽长比各不相同，因此各种不同的N型MOS管打开和关闭的组合形式便实现了各种不同程度的漏电状态。本方案运用于无源RFID标签电路中的限幅电路模块中，使得与电感线圈天线所连接的器件的耐压得以可靠的保证。
图2为本发明采用的整流电路实施例一结构图。所述整流电路2包括并联连接于第一天线端in1与第二天线端in2之间的第一整流支路，第二整流支路以及第三整流支路。
所述第一整流支路为桥式整流电路，其一输出端接地，第一输出端Vdd_out连接至外部负载电路，用于将谐振电路耦合的交流电源转换为直流电源为外部负载电路提供电源。
所述第二整流支路为连接于第一天线端in1与第二天线端in2之间的第五二极管D5和第六二极管D6，如图2，所述第五二极管D5和第六二极管D6用于将谐振电路耦合的交流电源转换为直流电源，并从所述整流电路的第二输出端V1输出至电源电压探测与判定电路3输入端，用于为电源电压探测与判定电路3提供判定电压。
第二整流支路的第二种实施例结构如图3所示，该实施例中所述第二整流支路为连接于第一天线端in1与第二天线端in2之间的第五N型MOS管M5和第六N型MOS管M6，所述第五N型MOS管M5栅极和漏极分别耦接至第一天线端in1，第六N型MOS管M6栅极和漏极分别耦接至第二天线端in2，第五N型MOS管M5源极耦接至第六N型MOS管M6源极,用于将谐振电路耦合的交流电源转换为直流电源，并从所述整流电路的第二输出端V1输出至电源电压探测与判定电路3输入端，用于为电源电压探测与判定电路3提供判定电压。
上述第五二极管D5和第五N型MOS管M5，以及第六二极管D6和第六N型MOS管M6均为单向导通的电子元件，用于将第一天线端in1与第二天线端in2之间的交流电源整流为直流电源V1，则V1的电压值为Vin1(正半周交流信号)或Vin2(负半周交流信号)减去二极管或MOS管的阈值电压。
所述第三整流支路为连接于第一天线端in1与第二天线端in2之间的第七二极管D7和第八二极管D8，如图2，所述第七二极管D7和第八二极管D8阴极端耦接至所述至少两个并联连接的N型MOS管的漏极，所述至少两个并联连接的N型MOS管栅极分别连接至电源电压探测与判定电路3的输出端VCTRL，各N型MOS管的源极均接地，用于在场强过强时将谐振电路耦合的电荷输出至地，从而减小第一天线端in1与第二天线端in2之间的电荷量。
第三整流支路的第二种实施例结构如图3所示，该实施例中所述第三整流支路为连接于第一天线端in1与第二天线端in2之间的第七N型MOS管M7和第八N型MOS管M8，所述第七N型MOS管M7栅极和漏极分别耦接至第一天线端in1，第八N型MOS管M8栅极和漏极分别耦接至第二天线端in2，第七N型MOS管M7源极耦接至第八N型MOS管M8源极并耦接至所述至少两个并联连接的N型MOS管的漏极，所述至少两个并联连接的N型MOS管栅极分别连接至电源电压探测与判定电路3的输出端VCTRL，各N型MOS管的源极均接地，用于在场强过强时将谐振电路耦合的电荷输出至地，从而减小第一天线端in1与第二天线端in2之间的电荷量。
上述第七二极管D7和第七N型MOS管M7，以及第八二极管D8和第八N型MOS管M8均为单向导通的电子元件，用于将第一天线端in1与第二天线端in2之间的交流电源整流为直流电源并输入至所述至少两个并联连接的N型MOS管 的漏极端。
所述第一整流支路、第二整流支路以及第三整流支路中起整流作用的单向导通电子元件均可采用二极管或MOS管的任意形式的组合，包含但并不限于附图中所示出的两种组合方式，且可以通过调整所述二极管的尺寸(即PN结的面积)或调整MOS管的沟道尺寸比例来设定二极管或MOS管的放大比例，达到节省功耗的目的。
图4是本发明采用的电源电压探测与判定电路总体结构框图。所述电源电压探测与判定电路3为至少两路，各路电源电压探测与判定电路3成并联结构连接于整流电路的第二输出端V1与地线之间，它们的输出端VCTRL分别连接至整流电路各放电通路的N型MOS管的栅极端，用于根据第一天线端与第二天线端之间的电荷量大小控制所述整流电路的放电通路打开或关闭，实现控制该输出端的漏电状态或关闭状态。
所述电源电压探测与判定电路3包括第一分压单元31，第二分压单元32，阈值比较单元33，第一限流单元34以及逻辑信号生成单元35。所述第一分压单元31与第二分压单元32依次串接于电源端V1与地线之间，阈值比较单元33控制端连接于第一分压单元31与第二分压单元32之间，其输入端通过第一限流单元34接入电流源V1，其输出端接地，所述逻辑信号生成单元35输入端连接于阈值比较单元33输入端与第一限流单元34之间，用于生成逻辑控制信号，控制整流电路的放电通路打开或关闭。
所述第一分压单元31为至少一个电阻，或至少一个P型MOS管，或至少一个N型MOS管中的任一种。
当第一分压单元31为至少一个电阻时，其结构如图5所示，所述至少一个 电阻与相邻电阻首尾连接形成串联结构，第一个电阻连接至电源V1作为第一分压单元31输入端，最后一个电阻连接至第二分压单元32作为第一分压单元31的输出端；
当第一分压单元31为至少一个P型MOS管时，其结构如图6所示，所述至少一个P型MOS管漏极端与相邻P型MOS管的源极端连接形成串联结构，第一个所述P型MOS管的源极连接至电源V1作为第一分压单元31输入端，最后一个P型MOS管的漏极连接至第二分压单元32作为第一分压单元31的输出端,各P型MOS管的栅极均连接至最后一个P型MOS管的漏极；
当第一分压单元31为至少一个N型MOS管时，其结构如图7所示，所述至少一个N型MOS管源极端与相邻N型MOS管的漏极端连接形成串联结构，第一个所述N型MOS管的漏极连接至电源V1作为第一分压单元31输入端，最后一个N型MOS管的源极连接至第二分压单元32作为第一分压单元31的输出端，各N型MOS管的栅极均连接至第一个N型MOS管的漏极。
所述第二分压单元32为至少一个电阻，或至少一个P型MOS管，或至少一个N型MOS管中的任一种。
当第二分压单元32为至少一个电阻时，其结构如图5所示，所述至少一个电阻与相邻电阻首尾连接形成串联结构，第一个电阻连接至第一分压单元31作为第二分压单元32输入端，最后一个电阻接地作为第二分压单元32的输出端；
当第二分压单元32为至少一个P型MOS管时，其结构如图6所示，所述至少一个P型MOS管漏极端与相邻P型MOS管的源极端连接形成串联结构，第一个所述P型MOS管的源极连接至第一分压单元31作为第二分压单元32输入端，最后一个P型MOS管的漏极接地作为第二分压单元32的输出端,各P型MOS管 的栅极均连接至最后一个P型MOS管的漏极；
当第二分压单元32为至少一个N型MOS管时，其结构如图7所示，所述至少一个N型MOS管源极端与相邻N型MOS管的漏极端连接形成串联结构，第一个所述N型MOS管的漏极连接至第一分压单元31作为第二分压单元32输入端，最后一个N型MOS管的源极接地作为第二分压单元32的输出端，各N型MOS管的栅极均连接至第一个N型MOS管的漏极。
所述第一限流单元34为至少一个电阻，或至少一个P型MOS管，或至少一个N型MOS管中的任一种，
当第一限流单元34为至少一个电阻时，其结构如图5所示，所述至少一个电阻与相邻电阻首尾连接形成串联结构，第一个电阻连接至电源V1作为第一限流单元34输入端，最后一个电阻连接至阈值比较单元33作为第一限流单元34的输出端；
当第一限流单元34为至少一个P型MOS管时，其结构如图6所示，所述至少一个P型MOS管漏极端与相邻P型MOS管的源极端连接形成串联结构，第一个所述P型MOS管的源极连接至电源V1作为第一限流单元34输入端，最后一个P型MOS管的漏极连接至阈值比较单元33作为第一限流单元34的输出端,各P型MOS管的栅极均连接至最后一个P型MOS管的漏极；
当第一限流单元34为至少一个N型MOS管时，其结构如图7所示，所述至少一个N型MOS管源极端与相邻N型MOS管的漏极端连接形成串联结构，第一个所述N型MOS管的漏极连接至电源V1作为第一限流单元34输入端，最后一个N型MOS管的源极连接至阈值比较单元33作为第一限流单元34的输出端，各N型MOS管的栅极均连接至第一个N型MOS管的漏极。
上述第一分压单元、第二分压单元及第一限流单元可分别采用一个或一个以上的电阻或MOS管等阻抗性元件串连而成，且各实施例内，第一分压单元、第二分压单元及第一限流单元内所采用的阻抗性元件无需保持对称性，并且各单元内也可以任意选择一种或多种阻抗性元件串联连接。由于多个串联的MOS管沟道尺寸变长，其电阻值变大，因而具有较好的阻抗特性，并且其面积相对于同样阻抗的电阻要小的多，因此本发明优选的实施例为采用多个MOS管串联的结构。
所述阈值比较单元33为至少一个N型MOS管，其结构如图5-图8所示，所述N型MOS管栅极连接于第一分压单元31与第二分压单元32之间作为阈值比较单元33的控制端，其漏极通过第一限流单元34接入电流源V1作为阈值比较单元33的输入端，其源极接地作为阈值比较单元33的输出端。
同理，本发明所述阈值比较单元33还可以为两个或两个以上的N型MOS管串联连接而成，各N型MOS管源极端与相邻N型MOS管的漏极端连接形成串联结构，第一个所述N型MOS管的漏极通过第一限流单元34接入电流源V1作为阈值比较单元33的输入端，最后一个N型MOS管的源极接地作为阈值比较单元33的输出端，各N型MOS管的栅极均连接至第一分压单元31与第二分压单元32之间作为阈值比较单元33的控制端，如图9所示。采用此种多个N型MOS管串联连接的结构，加长了MOS管的沟道尺寸，使其宽长比缩小，可使该MOS管的翻转时间常数变长，延缓该阈值单元的翻转速度，从而达到降低输出电源纹波的目的，同时，由于MOS管的沟道尺寸变长，其电阻值增加，也可达到降低功耗及限流的作用。
当所述阈值比较单元33为P型MOS管时，其结构如图10所示，所述P型 MOS管栅极连接于第一分压单元31与第二分压单元32之间作为阈值比较单元33的控制端，其源极连接至电流源V1作为阈值比较单元33的输入端，其漏极通过第一限流单元34接地作为阈值比较单元33的输出端。
同样，本发明所述阈值比较单元还可将图10中所示的单个P型MOS管的结构改为采用多个P型MOS管的结构，其连接结构及原理在此不再赘述。
所述逻辑信号生成单元35为串接的奇数个反相器(当阈值比较单元为P型MOS管时，逻辑信号生成单元内串接的反相器数目为偶数个)，第一个反相器输入级连接于阈值比较单元与第一限流单元之间作为逻辑信号生成单元的输入端，最后一个反相器输出级VCTRL连接至整流电路放电通路的控制输入端，用于生成逻辑控制信号，控制整流电路的放电通路打开或关闭。
本发明所公开的技术方案可以表述为:射频识别标签的整流器从周围环境的电磁场能量中转换出直流电压V1，该电压V1输入至电源电压探测与判定电路3。设定第一分压单元的阻抗为R1，第二分压单元阻抗为R2，则第一及第二分压单元支路的电流值为：
I＝V1/(R1+R2)
则A点的电压值为
VA＝V1〃R2/(R1+R2)
即阈值比较单元控制端的电压值为
VGS＝VA＝V1〃R2/(R1+R2)
由上式可以看出，在各并联的电源电压探测与判定电路两端的电压值V1相同的情况下，可以通过设定第一及第二分压单元的阻抗比来达到控制阈值比较单元控制端的电压值，即控制各电源电压探测与判定电路的限幅点的目的。
作为一个实施实例，设定V1为3V，设定第一路电源电压探测与判定电路中，第一及第二分压单元的阻抗比R1:R2＝1:1，则VGS＝VA＝1.5V,高于阈值比较单元的阈值导通电压0.7V，则该路电源电压探测与判定电路的阈值比较单元导通，输出低电平信号至逻辑信号生成单元，逻辑信号生成单元内串接的奇数个反相器将该低电平信号输出为代表高电平逻辑信号的1，并将该高电平逻辑信号VCTRL1输入至与其连接的整流电路第一路放电通路的N型MOS管的栅极，将该N型MOS管导通，通过其源极将第一天线端与第二天线端之间的电荷输出至地，使得第一天线端与第二天线端之间的电荷量减小，则桥式整流电路整流出的直流电源Vdd_out减小，即负载电路两端的电压降低，达到对电路进行限幅的目的。
同理，设定第二路电源电压探测与判定电路中，第一及第二分压单元的阻抗比R1:R2＝1:2，则VGS＝VA＝2V,高于阈值比较单元的阈值导通电压0.7V，则该路电源电压探测与判定电路的阈值比较单元也导通，经过逻辑信号生成单元也生成代表高电平逻辑信号的1，则与其连接的整流电路第二路放电通路的N型MOS管导通开始放电。
设定第x路电源电压探测与判定电路中，第一及第二分压单元的阻抗比R1:R2＝4:1，则VGS＝VA＝0.6V,低于阈值比较单元的阈值导通电压0.7V，阈值比较单元截止，逻辑信号生成单元输出代表低电平逻辑信号的0，该低电平信号VCTRLx输入至与其连接的整流电路第x路放电通路N型MOS管的栅极，该N型MOS管不导通，则该路放电通路截止不放电。
本发明所述的并联的N型MOS管组成的放电通路与电源电压探测与判定电路的数目为x个，则放电通路打开与关闭的组合形式为2x种(x为自然数且大于等于2)，x的数值越大，放电通路的组合形式越多，则在限幅电压范围内的限 幅放电点越多，即限幅的精度越高。
同时，本发明所述的开关信号控制的整流与限幅电路，还可根据该控制回路的反应时间快慢的需求，将所述至少两路电源电压探测与判定电路的输出端分别通过延迟电路与所述至少两路放电通路的控制输入端连接。最简单的延迟电路的实施形式可以为一个由电阻器件和电容器件组合而成的低通滤波器构成。在反应时间要求最快的应用场合下，所述至少两路电源电压探测与判定电路的输出端可以直接与所述至少两路放电通路的控制输入端连接，但是实际应用中，一般会给控制回路一定的反应时间来避免N型MOS管这样的开关器件反复的跳变而使输出电源产生较大的纹波。
本发明实施例的另一目的在于提供一种包括上述开关信号控制的整流与限幅电路的无源射频标签。所述该射频标签内整流电路各路放电通路的N型MOS管的宽长比各不相同，因此各路放电通路的放电能力各不相同，并且各种组合的放电通路打开与关闭，使得该限幅电路的放电能力也各不相同，而各路放电通路N型MOS管的打开与关闭，取决于连接至其栅极端的输入控制信号VCTRL。因此，通过合理设计各电源电压探测与判定电路中第一及第二分压单元的阻抗比，使得各电路的VGS各不相同，即各电路阈值比较单元的导通电压各不相同，简而言之，将阈值导通电压较低的电源电压探测与判定电路连接至放电能力较弱的N型MOS管，将阈值导通电压最高的电源电压探测与判定电路连接至放电能力最强的N型MOS管。则，当标签的整流电路整流出的V1值过低时，所有的电源电压探测与判定电路限幅点均高于该V1值，则所有的电源电压探测与判定电路均截止，输出低电平信号使放电通路的N型MOS管处于截止，整流电路将天线端的全部电荷整流为直流电源供负载电路使用；当V1值过高时，具有较强放电能 力的N型MOS管被打开实现快速放电，实现对电路电压进行循环的动态整流控制，防止过高的电压击穿负载电路。

Claims (11)

  1. 一种开关信号控制的整流与限幅电路，其特征在于，所述电路包括：
    谐振电容，与谐振电感并联连接于第一天线端与第二天线端之间，用于与谐振电感组成谐振电路，接收外部电磁场并将其耦合至整流电路；
    整流电路，其输入端连接至第一天线端与第二天线端，用于将所述谐振电路耦合的交流电源转换为直流电源，所述整流电路的第一输出端输出至外部负载电路，其第二输出端输出至电源电压探测与判定电路，用于为电源电压探测与判定电路提供判定电压，其第三输出端通过至少两个并联的N型MOS管接地作为放电通路，用于在场强过强时将电荷输出至地；
    至少两路电源电压探测与判定电路，其电源输入端连接至所述整流电路第二输出端，其输出端连接至所述整流电路的至少两路放电通路的控制输入端，用于根据第一天线端与第二天线端之间的电荷量大小控制所述整流电路的放电通路打开或关闭，实现控制该输出端的漏电状态。
  2. 根据权利要求1所述的开关信号控制的整流与限幅电路，其特征在于，所述整流电路包括并联连接于第一天线端与第二天线端之间的第一整流支路，第二整流支路以及第三整流支路。
  3. 根据权利要求2所述的开关信号控制的整流与限幅电路，其特征在于，所述第二整流支路为连接于第一天线端与第二天线端之间的第五二极管和第六二极管，或者是连接于第一天线端与第二天线端之间的第五N型MOS管和第六N型MOS管，
    所述第五二极管和第六二极管阴极端连接至电源电压探测与判定电路输入端，用于为电源电压探测与判定电路提供判定电压；
    所述第五N型MOS管栅极和漏极分别连接至第一天线端，第六N型MOS管 栅极和漏极分别连接至第二天线端，第五N型MOS管源极连接至第六N型MOS管源极并输出至电源电压探测与判定电路输入端，用于为电源电压探测与判定电路提供判定电压。
  4. 根据权利要求2所述的开关信号控制的整流与限幅电路，其特征在于，所述第三整流支路为连接于第一天线端与第二天线端之间的第七二极管和第八二极管，或者是连接于第一天线端与第二天线端之间的第七N型MOS管和第八N型MOS管，
    所述第七二极管和第八二极管阴极端连接至所述至少两个并联的N型MOS管的漏极，所述至少两个并联的N型MOS管栅极分别连接至电源电压探测与判定电路的输出端，各N型MOS管的源极均接地，用于在场强过强时将电荷输出至地；
    所述第七N型MOS管栅极和漏极分别连接至第一天线端，第八N型MOS管栅极和漏极分别连接至第二天线端，第七N型MOS管源极连接至第八N型MOS管源极并连接至所述至少两个并联的N型MOS管的漏极，所述至少两个并联的N型MOS管栅极分别连接至电源电压探测与判定电路的输出端，各N型MOS管的源极均接地，用于在场强过强时将电荷输出至地。
  5. 根据权利要求1所述的开关信号控制的整流与限幅电路，其特征在于，所述电源电压探测与判定电路包括第一分压单元，第二分压单元，阈值比较单元，第一限流单元以及逻辑信号生成单元，
    所述第一分压单元与第二分压单元依次串接于电源端与地线之间，阈值比较单元控制端连接于第一分压单元与第二分压单元之间，其输入端通过第一限流单元接入电流源，其输出端接地，所述逻辑信号生成单元输入端连接于阈值 比较单元输入端与第一限流单元之间，用于生成逻辑控制信号，控制整流电路的放电通路打开或关闭。
  6. 根据权利要求5所述的开关信号控制的整流与限幅电路，其特征在于，所述第一分压单元为至少一个电阻，或至少一个P型MOS管，或至少一个N型MOS管中的任一种，
    所述至少一个电阻中，任一电阻与相邻电阻首尾连接形成串联结构，第一个电阻连接至电源作为第一分压单元输入端，最后一个电阻连接至第二分压单元作为第一分压单元的输出端；
    所述至少一个P型MOS管中，任一P型MOS管漏极端与相邻P型MOS管的源极端连接形成串联结构，第一个所述P型MOS管的源极连接至电源作为第一分压单元输入端，最后一个P型MOS管的漏极连接至第二分压单元作为第一分压单元的输出端,各P型MOS管的栅极均连接至最后一个P型MOS管的漏极；
    所述至少一个N型MOS管中，任一N型MOS管源极端与相邻N型MOS管的漏极端连接形成串联结构，第一个所述N型MOS管的漏极连接至电源作为第一分压单元输入端，最后一个N型MOS管的源极连接至第二分压单元作为第一分压单元的输出端，各N型MOS管的栅极均连接至第一个N型MOS管的漏极。
  7. 根据权利要求5所述的开关信号控制的整流与限幅电路，其特征在于，所述第二分压单元为至少一个电阻，或至少一个P型MOS管，或至少一个N型MOS管中的任一种，
    所述至少一个电阻中，任一电阻与相邻电阻首尾连接形成串联结构，第一个电阻连接至第一分压单元作为第二分压单元输入端，最后一个电阻接地作为第二分压单元的输出端；
    所述至少一个P型MOS管中，任一P型MOS管漏极端与相邻P型MOS管的源极端连接形成串联结构，第一个所述P型MOS管的源极连接至第一分压单元作为第二分压单元输入端，最后一个P型MOS管的漏极接地作为第二分压单元的输出端,各P型MOS管的栅极均连接至最后一个P型MOS管的漏极；
    所述至少一个N型MOS管中，任一N型MOS管源极端与相邻N型MOS管的漏极端连接形成串联结构，第一个所述N型MOS管的漏极连接至第一分压单元作为第二分压单元输入端，最后一个N型MOS管的源极接地作为第二分压单元的输出端，各N型MOS管的栅极均连接至第一个N型MOS管的漏极。
  8. 根据权利要求5所述的开关信号控制的整流与限幅电路，其特征在于，所述第一限流单元为至少一个电阻，或至少一个P型MOS管，或至少一个N型MOS管中的任一种，
    所述至少一个电阻中，任一电阻与相邻电阻首尾连接形成串联结构，第一个电阻连接至电源作为第一限流单元输入端，最后一个电阻连接至阈值比较单元作为第一限流单元的输出端；
    所述至少一个P型MOS管中，任一P型MOS管漏极端与相邻P型MOS管的源极端连接形成串联结构，第一个所述P型MOS管的源极连接至电源作为第一限流单元输入端，最后一个P型MOS管的漏极连接至阈值比较单元作为第一限流单元的输出端,各P型MOS管的栅极均连接至最后一个P型MOS管的漏极；
    所述至少一个N型MOS管中，任一N型MOS管源极端与相邻N型MOS管的漏极端连接形成串联结构，第一个所述N型MOS管的漏极连接至电源作为第一限流单元输入端，最后一个N型MOS管的源极连接至阈值比较单元作为第一限流单元的输出端，各N型MOS管的栅极均连接至第一个N型MOS管的漏极。
  9. 根据权利要求5所述的开关信号控制的整流与限幅电路，其特征在于，所述阈值比较单元为至少一个N型MOS管，
    所述至少一个N型MOS管中，任一N型MOS管源极端与相邻N型MOS管的漏极端连接形成串联结构，第一个所述N型MOS管的漏极通过第一限流单元接入电流源作为阈值比较单元的输入端，最后一个N型MOS管的源极接地作为阈值比较单元的输出端，各N型MOS管的栅极均连接于第一分压单元与第二分压单元之间作为阈值比较单元的控制端。
  10. 根据权利要求5所述的开关信号控制的整流与限幅电路，其特征在于，所述逻辑信号生成单元为串接的奇数个反相器，第一个反相器输入级连接于阈值比较单元与第一限流单元之间作为逻辑信号生成单元的输入端，最后一个反相器输出级连接至整流电路放电通路的控制输入端，用于生成逻辑控制信号，控制整流电路的放电通路打开或关闭。
  11. 一种无源射频标签，其特征在于，所述无源射频标签包括如权利要求1-10中任一所述的开关信号控制的整流与限幅电路。
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