WO2018000251A1 - 一种打印并口转换串口电路 - Google Patents

一种打印并口转换串口电路 Download PDF

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Publication number
WO2018000251A1
WO2018000251A1 PCT/CN2016/087712 CN2016087712W WO2018000251A1 WO 2018000251 A1 WO2018000251 A1 WO 2018000251A1 CN 2016087712 W CN2016087712 W CN 2016087712W WO 2018000251 A1 WO2018000251 A1 WO 2018000251A1
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Prior art keywords
pin
inverter
parallel port
pins
latch
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PCT/CN2016/087712
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English (en)
French (fr)
Inventor
黄新山
余华堂
程晓钟
曹静
丘文泽
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深圳市华阳信通科技发展有限公司
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Application filed by 深圳市华阳信通科技发展有限公司 filed Critical 深圳市华阳信通科技发展有限公司
Priority to PCT/CN2016/087712 priority Critical patent/WO2018000251A1/zh
Publication of WO2018000251A1 publication Critical patent/WO2018000251A1/zh

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure

Definitions

  • the present invention relates to a conversion circuit, and more particularly to a circuit for parallel port data conversion serial port data.
  • the printer mainly uses a parallel interface as a printer port, and uses a 25-pin D-line connector.
  • Parallel interface printers use 8-bit data to transmit through parallel lines. They also occupy 8 pins at the same time.
  • the transmission rate is much faster than the traditional serial interface, but the transmission quality of parallel transmission and the length of the parallel transmission route are very large. Relationships, the longer the route, the greater the interference, and the data is more prone to errors.
  • the serial interface generally requires only three pins to complete the data transfer, the wiring is simple, and the long-distance data transmission does not affect the transmission quality.
  • the present invention solves the problem of data transmission in a parallel interface by converting a simple circuit, and converting the parallel data of the printer into serial port data for transmission, thereby realizing the improvement of the transmission quality of the print data.
  • the utility model relates to a printing parallel port conversion serial port circuit, which is used for realizing printer parallel port data output by a serial port, the circuit comprises: a parallel port for inputting data; a micro control unit, which is connected with a serial port to realize data transmission; Inverter component for converting high and low level of connection pin; trigger for accurate data transmission; latch for latching and transmitting data from parallel port; serial port, for data
  • the output of the parallel port is connected to the inverter component, the latch and the micro control unit, and the micro control unit pin is connected to the serial port, the parallel port, the inverter component, the flip-flop and the latch pin.
  • Inverter component pins are connected to micro control unit, latch, flip-flop and parallel port pins, flip-flop pins It is connected to the inverter component and the micro processing unit pins, and the latch pins are connected to the parallel port, the inverter component and the micro control unit pins.
  • the inverter model is 74HC02
  • the inverter pin 2 and pin 3 pins are connected to the parallel port pin 1l
  • the inverter pin pin is connected to the latch pin pinl l and the trigger pin pin3.
  • the inverter pin5 and pin6 pins are connected to the micro processing unit pin PB1
  • the inverter pinl2 is connected to the micro processing unit pin PB0
  • the inverter pinl l is connected to the flip-flop pin 5
  • the inverter pinl3 and the inverter pin 8 are connected.
  • the trigger pinlO is connected to the parallel port pinl l.
  • the trigger model is HC74
  • the flip-flop pin 3 is connected to the inverter pin1
  • the flip-flop pin1 is connected to the inverter pin4
  • the flip-flop pin 5 is connected to the inverter pinl l
  • the trigger pin 6 and the micro control unit are connected.
  • PA0 is connected
  • the pin 2 of the flip-flop is connected to the pin 4 of the flip-flop, and the pull-up voltage is +3.3V.
  • the latch type is LC574A
  • the latches pin 2 to pin 9 are connected to the pin 2 to pin 9 of the parallel port one-to-one, wherein the pin number of the latch is the same as the pin number of the parallel port.
  • the latch pins pinl2 to pin9 are respectively connected to the microprocessor pins PB8 to PB15, the latch pin 11 is connected to the inverter pin1, and the latch pin1 is connected to the inverter pin4.
  • the micro control unit model is STM32F103X series
  • the micro control unit pins PC13, PC14, PC15 are respectively connected with the parallel port pins 1010, pinl5, pinl2
  • the micro control unit PAO is connected with the trigger pin6, and the micro processing unit is connected.
  • Pin PB1 is connected to the pin 5 and pin 6 of the inverter
  • the pin PB0 of the microprocessor unit is connected to the pin 2 of the inverter pin1.
  • the parallel port pins pin2 to pin9 and the latch pins pin2 to pin9 are connected to each other, and the parallel port pin is connected to the pinl3 pull-up voltage, wherein the pull-up voltage is +3.3V, and the parallel port pin 1 is the same.
  • the parallel port pinl l is connected to the inverter pin pinlO
  • the parallel port pinlO is connected to the micro control unit pin PC13
  • the parallel port pinl5 is connected to the micro control unit PC14.
  • Pin pinl2 is connected to micro control unit pin PC15.
  • the parallel data of the printer is converted into serial port data for transmission, thereby realizing the improvement of the transmission quality of the print data.
  • FIG. 1 is a structural block diagram of a print parallel port conversion serial port circuit according to an embodiment of the present invention
  • FIG. 2 is a flip-flop pin connection diagram of an embodiment of the present invention.
  • FIG. 3 is a pin connection diagram of an inverter according to an embodiment of the present invention.
  • FIG. 4 is a pin connection diagram of a latch of an embodiment of the present invention.
  • FIG. 5 is a pin connection diagram of a micro processing unit according to an embodiment of the present invention.
  • FIG. 6 is a parallel port pin connection diagram of an embodiment of the present invention.
  • FIG. 1 is a structural block diagram of a printed parallel port conversion serial port circuit, wherein the arrow represents the transmission of information and data of the previous component to the next component device.
  • the parallel port to the latch, the latch to the micro processing unit, the micro processing unit to the serial port for printing information, and the rest of the information is the control information of the previous component to the next component.
  • FIG. 2 to FIG. 6 are diagrams showing the connection of a flip-flop, an inverter, a latch, a micro-processing unit, and a parallel port pin to other device pins.
  • the specific operation is as follows: after the entire circuit is powered on, under the action of loading the compilable program, the micro-processing unit pins PC13, PC14 are set to a high potential, and the parallel port pinlO connected to the PC13 is at a high level, and the PC14
  • the connected parallel port pinl5 is high level, wherein the parallel port pinl5 is high level to indicate that the printer is faultless, the micro processing unit pin PC15 is set low, and the parallel port pinl2 connected to the micro processing unit is low level.
  • the parallel port pinl2 is low to indicate that the printer has paper.
  • the PB1 of the microprocessor unit is set to a high level delay of 1 microsecond to be low, and the inverter pin pin5 of the connection pin PB1 is connected to pin6, and the inverter pin pins 5 and p in6 are set low.
  • the inverter pin pin4 Under the action of the internal circuit of the inverter chip, the inverter pin pin4 is at a high level, and the flip-flop pin is at a high level. Since the flip-flop pin 4 is connected to the pull-up voltage, the flip-flop pin 4 is at a high level. Since the flip-flop pin1 is known to be at a high level, according to the known true trigger table, it can be found that the inverter pin 5 is low-powered. Flat, pin6 is high.
  • This ⁇ determines that the parallel port pinl l is low level, before the parallel port pinl is set to a high level, and the port pinl sends a negative pulse of not less than 1 microsecond, due to the action of the inverter, the inverter pin pinl and The flip-flop pin P in3 is connected, the latch pin pinl l generates a rising edge signal, the latch stores the print information, and the flip-flop pin 3 generates a rising edge signal, according to the true trigger of the known flip-flop The flip-flop pin 5 is at a high level and the flip-flop pin 6 is at a low level.
  • the flip-flop pin 6 Since the flip-flop pin 6 is connected to the pin PA0 of the micro-processing unit, the PA0 level changes from a high level to a low level, and a falling edge trigger is generated. Thereafter, the micro-processing unit starts collecting print f ⁇ information.
  • the micro processing unit sets the pin PB1 to a high level, PB0 is a high level, and the micro processing unit pin PB1 is connected to the inverter pins pin5 and pin6. Under the action of the inverter, the inverter pin4 Low, the flip-flop pin p inl is low. According to the known trigger true table, the trigger pin pin5 is low, and the flip-flop pi n5 is connected to the inverter pin pinl l.
  • PB0 of the micro processing unit is high level and is connected to the inverter pin pinl2, so that the inverter pin pinl3 is low, and the inverter pin pinl3 is connected with the inverter pins pin8 and pin 9.
  • the inverter pinlO is connected to the parallel port pinl l, and the parallel port pinlO can be obtained as a high level. It can be seen that the printer is in the working phase.
  • the inverter pin4 is low level
  • the latch pin pinl is connected to the inverter pin4, so the latch pinl is low level
  • the micro processing unit starts to read the print data in the latch, when the micro processing
  • the microprocessor unit PB0 is set low by the program
  • PB 1 is set to the high level
  • the inverter pin acts as the low level, indicating that the idle mode is printed.
  • the micro control unit outputs a negative pulse with a width greater than 5 microseconds, and the printer resumes its initial state, ready to accept the input of the next byte of print data.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Accessory Devices And Overall Control Thereof (AREA)

Abstract

一种打印并口转换串口电路,用于实现打印机并口数据由串口输出,所述电路包括:并口,用于数据的输入;微控制单元,与串口连接,实现数据的传输;反相器组件,用于对连接引脚高低电平实现转化;触发器,用于实现数据的准确传输;锁存器,用于对并口出来的数据进行锁存和传输;串口,用于数据的输出;并口引脚与反相器组件、锁存器和微控制单元引脚连接,微控制单元引脚与串口、并口、反相器组件、触发器和锁存器引脚连接,反相器组件引脚与微控制单元、锁存器、触发器和并口引脚连接,触发器引脚与反相器组件和微处理单元引脚连接,锁存器引脚与并口、反相器组件和微控制单元引脚连接。

Description

说明书 明名称:一种打印并口转换串口电路 技术领域
[0001] 本实用新型涉及一种转换电路, 特别是涉及一种并口数据转换串口数据的电路 背景技术
[0002] 现目前打印机主要还是采用并行接口作为打印机端口, 采用的是 25针 D行接头 。 并行接口打印机采用 8位数据同吋通过并行线进行传输, 同吋占用 8个管脚, 传输速率比传统的串行接口快很多, 但是并行传送的传输质量与并行传送的路 线长度有很大的关系, 路线越长, 干扰越大, 数据也更容易出现错误。 而串行 接口一般只需三个管脚的连接就能完成数据的传输, 接线简单, 且较长路线的 数据传输并不影响传输质量。
技术问题
问题的解决方案
技术解决方案
[0003] 基于上述问题, 本实用新型针对并行接口传输数据吋出现的问题通过简单电路 的转换, 实现打印机并口数据转换成串口数据进行传输, 实现了打印数据的传 输质量的提高。
[0004] 本实用新型一种打印并口转换串口电路, 用于实现打印机并口数据由串口输出 , 所述电路包括: 并口, 用于数据的输入; 微控制单元, 与串口连接, 实现数 据的传输; 反相器组件, 用于对连接引脚高低电平实现转化; 触发器, 用于实 现数据的准确传输; 锁存器, 用于对并口出来的数据进行锁存和传输; 串口, 用于数据的输出; 其中, 并口引脚与反相器组件、 锁存器和微控制单元引脚连 接, 微控制单元引脚与串口、 并口、 反相器组件、 触发器和锁存器引脚连接, 反相器组件引脚与微控制单元、 锁存器、 触发器和并口引脚连接, 触发器引脚 与反相器组件和微处理单元引脚连接, 锁存器引脚与并口、 反相器组件和微控 制单元引脚连接。
[0005] 进一步地, 反相器型号为 74HC02, 反相器 pin2和 pin3引脚与并口引脚 pinl连接 , 反相器 pinl引脚与锁存器引脚 pinl l和触发器引脚 pin3连接, 反相器 pin5和 pin6 引脚与微处理单元引脚 PB1连接, 反相器 pinl2与微处理单元引脚 PB0连接, 反相 器 pinl l与触发器 pin5连接, 反相器 pinl3与反相器 pin8和 pin9连接, 触发器 pinlO 与并口 pinl l连接。
[0006] 进一步地, 触发器型号为 HC74, 触发器 pin3与反相器 pinl连接, 触发器 pinl与 反相器 pin4连接, 触发器 pin5与反相器 pinl l连接, 触发器 pin6与微控制单元 PA0 连接, 触发器 pin2与触发器 pin4接上拉电压, 其中上拉电压为 +3.3V。
[0007] 进一步地, 锁存器型号为 LC574A, 锁存器 pin2至 pin9与并口的 pin2至 pin9进行 一对一连接, 其中连接方式为锁存器的引脚编号与并口的引脚编号保持一致, 锁存器引脚 pinl2至 pinl9分别与微处理器引脚 PB8至 PB15—对一连接, 锁存器 pin 11与反相器 pinl连接, 锁存器 pinl与反相器 pin4连接。
[0008] 进一步地, 微控制单元型号为 STM32F103X系列,微控制单元引脚 PC13、 PC14 、 PC15分别与并口引脚 pinl0、 pinl5、 pinl2连接, 微控制单元 PAO与触发器 pin6 连接, 微处理单元引脚 PB1与反相器 pin5和 pin6引脚连接, 微处理单元引脚 PB0 与反相器 pinl2连接。
[0009] 进一步地, 并口引脚 pin2至 pin9与锁存器引脚 pin2至 pin9—对一连接, 并口引脚 接 pinl3上拉电压, 其中上拉电压为 +3.3V, 并口引脚 1同吋连接反相器引脚 pin2 和 pin3, 并口引脚 pinl l与反相器引脚 pinlO连接, 并口引脚 pinlO与微控制单元引 脚 PC13连接, 并口引脚 pinl5与微控制单元 PC14连接, 并口引脚 pinl2与微控制 单元引脚 PC15连接。
发明的有益效果
有益效果
[0010] 本实施例实现打印机并口数据转换成串口数据进行传输, 实现了打印数据的传 输质量的提高。
对附图的简要说明 附图说明
[0011] 图 1是本发明实施例的打印并口转换串口电路的结构框图;
[0012] 图 2是本发明实施例的触发器引脚连接图;
[0013] 图 3是本发明实施例的反相器引脚连接图;
[0014] 图 4是本发明实施例的锁存器引脚连接图;
[0015] 图 5是本发明实施例的微处理单元引脚连接图;
[0016] 图 6是本发明实施例的并口引脚连接图。
[0017] 在上述附图中, 涉及到元器件引脚连接的, 上述各个元器件的编号引脚功能与 各个元器件的原理图中的相同编号引脚功能保持一致。
本发明的实施方式
[0018] 下面将结合本实用新型例中附图, 对本实用新型实施例中的技术方案清楚、 完 整的描述, 显然, 所描述的实施例仅仅为本实用新型一个实施例, 而不是全部 的实施例。 基于本实用新型实施例, 本领域技术人员在没有做出创造性劳动的 前提下所获得的所有其他实施例, 都属于本实用新型保护的范围。
[0019] 图 1为打印并口转换串口电路的结构框图, 其中箭头代表上一元器件对下一元 器件的信息及数据的传递。 其中, 并口至锁存器、 锁存器至微处理单元、 微处 理单元至串口为打印信息, 其余信息均为上一元器件对下一元器件的控制信息
[0020] 图 2至图 6分别为触发器、 反相器、 锁存器、 微处理单元、 并口的引脚与其他元 器件引脚的连接。 在实现打印信息通过转换电路由并口数据转换成串口数据之 前, 需将可编译程序导入微处理单元并进行调试成功。 当需要该转换电路工作 吋, 对该电路进行通电, 此吋微处理单元对该电路中部分元器件进行初始化, 初始化完成之后, 当有打印数据输出吋, 各元器件在加载在微处理单元里的可 编译程序的作用下, 对打印数据传递及各元器件管脚状态进行控制, 直至完成 打印数据的传递及转换。
[0021] 具体操作如下, 在整个电路通电之后, 在载入可编译程序的作用下, 微处理单 元引脚 PC13、 PC14置高电位, 与 PC13连接的并口引脚 pinlO为高电平, 与 PC14 连接的并口引脚 pinl5为高电平, 其中并口引脚 pinl5为高电平代表打印机无故障 , 微处理单元引脚 PC15置低电平, 与微处理单元连接的并口引脚 pinl2为低电平 , 并口引脚 pinl2为低电平代表打印机有纸张。 微处理单元的 PB1置高电平延迟 1 微秒置低电平, 连接引脚 PB1的反相器引脚 pin5与 pin6连接, 此吋反相器引脚 pin 5与 pin6同置低电平, 在反相器芯片内部电路作用下, 反相器引脚 pin4为高电平 , 触发器 pinl为高电平。 由于触发器 pin4接上拉电压, 因此触发器 pin4为高电平 , 由于已知触发器 pinl为高电平, 根据已知的该触发器真指表, 可以得出反相器 pin5为低电平, pin6为高电平。
[0022] 此吋确定并口 pinl l为低电平, 之前并口 pinl置高电平, 并口 pinl发出一个不低 于 1微秒的负脉冲, 由于反相器的作用, 反相器引脚 pinl与触发器引脚 Pin3连接 , 锁存器引脚 pinl l产生一个上升沿信号, 锁存器将打印信息储存起来, 同吋触 发器 pin3产生一个上升沿信号, 根据已知触发器的真指表, 触发器 pin5为高电平 , 触发器 pin6为低电平。 由于触发器 pin6连接微处理单元的引脚 PA0, PA0电平 由高电平变为低电平, 产生一个下降沿触发, 此吋, 微处理单元幵始收集打印 f π息。
[0023] 微处理单元此吋设置引脚 PB1为高电平, PB0为高电平, 微处理单元引脚 PB1连 接反相器引脚 pin5与 pin6, 在反相器作用下, 反相器 pin4为低电平, 触发器引脚 p inl为低电平, 根据已知触发器真指表, 得出触发器引脚 pin5为低电平, 触发器 pi n5与反相器引脚 pinl l连接, 微处理单元的 PB0为高电平且与反相器引脚 pinl2连 接, 可得到反相器引脚 pinl3为低电平, 反相器引脚 pinl3与反相器引脚 pin8和 pin 9连接, 反相器 pinlO与并口引脚 pinl l连接, 可以得到并口引脚 pinlO为高电平, 由此可知, 打印机处于工作阶段。 反相器 pin4为低电平, 锁存器引脚 pinl与反相 器 pin4连接, 因此锁存器 pinl为低电平, 微处理单元幵始读取锁存器中的打印数 据, 当微处理单元接受完数据后, 通过程序将微处理单元 PB0置低电平, PB 1置 高电平, 通过反相器作用, 并口 pinl l为低电平, 表明打印空闲模式。 再通过程 序控制, 微控制单元输出一个宽度大于 5微秒的负脉冲, 打印机恢复初始状态, 准备接受下一字节的打印数据的输入。
[0024] 由上所述, 仅为本实用新型的具体实施方式, 但本实用新型的保护范围并不局 限与此, 任何熟悉本技术领域的技术人员在本实用新型揭露的技术范围内, 可 轻易想到变化或替换, 都应涵盖在本实用新型的保护范围之内。 因此, 本实用 新型的保护范围以权力要求的保护范围为准。

Claims

权利要求书
[权利要求 1] 一种打印并口转换串口电路, 用于实现打印机并口数据由串口输出, 其特征在于, 所述电路包括:
并口, 用于数据的输入;
微控制单元, 与串口连接, 实现数据的传输;
反相器组件, 用于对连接引脚高低电平实现转化; 触发器, 用于实现数据的准确传输;
锁存器, 用于对并口出来的数据进行锁存和传输; 串口, 用于数据的输出;
其中, 并口引脚与反相器组件、 锁存器和微控制单元引脚连接, 微控 制单元引脚与串口、 并口、 反相器组件、 触发器和锁存器引脚连接, 反相器组件引脚与微控制单元、 锁存器、 触发器和并口引脚连接, 触 发器引脚与反相器组件和微处理单元引脚连接, 锁存器引脚与并口、 反相器组件和微控制单元引脚连接。
[权利要求 2] 如权利要求 1所述的一种打印并口转换串口电路, 其特征在于, 反相 器型号为 74HC02, 反相器 pin2和 pin3引脚与并口引脚 pinl连接, 反相 器 pinl引脚与锁存器弓 I脚 pinl 1和触发器弓 I脚 pin3连接, 反相器 pin5和 pin6弓 I脚与微处理单元弓 I脚 PB 1连接, 反相器 pinl2与微处理单元弓 |脚 PB0连接, 反相器 pinl l与触发器 pin5连接, 反相器 pin 13与反相器 pin8 和 pin9连接, 触发器 pinlO与并口 pinl l连接。
[权利要求 3] 如权利要求 1所述的一种打印并口转换串口电路, 其特征在于, 触发 器型号为 HC74, 触发器 pin3与反相器 pinl连接, 触发器 pinl与反相器 pin4连接, 触发器 pin5与反相器 pinl l连接, 触发器 pin6与微控制单元 PA0连接, 触发器 pin2与触发器 pin4接上拉电压, 其中上拉电压为 +3. 3V。
[权利要求 4] 如权利要求 1所述的一种打印并口转换串口电路, 其特征在于, 锁存 器型号为 LC574A, 锁存器 pin2至 pin9与并口的 pin2至 pin9进行一对一 连接, 其中连接方式为锁存器的引脚编号与并口的引脚编号保持一致 , 锁存器引脚 pinl2至 pinl9分别与微处理器引脚 PB8至 PB15—对一连 接, 锁存器 pinl l与反相器 pinl连接, 锁存器 pinl与反相器 pin4连接。
[权利要求 5] 如权利要求 1所述的一种打印并口转换串口电路, 其特征在于, 微控 制单元型号为 STM32F103X系列,微控制单元引脚 PC13、 PC 14. PC15 分别与并口引脚 pinl0、 pinl5、 pinl2连接, 微控制单元 PA0与触发器 pin6连接, 微处理单元引脚 PB1与反相器 pin5和 pin6引脚连接, 微处理 单元引脚 PB0与反相器 pinl2连接。
[权利要求 6] 如权利要求 1所述的一种打印并口转换串口电路, 其特征在于,
并口引脚 pin2至 pin9与锁存器弓 |脚 pin2至 pin9—对一连接, 并口引脚 接 pinl3上拉电压, 其中上拉电压为 +3.3V, 并口引脚 1同吋连接反相 器引脚 pin2和 pin3, 并口引脚 pinl l与反相器引脚 pinlO连接, 并口引 脚 pinlO与微控制单元引脚 PC13连接, 并口引脚 pinl5与微控制单元 PC 14连接, 并口引脚 pinl2与微控制单元引脚 PC15连接。
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