WO2017206624A1 - 走线结构、阵列基板及其制备方法、显示面板 - Google Patents
走线结构、阵列基板及其制备方法、显示面板 Download PDFInfo
- Publication number
- WO2017206624A1 WO2017206624A1 PCT/CN2017/081633 CN2017081633W WO2017206624A1 WO 2017206624 A1 WO2017206624 A1 WO 2017206624A1 CN 2017081633 W CN2017081633 W CN 2017081633W WO 2017206624 A1 WO2017206624 A1 WO 2017206624A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- metal
- trace
- metal trace
- array substrate
- thin film
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 58
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 256
- 239000002184 metal Substances 0.000 claims abstract description 256
- 238000000034 method Methods 0.000 claims description 30
- 239000010409 thin film Substances 0.000 claims description 29
- 239000000463 material Substances 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 11
- 239000000956 alloy Substances 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 5
- 229910044991 metal oxide Inorganic materials 0.000 claims description 5
- 150000004706 metal oxides Chemical class 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/80—Constructional details
- H10K50/805—Electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
- H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/17—Passive-matrix OLED displays
- H10K59/179—Interconnections, e.g. wiring lines or terminals
- H10K59/1795—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
Definitions
- the present invention relates to the field of display technologies, and in particular, to a trace structure, an array substrate, a preparation method thereof, and a display panel.
- the narrow border of the display panel is realized, which is generally to reduce the distribution area of the trace structure by reducing the line width of the trace structure around the display panel, thereby reducing the width of the border.
- the line width of the trace structure is reduced, the resistance of the trace structure becomes large, which is disadvantageous for signal conduction.
- Embodiments of the present invention provide a trace structure, an array substrate, a method for fabricating the same, and a display panel, which can reduce the resistance of the trace structure while reducing the line width of the trace structure.
- a trace structure including a first metal trace and a second metal trace stacked in a stack; wherein the first metal trace and the second metal trace are in direct contact .
- the line width of the first metal trace and the second metal trace are the same, and the projection of the first metal trace and the second metal trace on a plane perpendicular to the stacking direction is completely overlapping.
- the line width of the first metal trace and the second metal trace The line width is 5 to 50 ⁇ m.
- the material of the first metal trace and the second metal trace is selected from at least one of a metal element, an alloy, and a metal oxide.
- an array substrate including the above-described trace structure.
- the array substrate further includes an insulating layer; wherein the first metal trace and the insulating layer are disposed in the same layer.
- the routing structure is disposed at an edge region of the array substrate.
- the array substrate includes a thin film transistor and a first electrode; the first metal trace and the second metal trace are formed in synchronization with the thin film transistor; or the first metal trace and the The second metal trace is formed in synchronization with the thin film transistor and the first electrode.
- the array substrate includes a thin film transistor, a pixel electrode, and a common electrode; the first metal trace and the second metal trace are formed in synchronization with the thin film transistor and the common electrode; or The first metal trace and the second metal trace are formed in synchronization with the pixel electrode and the common electrode.
- a display panel including the above array substrate.
- a fourth aspect provides a method for fabricating an array substrate, comprising: forming a first metal pattern, wherein a region where the first metal pattern is located corresponds to a region where a trace structure to be formed exists; forming an insulating layer, and removing the region by an etching process a material of the insulating layer on the first metal pattern; and forming a second metal pattern, forming a plurality of trace structures by an etching process, each of the trace structures including the stacked first metal traces and Two metal traces.
- the step of forming the first metal pattern comprises: forming a first metal layer, and performing an etching process on the first metal layer to form a first metal pattern.
- Embodiments of the present invention provide a trace structure, an array substrate, a method for fabricating the same, and a display panel. Since the trace structure includes stacked first metal traces and second metal traces, even if the line width of the trace structure is reduced The increase in the resistance of the trace structure is also small. On the basis of this, since the first metal trace and the second metal trace are in direct contact, the contact resistance between the first metal trace and the second metal trace can be greatly reduced, thereby further reducing the trace Structural resistance. Therefore, the embodiment of the present invention can reduce the resistance of the trace structure while reducing the line width of the trace structure.
- FIG. 1 is a schematic structural diagram of a trace structure according to an embodiment of the present invention.
- FIG. 2 is a schematic structural diagram of an array substrate including a trace structure according to an embodiment of the present invention
- FIG. 3 is a schematic flow chart of a method for preparing an array substrate according to an embodiment of the present invention.
- FIG. 4(a) is a schematic structural view of forming a first metal pattern according to an embodiment of the present invention.
- 4(b) is a schematic structural view showing forming an insulating layer on a first metal pattern according to an embodiment of the present invention
- 4(c) is a schematic structural view of removing an insulating layer material on a first metal pattern according to an embodiment of the present invention
- 4(d) is a schematic structural view showing formation of a second metal pattern on a first metal pattern according to an embodiment of the present invention
- FIG. 4(e) is a schematic structural diagram of forming a first metal trace and a second metal trace according to an embodiment of the present invention.
- 01-wire structure 01-wire structure; 10-first metal trace; 101-first metal pattern; 20-second metal trace; 102-second metal pattern; 30-substrate; 40-insulation layer.
- An embodiment of the present invention provides a trace structure 01, as shown in FIGS. 1 and 2.
- Figure 1 shows a partial cross-sectional view of the trace structure 01 of Figure 2.
- the trace structure 01 includes a first metal trace 10 and a second metal trace 20 stacked in a stack; wherein the first metal trace 10 and the first The two metal traces 20 are in direct contact.
- the materials of the first metal trace 10 and the second metal trace 20 are not limited as long as the signal can be transmitted.
- the material of the first metal trace 10 may be the same as the material of the second metal trace 20 .
- the material of the first metal trace 10 and the material of the second metal trace 20 may also be different.
- the line width of the first metal trace 10 and the line width of the second metal trace 20 may be the same or different.
- the first metal trace 10 may be formed by a patterning process, and then the second metal trace 20 may be formed by a patterning process.
- the first metal trace 10 is first formed, in order to ensure that the first metal trace 10 and the second metal trace 20 can be contacted when the second metal trace 20 is fabricated, the first metal is optionally taken.
- the line width of the line 10 is greater than the line width of the second metal trace 20.
- first metal trace 10 and the second metal trace 20 are in direct contact, that is, the first metal trace 10 and the second metal trace 20 are in close contact and are in electrical contact, and the first metal trace 10 No film layer is provided between the second metal trace 20.
- the trace structure 01 since the trace structure 01 includes the stacked first metal traces 10 and the second metal traces 20, even if the line width of the trace structure 01 is reduced, the trace structure 01 The increase in resistance is also small. On the basis of this, since the first metal trace 10 and the second metal trace 20 are in direct contact, the contact resistance between the first metal trace 10 and the second metal trace 20 can be greatly reduced, thereby Further reduce the resistance of the trace structure 01. Therefore, the embodiment of the present invention can reduce the resistance of the trace structure 01 while reducing the line width of the trace structure 01.
- the first metal trace 10 and the second metal trace 20 have the same line width, and the first metal trace 10 and the second metal trace 20 are perpendicular to the stacking direction.
- the projections on the plane are completely overlapping.
- the first metal trace 10 and the second metal trace 20 have the same line width, and the first metal trace 10 and the second metal trace 20 are on a plane perpendicular to the stacking direction.
- the projections are completely overlapped, so that when the first metal traces 10 and the second metal traces 20 are formed, they can be simultaneously formed by one patterning process, which simplifies the fabrication process of the first metal traces 10 and the second metal traces 20.
- first metal trace 10 and the second The metal traces 20 have the same line width, and the projections of the first metal traces 10 and the second metal traces 20 on a plane perpendicular to the stacking direction completely overlap, and the first metal traces 10 and the second metal The traces 20 can be directly aligned between the traces 20, so that it is not necessary to reserve a certain spacing between the respective trace structures 01 (each of the trace structures 01 including the first metal traces 10 and the second metal traces 20). The alignment accuracy between the first metal trace 10 and the second metal trace 20 is ensured. Therefore, the spacing between the individual trace structures 01 in the embodiment of the present invention can be set smaller, thereby reducing the distribution area of the trace structure 01.
- the signal may not be transmitted; if the line width of the first metal trace 10 and the second metal trace 20 is too large, it may be made
- the trace structure 01 has a large distribution area. Therefore, in order to ensure that the first metal trace 10 and the second metal trace 20 can transmit signals, the distribution area of the trace structure 01 can be reduced.
- the line width and the second trace of the first metal trace 10 The metal traces 20 have a line width of 5 to 50 ⁇ m.
- the material of the first metal trace 10 and the second metal trace 20 is selected from at least one of a metal element, an alloy, and a metal oxide.
- a metal element for example, Mo (molybdenum), Cu (copper), Ag (silver), or IZO (Indium Zinc Oxide) can be used.
- Embodiments of the present invention provide an array substrate including the above-described trace structure.
- the array substrate further includes an insulating layer 40 ; wherein the first metal trace 10 and the insulating layer 40 are disposed in the same layer.
- the number of the routing structures 01 on the array substrate is not limited, and may be correspondingly set according to signals to be transmitted on the array substrate.
- the first metal trace 10 and the display element in the same layer as the first metal trace 10 are formed, the first metal trace 10 and the first metal trace 10 are required for process reasons.
- An insulating layer is formed on the display element of the same layer. In order to make the first metal trace 10 and the second metal trace 20 directly contact, the insulating layer formed on the first metal trace 10 needs to be removed, so that between the first metal trace 10 and the second metal trace 20 The insulation layer is hollowed out.
- the trace structure 01 of the array substrate includes the stacked first metal traces 10 and the second metal traces 20, even if the line width of the trace structure 01 is reduced, the trace structure The increase in resistance of 01 is also small.
- the first metal trace 10 and the second metal trace 20 are in direct contact, the contact resistance between the first metal trace 10 and the second metal trace 20 can be greatly reduced, thereby Further Reduce the resistance of the trace structure 01. Therefore, the embodiment of the present invention can reduce the resistance of the trace structure 01 while reducing the line width of the trace structure 01.
- the trace structure 01 is disposed at an edge region of the array substrate.
- the intermediate portion of the array substrate may be provided with display elements.
- the trace structure 01 in the embodiment of the present invention is disposed in the edge region of the array substrate, that is, the trace structure 01 of the edge region of the array substrate includes the stacked first metal traces 10 and the second metal traces 20, even if it is reduced
- the line width of the trace structure 01 the increase in the resistance of the trace structure 01 is also small.
- the first metal trace 10 and the second metal trace 20 are in direct contact, the contact resistance between the first metal trace 10 and the second metal trace 20 can be greatly reduced, thereby Further reduce the resistance of the trace structure 01. Therefore, the array substrate of the embodiment of the present invention can reduce the resistance of the trace structure 01 while reducing the line width of the trace structure 01.
- the array substrate comprises a thin film transistor and a first electrode
- the first metal trace 10 and the second metal trace 20 are formed in synchronization with the thin film transistor.
- the first metal trace 10 and the second metal trace 20 are formed in synchronization with the thin film transistor and the first electrode.
- the thin film transistor includes a gate, an insulating layer, a semiconductor layer, a source, and a drain.
- the array substrate is a liquid crystal display (LCD) array substrate
- the first electrode is a pixel electrode
- the pixel electrode is electrically connected to a drain of the thin film transistor.
- Further array substrates may also include a common electrode.
- the array substrate is an array substrate of an Organic Light-Emitting Diode (OLED) display
- the first electrode is an anode, and the anode is electrically connected to a drain of the thin film transistor.
- the array substrate further includes a functional layer of an organic material and a cathode.
- the first metal trace 10 and the second metal trace 20 are formed in synchronization with the thin film transistor, that is, the first metal trace 10 and the second metal trace 20 and the gate, source and drain of the thin film transistor Any two synchronizations are formed.
- the first metal trace 10 and the second metal trace 20 are formed in synchronization with the thin film transistor and the first electrode, that is, the first metal trace 10 is formed in synchronization with any one of the gate, the source and the drain of the thin film transistor, and the second The metal trace 20 is formed in synchronization with the first electrode.
- the first metal trace 10 is formed in synchronization with the first electrode
- the second metal trace 20 is formed in synchronization with any one of the gate, the source and the drain of the thin film transistor.
- the first metal trace 10 and the second metal trace 20 may be formed in synchronization with the thin film transistor, or the first metal trace 10 and the second metal trace 20 may be synchronized with the thin film transistor and the first electrode. Formed, which simplifies the fabrication of the array substrate Process.
- the array substrate comprises a thin film transistor, a pixel electrode and a common electrode; the first metal trace 10 and the second metal trace 20 are formed in synchronization with the thin film transistor and the common electrode.
- the first metal trace 10 and the second metal trace 20 are formed in synchronization with the pixel electrode and the common electrode.
- the first metal trace 10 and the second metal trace 20 are formed in synchronization with the thin film transistor and the common electrode, that is, any of the gate, source or drain of the first metal trace 10 and the thin film transistor.
- One is formed synchronously, the second metal trace 20 is formed in synchronization with the common electrode; or the first metal trace 10 is formed in synchronization with the common electrode, and the second metal trace 20 and any of the gate, source or drain of the thin film transistor A simultaneous formation.
- the first metal trace 10 and the second metal trace 20 are formed in synchronization with the pixel electrode and the common electrode, that is, the first metal trace 10 is formed in synchronization with the pixel electrode, and the second metal trace 20 is formed in synchronization with the common electrode, or first.
- the metal trace 10 is formed in synchronization with the common electrode, and the second metal trace 20 is formed in synchronization with the pixel electrode.
- the first metal trace 10 and the second metal trace 20 may be formed in synchronization with the thin film transistor and the common electrode; or the first metal trace 10 and the second metal trace 20 may be combined with the first electrode. It is formed in synchronization with the common electrode, which simplifies the fabrication process of the array substrate.
- Embodiments of the present invention provide a display panel including the above array substrate.
- the trace structure 01 of the display panel includes the stacked first metal traces 10 and the second metal traces 20, even if the line width of the trace structure 01 is reduced, the trace structure The increase in resistance of 01 is also small.
- the contact resistance between the first metal trace 10 and the second metal trace 20 can be greatly reduced, thereby Further reduce the resistance of the trace structure 01. Therefore, the display panel of the embodiment of the present invention can reduce the resistance of the trace structure 01 while reducing the line width of the trace structure 01.
- the embodiment of the invention further provides a method for preparing an array substrate, as shown in FIG. 3, comprising:
- a first metal pattern 101 is formed, and a region where the first metal pattern 101 is located corresponds to a region where the trace structure to be formed is located.
- the step of forming the first metal pattern comprises: forming a first metal layer, and performing an etching process on the first metal layer to form a first metal pattern.
- the material of the first metal pattern 101 is not limited, and the material of the first metal pattern 101 may be selected from at least one of a metal element, an alloy, and a metal oxide.
- a metal element such as Mo, Cu, Ag, IZO, or the like.
- the first metal pattern 101 is formed on the substrate 30, and for other structures on the substrate 30, FIG. 4(a) is not illustrated.
- the first metal pattern is formed on the substrate 30 is not limited, and may be formed, for example, by a chemical vapor deposition method or an evaporation process.
- the material of the insulating layer 40 is not limited, and may be, for example, one of SiN (silicon oxide) or SiO (silicon oxide), silicon oxynitride (SiO x N y ), or silicon carbonitride (SiC x N y ). kind or several.
- each trace structure 01 includes a stacked first layer.
- Metal trace 10 and second metal trace 20 are formed by an etching process.
- the material of the second metal pattern 102 is not limited, and the material of the second metal pattern 102 may be selected from at least one of a metal element, an alloy, and a metal oxide. For example, it may be Mo, Cu, Ag, IZO, or the like. The material of the second metal pattern 102 may be the same as or different from the first metal pattern 101.
- the line width and the number of the first metal traces 10 and the second metal traces 20 are not limited, and may be etched according to the needs of the array substrate. For the spacing between the trace structures 01, the trace structures 01 can be separated.
- the area where the first metal trace 10 and the second metal trace 20 are in contact can be maximized, thereby being greatly reduced.
- the contact resistance between the first metal trace 10 and the second metal trace 20 can reduce the line width of the trace structure 01.
- the embodiment of the present invention provides a method for fabricating an array substrate. Since the trace structure 01 of the array substrate includes the stacked first metal traces 10 and the second metal traces 20, even if the line width of the trace structure 01 is reduced, The increase in the resistance of the trace structure 01 is also small. On the basis of this, since the first metal trace 10 and the second metal trace 20 are in direct contact, the contact resistance between the first metal trace 10 and the second metal trace 20 can be greatly reduced, thereby Further reduce the resistance of the trace structure 01. Therefore, the embodiment of the present invention is reducing the walking When the line structure 01 is wide, the resistance of the trace structure 01 can be reduced.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Thin Film Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明实施例提供一种走线结构、阵列基板及其制备方法、显示面板，涉及显示技术领域，可在减小走线结构线宽的同时，降低走线结构的电阻。该走线结构包括层叠设置的第一金属走线和第二金属走线；其中，所述第一金属走线和所述第二金属走线直接接触。本发明实施例可用于阵列基板。
Description
相关申请
本申请要求保护在2016年6月1日提交的申请号为201610383827.4的中国专利申请的优先权，该申请的全部内容以引用的方式结合到本文中。
本发明涉及显示技术领域，尤其涉及一种走线结构、阵列基板及其制备方法、显示面板。
随着显示技术的快速发展，显示面板已应用于各种尺寸的显示装置中。消费者除了要求显示面板有良好的显示性能外，对外观美感的追求也逐渐提高。其中，窄边框显示面板，以使显示面板具有更轻薄短小的特性，已成为消费者追求的目标之一。
目前实现显示面板的窄边框，通常是通过减少显示面板周边走线结构的线宽来减小走线结构的分布面积，从而减小边框的宽度。然而，由于走线结构线宽的减小会使得走线结构的电阻变大，因而不利于信号的传导。
发明内容
本发明的实施例提供一种走线结构、阵列基板及其制备方法、显示面板，可在减小走线结构线宽的同时，降低走线结构的电阻。
为达到上述目的，本发明的实施例采用如下技术方案：
第一方面，提供一种走线结构，所述走线包括层叠设置的第一金属走线和第二金属走线；其中，所述第一金属走线和所述第二金属走线直接接触。
可选的，所述第一金属走线和所述第二金属走线的线宽相同，所述第一金属走线和所述第二金属走线在垂直于层叠方向的平面上的投影完全重叠。
进一步可选的，所述第一金属走线的线宽和所述第二金属走线的
线宽均为5～50μm。
可选的，所述第一金属走线和所述第二金属走线的材料选自金属单质、合金、金属氧化物中的至少一种。
第二方面，提供一种阵列基板，包括上述的走线结构。
可选的，所述阵列基板还包括绝缘层；其中所述第一金属走线和所述绝缘层同层设置。
可选的，所述走线结构设置在所述阵列基板的边缘区域。
可选的，所述阵列基板包括薄膜晶体管和第一电极；所述第一金属走线和所述第二金属走线与所述薄膜晶体管同步形成；或者，所述第一金属走线和所述第二金属走线与所述薄膜晶体管和所述第一电极同步形成。
可选的，所述阵列基板包括薄膜晶体管、像素电极和公共电极；所述第一金属走线和所述第二金属走线与所述薄膜晶体管和所述公共电极同步形成；或者，所述第一金属走线和所述第二金属走线与所述像素电极和所述公共电极同步形成。
第三方面，提供一种显示面板，包括上述的阵列基板。
第四方面，提供一种阵列基板的制备方法，包括：形成第一金属图案，所述第一金属图案所在区域与待形成的走线结构所在区域对应；形成绝缘层，通过刻蚀工艺去除所述第一金属图案上的所述绝缘层的材料；以及，形成第二金属图案，通过刻蚀工艺形成多个走线结构，每个所述走线结构包括层叠的第一金属走线和第二金属走线。
可选的，形成第一金属图案的步骤包括：形成第一金属层，并对所述第一金属层执行蚀刻工艺，从而形成第一金属图案。
本发明实施例提供一种走线结构、阵列基板及其制备方法、显示面板，由于走线结构包括层叠的第一金属走线和第二金属走线，因而即使减小走线结构的线宽，走线结构电阻的增加幅度也较小。在此基础上，由于第一金属走线和第二金属走线直接接触，使得第一金属走线和第二金属走线之间的接触电阻便可以大幅度减小，从而可以进一步降低走线结构电阻。因此，本发明实施例在减小走线结构线宽的同时，能够降低走线结构的电阻。
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种走线结构的结构示意图；
图2为本发明实施例提供的一种阵列基板包括走线结构的结构示意图；
图3为本发明实施例提供的一种阵列基板的制备方法的流程示意图；
图4(a)为本发明实施例提供的形成第一金属图案的结构示意图；
图4(b)为本发明实施例提供的在第一金属图案上形成绝缘层的结构示意图；
图4(c)为本发明实施例提供的去除第一金属图案上的绝缘层材料的结构示意图；
图4(d)为本发明实施例提供的在第一金属图案上形成第二金属图案的结构示意图；以及
图4(e)为本发明实施例提供的形成第一金属走线和第二金属走线的结构示意图。
附图标记：
01-走线结构；10-第一金属走线；101-第一金属图案；20-第二金属走线；102-第二金属图案；30-基板；40-绝缘层。
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供一种走线结构01，如图1和图2所示。图1示出了图2中走线结构01的局部剖面视图。走线结构01包括层叠设置的第一金属走线10和第二金属走线20；其中，第一金属走线10和第
二金属走线20直接接触。
需要说明的是，第一，对于第一金属走线10和第二金属走线20的材料不进行限定，只要能传导信号即可。其中，第一金属走线10的材料可以和第二金属走线20的材料相同，当然第一金属走线10的材料和第二金属走线20的材料也可以不相同。
第二，第一金属走线10的线宽和第二金属走线20的线宽可以相同，也可以不相同。
当第一金属走线10的线宽和第二金属走线20的线宽不相同时，可以先通过构图工艺形成第一金属走线10，再通过构图工艺形成第二金属走线20。此处，由于第一金属走线10先制作，为了在制作第二金属走线20时，便于确保第一金属走线10和第二金属走线20能够接触，可选地，第一金属走线10的线宽大于第二金属走线20的线宽。当第一金属走线10的线宽和第二金属走线20的线宽相同时，可以通过构图工艺同时形成第一金属走线10和第二金属走线20。
第三，第一金属走线10和第二金属走线20直接接触，即指第一金属走线10和第二金属走线20是紧挨的并且是电接触的，第一金属走线10和第二金属走线20之间不设置任何膜层。
本发明实施例提供的走线结构01中，由于走线结构01包括层叠的第一金属走线10和第二金属走线20，因而即使减小走线结构01的线宽，走线结构01电阻的增加幅度也较小。在此基础上，由于第一金属走线10和第二金属走线20直接接触，使得第一金属走线10和第二金属走线20之间的接触电阻便可以大幅度减小，从而可以进一步降低走线结构01电阻。因此，本发明实施例在减小走线结构01线宽的同时，能够降低走线结构01的电阻。
可选的，如图1所示，第一金属走线10和第二金属走线20的线宽相同，所述第一金属走线10和所述第二金属走线20在垂直于层叠方向的平面上的投影完全重叠。
本发明实施例中，第一金属走线10和第二金属走线20的线宽相同，所述第一金属走线10和所述第二金属走线20在垂直于层叠方向的平面上的投影完全重叠，这样在制作第一金属走线10和第二金属走线20时，可以通过一次构图工艺同时形成，简化了第一金属走线10和第二金属走线20的制作工艺。进一步地，第一金属走线10和第二
金属走线20的线宽相同，所述第一金属走线10和所述第二金属走线20在垂直于层叠方向的平面上的投影完全重叠，则第一金属走线10和第二金属走线20之间可以直接对位，因而不需要在各个走线结构01(每个走线结构01包括第一金属走线10和第二金属走线20)之间预留一定的间距，以确保第一金属走线10和第二金属走线20之间的对位精度。因此，本发明实施例各个走线结构01之间的间距可以设置的更小，从而减小走线结构01分布面积。
如果第一金属走线10和第二金属走线20的线宽太小，可能会导致不能传递信号；如果第一金属走线10和第二金属走线20的线宽太大，可能会使得走线结构01分布面积较大。因此，为了确保第一金属走线10和第二金属走线20既可以传递信号，又可以减小走线结构01的分布面积，可选的，第一金属走线10的线宽和第二金属走线20的线宽均为5～50μm。
可选的，第一金属走线10和第二金属走线20的材料选自金属单质、合金、金属氧化物中的至少一种。例如可以使用Mo(钼)、Cu(铜)、Ag(银)或IZO(Indium Zinc Oxide，氧化铟锌)等。
本发明实施例提供一种阵列基板，包括上述的走线结构。
可选的，如图4(e)所示，所述阵列基板还包括绝缘层40；其中所述第一金属走线10和所述绝缘层40同层设置。
其中，对于阵列基板上走线结构01的个数不进行限定，具体可以根据阵列基板上需要传递的信号进行相应的设置。
在阵列基板的制作工艺中，第一金属走线10以及与第一金属走线10同层的显示元件在形成后，由于工艺原因需要在第一金属走线10以及与第一金属走线10同层的显示元件上形成绝缘层。为了使第一金属走线10和第二金属走线20直接接触，需要将形成在第一金属走线10上绝缘层去除掉，因而第一金属走线10和第二金属走线20之间的绝缘层是镂空的。
本发明实施例提供的阵列基板中，由于阵列基板的走线结构01包括层叠的第一金属走线10和第二金属走线20，因而即使减小走线结构01的线宽，走线结构01电阻的增加幅度也较小。在此基础上，由于第一金属走线10和第二金属走线20直接接触，使得第一金属走线10和第二金属走线20之间的接触电阻便可以大幅度减小，从而可以进一步
降低走线结构01电阻。因此，本发明实施例在减小走线结构01线宽的同时，能够降低走线结构01的电阻。
可选的，如图2所示，走线结构01设置在阵列基板的边缘区域。阵列基板的中间区域可以设置有显示元件。
由于本发明实施例中的走线结构01设置在阵列基板的边缘区域，即阵列基板边缘区域的走线结构01包括层叠的第一金属走线10和第二金属走线20，因而即使减小走线结构01的线宽，走线结构01电阻的增加幅度也较小。在此基础上，由于第一金属走线10和第二金属走线20直接接触，使得第一金属走线10和第二金属走线20之间的接触电阻便可以大幅度减小，从而可以进一步降低走线结构01电阻。因此，本发明实施例的阵列基板在减小走线结构01线宽的同时，能够降低走线结构01的电阻。
可选的，阵列基板包括薄膜晶体管和第一电极，第一金属走线10和第二金属走线20与薄膜晶体管同步形成。或者，第一金属走线10和第二金属走线20与薄膜晶体管和第一电极同步形成。
其中，薄膜晶体管包括栅极、绝缘层、半导体层、源极和漏极。如果该阵列基板为液晶显示器的(Liquid Crystal Display，简称LCD)阵列基板，所述第一电极为像素电极，像素电极与薄膜晶体管的漏极电连接。进一步的阵列基板还可以包括公共电极。如果该阵列基板为有机电致发光二极管(Organic Light-Emitting Diode，简称OLED)显示器的阵列基板，所述第一电极为阳极，阳极与薄膜晶体管的漏极电连接。进一步地，阵列基板还包括有机材料功能层以及阴极。
此处，第一金属走线10和第二金属走线20与薄膜晶体管同步形成，即第一金属走线10和第二金属走线20与薄膜晶体管的栅极、源极和漏极中的任意两个同步形成。第一金属走线10和第二金属走线20与薄膜晶体管和第一电极同步形成，即第一金属走线10与薄膜晶体管的栅极、源极和漏极中任意一个同步形成，第二金属走线20与第一电极同步形成。或者，第一金属走线10与第一电极同步形成，第二金属走线20与薄膜晶体管的栅极、源极和漏极中任意一个同步形成。
本发明实施例中，第一金属走线10和第二金属走线20可以与薄膜晶体管同步形成，或者，第一金属走线10和第二金属走线20可以与薄膜晶体管和第一电极同步形成，这样便可以简化阵列基板的制作
工艺。
可选的，所述阵列基板包括薄膜晶体管、像素电极和公共电极；第一金属走线10和第二金属走线20与薄膜晶体管和公共电极同步形成。或者，第一金属走线10和第二金属走线20与像素电极和公共电极同步形成。
在该实施例中，第一金属走线10和第二金属走线20与薄膜晶体管和公共电极同步形成，即第一金属走线10与薄膜晶体管的栅极、源极或漏极中的任意一个同步形成，第二金属走线20与公共电极同步形成；或者第一金属走线10与公共电极同步形成，第二金属走线20与薄膜晶体管的栅极、源极或漏极中的任意一个同步形成。第一金属走线10和第二金属走线20与像素电极和公共电极同步形成，即第一金属走线10与像素电极同步形成，第二金属走线20与公共电极同步形成，或者第一金属走线10与公共电极同步形成，第二金属走线20与像素电极同步形成。
本发明实施例中，由于第一金属走线10和第二金属走线20可以与薄膜晶体管和公共电极同步形成；或者，第一金属走线10和第二金属走线20可以与第一电极和公共电极同步形成，这样便可以简化阵列基板的制作工艺。
本发明实施例提供一种显示面板，包括上述的阵列基板。
本发明实施例提供的显示面板中，由于显示面板的走线结构01包括层叠的第一金属走线10和第二金属走线20，因而即使减小走线结构01的线宽，走线结构01电阻的增加幅度也较小。在此基础上，由于第一金属走线10和第二金属走线20直接接触，使得第一金属走线10和第二金属走线20之间的接触电阻便可以大幅度减小，从而可以进一步降低走线结构01电阻。因此，本发明实施例的显示面板在减小走线结构01线宽的同时，能够降低走线结构01的电阻。
本发明实施例还提供一种阵列基板的制备方法，如图3所示，包括：
S100、如图4(a)所示，形成第一金属图案101，第一金属图案101所在区域与待形成的走线结构所在区域对应。
可选的，形成第一金属图案的步骤包括：形成第一金属层，并对所述第一金属层执行蚀刻工艺，从而形成第一金属图案。其中，对于
第一金属图案101的材料不进行限定，第一金属图案101的材料可以选自金属单质、合金、金属氧化物中的至少一种。例如可以为Mo、Cu、Ag或IZO等。
此处，第一金属图案101形成在基板30上，对于基板30上的其它结构，附图4(a)并未示意出。对于第一金属图案如何形成在基板30上不进行限定，例如可以通过化学气相沉积法形成或蒸镀工艺形成。
S101、如图4(b)所示形成绝缘层40，如图4(c)所示通过刻蚀工艺去除第一金属图案101上的绝缘层40。
其中，对于绝缘层40的材料不进行限定，例如可以为SiN(氧化硅)或SiO(氧化硅)、氮氧化硅(SiOxNy)、碳氮化硅(SiCxNy)中的一种或几种。
此处，通过刻蚀工艺只需将第一金属图案101上的绝缘层40的材料去除，对于阵列基板其它位置处的绝缘层40的材料保留。
S102、如图4(d)所示，形成第二金属图案102，如图4(e)所示，通过刻蚀工艺形成多个走线结构01，每个走线结构01包括层叠的第一金属走线10和第二金属走线20。
其中，对于第二金属图案102的材料不进行限定，第二金属图案102的材料可以选自金属单质、合金、金属氧化物中的至少一种。例如可以为Mo、Cu、Ag或IZO等。第二金属图案102的材料可以和第一金属图案101相同，也可以不相同。
对于形成的第一金属走线10和第二金属走线20的线宽和数目不进行限定，可以根据阵列基板的需要进行刻蚀。对于各走线结构01之间的间距，以能将各走线结构01隔开为准。
由于第一金属走线10和第二金属走线20是通过刻蚀工艺同时形成的，这样可以使得第一金属走线10和第二金属走线20接触的面积达到最大，因而可以大幅度降低第一金属走线10和第二金属走线20之间的接触电阻，且能够减小走线结构01的线宽。
本发明实施例提供一种阵列基板的制备方法，由于阵列基板的走线结构01包括层叠的第一金属走线10和第二金属走线20，因而即使减小走线结构01的线宽，走线结构01电阻的增加幅度也较小。在此基础上，由于第一金属走线10和第二金属走线20直接接触，使得第一金属走线10和第二金属走线20之间的接触电阻便可以大幅度减小，从而可以进一步降低走线结构01电阻。因此，本发明实施例在减小走
线结构01线宽的同时，能够降低走线结构01的电阻。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。
Claims (12)
- 一种走线结构，包括层叠设置的第一金属走线和第二金属走线；其中，所述第一金属走线和所述第二金属走线直接接触。
- 根据权利要求1所述的走线结构，其中所述第一金属走线和所述第二金属走线的线宽相同，所述第一金属走线和所述第二金属走线在垂直于层叠方向的平面上的投影完全重叠。
- 根据权利要求2所述的走线结构，其中所述第一金属走线的线宽和所述第二金属走线的线宽均为5～50μm。
- 根据权利要求1所述的走线结构，其中所述第一金属走线和所述第二金属走线的材料选自金属单质、合金、金属氧化物中的至少一种。
- 一种阵列基板，包括权利要求1-4任一项所述的走线结构。
- 根据权利要求5所述的阵列基板，还包括绝缘层；其中所述第一金属走线和所述绝缘层同层设置。
- 根据权利要求5所述的阵列基板，其中所述走线结构设置在所述阵列基板的边缘区域。
- 根据权利要求5所述的阵列基板，其中所述阵列基板包括薄膜晶体管和第一电极；所述第一金属走线和所述第二金属走线与所述薄膜晶体管同步形成；或者，所述第一金属走线和所述第二金属走线与所述薄膜晶体管和所述第一电极同步形成。
- 根据权利要求5所述的阵列基板，其中所述阵列基板包括薄膜晶体管、像素电极和公共电极；所述第一金属走线和所述第二金属走线与所述薄膜晶体管和所述公共电极同步形成；或者，所述第一金属走线和所述第二金属走线与所述像素电极和所述公共电极同步形成。
- 一种显示面板，包括权利要求5-9任一项所述的阵列基板。
- 一种阵列基板的制备方法，包括：形成第一金属图案，所述第一金属图案所在区域与待形成的走线 结构所在区域对应；形成绝缘层，通过刻蚀工艺去除所述第一金属图案上的所述绝缘层的材料；以及形成第二金属图案，通过刻蚀工艺形成多个走线结构，每个所述走线结构包括层叠的第一金属走线和第二金属走线。
- 如权利要求11所述的阵列基板的制备方法，其中形成第一金属图案的步骤包括：形成第一金属层，并对所述第一金属层执行蚀刻工艺，从而形成第一金属图案。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/570,712 US20180226465A1 (en) | 2016-06-01 | 2017-04-24 | Wiring structure, array substrate and manufacturing method thereof, and display panel |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610383827.4A CN105914227A (zh) | 2016-06-01 | 2016-06-01 | 一种走线结构、阵列基板及其制备方法、显示面板 |
| CN201610383827.4 | 2016-06-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2017206624A1 true WO2017206624A1 (zh) | 2017-12-07 |
Family
ID=56741978
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/CN2017/081633 WO2017206624A1 (zh) | 2016-06-01 | 2017-04-24 | 走线结构、阵列基板及其制备方法、显示面板 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20180226465A1 (zh) |
| CN (1) | CN105914227A (zh) |
| WO (1) | WO2017206624A1 (zh) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105914227A (zh) * | 2016-06-01 | 2016-08-31 | 京东方科技集团股份有限公司 | 一种走线结构、阵列基板及其制备方法、显示面板 |
| CN110164359B (zh) * | 2019-06-28 | 2022-03-22 | 武汉天马微电子有限公司 | 显示面板及显示装置 |
| CN112669710A (zh) * | 2020-12-30 | 2021-04-16 | 武汉华星光电半导体显示技术有限公司 | 显示面板及显示装置 |
| CN114185213B (zh) * | 2021-12-30 | 2023-11-24 | 滁州惠科光电科技有限公司 | 阵列基板、显示面板及显示装置 |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1495851A (zh) * | 2002-07-19 | 2004-05-12 | ���ǵ�����ʽ���� | 薄膜晶体管阵列板及其制造方法 |
| US20080185590A1 (en) * | 2007-02-07 | 2008-08-07 | Byoung-June Kim | Thin Film Transistor Array Panel and Method for Manufacturing the Same |
| CN103258743A (zh) * | 2012-02-15 | 2013-08-21 | 乐金显示有限公司 | 薄膜晶体管、薄膜晶体管阵列基板及其制造方法 |
| CN104635981A (zh) * | 2014-11-26 | 2015-05-20 | 业成光电（深圳）有限公司 | 触控模组及具有该触控模组的触控显示装置 |
| CN105914227A (zh) * | 2016-06-01 | 2016-08-31 | 京东方科技集团股份有限公司 | 一种走线结构、阵列基板及其制备方法、显示面板 |
-
2016
- 2016-06-01 CN CN201610383827.4A patent/CN105914227A/zh active Pending
-
2017
- 2017-04-24 US US15/570,712 patent/US20180226465A1/en not_active Abandoned
- 2017-04-24 WO PCT/CN2017/081633 patent/WO2017206624A1/zh active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1495851A (zh) * | 2002-07-19 | 2004-05-12 | ���ǵ�����ʽ���� | 薄膜晶体管阵列板及其制造方法 |
| US20080185590A1 (en) * | 2007-02-07 | 2008-08-07 | Byoung-June Kim | Thin Film Transistor Array Panel and Method for Manufacturing the Same |
| CN103258743A (zh) * | 2012-02-15 | 2013-08-21 | 乐金显示有限公司 | 薄膜晶体管、薄膜晶体管阵列基板及其制造方法 |
| CN104635981A (zh) * | 2014-11-26 | 2015-05-20 | 业成光电（深圳）有限公司 | 触控模组及具有该触控模组的触控显示装置 |
| CN105914227A (zh) * | 2016-06-01 | 2016-08-31 | 京东方科技集团股份有限公司 | 一种走线结构、阵列基板及其制备方法、显示面板 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20180226465A1 (en) | 2018-08-09 |
| CN105914227A (zh) | 2016-08-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP7438971B2 (ja) | フレキシブル基板、その作製方法、ディスプレイ装置 | |
| WO2020124921A1 (zh) | 显示面板及其制作方法 | |
| WO2017206624A1 (zh) | 走线结构、阵列基板及其制备方法、显示面板 | |
| US10788907B2 (en) | Touch display substrate, fabrication method and touch display device | |
| WO2015027569A1 (zh) | 阵列基板及其制作方法、显示装置 | |
| JP2007157916A (ja) | Ｔｆｔ基板及びｔｆｔ基板の製造方法 | |
| WO2021022594A1 (zh) | 阵列基板、显示面板及阵列基板的制作方法 | |
| WO2014206035A1 (zh) | 阵列基板及其制作方法、显示面板和显示装置 | |
| WO2016000342A1 (zh) | 阵列基板及其制作方法、显示装置 | |
| JP2013225645A (ja) | アレイ基板及びその製造方法 | |
| WO2017215075A1 (zh) | 一种阵列基板及其制备方法 | |
| WO2016206206A1 (zh) | 薄膜晶体管及其制备方法、阵列基板、显示装置 | |
| CN111312731B (zh) | 一种阵列基板及其制备方法、显示面板 | |
| KR101134989B1 (ko) | 어레이 기판의 제조방법 | |
| WO2018099079A1 (zh) | 阵列基板和显示装置 | |
| WO2021017243A1 (zh) | 显示面板母板和显示面板母板的制备方法 | |
| WO2020113771A1 (zh) | 阵列基板及其制作方法、显示面板 | |
| TW202043867A (zh) | 顯示面板及顯示面板製作方法 | |
| US10361261B2 (en) | Manufacturing method of TFT substrate, TFT substrate, and OLED display panel | |
| EP3261127B1 (en) | Thin-film transistor and manufacturing method therefor, array substrate and display device | |
| JP6055077B2 (ja) | トランジスタの製造方法、トランジスタ、アレイ基板及び表示装置 | |
| US10204833B2 (en) | Array substrate and manufacturing method for the same | |
| WO2016000363A1 (zh) | 低温多晶硅薄膜晶体管阵列基板及其制备方法、显示装置 | |
| JP7042621B2 (ja) | アレイ基板、表示パネル、アレイ基板を備える表示装置及びアレイ基板の製造方法 | |
| WO2021142870A1 (zh) | 像素驱动电路及其制作方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WWE | Wipo information: entry into national phase |
Ref document number: 15570712 Country of ref document: US |
|
| NENP | Non-entry into the national phase |
Ref country code: DE |
|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 17805569 Country of ref document: EP Kind code of ref document: A1 |
|
| 122 | Ep: pct application non-entry in european phase |
Ref document number: 17805569 Country of ref document: EP Kind code of ref document: A1 |
|
| 32PN | Ep: public notification in the ep bulletin as address of the adressee cannot be established |
Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 28/06/2019) |
|
| 122 | Ep: pct application non-entry in european phase |
Ref document number: 17805569 Country of ref document: EP Kind code of ref document: A1 |