WO2017197946A1 - 一种基于pvtm的宽电压时钟拉伸电路 - Google Patents

一种基于pvtm的宽电压时钟拉伸电路 Download PDF

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WO2017197946A1
WO2017197946A1 PCT/CN2017/074785 CN2017074785W WO2017197946A1 WO 2017197946 A1 WO2017197946 A1 WO 2017197946A1 CN 2017074785 W CN2017074785 W CN 2017074785W WO 2017197946 A1 WO2017197946 A1 WO 2017197946A1
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clock
circuit
pvtm
stretching
phase
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单伟伟
万亮
时龙兴
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Southeast University
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Southeast University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Definitions

  • the Razor monitoring unit is used to replace the traditional trigger to complete the timing monitoring and error correction of the circuit.
  • the trigger function in the monitoring unit is the same as the traditional trigger; when the circuit timing is wrong, the shadow register stores the normal timing result, and the data error correction can be completed.
  • the PVT environment in the circuit can be obtained.
  • the information is fed back into the system, and the system monitors the information according to the timing of the feedback so that the target circuit can be adjusted with corresponding voltage or frequency to achieve high performance or high energy efficiency of the chip.
  • the chip timing margin is small.
  • an immediate down-conversion operation is needed to improve the timing margin and solve the circuit timing default problem.
  • the traditional methods of frequency reduction include: frequency division operation and PLL configuration.
  • the frequency division method can achieve immediate frequency reduction, but since it can only achieve integer multiple frequency division (usually using two-way frequency), the chip frequency is greatly reduced, and the chip performance is also reduced.
  • the method of using PLL dynamic configuration is A relatively small range of frequency adjustments can be achieved, but since the PLL adjustment requires a certain settling time, the method of using the PLL configuration is not suitable for fast frequency adjustment.
  • the published clock stretching circuit has a complicated structure, usually composed of multiple DLLs (Delay-Locked Loop) Multi-phase clock generation, delay phase control is more accurate, but the area overhead is relatively large, not suitable for embedded low-power chips.
  • the invention aims at a clock stretching circuit designed by using a PLL module and a disadvantage and disadvantage of using a frequency division to realize a clock frequency reducing circuit, and provides a clock stretching circuit with faster response time and finer tensile scale.
  • the invention can stretch the clock under the control signal, can complete the fine-grained fast frequency-down operation, and can effectively reduce the area overhead of the frequency adjustment module.
  • the invention is particularly suitable for use in an adaptive voltage frequency adjustment circuit based on online timing monitoring. When a circuit timing violation occurs, a control signal is generated to stretch the clock, and the circuit timing margin is increased, thereby avoiding circuit operation errors.
  • a PVTM-based wide voltage clock stretching circuit includes:
  • the PVTM (Process Voltage Temperature Monitor) circuit module monitors the delay information of the delay unit in the chip in real time, and feeds back the delay information to the control module;
  • phase clock generation module that uses the system clock to generate N phase clocks having different phases, where N is an integer greater than one;
  • the control module generates a control signal according to the delay information fed back by the PVTM circuit module under the action of the clock stretching enable signal and the clock stretching scale signal;
  • the clock synchronization selection module selects the target phase clock output from the system clock and the N phase clocks in response to the control signal, so as to stretch the system clock in a single cycle.
  • the PVTM circuit module comprises:
  • a frequency dividing circuit using a D flip-flop to divide the system clock to obtain a frequency dividing clock
  • a ring-vibrating circuit is formed by connecting two 2-input NAND gates and M-stage delay units in series, M is an integer greater than 1, and the oscillating signal output by the last-stage delay unit is combined with the frequency-divided clock as the two inputs.
  • the input of the NAND gate forms a closed loop;
  • a counter circuit 1 inputs the oscillating signal, samples the number of oscillations, and outputs the sampling result to the control module.
  • control module includes a counter circuit 2 for generating an N+1 bit clock selection control signal ctrl[N:0], determining a target phase clock selection, and having only one clock selection control in each cycle. The signal is valid.
  • the control module further includes an encoder, when the encoder detects that the stretch enable signal is changed from active to inactive, generating a gated clock control signal to determine whether to gate the target phase clock for one cycle before outputting .
  • the clock synchronization selection module comprises N D flip-flops and a plurality of gate circuits, the lowest bit control signal and the system clock are operated and operated by an AND gate, and the remaining N bits of control signals are respectively used as data of N D flip-flops.
  • the input signal, N phase clocks are respectively used as clock input signals of N D flip-flops, and are synchronously processed with corresponding control signals, and the data output signals of the N D flip-flops and their clock input signals are respectively operated and operated by the AND gate.
  • the PVTM-based wide voltage clock stretching circuit of the present invention mainly adopts N delay units to acquire N phase clocks whose phases are mutually offset. Since the delay of the delay unit is susceptible to changes in the PVT environment, the clock stretching result is rough. Therefore, the circuit structure is added to the PVTM circuit module, and based on the external control signal, the correct phase clock is selected by using the feedback information of the PVTM to realize fast and accurate clock stretching. Compared with other traditional clock stretching methods, including the method of frequency division or PLL configuration, the method can not only respond quickly in one cycle, but also achieve a finer degree of stretching of the system clock, that is, the clock frequency.
  • the present invention requires less number of cells required for implementation of circuit functions, does not require complicated gate devices, and is less expensive in area and power consumption.
  • the circuit structure of the invention is simple, the circuit is simple to implement, and the area cost is exchanged with a certain precision cost, and is particularly suitable for the adaptive voltage frequency adjustment circuit based on online time series monitoring.
  • Figure 1 is a block diagram of a wide voltage clock stretching circuit based on PVTM
  • FIG. 2 is a schematic diagram of a wide voltage clock stretching circuit based on PVTM
  • Figure 3 is a timing diagram of the clock stretching principle
  • Figure 4 shows the comparison of PVTM counts and actual results in different PVT environments.
  • Figure 5 is a simulation waveform diagram of clk at a FF process angle of 0.7 V, 25 ° C and a stretching period of 1/8;
  • Figure 6 is a simulation waveform diagram of clk at a TT process angle of 0.8 V, 25 ° C and a stretching period of 1/4;
  • Figure 7 is a simulation waveform diagram of clk at the SS process angle of 1.1 V, 25 ° C and a tensile period of 1/2.
  • the PVTM-based wide voltage clock stretching circuit of the present invention includes a PVTM circuit module, a phase clock. Generate module, clock synchronization selection module and control module.
  • the external input signal of the circuit is the system clock clk, the reset signal rst, the clock stretching enable signal slow and the clock stretch scale signal user_mux, and the output signal is the clock clk_out after stretching.
  • the PVTM circuit module monitors the delay information of the delay unit in the real-time chip to detect the operating environment of the current circuit, and feeds the delay information to the control module.
  • the control module selects the target phase clock from the clock generated by the phase clock generation module according to the feedback information of the PVTM under the action of the clock stretching enable signal slow and the clock stretching scale signal user_mux, so as to realize different PVT environments in a single cycle.
  • the stretching of the system clock is not limited to the following parameters:
  • the input signal of the PVTM circuit module is the system clock clk, the reset signal rst, and the output signal is the number of ring oscillations counter, which is connected to the input terminal of the control module.
  • the input signals of the control module are the system clock clk, the reset signal rst, the clock stretch scale signal user_mux, and the feedback signal counter from the PVTM circuit module, and the output signal is connected to the input of the clock synchronization selection module, which is respectively N+1 bit control.
  • the PVTM circuit module uses a delay unit to form a ring oscillator, input excitation, so that it starts to oscillate in the environment, and records the number of oscillations counter.
  • the number of counters represents the PVT environment of the current circuit. . It can be seen from the calculation that the number of oscillations counter is also the number of delay units required to obtain a system clock delayed by one cycle in the environment.
  • the output control signal ctrl[N:0] is generated from the system clock and the phase clock generating module.
  • the clock of the target phase is selected in the clock to realize the stretching of the system clock in different PVT environments in a single cycle.
  • the PVTM circuit module is composed of three sub-circuits, which are a frequency dividing circuit, a ring vibration circuit, and a counter circuit 1.
  • the frequency dividing circuit is constructed by a D flip-flop triggered by a rising edge, and the frequency dividing clock clk_div is obtained by dividing the system clock clk by K (K is an integer greater than 1).
  • the ring-vibrating circuit is formed by connecting two 2-input NAND gates and M-level delay units in series (M is an integer greater than 1).
  • the delay unit selected in the present invention is equivalent to a buffer connected in series. .
  • the input signal divided by the two input NAND gates clock clk_div is the start-up signal of the ring oscillator.
  • the oscillation signal osc_out is output.
  • the oscillation signal is input to the counter circuit 1 in the PVTM circuit module, and the number of oscillations is counted.
  • the frequency dividing circuit When the frequency-divided clock changes from a high level to a low level, the ring oscillator ends to oscillate, and the counter circuit 1 stops counting at the same time. At the same time, the frequency dividing circuit outputs a valid sampling signal clk_sample_counter to the counter circuit 1, and samples the number of oscillations. After the data sampling is completed, the frequency dividing circuit outputs a reset signal out_rst to the counter circuit 1, resets the count data, and outputs the sampled data counter to the control module.
  • the number of delay units N1 required for the delay chain of the phase clock generation module in the current PVT environment can be calculated by the following formula:
  • M and K are respectively the number of delay units in the ring vibration of the PVTM circuit module and the frequency division number of the frequency dividing circuit.
  • N is the number of delay units required to integrate all PVT environments, taking the maximum number of delay units required in each PVT environment. This formula is theoretically derived.
  • the phase clock clk_dlyN1 obtained from the N1th delay unit on the delay chain and the system clock clk have a phase difference of 2 ⁇ .
  • the number N1 has a certain error with the number of delay units N0 actually required by the delay chain, but the error is within the allowable range.
  • the ring oscillator of the PVTM circuit module when the divided clock clk_div turns from high level to low level, the ring oscillator should stop oscillating. However, since the transition of clk_div signal may still cause the last oscillation of the ring oscillator, the counter data should Round off the last time to improve the accuracy of the count.
  • the phase clock generation module is composed of N stages of delay units connected in series to form a delay chain.
  • the delay unit in the delay chain is the same type as the delay unit used in the PVTM.
  • the phase clock generation module uses the system clock clk as the initial input signal of the delay chain, and each stage delay unit generates a certain phase offset to the system clock, thereby obtaining N+1 phase clocks with different phases.
  • the system clock is also treated as a phase clock.
  • the delay between adjacent phase clocks is the delay time of one delay unit in the current PVT environment.
  • the period of the clock after stretching is determined by the following formula:
  • T Stretch T Original + ⁇ t*N1/2 user_mux
  • T Stretch is the clock period after stretching
  • T Original is the period value before the clock is stretched, that is, the system clock period
  • ⁇ t is the delay of a delay unit in the current PVT environment
  • N1 is in the current environment.
  • User_mux is an input variable that controls the stretch clock output cycle.
  • the user_mux signal determines the scale of the clock stretch, and its bit width is an integer X, which depends on the minimum clock stretch granularity 1/2L that the user needs to implement, where L is the maximum decimal value that can be represented by a binary number with a bit width of X. number.
  • the maximum decimal number that can be represented is 3
  • the minimum clock stretching time that can be achieved is 1/8 cycles, in addition to stretching 1/4, 1/2 cycles.
  • N0 is the number of delay units actually required to obtain a clock with a phase difference of 2 ⁇ from the system clock clk in the current environment, there is ⁇ t*N0 ⁇ T Original , and N0 and N1 have small errors, so there is ⁇ t*N1 ⁇ T Original , so you can get different periods of stretching clock by configuring different user_mux.
  • the clock period after stretching is:
  • T Stretch T Original + ⁇ t*N1/2 ⁇ 3*T Original /2
  • the control module output signal is a ctrl signal with a bit width of N+1. In each cycle, only one bit is high level, and the rest is low level, wherein the control signal with high level represents the corresponding phase clock.
  • the control module is composed of a counter circuit 2 and an encoder.
  • the encoder circuit generates a gated clock signal gate_clk by detecting a falling edge of the stretch enable signal, that is, when the stretch enable signal is changed from active to inactive, and determines whether the output clock is output. Gating for one cycle.
  • phase clock needs to be reselected from clk_dly1.
  • the ctrl_synM signal and the clk_dlyS signal in the clock synchronization module will be simultaneously high for a period of time between the valid edges of clk_dlyM and clk_dlyS, indicating that simultaneously Two phase clocks were selected, causing a malfunction.
  • the control signal ctrl[0] is directly synchronized with the system clock clk without being synchronized.
  • phase clock generation module used in the present invention is composed of a delay chain
  • the control module needs to select whether to output or not.
  • Clock is gated for one week Period, that is, let the current clock output a high period for one cycle to avoid unnecessary glitch or short pulse.
  • the gated clock control signal gate_clk is set to a high level, that is, the current output is indicated.
  • the clock is gated for one cycle; if the phase difference between the phase clock selected by the current clock synchronization selection module and the system clock is greater than ⁇ , the gated clock control signal gate_clk is set to a low level, that is, the current output clock selects the system clock, and stops. Stretching.
  • FIG. 3 shows the timing diagram of the clock stretching principle.
  • the operation of clock stretching is to select the desired target phase clock according to the different stretching scales.
  • the invention uses FIG. 3 as an example to specifically describe the principle of clock stretching, that is, the time during which the clock is elongated is the delay value of two delay units.
  • the output signal clk_out outputs the system clock clk (as shown by 1 in FIG. 3).
  • the clock stretching enable signal slow is active - that is, high, the clock is stretched. Since the flip-flops employed in the circuit of the present invention are all valid for the falling edge, the control signal ctrl[2] is at a high level when the falling edge of clk arrives. Since each phase clock and control signal are asynchronous signals, unnecessary glitch may be generated in the clock selection, which affects the circuit function.
  • phase difference between clk_out and clk is unknown at this time, if the system clock clk is directly selected after the clock stretching enable signal is invalid, glitch or clock compression may occur. As shown in this example, after the clock stretching is completed, the system clock is selected. Since the phase difference between clk_dly4 and clk is less than ⁇ , a short pulse (shown as 4, 5 in Figure 3, that is, the dotted line) appears, which will affect the normal operation of the circuit. . Therefore, at this moment, it is necessary to gate a clock to clk_out, that is, gate_clk is at a high level (as shown by 6 in FIG. 3), and a high level is outputted, and when the gate_clk is low, the system clock is output (see FIG. 3). 7 shows)
  • the circuit is simulated in the environment of different process angles, voltages and temperatures using Hsim software based on the SMIC 40nm process library, and the data comparison between N0 and N1 is obtained. By comparison, the two-number error is small, indicating that the timing monitoring module has high accuracy.
  • Figure 5 shows simulated waveforms with a tensile scale of 1/8 cycles at FF process angle, 0.7V, 25°C.
  • the stretch signal slow is active, it is sampled on the falling edge of the flip-flop.
  • the output clock is stretched at a low level, and the stretching time is about 1/8 cycle, and the response speed is in one cycle. Since the phase difference between the phase clock of the output clock and the system clock clk is about ⁇ /2 when the clock stretching enable signal is invalid, in order to avoid clock compression at the end of the circuit, the clock output is gated by one clock and output. A high level of a cycle.
  • Figure 6 shows the simulated waveforms with a tensile scale of 1/4 cycle at TT process angle, 0.8V, 25°C.
  • stretch signal slow When the stretch signal slow is active, it is sampled on the falling edge of the flip-flop. It can be seen from the figure that the output clock is stretched, and the stretching time is about 1/4 cycle, and the response speed is one cycle. Since the phase difference between the phase clock of the output clock and the system clock clk is about ⁇ when the clock stretching enable signal is invalid, in order to avoid clock compression at the end of the circuit, a clock is clocked on the clock output, and the output is high. level.
  • Figure 7 shows the simulated waveforms with a tensile dimension of 1/2 cycle at an SS process angle of 1.1 V and 25 °C.
  • stretch signal slow When the stretch signal slow is active, it is sampled on the falling edge of the flip-flop. It can be seen from the figure that the output clock is stretched, and the stretching time is about 1/2 cycle, and the response speed is one cycle. Since the phase difference between the output clock selection and the system clock clk is about 2 ⁇ when the clock stretching enable signal slow is invalid, the clock compression is not generated, so the circuit does not need to be gated.
  • the 40nm process library provided by SMIC is used to simulate the circuit in different PVT environments using the software simulation platform provided by Synopsys.
  • the circuit structure of each module is designed, the circuit is modeled by hardware circuit language, the circuit function is simulated and verified, and optimized.
  • Set the operating frequency of the circuit to 200MHz, the clock division number K of the frequency division circuit in the selected PVTM circuit module is 16, the number of delay units M in the ring vibration is 4, and the number of delay units in the delay chain of the phase clock generation module N Is 59.
  • the values of the clock stretching scale signal user_mux are changed at different process angles of FF, TT, SS, and different voltages and temperatures, and simulation results are obtained.
  • the simulation results are shown in Figures 5, 6, and 7.
  • Figures 5, 6, and 7 show that the circuit begins to respond to the clock stretching request on the falling edge of the system clock (in one cycle) when the clock stretching enable signal is asserted, and begins to stretch the system clock.
  • different clock stretching times are achieved.
  • the clock stretching scale signal user_mux is 2, that is, the clock is stretched to 1/4 cycle. It can be seen from the simulation waveform that when the stretch signal slow is valid, it is sampled on the falling edge of the flip-flop. It can be seen from the figure that the output clock is stretched, and the stretching time is about 1/4 cycle, and the response speed is one cycle.
  • phase difference between the phase clock of the output clock and the system clock clk is about ⁇ when the clock stretching enable signal is invalid, in order to avoid clock compression at the end of the circuit, a clock is clocked on the clock output, and the output is high. level.

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Abstract

一种基于PVTM的宽电压时钟拉伸电路，该电路由PVTM电路模块、相位时钟生成模块、时钟同步选择模块以及控制模块组成。PVTM电路模块实时监测芯片中延时单元的延时信息来检测当前电路的运行环境，并将该信息反馈到控制模块中。控制模块在时钟拉伸使能信号以及时钟拉伸尺度信号的作用下，根据PVTM的反馈信息，从相位时钟生成模块产生的时钟中选择目标相位时钟，实现在单周期内对不同PVT环境下系统时钟的拉伸。不需要复杂的门器件，面积和功耗代价较小。电路结构精简，电路实现简单，用一定的精度代价换取了面积代价，尤其适合基于在线时序监测的自适应电压频率调整电路使用。

Description

一种基于PVTM的宽电压时钟拉伸电路 技术领域
本发明涉及一种基于PVTM的宽电压时钟拉伸电路，利用数字逻辑实现，属于集成电路设计领域。
技术背景
近些年，宽电压(Wide voltage range)集成电路得到了广泛关注，它通常涵盖近/亚阈值区至常规电压区，可以在宽电压范围内进行切换，以便在满足芯片不同负载下的高性能或高能效需求。然而，由于PVT(Process,Voltage,Temperature)偏差的存在以及电路老化的问题，在电路设计中需要预留一定的时序余量使电路在最坏情况下能仍正常工作，造成了性能和功耗浪费，但这些不利时序偏差因素实际很难同时发生甚至根本不发生，因此这就造成所选择的工作电压过于保守，芯片的性能没有达到最佳。
为了实现芯片的高性能或者高能效设计，通常会减少时序余量以让芯片在更低电压或者更高的频率下运行，但容易造成关键路径时序违规情况发生，使芯片运行出错。以razor结构为代表的电路是典型的在线时序监测方法，将电压降低到极限值至电路时序出错，并利用原地恢复或者上层恢复机制来恢复芯片的正确工作状态。这类监控方法的监控单元有两个特点，一是，监控时序工作情况，能有效的判断某一个时钟周期内，电路的时序是否出现错误；二是，保留正确的时序结果，在时序出错时需要实现纠错功能，因此监控单元需要保留正确的时序值。其结构主要是由两个时序单元组成：普通触发器和影子锁存器。在设计过程中，使用Razor监控单元替换传统的触发器，即可完成电路的时序监控及纠错。当电路时序正常时，监控单元中的触发器作用与传统触发器无异；当电路时序出错时，影子寄存器保存着正常时序结果，可以完成数据纠错。
利用在线时序监测方法，检测片上时序监测单元的延时变化情况，便可以得到电路中PVT环境情况。将该信息反馈到系统中，系统根据反馈的时序监测信息从而可以对目标电路进行相应的电压或者频率调节，以实现芯片的高性能或者高能效。一旦芯片的数据出现错误即表明出现时序违约，此时芯片时序余量较小，为了保证芯片工作正常，需要实现立刻降频操作，以提高时序余量，解决电路时序违约问题。而传统的降频方法有：分频操作和PLL配置。分频的方法可以实现立即降频，但是由于只能实现整数倍分频(通常使用二分频)，因此芯片频率降低幅度较大，芯片工作性能降低也比较多；使用PLL动态配置的方法虽然可以实现比较小范围的频率调节，但是由于PLL调节需要一定的稳定时间，因此使用PLL配置的方法不适用于快速频率调节。已公布的时钟拉伸电路结构复杂，通常由多个DLL(Delay-Locked Loop) 实现多相位时钟生成，延时相位控制比较精确，但面积开销比较大，不适用于嵌入式低功耗芯片。
发明内容
发明目的：
本发明针对采用PLL模块设计的时钟拉伸电路以及利用分频实现时钟降频电路的缺点和不足，提供了一种响应时间更快，拉伸尺度更细的时钟拉伸电路。本发明根据PVTM反馈的信息能够在控制信号下对时钟进行拉伸，可以完成细粒度的快速降频操作，能有效减小频率调节模块面积开销。本发明尤其适合基于在线时序监测的自适应电压频率调整电路使用，当出现电路时序违规时，即产生控制信号使时钟拉伸，增加电路时序余量，从而避免电路工作出错。
技术方案：
本发明所述的一种基于PVTM的宽电压时钟拉伸电路包括：
PVTM(Process Voltage Temperature Monitor，PVT监测)电路模块，实时监测芯片中延时单元的延时信息，并将延时信息反馈到控制模块；
相位时钟生成模块，利用系统时钟产生N个具有不同相位的相位时钟，N为大于1的整数；
控制模块，在时钟拉伸使能信号以及时钟拉伸尺度信号的作用下，根据PVTM电路模块反馈的延时信息，产生控制信号；
时钟同步选择模块，响应所述控制信号，从系统时钟及N个相位时钟中选择目标相位时钟输出，实现在单周期内，对系统时钟拉伸。
优选地，所述PVTM电路模块包括：
一分频电路，利用D触发器对系统时钟进行分频，得到分频时钟；
一环振电路，由1个二输入与非门以及M级延时单元串联而成，M为大于1的整数，最后一级延时单元输出的振荡信号与分频时钟共同作为所述二输入与非门的输入，形成闭环；
一计数器电路1，输入所述振荡信号，对振荡次数进行采样，并输出采样结果至控制模块。
优选地，所述控制模块包括一计数器电路2，用于产生N+1位时钟选择控制信号ctrl[N:0]，决定目标相位时钟的选择，在每个周期内，只有一位时钟选择控制信号有效。
所述控制模块进一步还包括一编码器，当编码器检测到拉伸使能信号由有效变为无效时，产生一门控时钟控制信号，决定是否对目标相位时钟进行门控一个周期后再输出。
另一优选地，所述时钟同步选择模块包括N个D触发器及若干门电路，最低位控制信号与系统时钟通过与门进行与操作，其余N位控制信号分别作为N个D触发器的数据输入信号，N个相位时钟分别作为N个D触发器的时钟输入信号，与对应的控制信号进行同步处理，N个D触发器的数据输出信号与其时钟输入信号分别通过与门进行与操作后，将所有N+1个与门的输出连接到一个具有N+1个输入端口的或门，该或门的输出即为拉伸时钟。
有益效果：
本发明的基于PVTM的宽电压时钟拉伸电路，主要采用N个延时单元获取N个相位相互偏移的相位时钟。由于延时单元的延时易受PVT环境变化影响，造成时钟拉伸结果粗糙。因此本电路结构加入PVTM电路模块，根据外部控制信号，利用PVTM的反馈信息，选择正确的相位时钟，实现快速准确的时钟拉伸。该方法相对于传统其他的时钟拉伸方法，包括使用分频或者PLL配置的方法，不仅能在一个周期内做到快速响应，而且能够做到对系统时钟较为精细程度的拉伸，即时钟频率不会变化太大，保证芯片能在解决电路时序违约的情况下，芯片的性能不会有太大的损失，使电路的时序违约问题得到及时解决。同时，本发明对于电路功能的实现所需单元数目相比少，不需要复杂的门器件，面积和功耗代价较小。本发明电路结构精简，电路实现简单，用一定的精度代价换取了面积代价，尤其适合基于在线时序监测的自适应电压频率调整电路使用。
附图说明：
图1为基于PVTM的宽电压时钟拉伸电路框图；
图2为基于PVTM的宽电压时钟拉伸电路原理图；
图3为时钟拉伸原理时序图；
图4为不同PVT环境PVTM的计数与实际结果对比
图5为在FF工艺角，0.7V，25℃，拉伸周期为1/8的clk的仿真波形图；
图6为在TT工艺角，0.8V，25℃，拉伸周期为1/4的clk的仿真波形图；
图7为在SS工艺角，1.1V，25℃，拉伸周期为1/2的clk的仿真波形图
具体实施方式
下面结合附图对本发明技术方案进行详细说明，但是本发明的保护范围不局限于所述实施例。
如图1所示，本发明基于PVTM的宽电压时钟拉伸电路包括PVTM电路模块，相位时钟 生成模块，时钟同步选择模块以及控制模块。该电路的外部输入信号为系统时钟clk，复位信号rst，时钟拉伸使能信号slow以及时钟拉伸尺度信号user_mux，输出信号为拉伸之后的时钟clk_out。PVTM电路模块是实时监测芯片中延时单元的延时信息来检测当前电路的运行环境，并将该延时信息反馈到控制模块中。控制模块在时钟拉伸使能信号slow以及时钟拉伸尺度信号user_mux的作用下，根据PVTM的反馈信息，从相位时钟生成模块产生的时钟中选择目标相位时钟，实现在单周期内对不同PVT环境下系统时钟的拉伸。
PVTM电路模块的输入信号为系统时钟clk，复位信号rst，输出信号为环振振荡次数counter，连接到控制模块的输入端。
相位时钟生成模块的输入信号为系统时钟clk，输出信号为N个具有不同相位的相位时钟clk_dly1…clk_dlyi…clk_dlyN，连接到时钟同步选择模块的输入端，i＝2，3…N-1；N为大于1的整数。
控制模块的输入信号为系统时钟clk，复位信号rst，时钟拉伸尺度信号user_mux以及来自PVTM电路模块的反馈信号counter，输出信号连接到时钟同步选择模块的输入端，分别为N+1位的控制信号ctrl[N:0]以及门控时钟控制信号gate_clk。
时钟同步选择模块的输入信号为系统时钟clk，复位信号rst，门控时钟控制信号gate_clk，相位时钟clk_dlyi(i＝1，2…N)以及来自控制模块的控制信号ctrl[N:0]，输出为经过拉伸的时钟clk_out。
如图2所示，PVTM电路模块是利用延时单元组成环振，输入激励，令其在该环境下开始振荡，并记录振荡次数counter，counter数目的大小代表着当前电路的PVT环境的好坏。通过计算可知，该振荡次数counter也即为在该环境下为获得延迟一个周期的系统时钟所需的延时单元数目。通过将counter传递给后续的控制模块中，结合外部输入的时钟拉伸使能信号slow以及时钟拉伸尺度信号user_mux，输出控制信号ctrl[N:0]，从系统时钟及相位时钟生成模块产生的时钟中选择目标相位的时钟，实现在单周期内，对不同PVT的环境下系统时钟的拉伸。
PVTM电路模块由三个子电路组成，分别是分频电路、环振电路以及计数器电路1。分频电路利用上升沿触发的D触发器构建，通过将系统时钟clk进行K分频(K为大于1的整数)，得到分频时钟clk_div。环振电路由1个二输入与非门以及M级延时单元串联而成(M为大于1的整数)，本发明所选择的延时单元相当于数级串联而成的缓冲器(buffer)。最后一级延时单元的输出信号osc_out与分频时钟clk_div共同作为上述二输入与非门的输入，形成闭环。二输入与非门的输入信号分频时钟clk_div为环振的起振信号，当分频时钟clk_div为低电平时，锁定与非门的输出为高电平，环振不振荡；当分频时钟clk_div为高电平时，环振开始振 荡，在其最后一级延时单元输出振荡信号osc_out。输入该振荡信号至PVTM电路模块中的计数器电路1，统计其振荡次数。当分频时钟由高电平转为低电平时，环振结束振荡，计数器电路1同时停止计数。同时分频电路输出有效的采样信号clk_sample_counter至计数器电路1，对振荡次数进行采样。数据采样结束后，分频电路输出复位信号out_rst至计数器电路1，令计数数据复位，并输出采样之后的数据counter至控制模块。
利用振荡次数counter数据，通过下式可计算出当前PVT环境下相位时钟生成模块延时链所需要的延时单元数目N1：
Figure PCTCN2017074785-appb-000001
其中M，K分别为PVTM电路模块环振中延时单元数目、分频电路时钟分频数。N为综合所有PVT环境所需延时单元数目，取各PVT环境下所需延时单元数目的最大值。该式从理论上推出，在当前环境下，从延时链上第N1个延时单元得到的相位时钟clk_dlyN1与系统时钟clk相位差为2π。该数N1与延时链实际所需要的延时单元数目N0有一定的误差，但误差在允许范围之内。在PVTM电路模块环振中，当分频时钟clk_div由高电平转为低电平时，环振应停止振荡，然而由于clk_div信号的转变仍可能会导致环振产生最后一次振荡，因此counter数据应该舍去最后一次，以提高计数的精确度。
相位时钟生成模块由N级延时单元串联而成，组成延时链，为提高时钟拉伸的准确度，该延时链中的延时单元与上述PVTM中环振所用延时单元为同一型号。相位时钟生成模块以系统时钟clk作为延时链的初始输入信号，每一级延时单元对系统时钟将产生一定的相位偏移，由此可获取具有不同相位的N+1个相位时钟(把系统时钟也视为一个相位时钟)，相邻相位时钟之间的延迟时间即为在当前PVT环境下的1个延时单元的延迟时间。
在本发明中，拉伸后时钟的周期由下式决定：
TStretch＝TOriginal+Δt*N1/2user_mux
其中TStretch为拉伸后的时钟周期，TOriginal为时钟拉伸前时的周期值，即为系统时钟周期，Δt为一个延时单元在当前PVT环境下的延时，N1为在当前环境下，相位时钟生成模块延时链所需要的延时单元数目。user_mux为可配输入变量，控制拉伸时钟输出周期。user_mux信号决定了时钟拉伸的尺度，其位宽为整数X，该数值取决于用户需要实现的最小时钟拉伸粒度1/2L，其中L是位宽为X的二进制数字所能表示的最大十进制数。举例位宽X为2时，能表示的最大十进制数为3，则可实现的最小时钟拉伸时间为1/8个周期，除此还可实现拉伸1/4、1/2个周期，具体可通过配置user_mux的数值来实现。由于N0为当前环境下获得一个与系统时钟clk相位差为2π的时钟实际所需要的延时单元数目，因此有Δt*N0≈TOriginal， N0与N1误差较小，因此有Δt*N1≈TOriginal，故通过配置不同user_mux便可得到不同周期的拉伸时钟。例如当user_mux为1时，则拉伸之后的时钟周期为：
TStretch＝TOriginal+Δt*N1/2≈3*TOriginal/2
控制模块根据外部输入的时钟拉伸使能信号slow以及时钟拉伸尺度信号user_mux产生控制信号，以决定时钟的选择。在时钟拉伸使能信号slow的作用下，选择是否对时钟进行拉伸。slow＝0时，时钟控制信号ctrl[0]有效，模块输出为系统时钟，slow＝1时，模块对系统时钟进行拉伸，选择相应的时钟控制信号ctrl[N:1]，输出拉伸之后的时钟clk_out。控制模块输出信号为位宽为N+1的ctrl信号，在每个周期内，只有一位为高电平，其余为低电平，其中电平为高的控制信号代表选择对应的相位时钟。
控制模块由计数器电路2以及编码器组成，编码器电路通过检测拉伸使能信号的下降沿，即拉伸使能信号由有效变为无效时，产生门控时钟信号gate_clk，决定是否对输出时钟进行门控一个周期。计数器电路2以步长Z在每周期内累加一次产生唯一的高电平控制信号ctrl[S]，即代表选择相位时钟clk_dlyS，S＝Z*i(i＝1,2,3…)，步长Z＝counter/2user_mux。若当S大于counter数值时，即表示所选的相位时钟clk_dlyS与当前主时钟clk的相位大于2π，则需从clk_dly1开始重新选择相位时钟。另外，此时需将控制信号ctrl[N:0]置为低电平，保持一个周期，在下一个周期置控制信号ctrl[M]为高电平，即选择clk_dlyM，M＝S-counter。否则由于M小于S，即clk_dlyM的有效沿在clk_dlyS之前，将导致在clk_dlyM与clk_dlyS的有效沿之间，时钟同步模块中的ctrl_synM信号与clk_dlyS信号在一段时间内会同时为高电平，表示同时选择了两个相位时钟，造成功能错误。
由于上述控制模块中的控制信号与对应的相位时钟信号为异步信号，在后续的时钟选择组合逻辑电路中可能产生毛刺，故需要进行数据同步处理。即利用N个下降沿有效的D触发器，将上述控制模块中的控制信号ctrl[N:1]与对应的相位时钟信号clk_dlyN…clk_dly2,clk_dly1进行同步处理，即第S位控制信号ctrl[S]作为第S个触发器的数据端输入信号，第S个相位时钟clk_dlyS作为该触发器的时钟信号，输出同步控制信号ctrl_syn[S]，以避免在时钟选择时产生毛刺(S＝1,2…N)。控制信号ctrl[0]不经过同步处理，直接与系统时钟clk进行与操作。同步之后的信号ctrl_syn[S]再与之前D触发器的时钟信号clk_dlyS进行与操作(S＝1,2…N)，将所有N+1个与门的输出连接到一个具有N+1个输入端口的或门，该或门的输出即为拉伸时钟。
由于本发明采用的相位时钟生成模块是由延时链组成，故在时钟拉伸使能信号由有效变为无效时(本发明中为由1到0的变化)，控制模块需要选择是否对输出时钟进行门控一个周 期，即让当前时钟输出高电平一个周期，以避免产生不必要的毛刺或者短脉冲。在时钟拉伸使能信号slow无效时，若当前时钟同步选择模块所选择的相位时钟与系统时钟的相位差小于等于π，则将门控时钟控制信号gate_clk置为高电平，即表示对当前输出时钟进行门控一个周期；若当前时钟同步选择模块所选择的相位时钟与系统时钟的相位差大于π，则将门控时钟控制信号gate_clk置为低电平，即表示当前输出时钟选择系统时钟，停止拉伸。
图3所示为时钟拉伸原理时序图。时钟拉伸的操作就是根据拉伸尺度的不同，选择所需的目标相位时钟。
本发明以图3为例具体说明时钟拉伸原理，即时钟拉长的时间为两个延时单元的延时值。在时钟拉伸使能信号slow为低电平时，输出信号clk_out输出的为系统时钟clk(如图3中①所示)。当时钟拉伸使能信号slow有效时——即为高电平，开始对时钟进行拉伸。由于本发明电路中采用的触发器均为下降沿有效，故在clk的下降沿到达时，控制信号ctrl[2]为高电平。由于各相位时钟和控制信号为异步信号，在时钟选择中可能产生不必要的毛刺，影响电路功能。故为了避免产生毛刺，我们将控制信号ctrl[2]与对应的相位时钟clk_dly2进行同步处理，则在clk_dly2的下降沿到达后，才会选择clk_dly2(如图3中②所示)。同理，在clk的第二个下降沿到达后，经过信号同步之后才会选择相应的相位时钟clk_dly4(如图3中③所示)，以此类推。在时钟拉伸使能信号slow转为低电平时，时钟输出应停止对时钟进行拉伸，选择系统时钟。由于此时clk_out与clk的相位差未知，若在时钟拉伸使能信号slow无效后直接选择系统时钟clk，可能产生毛刺或者时钟压缩。如本例所示，在时钟拉伸结束后选择系统时钟，由于clk_dly4与clk相位差小于π，故出现了短脉冲(如图3中④、⑤，即虚线所示)，将影响电路正常工作。因此在这个时刻需对clk_out门控一个时钟，即令gate_clk为高电平(如图3中⑥所示)，输出一个周期的高电平，在gate_clk为低电平时，输出系统时钟(如图3中所⑦示)。
图4所示，电路在基于SMIC 40nm工艺库，使用Hsim软件对PVTM电路模块在不同工艺角、电压、温度的环境下仿真，得到了N0与N1的数据比较。通过对比可知，两数误差较小，表示该时序监测模块准确度较高。
图5表示在FF工艺角，0.7V，25℃环境下，拉伸尺度为1/8个周期的仿真波形图。当拉伸信号slow有效时，在触发器下降沿被采样。从图中可以看出输出时钟低电平得到了拉伸，且拉伸时长为1/8个周期左右，响应速度在一个周期内。由于在时钟拉伸使能信号slow无效时，输出时钟选择的相位时钟与系统时钟clk相位差约为π/2，故为了避免在电路最后产生时钟压缩，对时钟输出采取门控一个时钟，输出一个周期的高电平。
图6所示，为在TT工艺角，0.8V，25℃环境下，拉伸尺度为1/4个周期的仿真波形图。 当拉伸信号slow有效时，在触发器下降沿被采样。从图中可以看出输出时钟得到了拉伸，且拉伸时长为1/4个周期左右，响应速度为一个周期内。由于在时钟拉伸使能信号slow无效时，输出时钟选择的相位时钟与系统时钟clk相位差约为π，故为了避免在电路最后产生时钟压缩，对时钟输出采取门控一个时钟，输出高电平。
图7所示，为在SS工艺角，1.1V，25℃环境下，拉伸尺度为1/2个周期的仿真波形图。当拉伸信号slow有效时，在触发器下降沿被采样。从图中可以看出输出时钟得到了拉伸，且拉伸时长为1/2个周期左右，响应速度为一个周期内。由于在时钟拉伸使能信号slow无效时，输出时钟选择的相位时钟与系统时钟clk相位差约为2π，并不会产生时钟压缩的情况，因此该情况不需要对电路进行门控。
一个实施案例
在基于PVTM的宽电压时钟拉伸电路的一个具体实施案例中，采用SMIC提供的40nm工艺库，利用synopsys公司提供的软件仿真平台，在不同PVT环境下对该电路进行功能仿真测试。首先设计各个模块的电路结构，利用硬件电路语言对电路进行建模，对其电路功能进行仿真验证，并不断优化。设定电路工作频率为200MHz，选定PVTM电路模块中分频电路的时钟分频数K为16，环振中延时单元数目M为4，相位时钟生成模块延时链中延时单元数目N为59。分别在FF、TT、SS不同工艺角，以及不同电压、温度下，改变时钟拉伸尺度信号user_mux的数值，进行仿真，得到仿真结果如图5、6、7所示。
图5、6、7显示了电路在时钟拉伸使能信号slow有效时，均在系统时钟下降沿(一个周期内)开始响应时钟拉伸的请求，开始对系统时钟进行拉伸。对于不同的拉伸尺度请求，分别实现对时钟拉长不同的时间。如图6所示，为在TT工艺角，0.8V，25℃环境下，时钟拉伸尺度信号user_mux为2，即时钟拉伸为1/4个周期。由仿真波形图可知，当拉伸信号slow有效时，在触发器下降沿被采样。从图中可以看出输出时钟得到了拉伸，且拉伸时长为1/4个周期左右，响应速度为一个周期内。由于在时钟拉伸使能信号slow无效时，输出时钟选择的相位时钟与系统时钟clk相位差约为π，故为了避免在电路最后产生时钟压缩，对时钟输出采取门控一个时钟，输出高电平。
以上结果显示了本发明能够在单周期内迅速实现时钟拉伸，时钟拉伸的精度较好，误差较小，使用的电路结构简单。

Claims (9)

  1. 一种基于PVTM的宽电压时钟拉伸电路，其特征在于包括：
    PVTM电路模块，实时监测芯片中延时单元的延时信息，并将延时信息反馈到控制模块；
    相位时钟生成模块，利用系统时钟产生N个具有不同相位的相位时钟，N为大于1的整数；
    控制模块，在时钟拉伸使能信号以及时钟拉伸尺度信号的作用下，根据PVTM电路模块反馈的延时信息，产生控制信号；
    时钟同步选择模块，响应所述控制信号，从系统时钟及N个相位时钟中选择目标相位时钟输出，实现在单周期内，对系统时钟拉伸。
  2. 根据权利要求1所述的基于PVTM的宽电压时钟拉伸电路，其特征在于所述PVTM电路模块包括：
    一分频电路，利用D触发器对系统时钟进行分频，得到分频时钟；
    一环振电路，由1个二输入与非门以及M级延时单元串联而成，M为大于1的整数，最后一级延时单元输出的振荡信号与分频时钟共同作为所述二输入与非门的输入，形成闭环；
    一计数器电路1，输入所述振荡信号，对振荡次数进行采样，并输出采样结果至控制模块。
  3. 根据权利要求1所述的基于PVTM的宽电压时钟拉伸电路，其特征在于：所述相位时钟生成模块由N级延时单元串联而成。
  4. 根据权利要求1所述的基于PVTM的宽电压时钟拉伸电路，其特征在于：所述控制模块包括一计数器电路2，用于产生N+1位时钟选择控制信号ctrl[N:0]，决定目标相位时钟的选择，在每个周期内，只有一位时钟选择控制信号有效。
  5. 根据权利要求4所述的基于PVTM的宽电压时钟拉伸电路，其特征在于：时钟拉伸使能信号有效时，所述计数器电路2以步长Z＝counter/2user_mux在每周期内累加一次产生唯一有效的时钟选择控制信号ctrl[S]，用于选择相应的相位时钟，counter为PVTM电路模块输出信号的值，user_mux为时钟拉伸尺度信号的值，S＝Z*i，i＝1,2,3…，当S大于counter时，从相位时钟生成模块生成的最低相位时钟开始重新选择相位时钟。
  6. 根据权利要求1所述的基于PVTM的宽电压时钟拉伸电路，其特征在于：所述控制模块包括一编码器，当编码器检测到拉伸使能信号由有效变为无效时，产生一门控时钟控制信号，决定是否对目标相位时钟进行门控一个周期后再输出。
  7. 根据权利要求1所述的基于PVTM的宽电压时钟拉伸电路，其特征在于：所述时钟同步选择模块包括N个D触发器及若干门电路，最低位控制信号与系统时钟通过与门进行与操作，其余N位控制信号分别作为N个D触发器的数据输入信号，N个相位时钟分别作为N个D触发器的时钟输入信号，与对应的控制信号进行同步处理，N个D触发器的数据输出信 号与其时钟输入信号分别通过与门进行与操作后，将所有N+1个与门的输出连接到一个具有N+1个输入端口的或门，该或门的输出即为拉伸时钟。
  8. 根据权利要求6所述的基于PVTM的宽电压时钟拉伸电路，其特征在于：当时钟拉伸使能信号无效时，若当前时钟同步选择模块所选择的相位时钟与系统时钟的相位差小于等于π，则将门控时钟控制信号置为有效，对当前输出时钟进行门控一个周期，之后停止时钟拉伸，输出系统时钟；若当前时钟同步选择模块所选择的相位时钟与系统时钟的相位差大于π，则将门控时钟控制信号置为无效，停止时钟拉伸，输出系统时钟。
  9. 根据权利要求1所述的基于PVTM的宽电压时钟拉伸电路，其特征在于：N为相位时钟生成模块延时链中延时单元数目，其确定原则为：在芯片当前工作环境下，通过相位时钟生成模块中的延时链的末端能获得一个与系统时钟相位差为2π的相位时钟。
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