WO2017185764A1 - 一种链路质量自适应调优方法 - Google Patents
一种链路质量自适应调优方法 Download PDFInfo
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- WO2017185764A1 WO2017185764A1 PCT/CN2016/109584 CN2016109584W WO2017185764A1 WO 2017185764 A1 WO2017185764 A1 WO 2017185764A1 CN 2016109584 W CN2016109584 W CN 2016109584W WO 2017185764 A1 WO2017185764 A1 WO 2017185764A1
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- Prior art keywords
- dfe
- serdes
- adaptive
- chip
- configuration
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0034—Sun microsystems bus [SBus]
Definitions
- the present invention relates to the field of integrated circuit chip design and the field of digital communication technologies, and particularly relates to a link quality adaptive tuning method, and a link quality adaptive tuning method for a high speed serial interface Serdes. Background technique
- Ser Des Serializer-Deserializer
- Ser Des is the main component of the high-speed serial interface protocol physical layer implementation, and its performance is directly related to the quality of high-speed communication.
- the linear equalizer For high speed (>501 ⁇ ) 8 6 11 ⁇ , since the jitter of the signal (such as the deterministic jitter of IS Xiangguan) may exceed or approach a symbol interval (UI, Unit Interval), only the linear equalizer is used. No longer applicable, the linear equalizer amplifies the noise and the signal together, with no significant improvement in the bit error rate.
- D FE Decision Feedback Equalization
- the sampling threshold of the current bit is predicted by tracking data of a plurality of UIs in the past, and only the signal is amplified, and the noise is not amplified, and the SN R can be effectively improved.
- the coefficients of the DFE are close to the corresponding pulses of the channel, the ideal result can be obtained.
- the channel is a metamorphic medium. Factors such as slow changes in the temperature and voltage process can change the characteristics of the channel ch annel. Therefore, the coefficients of the DFE require an adaptive algorithm that automatically captures and follows the changes in the channel. For each vendor, the DFE coefficient adaptive algorithm is confidential and not announced. From the perspective of the Serdes user, if the DFE ROM provided by the manufacturer does not improve the quality of the Serdes link, the performance of the product will be improved. Causes a greater impact.
- the technical problem to be solved by the present invention is:
- the present invention proposes a link quality adaptive tuning method for a high-speed serial interface Serdes, a PRBS-31 pseudo-random sequence code generation and comparison, supplemented by The chip temperature difference and the transmission error rate are used as a tuning method for the link transmission quality indicator.
- a link quality adaptive tuning method for a link of a high speed serial interface Serdes, the method adds a PRBS-31 pseudo random code generation/verification to a de-emphasis equalization process of a high speed serial interface, The bit error rate and temperature change are used as the DFE end judgment flag to form a fixed flow of high-speed Serdes link quality tuning.
- the method includes seven links:
- the EQ parameter value is written into the De-emphas is configuration register corresponding to the Serdes configuration module via the SMBUS bus.
- the Serde s transmitter Tx is configured to be in BIST mode, and the PRBS-31 pseudo-random sequence code is sent.
- the receiver Rx is snoring. Data comparison, and configure the desired pattern as PRBS-31;
- the implemented DFE program microcode is uploaded into the RA M memory of the chip through the SMBUS bus. After the upload is completed, the CRC is verified and passed.
- the Rx adaptive DFE process observes the DFE status register until both the Coarse status and the Fine status are displayed, and the DFE mode is switched to Adaptive one loop;
- step 6) DFE completion and data source switching at the transmitting end. If the two conditions in step 6) are not satisfied, that is, the bit error rate is less than 10E-10 and the temperature difference is less than 10 degrees Celsius, the DFE is completed, and after the DFE is disabled, Switch the data source of the high-speed serial interface from the BIST test data sequence to the core data.
- the method flow is solidified into an automated script, and the system is automatically executed each time the machine is powered on.
- the method uses a high-speed serial interface to communicate between the chip and the chip, and implements a physical layer of the high-speed serial interface protocol based on SerDes.
- the specific tuning steps are as follows:
- the de-emphasis parameter of the Serdes Tx is first configured, and the de-emphasis parameter is divided into three parts: Pre-cursor, Post-cursor and Attn (Amp), and the values of the three parameters are all Pre-simulation by PCB simulation to 'J;
- the BIST mode is set to i_tx_pattem_gen_en, and i_tx_pattern_gen_sel is configured, the transmitting end Tx starts to send a pseudo-random sequence code of the PRBS-31 pattern, and the 16-bit spico processor integrated in the serdes configuration management module sbus master
- the DFE program micro-code is uploaded to the corresponding RAM memory of the chip, which is provided by the Serdes IP manufacturer. After the upload is complete, issue a spico interrupt, perform a CRC check on the micro-code in the RAM, and return 00010001 to pass, otherwise re-upload the program.
- a Sync synchronization is performed on each chip by the BMC to ensure that the interactive Serses in each chip has completed the Tx EQ configuration and the micro-code upload;
- the DFE_USER_CON FIG register is configured in the coarse-tuning-adaptive order
- the Serdes adaptive equalization parameter adjustment process is started, and the chip before the DFE is started is recorded.
- the initial temperature is obtained by the sensor; after 10 seconds of Adaptive tuning, the Rx terminal error rate and chip temperature of the chirp are collected, and if the bit error rate is not less than 10E-10, that is, the error generated in each 100 billion bits Large one, or two times before and after the temperature difference is not less than 10 degrees Celsius, then continue to maintain Adaptive tuning
- the method of the present invention adds the PRBS-31 pseudo-random code generation/verification to the de-emphasis equalization process of the high-speed serial interface, and uses the bit error rate and the temperature change as the DFE end judgment flag to form a high-speed Serdes link quality adjustment.
- this method can effectively improve the transmission quality of the Serdes link, significantly reduce the transmission error rate, and thus improve the transmission performance of the chip bus, and has a high degree of automation, with fast link tuning speed and good effect. .
- FIG. 1 is a flow chart of Serdes link quality adaptive tuning.
- Embodiment 1 is a diagrammatic representation of Embodiment 1 :
- a link quality adaptive tuning method for a link of a high speed serial interface Serdes, the method adds a PRBS-31 pseudo random code generation/verification to a de-emphasis equalization process of a high speed serial interface, The bit error rate and temperature change are used as the DFE end judgment flag to form a fixed flow of high-speed Serdes link quality tuning.
- the method in this embodiment includes seven links:
- the Serde s transmitter Tx is configured to be in BIST mode, and the PRBS-31 pseudo-random sequence code is sent.
- the receiver Rx is snoring. Data comparison, and configure the desired pattern as PRBS-31;
- the implemented DFE program microcode is uploaded into the RA M memory of the chip through the SMBUS bus. After the upload is completed, the CRC is verified and passed.
- the Rx adaptive DFE process observes the DFE status register until both the Coarse status and the Fine status are displayed, and the DFE mode is switched to Adaptive one loop;
- step 6) DFE completion and data source switching at the transmitting end. If the two conditions in step 6) are not satisfied, that is, the bit error rate is less than 10E-10 and the temperature difference is less than 10 degrees Celsius, the DFE is completed, and after the DFE is disabled, Switch the data source of the high-speed serial interface from the BIST test data sequence to the core data.
- the embodiment solidifies the process into an automated script, and the system automatically executes each time the machine is powered on.
- Example 4 On the basis of Embodiment 1, 2 or 3, the method in this embodiment uses a high-speed serial interface for communication between the chip and the chip, and implements a physical layer of the high-speed serial interface protocol based on SerDes, and the specific tuning steps are performed. as follows
- the de-emphasis parameter of the Serdes Tx is first configured, and the de-emphasis parameter is divided into three parts: Pre-cursor, Post-cursor and Attn (Amp), and the values of the three parameters are all Pre-simulation by PCB simulation to 'J;
- the BIST mode is set to i_tx_pattem_gen_en, and the i_tx_pattern_gen_sel is configured, the transmitting end Tx starts to send the pseudo-random sequence code of the PRBS-31 pattern, and the 16-bit spico processor integrated in the serdes configuration management module sbus master
- the DFE program micro-code is uploaded to the corresponding RAM memory of the chip, which is provided by the Serdes IP manufacturer. After the upload is complete, issue a spico interrupt, perform a CRC check on the micro-code in the RAM, and return 00010001 to pass, otherwise re-upload the program.
- a Sync synchronization is performed on each chip by the BMC to ensure that the interactive Serses in each chip has completed the Tx EQ configuration and the micro-code upload;
- the DFE_USER_CON FIG register is configured in the coarse-tuning-adaptive order
- the Serdes adaptive equalization parameter adjustment process is started, and the chip before the DFE is started is recorded.
- the initial temperature is obtained by the sensor; after 10 seconds of Adaptive tuning, the Rx terminal error rate and chip temperature of the chirp are collected, and if the bit error rate is not less than 10E-10, that is, the error generated in each 100 billion bits Large one, or two times before and after the temperature difference is not less than 10 degrees Celsius, then continue to maintain Adaptive tuning
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
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Abstract
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CN201610259324.6 | 2016-04-25 | ||
CN201610259324.6A CN105930225B (zh) | 2016-04-25 | 2016-04-25 | 一种链路质量自适应调优方法 |
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Families Citing this family (11)
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CN105930225B (zh) * | 2016-04-25 | 2017-12-05 | 浪潮电子信息产业股份有限公司 | 一种链路质量自适应调优方法 |
CN108933600B (zh) * | 2017-05-26 | 2020-11-06 | 深圳市中兴微电子技术有限公司 | 一种SerDes链路参数自动调试方法 |
CN109213623B (zh) * | 2017-06-30 | 2022-02-22 | 慧荣科技股份有限公司 | 降低快闪储存介面中传收数据错误方法及装置 |
CN108763001A (zh) * | 2018-05-25 | 2018-11-06 | 郑州云海信息技术有限公司 | 一种通用串行总线测试发包方法 |
CN110035015B (zh) * | 2019-04-23 | 2022-12-06 | 苏州浪潮智能科技有限公司 | 一种优化级联Retimer链路协商过程的方法 |
CN112422354A (zh) * | 2019-08-21 | 2021-02-26 | 富港电子(东莞)有限公司 | 主动式传输线性能的诊断系统及其方法 |
TWI762828B (zh) * | 2019-11-01 | 2022-05-01 | 緯穎科技服務股份有限公司 | 高速序列電腦匯流排的訊號調整方法及其相關電腦系統 |
CN112350785B (zh) * | 2020-10-13 | 2022-05-10 | 苏州浪潮智能科技有限公司 | 一种检验serdes通信链路性能的方法及系统 |
CN113726425B (zh) * | 2021-07-31 | 2023-02-24 | 苏州浪潮智能科技有限公司 | 一种有线通信方法、装置、设备及可读存储介质 |
CN115150303B (zh) * | 2022-07-29 | 2023-08-08 | 苏州浪潮智能科技有限公司 | 一种交换机端口测试方法、系统、设备以及存储介质 |
CN117498858B (zh) * | 2024-01-02 | 2024-03-29 | 上海米硅科技有限公司 | 一种信号质量检测方法及信号质量检测电路 |
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