WO2017184358A1 - Combined anneal and selective deposition process - Google Patents

Combined anneal and selective deposition process Download PDF

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Publication number
WO2017184358A1
WO2017184358A1 PCT/US2017/026519 US2017026519W WO2017184358A1 WO 2017184358 A1 WO2017184358 A1 WO 2017184358A1 US 2017026519 W US2017026519 W US 2017026519W WO 2017184358 A1 WO2017184358 A1 WO 2017184358A1
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Prior art keywords
precursor
reaction chamber
film deposition
substrate
film
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PCT/US2017/026519
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French (fr)
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WO2017184358A8 (en
Inventor
Jan Willem Maes
Werner Knaepen
Roel Gronheid
Arjun Singh
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Interuniversitair Microelektronica Centrum vzw IMEC
ASM IP Holding BV
ASM America Inc
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Interuniversitair Microelektronica Centrum vzw IMEC
ASM IP Holding BV
ASM America Inc
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Priority to KR1020187032144A priority Critical patent/KR102148366B1/en
Priority to CN202511173291.9A priority patent/CN121065438A/en
Priority to CN201780025639.7A priority patent/CN109311052A/en
Publication of WO2017184358A1 publication Critical patent/WO2017184358A1/en
Publication of WO2017184358A8 publication Critical patent/WO2017184358A8/en
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4088—Processes for improving the resolution of the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/61—Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6339—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/68—Organic materials, e.g. photoresists
    • H10P14/683—Organic materials, e.g. photoresists carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
    • H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
    • H10P14/69391—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/405—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their composition, e.g. multilayer masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4083—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by their behaviours during the lithography processes, e.g. soluble masks or redeposited masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering

Definitions

  • the present disclosure generally relates to processes and systems for manufacturing electronic devices. More particularly, the disclosure relates to selective deposition of films. Specifically, the disclosure may disclose methods and systems to selectively form films using a directed self-assembly (DSA) patterning technique.
  • DSA directed self-assembly
  • DSA Directed self-assembly
  • PS-b-PMMA poly(styrene-block-methyl methacrylate)
  • Other block copolymers may include emerging "high-Chi" polymers, which may potentially enable small dimensions.
  • DSA can be used to form parallel lines or regular arrays of holes/pillars/posts with very small pitch and critical dimensions.
  • DSA can define sub-20 nm patterns through self-assembly, while guided by surface topography and/or surface chemical patterning.
  • a DSA polymer layer can be infiltrated with a precursor, or a film may be deposited selectively on one of the polymers of the DSA layers.
  • DSA polymers such as PMMA or polystyrene
  • PMMA or polystyrene have low etch resistance. This makes the transfer of the pattern to layers below more difficult. The issue of low etch resistance becomes greater when the advanced polymers needed to further downscale the size of the semiconductor device has an even lower etch resistance and etch selectivity.
  • the DSA may result in a high line edge roughness in the obtained patterns.
  • Another drawback is that the obtained structure of parallel lines or array of holes may have some defects at random locations.
  • a method to selectively form a film comprises: providing a substrate for processing in a reaction chamber, the substrate having at least one polymer layer disposed on the substrate; performing an annealing step on the substrate; and performing a film deposition by sequentially pulsing a first precursor and a second precursor onto the substrate, the film deposition being configured to enable infiltration of at least the first precursor into the at least one polymer layer, wherein an excess of the first precursor and the second precursor are purged from the reaction chamber; wherein a film forms on the at least one polymer from the first precursor.
  • a method for selectively forming a film may comprise: providing a substrate for processing in a reaction chamber, the substrate having at least one polymer layer disposed on the substrate; performing a film deposition by sequentially pulsing a first precursor and a second precursor onto the substrate, the film deposition being configured to enable infiltration of at least the first precursor into the at least one polymer layer, wherein an excess of the first precursor and the second precursor are purged from the reaction chamber; and performing an annealing step on the substrate; wherein a film forms on the at least one polymer from the first precursor.
  • FIG. 1 is a flowchart of a method in accordance with at least one embodiment of the invention.
  • Embodiments in accordance with the invention relate to the combination of DSA techniques with selective deposition. This combination can increase the etch resistance of polymers significantly. Selective deposition allows for particular polymers to be reacted with a precursor gas, while leaving other polymers untouched.
  • Combining selective deposition with DSA patterning may provide benefits previously unseen with prior approaches, such as the one described in US Patent Publication No. US 2014/0273514 Al .
  • a selective deposition of aluminum oxide (AI 2 O 3 ) at 90°C may allow the reaction with a PMMA polymer, while leaving a polystyrene polymer untouched.
  • the aluminum oxide will not only deposit on top of the PMMA polymer, but may be infused into the PMMA polymer to increase the rigidity of the PMMA polymer.
  • FIG. 1 illustrates a method 100 in accordance with at least one embodiment of the invention.
  • the method 100 includes a first step 110 of providing a wafer with multiple polymers in a processing chamber.
  • the wafer may have at least a first DSA polymer and a second DSA polymer, wherein the first DSA polymer and the second DSA polymer may be made of PMMA, polystyrene (PS), among other polymers.
  • the processing chamber may be a batch reactor or a cluster tool with two batch reactors.
  • One example of a potential processing chamber may include an A412 system from ASM International N.V., which may run in two reactor chambers the same process or run two different processes independently or sequentially.
  • the method 100 may include a second step 120 of performing a self- assembly anneal of the DSA polymers.
  • the purpose of the annealing process is to incite the self-assembly or self-organization in the DSA polymers or the block copolymer.
  • parallel lines or grids of holes/pillars/posts in the polymers may be formed as directed by guidance structures on the substrate.
  • this may mean that domains of PMMA and domains of PS may be formed in an alternating manner.
  • the benefits achieved by the self-assembly anneal may include improvement of the self-assembly process, reduction of defects, improved line width roughness, and improved critical dimension (CD) uniformity.
  • the anneal of the second step 120 may have a purpose of degassing moisture or other contaminants from the polymer, hardening the polymer, or selectively burning away one of the polymer types from the substrate surface.
  • process parameters such as the time, temperature, and the ambient conditions and pressure of the annealing process, are critical.
  • a long annealing time may be needed to obtain a low defect density.
  • the anneal may take place at a temperature ranging between 100°C and 400°C, preferably between 200°C and 300°C, and most preferably 250°C, for about 60 minutes. Other temperatures and durations are possible depending on the amount of anneal desired.
  • the temperature of the self-assembly anneal should not be increased too high or the polymers may start to decompose.
  • the ambient environment in which the annealing is done may comprise nitrogen, argon, helium, hydrogen, oxygen, ozone, water vapor, solvent vapors, or mixtures of these gases.
  • the pressure of the anneal ambient environment can be any pressure in the range from ultra-high vacuum to atmospheric pressure or even above atmospheric pressure.
  • the annealing process may take place on a single wafer hot plate.
  • a batch reactor may prove to be beneficial for processes needing a long anneal time.
  • the batch reactor may hold between 2 and 250 substrates, preferably between 5 and 150 substrates, or most preferably about 100 substrates.
  • the A412 may be operated such that one reactor may be used for an anneal process. This may enable to perform long anneals on the order of 1-2 hours in a cost effective way.
  • the method 100 may also include a third step 130 of performing a selective deposition of a metal or a dielectric film on top of either the first DSA polymer or the second DSA polymer.
  • the selective deposition may be done in a way that the deposited film may react selectively with only one of the two polymers.
  • the selective deposition may take place such that the deposited film may react with PMMA polymer and not PS polymer.
  • the third step 130 may comprise an atomic layer deposition of the metal or dielectric film.
  • the selective deposition may be done such that the deposited metal or dielectric film may infiltrate a polymer, while also depositing a second film on the whole volume of the polymer domain.
  • the third step 130 may take place in one reactor of an A412 system, such that the second step 120 takes place in the other reactor of the A412 system. It may also be possible that the second step 120 and the third step 130 take place in one single reactor of the A412 system.
  • the metal or dielectric deposited in the third step 130 may comprise aluminum oxide (AI 2 O 3 ), silicon dioxide (Si0 2 ), silicon nitride (SiN), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), aluminum nitride (AIN), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), cobalt (Co), titanium dioxide (Ti0 2 ), tantalum oxide (Ta 2 0 5 ), zirconium dioxide (Zr0 2 ), or hafnium dioxide (Hf0 2 ).
  • precursors to obtain the metal may be used, such as trimethylaluminum (TMA) and water (H 2 0) for the formation of A1 2 0 3 .
  • the selective deposition in the third step 130 may take place at a temperature ranging between 25°C and 300°C, with a preferable temperature range of 70°C- 90°C for the formation of A1 2 0 3 .
  • the temperature during the third step 130 may be less than the temperature during the second step 120, so a cooldown step may be needed to go from an example annealing temperature of 250°C to a third step 130 temperature of 70°C.
  • a temperature of the second step 120 is at least 25°C higher than that of the third step 130, preferably between 25°C -300°C higher than that of the third step 130, or more preferably between 100°C -250°C higher than that of the third step 130.
  • the third step 130 may comprise a first pulse of a first precursor, such as TMA, for a duration ranging from 30 seconds to 10 minutes.
  • the third step 130 may also then comprise a purge for a duration ranging from 10 to 60 seconds.
  • the third step 130 may then comprise a pulse of a second precursor, such as water, for a duration ranging from 10 to 60 seconds.
  • the third step 130 may then comprise a second purge having a duration ranging from 10 seconds to 2 minutes.
  • the third step 130 may be repeated as needed in order to obtain sufficient deposition of the metal.
  • the third step 130 of film deposition may precede the second step 120 of annealing.
  • the metal or dielectric film may first infiltrate the polymer, and then an annealing process may occur.
  • polymer that did not react with the metal or dielectric film during the third step 130 may be burned away in the second step 120.
  • the method 100 may also include a fourth step 140 of purging the precursors.
  • the fourth step 140 may involve introduction of a purge gas such as nitrogen, helium, argon, and other inert gases.
  • the purge gas would remove excess precursor from the fourth step 140 from the processing chamber.
  • the fourth step 140 may take place at a temperature similar to those of the third step 130.
  • the third step 130 may be repeated as necessary in order to allow the precursors to infiltrate into the DSA polymer.
  • the cycle may be repeated approximately 5 times to ensure sufficient amount of the metal or dielectric film in the DSA polymer.
  • the time duration of the third step 130 may be on the order of a few minutes. With these time durations, a batch reactor may be used to achieve high productivity and low process costs by processing up to 100 wafers or more at a time.
  • the method 100 may be operated such that the third step 130 may be repeated in a pulse-purge-pulse- purge manner.
  • the conditions of these steps may be set at higher pressure and a longer time in order to allow the precursors to infiltrate the polymers.
  • a single cycle in this manner may range between 1 and 20 minutes in duration.
  • the cycle may be repeated several times, typically five times, in order to obtain sufficient deposition of the material inside the polymer. Because infiltration of the material inside the polymer may take a longer amount of time, a combined annealing and deposition process provides an opportunity to perform steps in a batch manner.
  • a potential application for use of a combined annealing and selective deposition process may be for extreme ultraviolet (EUV) photoresist.
  • EUV extreme ultraviolet
  • the annealing for a EUV application may not be for the self-assembly of the polymer, but may serve a curing or stabilizing purpose.
  • the combined annealing and selective deposition process in accordance with at least one embodiment of the invention may assist in the sequential infiltration synthesis (SIS) step as potentially preventing conversion of carboxyl groups, or by degassing moisture from the polymer film or by stabilizing or hardening the photoresist.
  • SIS sequential infiltration synthesis

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical Vapour Deposition (AREA)
  • Formation Of Insulating Films (AREA)
  • Photovoltaic Devices (AREA)

Abstract

A method for forming a film with an annealing step and a deposition step is disclosed. The method comprises an annealing step for inducing self-assembly or alignment within a polymer. The method also comprises a selective deposition step in order to enable selective deposition on a polymer.

Description

COMBINED ANNEAL AND SELECTIVE DEPOSITION PROCESS
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is related to U.S. Non-Provisional Patent Application 15/132,084, filed April, 18, 2016 and entitled "COMBINED ANNEAL AND SELECTIVE DEPOSITION SYSTEMS," attorney docket no. ASMMC.129AUS, and U.S. Provisional Patent Application 62/324,255, filed April 18, 2016 and entitled "METHOD OF FORMING A DIRECTED SELF- ASSEMBLED LAYER ON A SUBSTRATE," attorney docket no. IMEC928.001PRF, the disclosures of which are hereby incorporated by reference in their entireties.
FIELD
[0002] The present disclosure generally relates to processes and systems for manufacturing electronic devices. More particularly, the disclosure relates to selective deposition of films. Specifically, the disclosure may disclose methods and systems to selectively form films using a directed self-assembly (DSA) patterning technique.
BACKGROUND
[0003] As the trend has pushed semiconductor devices to smaller and smaller sizes, different patterning techniques have arisen. These techniques include spacer defined quadruple patterning, extreme ultraviolet lithography (EUV), and EUV combined with Spacer Defined Double patterning. These approaches have allowed production of nodes in the 7 nm range.
[0004] Directed self-assembly (DSA) has been considered as an option for future lithography applications. DSA involves the use of block copolymers to define patterns for self- assembly. The block copolymers used may include poly(methyl methacrylate) (PMMA), polystyrene, or poly(styrene-block-methyl methacrylate) (PS-b-PMMA). Other block copolymers may include emerging "high-Chi" polymers, which may potentially enable small dimensions.
[0005] DSA can be used to form parallel lines or regular arrays of holes/pillars/posts with very small pitch and critical dimensions. In particular, DSA can define sub-20 nm patterns through self-assembly, while guided by surface topography and/or surface chemical patterning. As a result, a DSA polymer layer can be infiltrated with a precursor, or a film may be deposited selectively on one of the polymers of the DSA layers.
[0006] However, the DSA technique has several drawbacks. In particular, DSA polymers, such as PMMA or polystyrene, have low etch resistance. This makes the transfer of the pattern to layers below more difficult. The issue of low etch resistance becomes greater when the advanced polymers needed to further downscale the size of the semiconductor device has an even lower etch resistance and etch selectivity. In addition, the DSA may result in a high line edge roughness in the obtained patterns. Another drawback is that the obtained structure of parallel lines or array of holes may have some defects at random locations.
[0007] As a result, a method for selectively forming a film with higher etching resistance and etching selectivity is desired.
SUMMARY
[0008] In accordance with at least one embodiment of the invention, a method to selectively form a film is disclosed. The method comprises: providing a substrate for processing in a reaction chamber, the substrate having at least one polymer layer disposed on the substrate; performing an annealing step on the substrate; and performing a film deposition by sequentially pulsing a first precursor and a second precursor onto the substrate, the film deposition being configured to enable infiltration of at least the first precursor into the at least one polymer layer, wherein an excess of the first precursor and the second precursor are purged from the reaction chamber; wherein a film forms on the at least one polymer from the first precursor.
[0009] In accordance with at least one embodiment of the invention, a method for selectively forming a film is disclosed. The method may comprise: providing a substrate for processing in a reaction chamber, the substrate having at least one polymer layer disposed on the substrate; performing a film deposition by sequentially pulsing a first precursor and a second precursor onto the substrate, the film deposition being configured to enable infiltration of at least the first precursor into the at least one polymer layer, wherein an excess of the first precursor and the second precursor are purged from the reaction chamber; and performing an annealing step on the substrate; wherein a film forms on the at least one polymer from the first precursor.
[0010] For purposes of summarizing the invention and the advantages achieved over the prior art, certain objects and advantages of the invention have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught or suggested herein without necessarily achieving other objects or advantages as may be taught or suggested herein.
[0011] All of these embodiments are intended to be within the scope of the invention herein disclosed. These and other embodiments will become readily apparent to those skilled in the art from the following detailed description of certain embodiments having reference to the attached figures, the invention not being limited to any particular embodiment(s) disclosed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] These and other features, aspects, and advantages of the invention disclosed herein are described below with reference to the drawings of certain embodiments, which are intended to illustrate and not to limit the invention.
[0013] FIG. 1 is a flowchart of a method in accordance with at least one embodiment of the invention.
[0014] It will be appreciated that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of illustrated embodiments of the present disclosure. DETAILED DESCRIPTION
[0015] Although certain embodiments and examples are disclosed below, it will be understood by those in the art that the invention extends beyond the specifically disclosed embodiments and/or uses of the invention and obvious modifications and equivalents thereof. Thus, it is intended that the scope of the invention disclosed should not be limited by the particular disclosed embodiments described below.
[0016] Embodiments in accordance with the invention relate to the combination of DSA techniques with selective deposition. This combination can increase the etch resistance of polymers significantly. Selective deposition allows for particular polymers to be reacted with a precursor gas, while leaving other polymers untouched.
[0017] Combining selective deposition with DSA patterning may provide benefits previously unseen with prior approaches, such as the one described in US Patent Publication No. US 2014/0273514 Al . For example, a selective deposition of aluminum oxide (AI2O3) at 90°C may allow the reaction with a PMMA polymer, while leaving a polystyrene polymer untouched. The aluminum oxide will not only deposit on top of the PMMA polymer, but may be infused into the PMMA polymer to increase the rigidity of the PMMA polymer.
[0018] FIG. 1 illustrates a method 100 in accordance with at least one embodiment of the invention. The method 100 includes a first step 110 of providing a wafer with multiple polymers in a processing chamber. As described above, the wafer may have at least a first DSA polymer and a second DSA polymer, wherein the first DSA polymer and the second DSA polymer may be made of PMMA, polystyrene (PS), among other polymers. The processing chamber may be a batch reactor or a cluster tool with two batch reactors. One example of a potential processing chamber may include an A412 system from ASM International N.V., which may run in two reactor chambers the same process or run two different processes independently or sequentially.
[0019] The method 100 may include a second step 120 of performing a self- assembly anneal of the DSA polymers. The purpose of the annealing process is to incite the self-assembly or self-organization in the DSA polymers or the block copolymer. In other words, parallel lines or grids of holes/pillars/posts in the polymers may be formed as directed by guidance structures on the substrate. In accordance with at least one embodiment of the invention, this may mean that domains of PMMA and domains of PS may be formed in an alternating manner. The benefits achieved by the self-assembly anneal may include improvement of the self-assembly process, reduction of defects, improved line width roughness, and improved critical dimension (CD) uniformity. Alternatively, the anneal of the second step 120 may have a purpose of degassing moisture or other contaminants from the polymer, hardening the polymer, or selectively burning away one of the polymer types from the substrate surface.
[0020] In order to reach a low defect density in the obtained pattern, process parameters, such as the time, temperature, and the ambient conditions and pressure of the annealing process, are critical. A long annealing time may be needed to obtain a low defect density. The anneal may take place at a temperature ranging between 100°C and 400°C, preferably between 200°C and 300°C, and most preferably 250°C, for about 60 minutes. Other temperatures and durations are possible depending on the amount of anneal desired. However, the temperature of the self-assembly anneal should not be increased too high or the polymers may start to decompose.
[0021] The ambient environment in which the annealing is done may comprise nitrogen, argon, helium, hydrogen, oxygen, ozone, water vapor, solvent vapors, or mixtures of these gases. The pressure of the anneal ambient environment can be any pressure in the range from ultra-high vacuum to atmospheric pressure or even above atmospheric pressure.
[0022] In accordance with one embodiment of the invention, the annealing process may take place on a single wafer hot plate. In accordance with another embodiment of the invention, a batch reactor may prove to be beneficial for processes needing a long anneal time. The batch reactor may hold between 2 and 250 substrates, preferably between 5 and 150 substrates, or most preferably about 100 substrates. For example, the A412 may be operated such that one reactor may be used for an anneal process. This may enable to perform long anneals on the order of 1-2 hours in a cost effective way.
[0023] The method 100 may also include a third step 130 of performing a selective deposition of a metal or a dielectric film on top of either the first DSA polymer or the second DSA polymer. As such, the selective deposition may be done in a way that the deposited film may react selectively with only one of the two polymers. For example, the selective deposition may take place such that the deposited film may react with PMMA polymer and not PS polymer. In accordance with at least one embodiment of the invention, the third step 130 may comprise an atomic layer deposition of the metal or dielectric film.
[0024] Furthermore, the selective deposition may be done such that the deposited metal or dielectric film may infiltrate a polymer, while also depositing a second film on the whole volume of the polymer domain. In accordance with at least one embodiment of the invention, the third step 130 may take place in one reactor of an A412 system, such that the second step 120 takes place in the other reactor of the A412 system. It may also be possible that the second step 120 and the third step 130 take place in one single reactor of the A412 system.
[0025] The metal or dielectric deposited in the third step 130 may comprise aluminum oxide (AI2O3), silicon dioxide (Si02), silicon nitride (SiN), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), aluminum nitride (AIN), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), cobalt (Co), titanium dioxide (Ti02), tantalum oxide (Ta205), zirconium dioxide (Zr02), or hafnium dioxide (Hf02). In order to perform the selective deposition, precursors to obtain the metal may be used, such as trimethylaluminum (TMA) and water (H20) for the formation of A1203.
[0026] The selective deposition in the third step 130 may take place at a temperature ranging between 25°C and 300°C, with a preferable temperature range of 70°C- 90°C for the formation of A1203. The temperature during the third step 130 may be less than the temperature during the second step 120, so a cooldown step may be needed to go from an example annealing temperature of 250°C to a third step 130 temperature of 70°C. In accordance with at least one embodiment of the invention, a temperature of the second step 120 is at least 25°C higher than that of the third step 130, preferably between 25°C -300°C higher than that of the third step 130, or more preferably between 100°C -250°C higher than that of the third step 130.
[0027] The third step 130 may comprise a first pulse of a first precursor, such as TMA, for a duration ranging from 30 seconds to 10 minutes. The third step 130 may also then comprise a purge for a duration ranging from 10 to 60 seconds. The third step 130 may then comprise a pulse of a second precursor, such as water, for a duration ranging from 10 to 60 seconds. The third step 130 may then comprise a second purge having a duration ranging from 10 seconds to 2 minutes. In addition, the third step 130 may be repeated as needed in order to obtain sufficient deposition of the metal.
[0028] In accordance with at least one embodiment of the invention, the third step 130 of film deposition may precede the second step 120 of annealing. In this case, the metal or dielectric film may first infiltrate the polymer, and then an annealing process may occur. As a result of the annealing process, polymer that did not react with the metal or dielectric film during the third step 130 may be burned away in the second step 120.
[0029] The method 100 may also include a fourth step 140 of purging the precursors. The fourth step 140 may involve introduction of a purge gas such as nitrogen, helium, argon, and other inert gases. The purge gas would remove excess precursor from the fourth step 140 from the processing chamber. The fourth step 140 may take place at a temperature similar to those of the third step 130.
[0030] In accordance with at least one embodiment of the invention, the third step 130 may be repeated as necessary in order to allow the precursors to infiltrate into the DSA polymer. The cycle may be repeated approximately 5 times to ensure sufficient amount of the metal or dielectric film in the DSA polymer. In each cycle, the time duration of the third step 130 may be on the order of a few minutes. With these time durations, a batch reactor may be used to achieve high productivity and low process costs by processing up to 100 wafers or more at a time.
[0031] In accordance with at least one embodiment of the invention, the method 100 may be operated such that the third step 130 may be repeated in a pulse-purge-pulse- purge manner. The conditions of these steps may be set at higher pressure and a longer time in order to allow the precursors to infiltrate the polymers. A single cycle in this manner may range between 1 and 20 minutes in duration. The cycle may be repeated several times, typically five times, in order to obtain sufficient deposition of the material inside the polymer. Because infiltration of the material inside the polymer may take a longer amount of time, a combined annealing and deposition process provides an opportunity to perform steps in a batch manner. [0032] A potential application for use of a combined annealing and selective deposition process may be for extreme ultraviolet (EUV) photoresist. The annealing for a EUV application may not be for the self-assembly of the polymer, but may serve a curing or stabilizing purpose. For example, the combined annealing and selective deposition process in accordance with at least one embodiment of the invention may assist in the sequential infiltration synthesis (SIS) step as potentially preventing conversion of carboxyl groups, or by degassing moisture from the polymer film or by stabilizing or hardening the photoresist.
[0033] The particular implementations shown and described are illustrative of the invention and its best mode and are not intended to otherwise limit the scope of the aspects and implementations in any way. Indeed, for the sake of brevity, conventional manufacturing, connection, preparation, and other functional aspects of the system may not be described in detail. Furthermore, the connecting lines shown in the various figures are intended to represent exemplary functional relationships and/or physical couplings between the various elements. Many alternative or additional functional relationship or physical connections may be present in the practical system, and/or may be absent in some embodiments.
[0034] It is to be understood that the configurations and/or approaches described herein are exemplary in nature, and that these specific embodiments or examples are not to be considered in a limiting sense, because numerous variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. Thus, the various acts illustrated may be performed in the sequence illustrated, in other sequences, or omitted in some cases.
[0035] The subject matter of the present disclosure includes all novel and nonobvious combinations and subcombinations of the various processes, systems, and configurations, and other features, functions, acts, and/or properties disclosed herein, as well as any and all equivalents thereof.

Claims

WHAT IS CLAIMED IS:
1. A method of selectively forming a film comprising:
providing a substrate for processing in a reaction chamber, the substrate having at least one polymer layer disposed on the substrate;
performing an annealing step on the substrate; and
performing a film deposition by sequentially pulsing a first precursor and a second precursor onto the substrate, the film deposition being configured to enable infiltration of at least the first precursor into the at least one polymer layer, wherein an excess of the first precursor and the second precursor are purged from the reaction chamber;
wherein a film forms on the at least one polymer from the first precursor.
2. The method of claim 1, wherein a film forms within the at least one polymer from the first precursor that infiltrates the at least one polymer.
3. The method of claim 1, wherein the film comprises at least one of: aluminum oxide (AI2O3), silicon dioxide (Si02), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), aluminum nitride (AIN), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), cobalt (Co), titanium dioxide (Ti02), tantalum oxide (Ta205), zirconium dioxide (Zr02), or hafnium dioxide (Hf02).
4. The method of claim 2, wherein the film comprises at least one of: aluminum oxide (AI2O3), silicon dioxide (Si02), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), aluminum nitride (AIN), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), cobalt (Co), titanium dioxide (Ti02), tantalum oxide (Ta205), zirconium dioxide (Zr02), or hafnium dioxide (Hf02).
5. The method of claim 1, wherein during the annealing step, a temperature of the reaction chamber ranges between 100°C and 400°C, preferably between 200°C and 300°C, or more preferably about 250°C.
6. The method of claim 1, wherein during the film deposition, the temperature of the reaction chamber ranges between 25°C and 300°C, preferably between 70°C and 90°C.
7. The method of claim 1, wherein the at least one polymer comprises at least one of:
poly(methyl methacrylate) (PMMA), polystyrene, poly(styrene-block-methyl methacrylate) (PS-b-PMMA), or an extreme UV photoresist.
8. The method of claim 1, wherein the substrate comprises a second polymer.
9. The method of claim 8, wherein the second polymer comprises at least one of: poly(methyl methacrylate) (PMMA), polystyrene, poly(styrene-block-methyl methacrylate) (PS-b-PMMA), or an extreme UV photoresist.
10. The method of claim 1, wherein purging the excess of the first precursor comprises purging the reaction chamber with at least one of: nitrogen (N2), argon (Ar), helium (He), or an inert gas.
11. The method of claim 1, wherein the performing the film deposition step is repeated in order to form the film of a desired thickness.
12. The method of claim 1, wherein the performing the film deposition is repeated in order to form the film of a desired thickness.
13. The method of claim 1, wherein the film deposition comprises:
pulsing the first precursor onto the substrate;
purging the first precursor from the reaction chamber;
pulsing the second precursor onto the substrate; and
purging the second precursor from the reaction chamber.
14. The method of claim 1, wherein the annealing step and the film deposition take place within a single reaction chamber.
15. The method of claim 1, wherein the annealing step and the film deposition take place within different reaction chambers located on the same cluster tool.
16. The method of claim 1, wherein the reaction chamber is a batch system for processing substrates.
17. The method of claim 1, wherein the reaction chamber is configured to process multiple substrates.
18. The method of claim 1, wherein the annealing step is configured to induce self- assembly within the at least one polymer layer.
19. The method of claim 1, wherein a temperature of the annealing step is at least 25°C higher than a temperature of the film deposition, preferably 25°C -300°C higher than the temperature of the film deposition, or more preferably 100°C -250°C higher than the temperature of the film deposition.
20. A method of selectively forming a film comprising:
providing a substrate for processing in a reaction chamber, the substrate having at least one polymer layer disposed on the substrate;
performing a film deposition by sequentially pulsing a first precursor and a second precursor onto the substrate, the film deposition being configured to enable infiltration of at least the first precursor into the at least one polymer layer, wherein an excess of the first precursor and the second precursor are purged from the reaction chamber; and
performing an annealing step on the substrate;
wherein a film forms on the at least one polymer from the first precursor.
21. The method of claim 20, wherein the film deposition comprises: pulsing the first precursor onto the substrate;
purging the first precursor from the reaction chamber;
pulsing the second precursor onto the substrate; and
purging the second precursor from the reaction chamber.
22. The method of claim 20, wherein the annealing step and the film deposition take place within a single reaction chamber.
23. The method of claim 20, wherein the annealing step and the film deposition take place within different reaction chambers located on the same cluster tool.
24. The method of claim 20, wherein the reaction chamber is a batch system for processing substrates.
25. The method of claim 20, wherein the reaction chamber is configured to process multiple substrates.
26. The method of claim 20, wherein the annealing step is configured to induce self-assembly within the at least one polymer layer.
27. The method of claim 20, wherein a temperature of the annealing step is at least 25°C higher than a temperature of the film deposition, preferably 25-300°C higher than the temperature of the film deposition, or more preferably 100-250°C higher than the temperature of the film deposition.
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