WO2017179748A1 - Procédé de fabrication de carte à circuits imprimés et carte à circuits imprimés fabriquée par ledit procédé - Google Patents

Procédé de fabrication de carte à circuits imprimés et carte à circuits imprimés fabriquée par ledit procédé Download PDF

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Publication number
WO2017179748A1
WO2017179748A1 PCT/KR2016/003920 KR2016003920W WO2017179748A1 WO 2017179748 A1 WO2017179748 A1 WO 2017179748A1 KR 2016003920 W KR2016003920 W KR 2016003920W WO 2017179748 A1 WO2017179748 A1 WO 2017179748A1
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WO
WIPO (PCT)
Prior art keywords
plating layer
circuit
forming
via hole
pir
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Application number
PCT/KR2016/003920
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English (en)
Korean (ko)
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WO2017179748A9 (fr
Inventor
손경애
강성원
Original Assignee
손경애
강성원
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 손경애, 강성원 filed Critical 손경애
Priority to PCT/KR2016/003920 priority Critical patent/WO2017179748A1/fr
Publication of WO2017179748A1 publication Critical patent/WO2017179748A1/fr
Publication of WO2017179748A9 publication Critical patent/WO2017179748A9/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Definitions

  • the present invention relates to a method of manufacturing a printed circuit board and a printed circuit board manufactured by the method.
  • the circuit on the outer layer surface of the multilayer board is connected through via holes, and additionally, there is no need to connect lead wires for connecting circuits on both sides and increase the integration efficiency of the miniaturized circuit.
  • the present invention relates to a method for manufacturing an outer layer printed circuit board of a double-sided or multi-layered substrate and an outer layer printed circuit board of a double-sided or multi-layered substrate manufactured by the method.
  • printed circuit boards are the most basic components in many fields of electrical and electronic products that are currently manufactured, and are widely used in household appliances such as TVs, VTRs, microwave ovens, desk computers, notebook PCs, and portable electronic products such as smartphones. Is being applied.
  • miniaturization of a printed circuit board circuit wiring refers to a case of 100 pitches or less (circuit width: 50, circuit spacing: 50) or less.
  • a fine pattern may be 50 pitches or less.
  • the reason why the fine circuit pitch is lowered is that the functions of smartphones, tablet PCs and wearable electronic devices such as mobile devices have recently been improved, and memory or CPU processing capacity has increased from 16 Giga Byte, 32 Giga Byte to 64 Giga Byte, Even if it is improved to 128 Giga Byte or more, more circuits must be wired in the same number of floors in order to suppress the cost increase of the product.
  • the present invention is to solve the problems of the prior art, the present invention to increase the degree of integration in the manufacturing of a printed circuit board having a miniaturization circuit on the outer layer surface of the double-sided or multi-layered substrate electrically through the via hole through the circuit on both sides of the printed circuit board It is an object of the present invention to provide a method for manufacturing a printed circuit board, and a printed circuit board manufactured by the method, which do not need to connect circuits on both sides by separate lead wires.
  • the present invention to solve this technical problem
  • PIR pattern ink resist
  • the circuits on both sides of the printed circuit board are electrically connected to each other through via holes. It is possible to simplify the structure of the printed circuit board manufactured without the need for connecting with lead wires.
  • the miniaturization circuit can fundamentally block the possibility of a short circuit that may occur when connecting the lead wire, thereby minimizing the miniaturization circuit on the printed circuit board. It is advantageous for the production of printed circuit boards to be formed.
  • FIGS. 1A to 1O are cross-sectional views illustrating a method of manufacturing a printed circuit board according to an exemplary embodiment of the present invention.
  • FIGS. 2A through 2P are cross-sectional views illustrating a method of manufacturing a printed circuit board according to another exemplary embodiment of the present invention.
  • the same reference numerals in particular, the tens and ones digits, or the same digits, tens, ones, and alphabets refer to members having the same or similar functions, and unless otherwise specified, each member in the figures The member referred to by the reference numeral may be regarded as a member conforming to these criteria.
  • FIGS. 1A to 1O are cross-sectional views illustrating a method of manufacturing a printed circuit board according to an exemplary embodiment of the present invention, and particularly, a cross-sectional view illustrating a method of manufacturing an outer layer printed circuit board of a double-sided or multilayer board.
  • a copper foil laminated plate 100 having a copper foil 104 coated on both surfaces of a substrate insulator 102 or an outer layer surface of a multilayer substrate is illustrated.
  • the copper foil laminated plate 100 is drilled to form a through hole 106 for forming a via hole.
  • the first plating layer 108 may be formed by electroless plating so that both surfaces of the copper foil laminate 100 may be electrically conductive. At this time, the first plating layer 108 is preferably formed to a thickness of 0.5 ⁇ 1.0um.
  • the electroless plating may be used as other metal materials such as copper, nickel, and carbon series.
  • dry films 110 and 112 including photoresist are adhered to both surfaces of the copper clad laminate 100 on which the first plating layer 108 is formed, and as shown in FIG. 1E, the dry films 110,
  • the etching resist 112a is formed on the entire surface of the etching resist 110a and the other surface for forming the micronization circuit 100a and the via hole circuit 100b on one surface through the exposure and development process by the photo process.
  • the micronization circuit 100a and the via hole circuit 100b formed through the exposure and development processes are formed on one surface, and the micronization circuit 100a and the via hole circuit 100b are not formed because the entire surface is exposed and developed on the other surface. Does not have features.
  • a liquid photoresist is applied to expose and develop or through a fine ink circuit (PIR) printing, thereby miniaturizing the circuit 100a and the via hole circuit ( It is also possible to form the etching resists 110a and 112a for forming 100b).
  • PIR fine ink circuit
  • the copper foil 104 and the first plating layer other than the etching resist 110a for forming the miniaturization circuit 100a and the via hole circuit 100b of one surface of the copper foil laminated plate 100 formed by a photolithography process ( 108 is etched, and the dry films used as the etching resists 110a and 112a are peeled off to form the micronization circuit 100a and the via hole circuit 100b on one surface, and the other surface is not etched, so the micronization circuit 100a is removed.
  • the via hole circuit 100b is not formed and the copper foil 104 and the first plating layer 108 remain in a ground state.
  • the dry film 114 including the photosensitizer may be re-adhered to one or both surfaces of the copper-clad laminate 100 having the micronization circuit 100a and the via hole circuit 100b formed on one surface thereof, and illustrated in FIG. 1H.
  • the photoresist is exposed and developed to form openings 114a for plating the via hole circuit 100b on one or both surfaces.
  • a liquid sensitizer is applied to expose and develop or to form a plating layer in the via hole circuit 100b through PIR (Pattern Ink Resist) printing. It is also possible to form openings for the same.
  • the dry film, the liquid photoresist, or the PIR ink serves as a plating resist during electroplating in FIG. 1I.
  • the second plating layer 116 is formed by electroplating the opening 114a for the via hole circuit 100b.
  • the second plating layer 116 is preferably formed to a thickness of 10 to 20um, it may be formed to a thickness of more or less.
  • the reason for forming the second plating layer 116 in the opening 114a for the via hole circuit 100b is that the thickness of the first plating layer performed in FIG. 1C is thin to ensure reliability of electrical conductivity in the via hole. Because you can't.
  • the electroplating may be used as other metal materials such as copper, nickel, and silver.
  • the dry film 114 used as the plating resist is removed through a predetermined peeling process to complete the micronization circuit 100a and the via hole circuit 100b on one surface or the copper foil 104 on the other surface.
  • the ground surface 100d including the first plating layer 108 and the second plating layer 116 is formed on the substrate, or the via hole land 100c is formed.
  • a) and b) of FIG. 1J are characterized in that the miniaturization circuit is wired on one surface and the miniaturization circuit is not wired on the other surface, and c) and d) are characterized in that the miniaturization circuit is wired on one surface and the other surface.
  • an etching resist for forming a miniaturization circuit 100a and a via hole circuit 100b may be formed by applying a liquid photoresist and exposing and developing or reprinting a pattern ink resist (PIR). It is also possible to form 118a and 120a.
  • the copper foil 104 and the first plating layer other than the etching resist 120a for forming the micronized circuit 100a and the via hole circuit 100b of the other surface formed by the photolithography process are formed on the copper foil laminated plate 100. 108), the second plating layer 116 is etched, or the copper foil 104 and the first plating layer 108 are etched, and then the dry films used as the etching resists 118a and 120a on both sides are peeled off to further refine the circuit on the other side. 100a and the via hole circuit 100b are completed.
  • the micronization circuit 100a and the via hole circuit 100b of the other surface are not etched.
  • a printing process or a PSR process is performed by selecting among polyimide-based, acryl-based, and epoxy-based insulating materials which are generally used to insulate the circuits or circuits on both surfaces of the etched surface, or polyimide-based
  • the insulating layer 130 is formed between circuits and circuits except for regions to be surface-treated by performing a lamination process by selecting among acrylic and epoxy insulating materials.
  • the method of applying the insulator may also include an insulator between the circuits or circuits by 3D printing or inkjet printing.
  • nickel plating, gold plating, or nickel and gold may be plated together by electroless or electrolytic plating on a region to be surface treated.
  • the metal layer 140 is formed.
  • the surface treatment may be performed by selecting the surface treatment with OSP (Organic Solderability Preservative) or silver plating instead of the nickel plating and gold plating.
  • OSP Organic Solderability Preservative
  • the metal layer 140 is preferably formed with a thickness of 3 to 7um when forming a layer by nickel plating, and when forming a layer with gold plating, it is preferable to form a thickness of 0.03 to 0.05um, It can also be formed in thicknesses above and below.
  • the process of FIGS. 1N and 1O may be performed by changing the process order.
  • an outer layer printed circuit board of a double-sided or multi-layered substrate is completed through a post-treatment process.
  • 2A to 2P are cross-sectional views illustrating a method of manufacturing a printed circuit board according to another exemplary embodiment, and are also cross-sectional views illustrating a method of manufacturing an outer layer printed circuit board of a double-sided or multilayer board.
  • a copper foil laminated plate 200 having a copper foil 204 coated on both surfaces of an insulator 202 or an outer layer surface of a multilayer substrate is illustrated.
  • the copper foil 204 of the copper-clad laminate 200 instead of the copper foil 204 of the copper-clad laminate 200, it is also possible to use other metal, such as aluminum, nickel (Ni), chromium.
  • other metal such as aluminum, nickel (Ni), chromium.
  • the copper foil laminated plate 200 is drilled to form a through hole 206 for forming a via hole.
  • the first plating layer 208 is formed by electroless plating so that both copper foil surfaces of the copper clad laminate 200 may be electrically connected to each other.
  • the first plating layer 208 is preferably formed to a thickness of 0.5 ⁇ 1.0um.
  • the electroless plating may be used as other metal materials such as copper, nickel, and carbon series.
  • a second plating layer 209 is formed on the first plating layer 208 through electrolytic plating.
  • the second plating layer 209 is preferably formed to a thickness of 5 to 10um, it may be formed to a thickness of more or less.
  • the electroplating may be used as other metal materials such as copper, nickel, and silver.
  • dry films 210 and 212 including photosensitive agents may be adhered to both surfaces of the copper-clad laminate 200 on which the second plating layer 209 is formed, and as shown in FIG.
  • the etching resists 212a are formed on the entire surface of the etching resist 210a and the other surface for forming the micronization circuit 200a and the via hole circuit 200b on one surface by exposing and developing the 210 and 212 using a photolithography process. .
  • a liquid photosensitive agent is coated to expose and develop or through a PIR (Pattern Ink Resist) printing, thereby miniaturizing the circuit 200a and the via hole circuit 200b. It is also possible to form etching resists 210a and 212a for formation.
  • the micronization circuit 200a and the via hole circuit 200b formed through the exposure and development are formed on one surface, and the micronizing circuit 200a and the via hole circuit 200b are not formed by exposing and developing the entire surface on the other surface. There is a characteristic.
  • the copper foil 204 and the first plating layer other than the etching resist 210a for forming the miniaturization circuit 200a and the via hole circuit 200b of one surface formed by the photolithography process are formed on the copper foil laminated plate 200.
  • the second plating layer 209 is etched and the dry films used as the etching resists 210a and 212a are peeled off to form the micronization circuit 200a and the via hole circuit 200b on one surface, and the other surface is not etched and micronized.
  • the circuit 200a or the via hole circuit 200b is not formed, and the copper foil 204, the first plating layer 208, and the second plating layer 209 remain in a ground state.
  • a dry film 214 including a photosensitive agent is re-adhered to one or both surfaces of the copper clad laminate 200 having the micronization circuit 200a and the via hole circuit 200b formed thereon, and illustrated in FIG. 2I.
  • exposure and development are performed by a photographic process to form openings 214a for the via hole circuit 200b on one or both surfaces.
  • the liquid sensitizer is applied to expose and develop the opening, or an opening 214a for forming a plating layer in the via hole circuit 200b through PIR (Pattern Ink Resist) printing. It is also possible to form).
  • PIR Plasma Ink Resist
  • the dry film, the liquid photoresist, or the PIR ink serves as a plating resist during electroplating in FIG. 2J.
  • a third plating layer 216 is formed by electroplating the opening 214a for the via hole circuit 200b.
  • the third plating layer 216 is preferably formed to a thickness of 5 to 10um, it may be formed to a thickness of more or less.
  • a) and b) of FIG. 2J are characterized in that the miniaturization circuit is wired on one surface and the miniaturization circuit is not wired on the other surface, and c) and d) are characterized in that the miniaturization circuit is wired on one surface and the other surface.
  • the electroplating may be used with various metal materials such as copper, nickel, and silver.
  • the dry film used as the plating resist 214 is removed through a predetermined peeling process to complete the micronization circuit 200a and the via hole circuit 200b on one surface or the copper foil 204 on the other surface.
  • the ground surface 200d including the first plating layer 208, the second plating layer 209, and the third plating layer 216 is formed on the via plate 200c, or the via hole land 200c is formed.
  • the photosensitive agent is dried on both surfaces of the copper foil laminated plate 200 on which one surface of the micronization circuit 200a and the via hole circuit 200b and the other surface of the ground surface 200d or the via hole land 200c are formed.
  • the films 218 and 220 are brought into close contact with each other, and the copper-clad laminate 200 is exposed and developed by a photolithography process as shown in FIG. 2M, and the etching resist for the micronization circuit 200a and the via hole circuit 200b of the other surface ( An etching resist 218a is formed on the entire surface of 220a) and one surface thereof.
  • the entire surface is exposed and developed so that the micronization circuit 200a and the via hole circuit 200b already formed on the one surface are not etched during etching. 218a).
  • a liquid photoresist is applied to expose and develop or through a pattern ink resist printing (PIR) to refine the micro circuit 200a and the via hole circuit 200b. It is also possible to form the etching resists 218a and 220a for formation.
  • PIR pattern ink resist printing
  • the copper foil 204 and the first plating layer other than the etching resist 220a may be formed to form the micronized circuit 200a and the via hole circuit 200b of the other surface formed by the photolithography process.
  • the dry film used as is peeled off to complete the micronization circuit 200a and the via hole circuit 200b of the other surface.
  • the insulating layer 230 forming process as shown in FIG. 2O and the metal layer 240 forming process as shown in FIG. 2P are sequentially performed.
  • a printing process or a PSR process may be performed by selecting among polyimide-based, acryl-based, and epoxy-based insulating materials which are generally used to insulate the circuits or circuits on both surfaces of the etched surface.
  • the insulating layer 230 is formed between the circuit and the circuit except for the region to be surface-treated by performing a lamination process by selecting among acrylic and epoxy insulating materials.
  • the method of applying the insulator may also include an insulator between the circuits or circuits by 3D printing or inkjet printing.
  • the surface treatment may be performed by selecting the surface treatment with OSP (Organic Solderability Preservative) or silver plating instead of the nickel plating and gold plating.
  • OSP Organic Solderability Preservative
  • the metal layer 240 is preferably formed with a thickness of 3 to 7um when the nickel plating layer is formed, and when formed with a gold plated layer, the metal layer 240 is preferably formed with a thickness of 0.03 to 0.05um. It can also be formed with the following thickness.
  • FIGS. 2O and 2P may be performed by changing the process order.
  • an outer layer printed circuit board of a double-sided or multilayer board is completed through a post-treatment process.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

La présente invention concerne un procédé de fabrication d'une carte à circuits imprimés, et une carte à circuits imprimés fabriquée par le procédé, caractérisés en ce qu'il n'est pas nécessaire de connecter séparément des circuits sur les deux faces de la carte à circuits imprimés en reliant électriquement les circuits situés sur les deux faces de la carte à circuits imprimés à travers des trous d'interconnexion, lorsque la carte à circuits imprimés présentant un motif fin sur les deux faces ou la surface extérieure d'un substrat multicouche est fabriquée afin d'accroître le degré d'intégration. Le procédé de fabrication de la carte à circuits imprimés comporte les étapes consistant: (a) après qu'un trou débouchant a été pratiqué pour former un trou d'interconnexion en perçant un stratifié revêtu de cuivre comprenant une feuille de cuivre appliquée sur les deux faces d'un isolant de substrat ou la surface extérieure d'un substrat multicouche, à former une première couche de placage par dépôt autocatalytique; (b) à former une réserve de gravure destinée à former un motif fin et un circuit de trou d'interconnexion sur une face du stratifié revêtu de cuivre, et une réserve de gravure située entièrement sur l'autre face du stratifié revêtu de cuivre en collant un film sec comportant un photosensibilisateur sur les deux faces du stratifié revêtu de cuivre sur lequel est formée la première couche de placage ou en appliquant, en exposant et en développant un photosensibilisateur liquide ou par une impression à l'encre pour motifs de réserve (PIR); (c) à former un motif fin et un circuit de trou d'interconnexion sur sa face en question en gravant la feuille de cuivre et la première couche de placage à côté de la réserve de gravure formée sur les deux faces du stratifié revêtu de cuivre et en décapant le film sec ou le photosensibilisateur liquide ou une encre PIR; (d) à former une ouverture du film sec, du photosensibilisateur liquide ou de l'encre PIR pour le circuit de trou d'interconnexion en recollant le film sec comportant le photosensibilisateur à la face ou aux deux faces du stratifié revêtu de cuivre ou en renouvelant l'application, l'exposition et le développement de la réserve photosensible liquide, ou par une réimpression à l'encre pour motifs de réserve (PIR); (e) après avoir formé une deuxième couche de placage en effectuant un dépôt électrolytique sur l'ouverture du film sec, du photosensibilisateur liquide ou de l'encre PIR, à achever le motif fin et le circuit de trou d'interconnexion sur la face en question en décapant le film sec, le photosensibilisateur liquide ou l'encre PIR, ou à former un plan de masse constitué de la première couche de placage et de la deuxième couche de placage ou à former une plage de trou d'interconnexion sur l'autre face de la feuille de cuivre; (f) après avoir recollé le film sec comportant le photosensibilisateur sur les deux faces du stratifié revêtu de cuivre ou réappliqué le photosensibilisateur liquide, à former une réserve de gravure pour le motif fin et le circuit de trou d'interconnexion sur son autre face et une réserve de gravure entièrement sur sa face en question en exposant et en développant le stratifié revêtu de cuivre, ou par une réimpression PIR; (g) après avoir gravé la feuille de cuivre, la première couche de placage et la deuxième couche de placage à côté de la réserve de gravure, ou avoir gravé la feuille de cuivre et la première couche de placage, à achever le motif fin et le circuit de trou d'interconnexion sur l'autre face en décapant le film sec ou le photosensibilisateur liquide ou l'encre PIR utilisée comme réserve de gravure.
PCT/KR2016/003920 2016-04-15 2016-04-15 Procédé de fabrication de carte à circuits imprimés et carte à circuits imprimés fabriquée par ledit procédé WO2017179748A1 (fr)

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PCT/KR2016/003920 WO2017179748A1 (fr) 2016-04-15 2016-04-15 Procédé de fabrication de carte à circuits imprimés et carte à circuits imprimés fabriquée par ledit procédé

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050031221A (ko) * 2003-09-29 2005-04-06 삼성전기주식회사 도금 인입선이 없는 인쇄회로기판 및 그 제조 방법
KR100498977B1 (ko) * 2002-12-31 2005-07-01 삼성전기주식회사 Ｅ-ｂｇａ 인쇄회로기판의 공동 내벽을 도금하는 방법
KR100723489B1 (ko) * 2005-06-17 2007-05-31 삼성전자주식회사 신뢰성을 개선할 수 있는 반도체 장치 및 그 제조방법
KR20140077441A (ko) * 2012-12-14 2014-06-24 타이코에이엠피(유) 인쇄회로기판 및 그 제조방법
KR20140123273A (ko) * 2013-04-12 2014-10-22 타이코에이엠피(유) 인쇄회로기판 및 그 제조방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100498977B1 (ko) * 2002-12-31 2005-07-01 삼성전기주식회사 Ｅ-ｂｇａ 인쇄회로기판의 공동 내벽을 도금하는 방법
KR20050031221A (ko) * 2003-09-29 2005-04-06 삼성전기주식회사 도금 인입선이 없는 인쇄회로기판 및 그 제조 방법
KR100723489B1 (ko) * 2005-06-17 2007-05-31 삼성전자주식회사 신뢰성을 개선할 수 있는 반도체 장치 및 그 제조방법
KR20140077441A (ko) * 2012-12-14 2014-06-24 타이코에이엠피(유) 인쇄회로기판 및 그 제조방법
KR20140123273A (ko) * 2013-04-12 2014-10-22 타이코에이엠피(유) 인쇄회로기판 및 그 제조방법

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