WO2017177389A1 - 具有集成磁性器件的转接板 - Google Patents

具有集成磁性器件的转接板 Download PDF

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Publication number
WO2017177389A1
WO2017177389A1 PCT/CN2016/079123 CN2016079123W WO2017177389A1 WO 2017177389 A1 WO2017177389 A1 WO 2017177389A1 CN 2016079123 W CN2016079123 W CN 2016079123W WO 2017177389 A1 WO2017177389 A1 WO 2017177389A1
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Prior art keywords
metal
magnetic device
substrate
metal wire
interposer
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PCT/CN2016/079123
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English (en)
French (fr)
Inventor
方向明
伍荣翔
单建安
Original Assignee
深圳线易科技有限责任公司
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Application filed by 深圳线易科技有限责任公司 filed Critical 深圳线易科技有限责任公司
Priority to PCT/CN2016/079123 priority Critical patent/WO2017177389A1/zh
Priority to CN201680058602.XA priority patent/CN108369852B/zh
Publication of WO2017177389A1 publication Critical patent/WO2017177389A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/28—Coils; Windings; Conductive connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

Definitions

  • the present invention relates to an integrated circuit, and more particularly to an integrated magnetic device.
  • Discrete magnetic devices such as discrete inductors, are typically mounted on a printed circuit board by surface mount methods and connected to the load via wires on the board. This part of the wiring introduces parasitic inductance, which limits the rate of current change and reduces the transient response of the power supply.
  • discrete magnetic devices are not conducive to miniaturization of the system.
  • a large number of discrete magnetic devices not only occupy the area of the board, but also increase the thickness of the system.
  • the thickness of the discrete magnetic device itself is typically hundreds of microns or even millimeters, while the thickness of the printed circuit board is at the millimeter level. Therefore, it is very difficult to further reduce the area and thickness of the system for a power supply using a discrete magnetic device.
  • the prior art uses a silicon interposer for inductive integration. Inductance Integrated on the silicon adapter board, the connection between the inductor and the circuit chip is easier and more convenient, and partially solves the problem of system miniaturization.
  • the metal interconnect wires on the front side of the silicon adapter plate due to the small thickness and high density of the metal interconnect wires on the front side of the silicon adapter plate, the use of these wires as integrated inductor coils can significantly limit the performance of the inductor, especially the power inductor. Therefore, the prior art solution cannot provide a high performance integrated power inductor on the silicon interposer.
  • the structure of the prior art silicon adapter board and the inductor integrated system is as shown in FIG. 1.
  • the system 100 includes a silicon adapter board.
  • the front surface of the 101 is a two-layer metal interconnection line 111 and 112 (front metal layer, actually used).
  • the medium metal interconnection line may be one or more layers, and the front side chip is connected by a bump 121 (for example, a copper pillar bump) connecting the metal interconnection lines.
  • Chip 131 and chip 132 are typically flip chip bonded to a silicon interposer.
  • the chip 1 31 has a large number of ports that need to be electrically connected to the chip 132 via the bumps 121 via the metal layers 111 and 112.
  • the metal layer 111 and the metal layer 112 have a high wiring density, and usually the spacing between the metal lines is only a few. Micrometers, for example 2 microns, have a very small line width, for example 0.5 microns. The wiring density and width limit the thickness of the metal layers 111 and 112, for example, 0.5 ⁇ m.
  • the front metal interconnections 111 and 112 are connected to the back metal redistribution layer (back metal layer) 141 through a through silicon via (TSV) 102 on the silicon via 101.
  • the back metal layer 141 is connected to other devices (not shown) by solder balls 142 (e.g., controllable collapse chip interconnect C4) and metal lines 152 on substrate 151 (e.g., printed circuit board PCB). Since the back metal lines are usually only one layer and the surface flattening requirement is lower than the front metal interconnection lines, the metal redistribution layer 141 has a line width and thickness requirement that is looser than the front metal interconnection lines 111 and 112, and the line width can be reached. It is several tens of micrometers, and the thickness can reach several micrometers.
  • the prior art utilizes the front metal layers 111, 112, the back metal layer 141 and the through silicon vias 102 to form an inductor.
  • the spiral 201 is formed by the front metal interconnection layers 111, 112, the spiral 203 is formed by the back metal layer 141, and a multilayer double-sided spiral inductor is formed through the through silicon vias 202.
  • FIG. 2-2 Another structure is shown in FIG. 2-2.
  • the inductor 210 on the silicon interposer forms a metal line 211 from the front metal interconnection layers 111, 112, a metal line 213 from the back metal layer 141, and is formed by the through silicon via 212.
  • the insufficiency of the inductive structure formed by the front metal layers 111, 112 is manifested in two aspects: First, the thickness of the front metal layer is too small and cannot be significantly increased, otherwise the metal line width and the line pitch are increased, thereby causing The interconnect density is reduced. Therefore, using the front metal wire as part of the inductor coil significantly increases the resistance of the inductor, increases the inductor power consumption, and reduces the inductor efficiency. Second, the trace of the inductor consumes one of the areas The front metal wire above the layer. The reduction in the number of metal lines limits the flexibility of the layout and interconnection of the metal lines in the area, thereby reducing the interconnectivity of the silicon interposer.
  • Comparative Document 1 US 8,072,042 (CN 102479685 B)
  • the electrical cross-connection of the metal wires on the front and back sides and the two conductive vias connecting the metal wires are on the surface of the substrate, the core of which passes through the entire substrate.
  • the metal wire of the inductor is formed by a metal stack formed on the front side of the metal layer in the dielectric layer, the through silicon via, and the metal redistribution layer on the back side of the silicon wafer. composition.
  • the first part of the metal forming the inductive coil uses the first layer formed on the surface of the substrate in a back-end-of-line (BEOL) process. metal.
  • BEOL back-end-of-line
  • the prior art integrates the inductor on the silicon adapter board, which not only loses the performance of the inductor, but also reduces the function of the silicon adapter board, and cannot integrate the high inductance in the silicon adapter board.
  • the present invention adopts the following technical solution: an interposer having an integrated magnetic device, on which a magnetic device is provided, and a coil of the magnetic device is composed of a metal wire connection, and the metal wire is disposed in the substrate.
  • the metal wires of the present invention are a first metal wire and a second metal wire, and the first metal wire and the second metal wire are electrically connected by a second via hole in which a metal is filled to constitute a coil.
  • the coil of the present invention is spiral.
  • the first metal line of the present invention is disposed within the substrate.
  • the first metal line of the present invention is embedded within a first surface above the substrate.
  • the second metal wire of the present invention is disposed outside the second surface.
  • the substrate of the present invention is provided with a first via hole electrically filled with a metal in which the second metal line and the first surface are electrically filled.
  • the first metal line, the second metal line, and the second through hole filled with metal therein constitute a coil group, and one set of coils is magnetically coupled with another set of coils;
  • a first metal wire and a second metal wire are adjacent to or spaced apart from each other between the first metal wire and the second metal wire of the group coil.
  • a planar magnetic core is disposed between the outer surface of the substrate, the second surface, and the second metal line, and the magnetic circuit of the magnetic core is closed or has a gap.
  • the second surface of the present invention is provided with an embedded magnetic core extending from the second surface into the interior of the substrate, the magnetic circuit of the magnetic core being closed or having a gap.
  • the present invention embeds a part of the metal wires of the magnetic device in the substrate, significantly reduces the resistance of the magnetic device, improves the inductance density and quality factor of the integrated magnetic device, and reduces the volume of the magnetic device. Improve the efficiency, and does not affect the flatness of the surface of the adapter plate, does not occupy the existing metal interconnection line, realizes the integration of high-performance magnetic devices under the premise of ensuring that the interconnection function of the silicon adapter plate itself is not damaged.
  • FIG. 1 is a schematic structural view of a prior art silicon adapter plate.
  • FIG. 2-1 is a schematic diagram of a prior art integrated inductor structure (1).
  • 2-2 is a schematic diagram of a prior art integrated inductor structure (2).
  • Embodiment 1 of the present invention is a schematic structural view of Embodiment 1 of the present invention.
  • FIG. 4 is a cross-sectional view taken along line A-A of FIG. 3.
  • Embodiment 2 of the present invention is a schematic structural view of Embodiment 2 of the present invention.
  • FIG. 6 is a cross-sectional view taken along line B-B of FIG. 5.
  • Embodiment 7 is a schematic structural view of Embodiment 3 of the present invention.
  • FIG. 8 is a cross-sectional view taken along line C-C of FIG. 7.
  • Embodiment 4 of the present invention is a plan view of Embodiment 4 of the present invention.
  • Embodiment 5 of the present invention is a plan view of Embodiment 5 of the present invention.
  • 11 is a plan view of a sixth embodiment of the present invention.
  • 12 is a plan view of a seventh embodiment of the present invention.
  • Comparative Example 1 is a spiral inductor, the thickness of the interposer is ⁇ , the substrate is made of high-resistance silicon with a resistivity of 1000 ⁇ -cm, and the first metal line is made of copper, using prior art deposition and graphics. According to the method, the first metal wire is located on the first surface and has a thickness of 1 ⁇ m.
  • the second metal line is made of copper and is obtained by a prior art electroplating method, located outside the second surface and having a thickness of 5 ⁇ m.
  • the second through hole is made of copper and is obtained by a prior art electroplating method having a diameter of 20 ⁇ m.
  • the spiral inductor has 10 turns, the width of each coil is 60 ⁇ , and the pitch of the coil is 100 ⁇ .
  • the width of the spiral inductor on the adapter plate ( ⁇ - ⁇ direction) is 500 ⁇ and the area of the adapter plate is 0.5 mm 2 .
  • the inductance of the spiral inductor is 6.7 nH
  • the inductance density is 13.4 nH/mm 2
  • the DC resistance is 1.7 ⁇
  • the typical frequency of the high-frequency power supply is 20 MHz.
  • the quality factor is 0.5.
  • Example 1 was also a spiral inductor, and the second metal wire and the second through hole were obtained by the same material and preparation method as in Comparative Example 1.
  • the first metal line 311 is embedded in the interposer 300, and the trench is obtained by a deep reactive ion etching method using photoresist or silicon dioxide as an etching mask layer, using 60 sccm of C 4 F 8 As a passivation layer deposition, 150 sccm of SF 6 was mixed with 15 sccm of 0 2 and 10 sccm of C 4 F 8 as an etching gas, and alternating cycle power of 500 W was performed for 15 seconds and 10 seconds, respectively. In the etching and passivation steps, the trench is gradually etched to the required depth.
  • the first wire thickness is 50
  • the inductance in Embodiment 1 may include 20 coils. According to the same method as in Comparative Example 1, the inductance of the inductor in Example 1 was 15.8 ⁇ ⁇ , the inductance density was 31.6 nH/mm 2 , the DC resistance was 1.2 ⁇ , and the quality factor of 20 MHz 1.3 was 1.33. It can be seen that, under the same adapter plate area, compared with the comparative example 1, the embodiment 1 can increase the inductance density by 2.4 times, significantly reduce the inductance DC resistance, reduce 30%, and improve the quality factor by 2.7 times.
  • Comparative Example 2 On the basis of the spiral inductor of Comparative Example 1, the thickness increased by 2 ⁇ at a position outside the second surface 520, the relative magnetic permeability was 600, and the specific resistance was 10 ( ⁇ . 9( ⁇ & 5 2]" 5 is used as a planar magnetic core 540. It is obtained by a patterning method using a sputtering process of the prior art. a metal wire, a second metal wire, and a second through hole. According to the same method as in Comparative Example 1, the inductance of the inductor in Comparative Example 2 was 34.5 nH, the inductance density was 69.0 nH/mm 2 , the DC resistance was 1.7 ⁇ , and the quality factor of 20 MHz was 2.4.
  • Example 2 The first metal wire, the second metal wire, and the second through hole were obtained in the same manner as in Example 1.
  • the planar magnetic core 540 was obtained in the same manner as in Comparative Example 2.
  • the inductance of the inductor in Example 2 was 145 nH
  • the inductance density was 290 nH/mm 2
  • the DC resistance was 1.2 ⁇
  • the quality factor of 20 MHz was 9.9.
  • Example 2 increases the inductance density by 4.2 times, reduces the DC resistance of the inductor by 30%, and improves the quality factor by 4.1 times.
  • Comparative Example 3 On the basis of the spiral inductor of Comparative Example 1, a NiFe having a thickness of 20 ⁇ m, a relative magnetic permeability of 600, and a specific resistance of 100 ⁇ was added as a position in the second surface 720.
  • the magnetic core 740 can incorporate carbon in the electroplating process to increase the electrical resistivity.
  • a trench is formed on the second surface by a deep reactive ion etching of the prior art, and plating and planarization of the magnetic material is performed to form a magnetic core embedded in the substrate from the second surface.
  • the first metal wire, the second metal wire, and the second through hole were obtained in the same manner as in Comparative Example 1.
  • the inductance of the inductor in Comparative Example 3 was 61.6 ⁇ ⁇
  • the inductance density was 123.2 nH/mm 2
  • the DC resistance was 1.7 ⁇
  • the quality factor of 20 MHz was 2.9.
  • Example 3 The first metal wire, the second metal wire, and the second through hole were obtained by the method of Example 1, and the embedded magnetic core 740 was obtained by the method of Comparative Example 3.
  • the inductance of the inductor in Example 3 was 274 nH
  • the inductance density was 548 nH/mm 2
  • the DC resistance was 1.2 ⁇
  • the quality factor of 20 MHz was 4.75.
  • Example 3 increases the inductance density by 4.4 times, reduces the DC resistance of the inductor by 30%, and improves the quality factor by 1.6 times.
  • the adapter board with integrated magnetic device of the present invention takes an integrated inductor as an example to illustrate the structure of an adapter plate (array plate, integrated inductor) having a magnetic device and a preparation method thereof.
  • Example 1 the magnetic device has no magnetic core.
  • an interposer 300 having an integrated magnetic device includes a substrate 301 on the substrate 301.
  • the substrate 301 is a semiconductor material or an insulating material, the semiconductor material is silicon, germanium or a compound semiconductor, and a preferred semiconductor material is silicon.
  • the compound semiconductors are gallium nitride (GaN), gallium arsenide (GaAs), silicon carbide (SiC), and silicon germanium (SiGe).
  • the insulating material is glass, quartz or an organic substrate.
  • a first metal line (embedded metal line) 311 is embedded in the trench under the first surface 310.
  • the trenches may be formed in the substrate 301 by etching, such as deep reactive ion etch.
  • the first metal line 311 is located inside the substrate 301, and the upper portion thereof is planarized with the first surface 310.
  • a plurality of insulating layers and metal layers may be deposited to form a metal interconnection for forming the first surface of the interposer.
  • no A metal interconnect structure over a surface 310 in order to clearly show the inductive structure.
  • a second metal line 321 is disposed outside the second surface 320, and the second metal line 321 and the first surface 310 are electrically realized by a metal (via) 331 filled in the first through hole vertically disposed in the substrate 301.
  • the electrical connection of the second metal line 321 with the lower end 312 of the embedded metal line 311 within the substrate is achieved by a second via 332 disposed vertically in the substrate 301.
  • the right end of the first metal wire 311, which is arranged at the front, is electrically connected to the right end of the first second metal wire 321 of the front surface via a second through hole 332.
  • the left end of the second metal line 321 is electrically connected to the left end of the second first metal line 311 via another second through hole 332.
  • the right end of the second metal wire 311 of the second figure is electrically connected to the right end of the second metal wire 321 of the second through the second through hole 332, and continues to electrically connect the first metal wire 311 and the second metal behind.
  • the line 321 is arranged at the left end of the last second metal line 321 to be electrically connected to the first surface 310 via the first through hole 331 to form a coil of integrated inductance.
  • the adapter plate 400 includes a substrate 4 01 (301), a first surface 4 10 (310), and a second surface 420 (320).
  • the first metal line 411 (311) extends from the first surface 410 into the interior of the substrate 401 to form an embedded metal line.
  • the first metal line 411 is connected to the second metal line 421 (321) located outside the second surface 420 of the substrate through the second through hole 4 32 (332) located inside the substrate 401.
  • An insulating layer 433 is disposed between the first metal line 4 11 , the second metal line 421 , and the second via 432 and the substrate 401 .
  • An insulating layer 422 is disposed outside the second surface 420, and the second metal line 421 is disposed in the insulating layer 422.
  • the first metal line 411, the second metal line 421, and the second through hole 432 constitute a coil of the integrated inductor coil.
  • the inductor includes a first metal line 411, a second metal line 421, a second via 432, an insulating layer 433, An insulating layer 422 outside the second surface 420.
  • an insulating layer is not required.
  • a coil of integrated inductance is formed by the embedded metal wire 411, the second metal wire 421 on the second surface, and the second through hole 432.
  • a metal interconnection layer of one or more metal lines 415, an insulating layer 413 disposed between the metal interconnection layers, and a bump connected to the outermost metal lines may be formed on the first surface 410 using a prior art process.
  • the bump 414 is used to connect the first surface of the adapter plate to the external circuit. Since the first metal line 411 and the first surface 410 of the interposer are planarized, the influence of the uneven surface on the subsequent manufacturing process is reduced, so the metal line 415 and the bump 414 are easy to achieve small pitch and line width. , thereby increasing the density of the metal interconnect layer. Therefore, the first surface 410 is more suitable for connecting a larger number of input/output port devices, such as a field editable gate array FPGA chip, a microprocessor chip, and a power management chip.
  • a metal interconnection layer of one or more second metal lines 421, an insulating or passivation layer 422 disposed between the metal interconnection layers, and a connection may be formed on the second surface 420 using a prior art process.
  • a solder ball 423 of the second metal line of the layer is used to connect the second surface of the interposer to the external circuit.
  • the thickness of the second metal wire 421 is greater than the thickness of the metal wire 415, so the pitch and line width of the second metal wire 421 are generally larger than the metal interconnection layer on the first surface 410. Therefore, the second surface is more suitable for the connection line width. Larger devices, such as printed circuit boards.
  • Embodiment 2 a planar magnetic core is disposed on the transfer plate.
  • Embodiment 2 adds a planar magnetic core located outside the second surface.
  • the adapter plate 500 includes a substrate 501 (301), a first surface 510 (310), a second surface 5 20 (320), and a first embedded in the first surface.
  • a planar magnetic core 540 is disposed outside the substrate 501, between the second surface 520 and the second metal line 521, and an insulating layer is disposed around the planar magnetic core 540, and the insulating layer is used for the planar magnetic core 540 and the second The insulation between the metal line 521 and the substrate 50 1 .
  • the planar magnetic core 540 is obtained by depositing, for example, sputtering, evaporation, or electroplating and patterning.
  • the planar magnetic core 540 is composed of a material layer having a high magnetic permeability such as an alloy of nickel (Ni), iron (Fe), cobalt (Co), and manganese (M) magnetic elements, an oxide or a composite material, or a high magnetic permeability material.
  • the layer is formed with an insulating laminate.
  • a coil of integrated inductance is formed by the first metal line 511, the second through hole 532, and the second metal line 521, and the coil surrounds the planar core 540.
  • the planar magnetic core 540 can be parallel to the magnetic field lines of the coil
  • the direction of the direction (perpendicular to BB) is divided into a plurality of (at least two) to reduce eddy currents in the planar core 540.
  • the adapter plate 600 (300) includes a substrate 601 (301), a first surface 610 (310), and a second surface 6 20 (320).
  • the first metal line 611 (311) extends from the first surface 610 to the inside of the substrate 601, and is electrically connected to the second metal line 621 (321) outside the second surface 620 through the second via 632 (332).
  • the first metal wire 611, the second metal wire 621, and the second via hole 632 may be insulated from the substrate 60 1 by an insulating layer 633 (433).
  • One or more metal layers 615 (415) may be formed on the first surface 610, and an insulating layer 613 (413) between the metal layers 615.
  • a bump 614 (41 4) and a solder ball 623 (423) may be formed outside the first surface 610 and the second surface 620, respectively, for connection of the interposer and other devices.
  • the planar magnetic core 640 (540) is located between the second surface 620 and the second metal line 621, and the planar magnetic core 640 (540) and the substrate 601 and the second metal line 621 can be realized by the insulating or passivation layer 622 (422). Insulation between.
  • Embodiment 3 an embedded magnetic core is embedded in the adapter plate.
  • Embodiment 3 adds an embedded magnetic core located in the second surface.
  • the adapter plate 700 (300) includes a substrate 701 (301), a first surface 710 (310), and a second surface 7 20 (320) embedded in the first surface 710.
  • the second surface 720 is provided with an embedded magnetic core 740 extending from the second surface 740 into the interior of the substrate 701.
  • An insulating layer may be disposed between the embedded magnetic core 740 and the substrate 701.
  • the embedded magnetic core 740 is etched to form a trench and then formed by deposition, for example, sputtering, evaporation or electroplating, and patterning or planarization.
  • the embedded magnetic core 740 is formed of a material layer having a high magnetic permeability such as an alloy of nickel Ni, iron Fe, cobalt Co and manganese Mn magnetic elements, an oxide or a composite material, or a layer of a high magnetic permeability material and an insulating laminate.
  • a coil of integrated inductance is formed by the first metal line 711, the second through hole 732, and the second metal line 721, and the coil surrounds the embedded magnetic core 740.
  • the embedded core 740 is divided into four along the length of the vertical first wire 711 to reduce eddy currents in the core. You can adjust the number of core splits to more than one as needed.
  • the adapter plate 800 includes a substrate 801 (301), a first surface 810 (310), and a second surface 8 20 (320).
  • the first metal line 811 (311) extends from the first surface to the inside of the substrate, and is electrically connected to the second metal line 821 (321) outside the second surface through the second through hole 832 (432). Insulation layer 8 can be used 33 (433)
  • the first metal wire 811, the second metal wire 821, and the second through hole 832 are insulated from the substrate 801.
  • One or more metal layers 815 (415) may be formed on the first surface 810, and an insulating layer 813 (413) between the metal layers 815.
  • Bumps 814 and solder balls 823 may be formed on the outside of the first surface 810 and the second surface 820, respectively, for connection of the interposer and other devices.
  • the embedded magnetic core 840 (740) is located in the second surface 820 and extends from the second surface 820 into the interior of the substrate 801.
  • the insulation between the embedded magnetic core 840 and the substrate 801 can be achieved by using the insulating layer 841.
  • Insulation between the second metal line 821 and the substrate 801 can be achieved using an insulating or passivation layer 822 (422).
  • the embedded core 841 (740) is divided into four along the length of the vertical first metal line 811 (711) to reduce eddy currents in the core.
  • Embodiment 2-3 it is described that a magnetic core is provided in an inductor using an embedded metal wire. It is also possible to arrange other magnetic components, such as coupled inductors and transformers, on the adapter plate by means of different coil arrangements. In order to clearly show the arrangement of the magnetic device coils, the magnetic core, the bumps, and the solder ball structure are not shown in Embodiments 4-7. In actual use, the magnetic core, the bump, and the solder ball structure can be arranged according to the structures of Embodiments 1-3.
  • Embodiment 4 in the direction of D in FIG. 3, is a plan view direction of the interposer 900 (300) including the magnetic device, as shown in FIG. 9, the interposer 900 (300) is included from the figure Immediately adjacent three first metal wires (embedded metal wires) 911 (311), two second metal wires 921 (321) located immediately above the second surface and connected to the first metal wires and the second A first set of coils 932 (332) of metal wires.
  • the adapter plate 900 also includes three first metal wires (embedded metal wires) 940 (311) immediately below the figure, and two second metal wires 950 (321) located immediately below the second surface in the immediately below view. And a second set of coils comprising a second via 960 (332) connecting the first metal line and the second metal line. There is a magnetic coupling between the first set of coils and the second set of coils.
  • the interposer 1000 (300) includes three first metal wires separated by a single strip (embedded) a metal wire 1011 (311), two second metal wires 1021 (321) spaced apart from the second surface and a second through hole 1032 (332) connecting the first metal wire and the second metal wire The first set of coils that make up.
  • the interposer 1000 further includes two other first metal wires (embedded metal wires) 1040 (311) separated by a single strip, and two other second metal wires 1050 (321) and a connection between the second strips spaced apart from the second surface.
  • the first metal line and the second metal line A second set of coils is formed by the second through holes 1060 (332).
  • the metal wires of the second set of coils are alternately placed with the first metal wire and the second metal wire of the first set of coils to form a structure intertwined with each other and magnetic coupling.
  • Embodiment 4 and Embodiment 5 show a case where two sets of coils are coupled to each other, and in actual use, two or more sets of mutually coupled coils may be included as needed.
  • Embodiment 6, in the direction of D in Fig. 3, is a plan view direction of the interposer 1100 (300) including the magnetic device.
  • the adapter plate 1100 (300) includes a magnetic core 1111 with a magnetic circuit closed.
  • Embodiment 7, in the direction of D in Fig. 3, is a plan view direction of the interposer 1200 (300) including the magnetic device.
  • the adapter plate 1200 (300) includes a magnetic core 1221 (1311) having a gap 1222. By adjusting the size of the gap, the inductance value and the saturation current value parameter of the magnetic device can be adjusted.
  • the interposer plate of Embodiments 1-7 may include other active devices, passive devices, or active devices in a semiconductor substrate in a region where the first surface or the second surface is not occupied by the magnetic device. In combination with passive devices, such as integrated circuits.
  • the inductance formed by the front and back metal lines of the through silicon via connecting substrate is the metal line using the surface of the substrate, and the contrast file 1 has no space in the substrate to form an embedded
  • the metal lines, the metal lines on the front side of the contrast files 2 and 3 are not embedded in the grooves on the front side of the substrate, and the contrast document 4 is not an embedded metal line formed in the grooves on the front side of the substrate.
  • the invention embeds a part of the metal conductor of the magnetic device in the substrate, significantly reduces the resistance of the inductor, improves the inductance density and the quality factor of the integrated magnetic device, and achieves the effect of reducing the volume and improving the efficiency.
  • the present invention integrates an integrated magnetic device having a high inductance density and a quality factor in the transfer board without losing the advantage of the small thickness of the interposer, the small interconnect width, and the high interconnect density.

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Abstract

一种具有集成磁性器件的转接板（300，400，500，600，700，800，900，1000，1100，1200），在衬底（301，401，501，601，701，801）上设有磁性器件，磁性器件的线圈由金属线（311，321，411，421，511，521，611，621，711，721，811，821，911，921，940，950，1011，1021，1040，1050）连接构成，所述金属线（311，321，411，421，511，521，611，621，711，721，811，821，911，921，940，950，1011，1021，1040，1050）设置在衬底（301，401，501，601，701，801）内。显著降低磁性器件的电阻，提高集成磁性器件的电感密度和品质因数，减小磁性器件的体积，提升了效率，并且不影响转接板表面的平坦性、不占用现有金属互联线，在保证硅转接板本身互联功能不受损的前提下，提高集成磁性器件的性能并实现了高性能磁性器件的集成。

Description

具有集成磁性器件的转接板 技术领域
[0001] 本发明涉及一种集成电路,特别是一种集成磁性器件。
背景技术
[0002] 随着集成电路制造方法的发展， 单位芯片面积上包含的晶体管数量和可以实现 的功能快速增加。 相应的， 集成电路对于电源性能的要求随之提高。 同吋， 便 携式、 可穿戴式、 可植入式电子设备的发展， 也对电源的体积提出了更严格的 要求。 传统的幵关电源 (switched-mode power supply)由于需要使用分立磁性器件 ， 例如分立电感， 显著限制了电源性能和对幵关电源体积的改进。
[0003] 首先， 使用分立磁性器件不利于实现细粒度电源管理 （fine granular power management) 。 复杂的集成电路 (系统)， 例如中央处理器 CPU、 数字信号处理器 DSP、 和图形处理器 GPU， 通常包含若干的独立电压区域 （voltage domain) 。 在不同的工作条件下， 可以随吋调整每个电压区域的工作电压， 从而优化系统 的总功耗。 这种动态电压调节方法要求给每一个电压区域配备一个专属的幵关 电源。 由于每个幵关电源都至少需要一个磁性器件， 例如电感， 导致使用分立 磁性器件会显著增加系统的体积和成本。
[0004] 第二， 使用分立磁性器件不利于电源的快速瞬态响应。 当负载电流或电压突变 的吋候， 电源提供的电流或电压应当能紧密的跟随负载变化。 分立磁性器件， 例如分立电感通常由表面贴装方法安装在印刷电路板上， 再经由板上的连线连 接到负载。 这一部分的连线会引入寄生电感， 从而限制电流变化的速度， 降低 电源的瞬态响应性能。
[0005] 第三， 分立磁性器件不利于系统的小型化。 数量众多的分立磁性器件不但占据 了电路板的面积， 也同吋增加了系统的厚度。 分立磁性器件本身的厚度通常为 数百微米甚至数毫米， 而印刷电路板的厚度则在毫米水平。 因此， 对于使用分 立磁性器件的幵关电源， 进一步的缩小系统的面积和厚度非常困难。
[0006] 现有技术采用硅转接板 （silicon interposer) 进行电感集成的技术方案。 将电感 集成在硅转接板上,使得电感和电路芯片的连接更加容易和方便， 部分解决了系 统小型化的问题。 但是， 由于硅转接板正面金属互联线厚度小、 密度大， 使用 这些金属线作为集成电感的线圈会显著限制电感特别是功率电感的性能。 因此 ， 现有技术方案不能在硅转接板上提供高性能的集成功率电感。
[0007] 现有技术的硅转接板及电感集成系统的结构如图 1所示,系统 100包括硅转接板 10 1,101的正面是两层金属互联线 111和 112 (正面金属层，实际使用中金属互联线可 以为一层以上） ， 通过连接金属互联线的凸块 （bump) 121 (例如铜柱凸块） 连 接正面的芯片。 芯片 131和芯片 132通常是以倒装芯片焊接在硅转接板上。 芯片 1 31有大量的端口需要由凸块 121经由金属层 111和 112与芯片 132实现电连接， 所 以金属层 111和金属层 112具有很高的布线密度， 通常金属线之间的间距只有几 个微米，例如 2微米， 线宽也很小,例如 0.5微米。 布线密度和宽度限制了金属层 111 和 112的厚度，例如 0.5微米。
[0008] 正面的金属互联线 111和 112通过硅转接板 101上的硅通孔 （TSV) 102连接到背 面的金属再分布层（背面金属层） 141。 背面金属层 141通过焊接球 142 (例如可控 塌陷芯片互联 C4) 与衬底 151 (例如印刷电路板 PCB) 上的金属线 152连接到其 他器件 （未示出） 。 由于背面金属线通常只有一层且对于表面平坦化的要求低 于正面金属互联线， 金属再分布层 141的线宽和厚度要求都比正面的金属互联线 111和 112宽松， 其线宽可达到几十微米， 而厚度可以达到几微米。
[0009] 现有技术利用正面金属层 111、 112， 背面金属层 141和硅通孔 102组成电感， 通 常有两种结构， 一种结构如图 2-1所示， 硅转接板上的电感 200由正面金属互联层 111、 112形成螺旋 201， 由背面金属层 141形成螺旋 203， 通过硅通孔 202形成一 个多层双面螺旋电感。 另一种结构如图 2-2所示， 硅转接板上的电感 210由正面金 属互联层 111、 112形成金属线 211， 由背面金属层 141形成金属线 213， 再由硅通 孔 212形成一个螺线形电感。
[0010] 使用正面金属层 111、 112构成的电感结构的不足， 表现在两方面： 其一， 正面 金属层的厚度太小且不能显著增加， 否则就会增加金属线宽、 线间距， 从而导 致互联密度降低。 所以用正面金属线作为电感线圈的一部分会显著增加电感的 电阻， 增加电感功耗， 降低电感效率。 其二， 电感的走线会消耗所在区域的一 层以上的正面金属线。 金属线层数的减少会限制该区域金属线布局和互联的灵 活性， 从而降低硅转接板的互联能力。
[0011] 在对比文件 1 US 8,072,042(CN 102479685B)中， 正反面的金属导线及连接金属 导线的两个导电通孔的电学交叉连接位于衬底表面， 其磁芯穿通整个衬底。
[0012] 在对比文件 2 US 20130335059,对比文件 3 US 2013/0020675中， 电感的金属导 线由硅衬底正面形成于介质层中的金属堆栈， 硅通孔， 以及硅片背面的金属再 分布层组成。
[0013] 在对比文件 4 US 8,143,952 (CN 102576657)中， 形成电感线圈的第一部分金属 使用的是后段工艺过程 （back-end-of-line, BEOL) 中形成于衬底表面的第一层 金属。
[0014] 根据上述可以看出， 现有技术将电感集成在硅转接板上， 既损失了电感的性能 ， 又降低了硅转接板的功能， 无法在硅转接板中集成具有高电感密度和品质因 数的集成磁性器件。
技术问题
[0015] 本发明的目的是提供一种具有集成磁性器件的转接板， 要解决的技术问题是提 高集成磁性器件的性能。
问题的解决方案
技术解决方案
[0016] 本发明采用以下技术方案:一种具有集成磁性器件的转接板， 在衬底上设有磁 性器件， 磁性器件的线圈由金属线连接构成， 所述金属线设置在衬底内。
[0017] 本发明的金属线为第一金属线和第二金属线,第一金属线和第二金属线由其中 填充有金属的第二通孔电连接构成线圈。
[0018] 本发明的线圈为螺线形。
[0019] 本发明的第一金属线设置在衬底内。
[0020] 本发明的第一金属线嵌入设置在衬底上面的第一表面内。
[0021] 本发明的第二金属线设置在第二表面外。
[0022] 本发明的所述衬底中设有电连接第二金属线与第一表面的其中填充有金属的 第一通孔。 [0023] 本发明的第一金属线、 第二金属线和其中填充有金属的第二通孔组成线圈组 ， 一组线圈与另一组线圈之间磁性耦合； 所述一组线圈与另一组线圈的第一金 属线和第二金属线之间紧邻或间隔单条第一金属线和第二金属线。
[0024] 本发明的衬底外、 第二表面与第二金属线之间设置有平面的磁芯， 所述磁芯 的磁路闭合或具有间隙。
[0025] 本发明的第二表面内设有嵌入式的磁芯， 嵌入式磁芯从第二表面延伸进入衬底 内部， 所述磁芯的磁路闭合或具有间隙。
发明的有益效果
有益效果
[0026] 本发明与现有技术相比， 将磁性器件的一部分金属线嵌入在衬底内， 显著降低 磁性器件的电阻， 提高集成磁性器件的电感密度和品质因数， 减小磁性器件的 体积， 提升了效率,并且不影响转接板表面的平坦性、 不占用现有金属互联线， 在保证硅转接板本身互联功能不受损的前提下， 实现了高性能磁性器件的集成 对附图的简要说明
附图说明
[0027] 图 1是现有技术的硅转接板结构示意图。
[0028] 图 2-1是现有技术的集成电感结构示意图 （一） 。
[0029] 图 2-2是现有技术的集成电感结构示意图 （二） 。
[0030] 图 3是本发明实施例 1的结构示意图。
[0031] 图 4是图 3的 A-A剖视图。
[0032] 图 5是本发明实施例 2的结构示意图。
[0033] 图 6是图 5的 B-B剖视图。
[0034] 图 7是本发明实施例 3的结构示意图。
[0035] 图 8是图 7的 C-C剖视图。
[0036] 图 9是本发明的实施例 4的俯视图。
[0037] 图 10是本发明的实施例 5的俯视图。
[0038] 图 11是本发明的实施例 6的俯视图。 [0039] 图 12是本发明的实施例 7的俯视图。
实施该发明的最佳实施例
本发明的最佳实施方式
[0040] 对比例 1为螺旋形电感， 转接板的厚度为 ΙΟΟ μηι, 衬底采用电阻率为 1000 Ω-cm 的高阻硅， 第一金属线采用铜， 用现有技术的沉积和图形化方法得到， 第一金 属线位于第一表面之上， 厚度为 1 μηι。 第二金属线采用铜， 用现有技术的电镀 方法得到， 位于第二表面之外， 厚度为 5 μηι。 第二通孔采用铜， 用现有技术的 电镀方法得到， 直径为 20 μηι。 该螺旋形电感为 10圈， 每圈线圈的宽度为 60 μηι ， 线圈的间距为 100 μηι。 螺旋形电感位于转接板上的宽度 （Α-Α方向） 为 500 μηι ， 转接板的面积为 0.5 mm 2。 根据 Ansoft HFSS三维电磁场仿真系统的仿真计算结 果， 该螺旋形电感的电感值为 6.7 nH， 电感密度为 13.4 nH/mm 2， 直流电阻为 1.7 Ω， 高频幵关电源的典型频率 20 MHz吋的品质因数为 0.5。
[0041] 实施例 1同样为螺旋形电感， 采用与对比例 1相同的材料、 制备方法得到第二金 属线和第二通孔。 将第一金属线 311嵌入在转接板 300中， 其沟槽用深反应离子 刻蚀方法得到，使用光刻胶或者二氧化硅作为刻蚀的掩模层， 使用 60 sccm的 C 4F 8 作钝化层沉积， 使用 150 sccm的 SF 6混合 15 sccm的 0 2及10 sccm的 C 4F 8作为刻蚀 气体， 以 500W的射频功率交替进行吋间周期分别为 15秒和 10秒的刻蚀及钝化步 骤， 逐步刻蚀沟槽至需要的深度。 第一金属线厚度为 50
μηι。 由于第一金属线 311的厚度增加使得单位长度导线的电阻减小， 所以可以使 线圈绕得更密集； 即将线圈宽度和间距分别减小为 30 μηι和 50 μηι， 在同样的转 接板面积下实施例 1中的电感可以包含有 20圈线圈。 按对比例 1相同的方法仿真 计算， 实施例 1中的电感的电感值为 15.8 ηΗ， 电感密度为 31.6 nH/mm 2， 直流电 阻为 1.2 Ω， 20 MHz吋的品质因数为 1.33。 由此可见， 在同样的转接板电感面积 下， 相比对比例 1， 实施例 1可以提高电感密度 2.4倍， 显著降低电感直流电阻， 减小 30%， 提高品质因数 2.7倍。
[0042] 对比例 2在对比例 1的螺旋形电感的基础上， 在第二表面 520外的位置增加厚度 为 2 μηι， 相对磁导率为 600， 电阻率为10(^ .(^的0) 9(^& 52]" 5作为平面磁芯540 。 采用现有技术的溅射工艺后用图形化的方方法得到。 按对比例 1的方法得到第 一金属线、 第二金属线和第二通孔。 按对比例 1相同的方法仿真计算， 对比例 2 中的电感的电感值为 34.5 nH， 电感密度为 69.0 nH/mm 2， 直流电阻为 1.7 Ω， 20 MHz吋的品质因数为 2.4。
[0043] 实施例 2按实施例 1的方法得到第一金属线、 第二金属线和第二通孔， 按对比例 2的方法得到平面磁芯 540。 按对比例 1相同的方法仿真计算， 实施例 2中的电感 的电感值为 145 nH， 电感密度为 290 nH/mm 2， 直流电阻为 1.2 Ω， 20 MHz日寸的品 质因数为 9.9。 在同样的转接板电感面积下， 相比对比例 2， 实施例 2提高电感密 度 4.2倍， 降低了电感的直流电阻 30%， 提高品质因数 4.1倍。
[0044] 对比例 3在对比例 1的螺旋形电感的基础上， 在第二表面 720内的位置增加厚度 为 20 μηι， 相对磁导率为 600， 电阻率为 100 μΩ·αη的 NiFe作为嵌入式磁芯 740， 可在电镀过程中参入碳元素以提高电阻率。 嵌入式磁芯 740共 20条， 每条的宽度 为 10 μηι。 在第二表面用现有技术的深反应离子刻蚀形成沟槽， 进行磁材料的电 镀和平坦化， 形成从第二表面嵌入衬底的磁芯。 按对比例 1的方法得到第一金属 线、 第二金属线和第二通孔。 按对比例 1相同的方法仿真计算， 对比例 3中的电 感的电感值为 61.6 ηΗ， 电感密度为 123.2 nH/mm 2， 直流电阻为 1.7 Ω， 20 MHz曰寸 的品质因数为 2.9。
[0045] 实施例 3按实施例 1的方法得到第一金属线、 第二金属线和第二通孔， 按对比例 3的方法得到嵌入式磁芯 740。 按对比例 1相同的方法仿真计算， 实施例 3中的电 感的电感值为 274 nH， 电感密度为 548 nH/mm 2， 直流电阻为 1.2 Ω， 20 MHz日寸的 品质因数为 4.75。 在同样的转接板电感面积下， 相比对比例 3， 实施例 3提高电感 密度 4.4倍， 降低了电感的直流电阻 30%， 提高品质因数 1.6倍。
本发明的实施方式
[0046] 下面结合附图和实施例对本发明作进一步详细说明。 本发明的具有集成磁性器 件的转接板,以集成电感为例， 说明具有磁性器件的转接板 （转接板， 集成电感 ) 的结构及其制备方法。
[0047] 实施例 1， 磁性器件无磁芯。
[0048] 如图 3所示， 具有集成磁性器件的转接板 300， 包含有衬底 301、 位于衬底 301上 面的第一表面 310和位于衬底 301下面的第二表面 320。 衬底 301为半导体材料或 绝缘材料， 半导体材料为硅、 锗或化合物半导体， 优选的半导体材料为硅。 化 合物半导体为氮化镓 （GaN) 、 砷化镓 （GaAs) 、 碳化硅 （SiC) 、 硅锗 （SiGe ) 。 绝缘材料为玻璃、 石英或有机基板。
[0049] 第一表面 310下的沟槽中嵌入有第一金属线 （嵌入式金属线） 311。 沟槽可以通 过刻蚀，例如深反应离子刻蚀 （deep reactive ion etch) 的方式形成于衬底 301中。 第一金属线 311位于衬底 301的内部， 其上部与第一表面 310实现平坦化。 在平坦 化的第一表面 310之上， 可以继续沉积多层绝缘层和金属层， 用于形成转接板第 一表面的金属互联， 在图 3中， 为了清晰展示电感结构， 未画出第一表面 310以 上的金属互联结构。 第二表面 320外设置有第二金属线 321， 通过竖直设置在衬 底 301中的第一通孔中填充的金属 (通孔 )331， 实现第二金属线 321与第一表面 310 的电连接， 通过竖直设置在衬底 301中的第二通孔 332， 实现第二金属线 321与嵌 入式金属线 311的位于衬底内的下端 312的电连接。
[0050] 在图 3中,图示排列在前面第一的第一金属线 311右端经一第二通孔 332电连接图 示前面第一的第二金属线 321的右端,图示前面第一的第二金属线 321的左端经另 一第二通孔 332电连接图示第二的第一金属线 311的左端，
图示第二的第一金属线 311的右端经再一第二通孔 332电连接图示第二的第二金 属线 321的右端,继续这样电连接后面的第一金属线 311和第二金属线 321,排列在 最后的第二金属线 321的左端经第一通孔 331电连接第一表面 310,形成集成电感的 线圈。
[0051] 如图 4所示， 转接板 400 (300) 包含衬底 401 (301) 、 第一表面 410 (310) 和 第二表面 420 (320) 。 第一金属线 411 (311) 由第一表面 410延伸进入衬底 401 内部， 形成嵌入式的金属线。 第一金属线 411通过位于衬底 401内部的第二通孔 4 32 (332) 连接位于衬底第二表面 420外的第二金属线 421 (321) 。 第一金属线 4 11、 第二金属线 421和第二通孔 432与衬底 401之间设有绝缘层 433。 第二表面 420 外设有绝缘层 422， 第二金属线 421设置在绝缘层 422中。 第一金属线 411、 第二 金属线 421和第二通孔 432构成集成电感线圈的一圈线圈。 当衬底 401为半导体材 料吋， 电感包含第一金属线 411、 第二金属线 421、 第二通孔 432、 绝缘层 433、 第二表面 420外的绝缘层 422。 对于绝缘体材料或高阻硅的衬底， 则无需绝缘层 。 由嵌入式金属线 411、 第二表面上的第二金属线 421和第二通孔 432组成集成电 感的线圈。
[0052] 在第一表面 410之上可以使用现有技术的工艺方法形成一层以上金属线 415的金 属互联层、 金属互联层之间设置的绝缘层 413和连接在最外层金属线的凸块 414 ， 凸块 414用于将转接板的第一表面与外界电路相连接。 由于第一金属线 411与 转接板的第一表面 410实现了平坦化， 减小了不平整表面对后续制造工艺的影响 ， 所以金属线 415和凸块 414容易做到小的间距及线宽， 从而增加金属互联层的 密度。 因此， 第一表面 410更适合于连接输入 /输出端口数量较多的器件， 例如现 场可编辑门阵列 FPGA芯片、 微处理器芯片和电源管理芯片。
[0053] 在第二表面 420之上可以使用现有技术的工艺方法形成一层以上第二金属线 421 的金属互联层、 金属互联层之间设置的绝缘或钝化层 422和连接在最外层第二金 属线的焊球 423， 焊球 423用于将转接板的第二表面与外界电路相连接。 通常第 二金属线 421的厚度会大于金属线 415的厚度， 所以第二金属线 421的间距及线宽 通常大于第一表面 410上的金属互联层， 因此， 第二表面更适合于连接线宽较大 的器件， 例如印刷电路板。
[0054] 实施例 2， 转接板上设有平面磁芯。
[0055] 在实施例 1的基础上， 实施例 2增加了位于第二表面外的平面磁芯。
[0056] 如图 5所示， 转接板 500(300)包含衬底 501(301)、 第一表面 510(310)、 第二表面 5 20(320)、 嵌入于第一表面内的第一金属线 511(311)、 形成于第二表面外的第二金 属线 521(321)、 用于实现电连接的第一通孔 531(331)和第二通孔 532(332)。
[0057] 在衬底 501外、 第二表面 520与第二金属线 521之间设置有平面磁芯 540， 在平面 磁芯 540周围覆盖有绝缘层， 绝缘层用于平面磁芯 540与第二金属线 521和衬底 50 1之间的绝缘。 平面磁芯 540通过沉积例如溅射、 蒸镀或电镀与图形化的方法得 到。 平面磁芯 540由具有高磁导率的材料层例如镍 （Ni) 、 铁 （Fe) 、 钴 （Co) 和锰 （M) 磁性元素的合金、 氧化物或复合材料， 或高磁导率材料层与绝缘层叠 片 （laminate) 形成。 由第一金属线 511、 第二通孔 532和第二金属线 521组成集成 电感的线圈， 线圈环绕平面磁芯 540。 可以将平面磁芯 540沿平行于线圈磁力线 的方向 （垂直于 B-B) 的方向分割成多条 （至少两条） ， 以降低平面磁芯 540中 的涡流。
[0058] 如图 6所示， 转接板 600(300)包含衬底 601(301)、 第一表面 610(310)、 第二表面 6 20 (320) 。 第一金属线 611 (311) 从第一表面 610延伸到衬底 601内部， 通过第 二通孔 632 (332) 与第二表面 620外的第二金属线 621 (321) 实现电连接。 可采 用绝缘层 633 (433) 将第一金属线 611、 第二金属线 621、 第二通孔 632与衬底 60 1绝缘。 第一表面 610上可以形成一层以上金属层 615 (415) ， 金属层 615之间为 绝缘层 613 (413) 。 在第一表面 610和第二表面 620外可以分别形成凸块 614 (41 4) 和焊球 623 (423) ， 用于转接板和其他器件的连接。 平面磁芯 640 (540) 位 于第二表面 620与第二金属线 621之间， 可以通过绝缘或钝化层 622 (422) 实现 平面磁芯 640 (540) 与衬底 601、 第二金属线 621之间的绝缘。
[0059] 实施例 3， 转接板内嵌入有嵌入式磁芯。
[0060] 在实施例 1的基础上， 实施例 3增加了位于第二表面内的嵌入式磁芯。
[0061] 如图 7所示， 转接板 700(300)包含衬底 701(301)、 第一表面 710(310)、 第二表面 7 20 (320) ， 嵌入于第一表面 710内的第一金属线 711 (311) ， 形成于第二表面 外的第二金属线 721 (321) ， 用于实现电连接的第一通孔 731 (331) 和第二通 孑 L732 (332) 。
[0062] 第二表面 720内设有嵌入式磁芯 740， 嵌入式磁芯 740从第二表面 740延伸进入衬 底 701内部， 嵌入式磁芯 740与衬底 701之间可以设置绝缘层。 嵌入式磁芯 740刻 蚀形成沟槽后通过沉积例如溅射、 蒸镀或电镀与图形化或平坦化的方法形成。 嵌入式磁芯 740由具有高磁导率的材料层例如镍 Ni、 铁 Fe、 钴 Co和锰 Mn磁性元 素的合金、 氧化物或复合材料， 或高磁导率材料层与绝缘层叠片形成。 由第一 金属线 711、 第二通孔 732和第二金属线 721组成集成电感的线圈， 线圈环绕嵌入 式磁芯 740。 嵌入式磁芯 740沿垂直第一金属线 711长度方向被分割成 4条， 以降 低磁芯中的涡流。 可以根据需要调整磁芯分割的数量在 1条以上。
[0063] 如图 8所示， 转接板 800(300)包含衬底 801(301)、 第一表面 810(310)、 第二表面 8 20 (320) 。 第一金属线 811 (311) 从第一表面延伸到衬底内部， 通过第二通孔 832 (432) 与第二表面外的第二金属线 821 (321) 实现电连接。 可使用绝缘层 8 33 (433) 将第一金属线 811、 第二金属线 821、 第二通孔 832与衬底 801绝缘。 第 一表面 810上可以形成一层以上金属层 815 (415) ， 金属层 815之间为绝缘层 813 (413) 。 在第一表面 810和第二表面 820外可以分别形成凸块 814和焊球 823， 用 于转接板和其他器件的连接。 嵌入式磁芯 840 (740) 位于第二表面 820内， 从第 二表面 820延伸进入衬底 801内部， 可以采用绝缘层 841实现嵌入式磁芯 840与衬 底 801之间的绝缘。 可以采用绝缘或钝化层 822 (422) 实现第二金属线 821与衬 底 801之间的绝缘。 嵌入式磁芯 841 (740) 沿垂直第一金属线 811 (711) 长度方 向被分割成 4条， 以降低磁芯中的涡流。
[0064] 实施例 2-3中， 记载了在使用嵌入式金属线的电感中设置磁芯。 还可以通过不 同的线圈排列， 在转接板上设置其他的磁性器件， 例如耦合电感和变压器。 为 了清晰的展示磁性器件线圈的排列方式， 在实施例 4-7中未示出磁芯、 凸块、 焊 球结构。 在实际使用吋， 可以根据实施例 1-3的结构设置磁芯、 凸块、 焊球结构
[0065] 实施例 4， 沿图 3中的 D向，为包含有磁性器件的转接板 900(300)的俯视方向， 如 图 9所示， 转接板 900(300)包含由图示上面紧邻的三条第一金属线 （嵌入式金属 线） 911(311)、 图示上面紧邻的两条位于第二表面外的第二金属线 921(321)和连 接所述第一金属线与第二金属线的第二通孔 932(332)组成的第一组线圈。 转接板 900还包含了由图示下面紧邻的三条第一金属线 （嵌入式金属线） 940(311)、 图 示下面紧邻的两条位于第二表面外的第二金属线 950(321)和连接所述第一金属线 与第二金属线的第二通孔 960(332)组成的第二组线圈。 第一组线圈与第二组线圈 之间存在着磁性耦合。
[0066] 实施例 5,
沿图 3中的 D向,为包含有磁性器件的转接板 1000(300)的俯视方向,如图 10所示， 转 接板 1000(300)包含由间隔单条的三条第一金属线 （嵌入式金属线） 1011(311)、 间隔单条的两条位于第二表面外的第二金属线 1021(321)和连接所述第一金属线 与第二金属线的第二通孔 1032(332)组成的第一组线圈。 转接板 1000还包含了由 间隔单条的另三条第一金属线 （嵌入式金属线） 1040(311)、 位于第二表面外的 间隔单条的另两条第二金属线 1050(321)和连接所述第一金属线与第二金属线的 第二通孔 1060(332)组成的第二组线圈。 第二组线圈的金属线与第一组线圈的第 一金属线和第二金属线交替放置， 形成相互交缠的结构,并存在着磁性耦合。
[0067] 实施例 4和实施例 5示出了两组线圈相互耦合的情况， 在实际使用中， 可以根据 需要包含两组以上相互耦合的线圈。
[0068] 实施例 6,沿图 3中的 D向,为包含有磁性器件的转接板 1100(300)的俯视方向。 如 图 11所示， 转接板 1100(300)中包含有磁路闭合的磁芯 1111。
[0069] 实施例 7,沿图 3中的 D向,为包含有磁性器件的转接板 1200(300)的俯视方向。 如 图 12所示， 转接板 1200(300)中包含有磁芯 1221(1311)具有空隙 1222， 通过调整空 隙的大小， 可以调节磁性器件的电感值和饱和电流值参数。
[0070] 实施例 1 -7中的转接板， 在第一表面或第二表面未被磁性器件占据的区域的半 导体衬底中,可以包含其他有源器件,无源器件， 或有源器件与无源器件的组合,例 如集成电路。
工业实用性
[0071] 相对于现有技术， 硅通孔连接衬底的正面和背面金属线形成的电感， 都是利用 了衬底表面的金属线， 对比文件 1在衬底中已经没有空间可以形成嵌入式的金属 线， 对比文件 2和 3正面的金属线不是嵌入在衬底正面的沟槽中， 对比文件 4也不 是形成于衬底正面的沟槽中的嵌入式金属线。 本发明将磁性器件的一部分金属 导体嵌入在衬底内， 显著降低电感的电阻， 提高集成磁性器件的电感密度和品 质因数，达到减小体积， 提升效率的作用。 将磁性器件的一部分金属导体嵌入在 衬底内， 不影响转接板表面的平坦性、 不占用现有金属互联线， 在保证硅转接 板本身互联功能不受损的前提下， 实现了高性能磁性器件的集成。 因此， 本发 明的在不损失转接板厚度小， 互联线宽小， 互联密度大的优势的情况下， 在转 接板中集成有高电感密度和品质因数的集成磁性器件。

Claims

权利要求书
[权利要求 1] 一种具有集成磁性器件的转接板， 在衬底上设有磁性器件， 磁性器件 的线圈由金属线连接构成， 其特征在于： 所述金属线设置在衬底内。
[权利要求 2] 根据权利要求 1所述的具有集成磁性器件的转接板， 其特征在于： 所 述金属线为第一金属线和第二金属线,第一金属线和第二金属线由其 中填充有金属的第二通孔电连接构成线圈。
[权利要求 3] 根据权利要求 2所述的具有集成磁性器件的转接板， 其特征在于： 所 述线圈为螺线形。
[权利要求 4] 根据权利要求 3所述的具有集成磁性器件的转接板， 其特征在于： 所 述第一金属线设置在衬底内。
[权利要求 5] 根据权利要求 4所述的具有集成磁性器件的转接板， 其特征在于： 所 述第一金属线嵌入设置在衬底上面的第一表面内。
[权利要求 6] 根据权利要求 5所述的具有集成磁性器件的转接板， 其特征在于： 所 述第二金属线设置在第二表面外。
[权利要求 7] 所述衬底中设有电连接第二金属线与第一表面的其中填充有金属的第
一通孔。
[权利要求 8] 根据权利要求 7所述的具有集成磁性器件的转接板， 其特征在于： 所 述第一金属线、 第二金属线和其中填充有金属的第二通孔组成线圈组 ， 一组线圈与另一组线圈之间磁性耦合； 所述一组线圈与另一组线圈 的第一金属线和第二金属线之间紧邻或间隔单条第一金属线和第二金 属线。
[权利要求 9] 根据权利要求 8所述的具有集成磁性器件的转接板， 其特征在于： 所 述衬底外、 第二表面与第二金属线之间设置有平面的磁芯， 所述磁芯 的磁路闭合或具有间隙。
[权利要求 10] 根据权利要求 8所述的具有集成磁性器件的转接板， 其特征在于： 所 述第二表面内设有嵌入式的磁芯， 嵌入式磁芯从第二表面延伸进入衬 底内部， 所述磁芯的磁路闭合或具有间隙。
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