WO2017166657A1 - 外设部件互联总线 - Google Patents

外设部件互联总线 Download PDF

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Publication number
WO2017166657A1
WO2017166657A1 PCT/CN2016/097022 CN2016097022W WO2017166657A1 WO 2017166657 A1 WO2017166657 A1 WO 2017166657A1 CN 2016097022 W CN2016097022 W CN 2016097022W WO 2017166657 A1 WO2017166657 A1 WO 2017166657A1
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WIPO (PCT)
Prior art keywords
interface circuit
circuit board
printed circuit
peripheral interface
contact line
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Ceased
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PCT/CN2016/097022
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English (en)
French (fr)
Inventor
常琪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Le Holdings Beijing Co Ltd
Leshi Zhixin Electronic Technology Tianjin Co Ltd
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Le Holdings Beijing Co Ltd
Leshi Zhixin Electronic Technology Tianjin Co Ltd
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Publication of WO2017166657A1 publication Critical patent/WO2017166657A1/zh
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/183—Internal mounting support structures, e.g. for supporting printed circuit boards
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4086—Bus impedance matching, e.g. termination

Definitions

  • the present application relates to the field of communication technologies, for example, to a peripheral component interconnection bus.
  • PCI Peripheral Component Interconnect
  • PCI-E PCI Express
  • PCI bus structures that combine high-speed peripheral devices with processors to meet the increasing data rate requirements of users.
  • a device with a PCI bus structure can achieve a theoretical data rate of 132 Mbytes/s.
  • One of the outstanding advantages of using the PCI bus is that the central processing unit (CPU) has a very low occupancy rate.
  • the interaction between the CPU and the memory is basically through direct memory access (DMA), so high data is required.
  • PCI bus devices can be used for both rate and low power consumption.
  • the PCI bus typically includes a PCI interface chip and a configuration chip.
  • the inventors have found that at least the following problems exist in the related art: at present, the design of the smart TV tends to be flat, which seriously compresses the space of the PCI bus, if the circuits of different peripheral interface circuit communication are combined On a printed circuit board, the differential impedance required by different peripheral interface circuits is inconsistent, which affects signal integrity and time delay, thereby reducing communication quality.
  • the embodiment of the present application provides a peripheral component interconnection bus and a smart TV, which implements PCI bus multiplexing.
  • an embodiment of the present application provides a peripheral component interconnection bus, including: a printed circuit board surface layer for communicating with a first peripheral interface circuit and a printed circuit board for communicating with a second peripheral interface circuit a bottom layer, wherein the printed circuit board surface layer includes a surface contact line that is matched to meet a differential impedance of the first peripheral interface circuit, and the printed circuit board bottom layer includes a differential impedance that is matched to the second peripheral interface circuit The bottom layer of the contact line.
  • the bus further includes a connector slot that mates with the printed circuit board.
  • the surface contact line includes: a first predetermined length of contact line, wherein the first preset length is determined according to a differential impedance of the first peripheral interface circuit;
  • the bottom layer contact line includes: a second predetermined length of contact line, the second set length being determined according to a differential impedance of the second peripheral interface circuit.
  • the surface contact line includes: a plurality of contact lines disposed at equal intervals, and the spacing is determined according to a differential impedance of the first peripheral interface circuit;
  • the bottom layer contact line includes: a plurality of contact lines disposed at equal intervals, the spacing being determined according to a differential impedance of the second peripheral interface circuit.
  • the surface contact line is bent and arranged on the surface of the printed circuit board according to the first preset length; and/or the bottom contact line is bent and arranged on the surface of the printed circuit board according to the second preset length.
  • the printed circuit board surface layer includes: a first material filled between the surface contact lines, the first material being determined according to a differential impedance of the first peripheral interface circuit;
  • the printed circuit board bottom layer includes a second material filled between the bottom layer contact lines, the second material being determined according to a second peripheral interface circuit differential impedance, the second material being different from the first material.
  • the first material is a plastic and the second material is a resin.
  • the first peripheral interface circuit is a universal serial bus USB interface circuit.
  • the second peripheral interface circuit is a high definition multimedia interface circuit or a universal asynchronous transceiver transmitter UART interface circuit.
  • the peripheral component interconnection bus provided by the embodiment of the present application can achieve dual interface multiplexing by connecting the surface layer and the bottom layer of the PCI bus to different peripheral interfaces respectively.
  • the surface contact line and the bottom contact line to meet the corresponding interface circuit differential impedance, the problem of different differential impedances of different interface circuits can be solved, and the communication quality is improved.
  • FIG. 1 is a schematic diagram of a peripheral component interconnection bus provided by Embodiment 1 of the present application;
  • FIG. 1a is a schematic structural diagram of a printed circuit board surface layer of a peripheral component interconnection bus according to Embodiment 1 of the present application;
  • FIG. 1b is a schematic structural diagram of a bottom layer of a printed circuit board of a peripheral component interconnection bus according to Embodiment 1 of the present application;
  • FIG. 2 is a schematic diagram showing a microscopic shape of a surface contact line in a peripheral component interconnect bus provided by Embodiment 2 of the present application;
  • FIG. 3 is a schematic diagram showing the microscopic shape of an underlying contact line in a peripheral component interconnect bus provided by Embodiment 2 of the present application;
  • FIG. 4 is a schematic diagram of a surface layer of a printed circuit board in a peripheral component interconnect bus provided by Embodiment 3 of the present application;
  • FIG. 5 is a schematic diagram of a bottom layer of a printed circuit board in a peripheral component interconnect bus provided by Embodiment 3 of the present application.
  • orientation words used are as follows: “upper, lower, The top and bottom” are generally used in terms of the directions shown in the drawings or are used to describe the positional relationship of the components in terms of vertical, vertical or gravity directions.
  • Embodiment 1 of the present application provides a peripheral component interconnection bus.
  • FIG. 1 is a schematic diagram of a peripheral component interconnection bus provided by Embodiment 1 of the present application.
  • the peripheral component interconnect bus includes a printed circuit board surface for communicating with the first peripheral interface circuit and a printed circuit board bottom layer for communicating with the second peripheral interface circuit.
  • the printed circuit board surface layer includes a surface contact line that is matched to meet a differential impedance of the first peripheral interface circuit
  • the printed circuit board bottom layer includes a bottom layer that is matched to conform to a differential impedance of the second peripheral interface circuit Contact line.
  • the interface multiplexed peripheral component interconnect bus PCI bus can be divided into a printed circuit board surface layer and a printed circuit board bottom layer.
  • the peripheral component interconnection bus includes: a printed circuit board 1 and a connector slot 2, and a contact line 5 is provided on the printed circuit board, and the printed circuit board 1 is matched with the connector slot 2 through the contact line 5 connection.
  • FIG. 1 is a schematic structural diagram of a printed circuit board surface layer of a peripheral component interconnection bus according to Embodiment 1 of the present application
  • FIG. 1B is a schematic structural diagram of a printed circuit board bottom layer of a peripheral component interconnection bus according to Embodiment 1 of the present application.
  • the printed circuit board surface layer and the printed circuit board bottom layer may respectively include an insulating substrate, a conductive pattern layer on the insulating substrate, and various integrated chips, wherein the conductive pattern layer and the integrated chip on the surface of the printed circuit board and on the bottom layer of the printed circuit board are respectively used Receive signals transmitted by different peripheral interfaces.
  • a contact line 5 is provided below the surface layer of the printed circuit board, which is composed of a plurality of conductive contacts.
  • the signal is transmitted through the contact line. Since the printed circuit board surface layer and the printed circuit board bottom layer respectively communicate with different peripheral interfaces, when the signal propagates through the transmission channel, the electromagnetic coupling affects the adjacent transmission line. In order to avoid the influence of crosstalk and ensure the integrity of the signal, it is necessary to ensure the matching and continuity of the differential impedance. Since the differential impedance required by different peripheral interfaces is different, it is necessary to match the surface contact line 3 and the bottom contact line 4 to the differential impedance of the peripheral interface corresponding to the corresponding connection. Correspondingly, the printed circuit board surface layer includes a surface contact line 3 matched to meet a differential impedance of the first peripheral interface circuit, and the printed circuit board bottom layer includes a differential impedance matched to the second peripheral interface circuit. The bottom contact line 4. In addition, the peripheral component interconnect bus also includes a connector slot 2 that is mated to the printed circuit board. The signal is transmitted to the corresponding channel through the pins of the connector slot 2.
  • the printed circuit board surface layer is used for interfacing with a universal serial bus (USB), and further, the printed circuit board bottom layer is used for Connected to the High Definition Multimedia Interface (HDMI).
  • USB interface and the HDMI interface are more commonly used interfaces in smart TVs.
  • the PCI bus can realize the purpose of transmitting USB interface data or HDMI interface data.
  • the second peripheral interface circuit can also be a Universal Asynchronous Receiver/Transmitter (UART) interface circuit. The interface circuit can be adjusted according to the design requirements.
  • FIG. 2 is a schematic diagram showing a microscopic shape of a surface contact line of a peripheral component interconnection bus provided in Embodiment 2 of the present application
  • FIG. 3 is a schematic diagram showing a microscopic shape of an underlying contact line in a peripheral component interconnection bus provided in Embodiment 2 of the present application.
  • the surface contact line 3 can be set as a contact line of a first preset length, and the first preset length is determined according to the differential impedance of the first peripheral interface circuit
  • a contact line of a second preset length may be set, the second preset length being determined according to a differential impedance of the second peripheral interface circuit.
  • the length of the contact line can affect the differential impedance
  • the length of the contact line can be experimentally determined according to the differential impedance value of the peripheral interface. Since the differential impedance of the first peripheral interface circuit is different from the differential impedance of the first peripheral interface circuit, the length of the surface contact line 3 is different from the length of the bottom contact line 4. As can be seen from FIG. 2, the microscopic shape of the surface contact line 3 is approximately "F" shaped, since the length of the region where the contact line is referred to on the circuit board is fixed, and in order to satisfy the length requirement of the surface contact line 3, The surface contact line 3 may be formed by bending the contact line regions in the surface layer of the printed circuit board in accordance with the first predetermined length. Similarly, as can be seen from FIG.
  • the bottom contact line 4 is set to a second predetermined length, and its microscopic shape is approximately "bow" shaped.
  • the length of the surface contact line 3 is smaller than the length of the underlying contact line 4. This is because the surface is connected to the USB interface and the bottom layer is connected to the HDMI interface.
  • the differential impedance of the USB interface is 90 ⁇ , and the differential impedance of the HDMI interface is 100 ⁇ .
  • the length of the contact line is proportional to the differential impedance, and the length of the contact line on the printed circuit board 1 can be determined experimentally based on the differential impedance value of the interface.
  • the surface contact line 3 may be bent and arranged on the surface of the printed circuit board according to the first predetermined length; and/or the bottom contact line 4 may be according to the second pre- Set the length to be curved on the surface of the printed circuit board.
  • FIG. 4 is a schematic diagram of a printed circuit board surface layer in a peripheral component interconnection bus according to Embodiment 3 of the present application
  • FIG. 5 is a schematic diagram of a printed circuit board bottom layer in a peripheral component interconnection bus according to Embodiment 3 of the present application
  • Figure. The embodiment is based on the above embodiment, the surface contact line 3 includes: a plurality of contact lines disposed at equal intervals, the spacing is determined according to a differential impedance of the first peripheral interface circuit; and the bottom contact line 4 includes: A plurality of contact lines disposed at a pitch, the spacing being determined according to a differential impedance of the second peripheral interface circuit.
  • the spacing between the contact lines can affect the differential impedance
  • the spacing between the contact lines can be experimentally determined based on the differential impedance values of the peripheral interfaces. Since the differential impedance of the first peripheral interface circuit is different from that of the first peripheral interface circuit, the pitch of the surface contact line 3 is different from the pitch of the bottom contact line 4. As can be seen from Figures 2 and 3, the pitch of the surface contact lines 3 is greater than the pitch of the bottom contact lines 4. Because the surface is connected to the USB interface, the bottom layer is connected to the HDMI interface. The differential impedance of the USB interface is 90 ⁇ , and the differential impedance of the HDMI interface is 100 ⁇ . The size of the pitch is inversely proportional to the differential impedance, and the spacing between the contact lines on the printed circuit board 1 can be determined experimentally based on the differential impedance values of the interface.
  • the differential impedance can also be adjusted by filling different materials between the contact lines.
  • a first material that may be filled between the surface contact lines 3, the first material being determined according to a differential impedance of the first peripheral interface circuit;
  • the printed circuit board underlayer comprising: filling between the underlying contact lines 4 a second material, the second material being determined according to a differential impedance of the second peripheral interface circuit, the second material being different from the first material.
  • the first material is a plastic and the second material is a resin.
  • the electromagnetic absorption characteristics of the materials can also be used to modulate the differential impedance, for example, The test determines the effect of different materials on the differential printed circuit on the same printed circuit board 1, and optionally fills the material between the contact lines.
  • the ratio of the differential impedance can be achieved by any combination of the above three methods, such as adjusting the length of the contact line, adjusting the spacing between the contact lines, and simultaneously filling the material between the contact lines.
  • the combination method will not be described here.
  • the peripheral component interconnection bus provided by the embodiment of the present application improves the communication quality.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Human Computer Interaction (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

本申请公开了一种外设部件互联总线，属于通信技术领域，包括：用于与第一外设接口电路通信的印刷电路板表层和用于与第二外设接口电路通信的印刷电路板底层，其中，所述印刷电路板表层包括被配比为符合第一外设接口电路差分阻抗的表层接触线，所述印刷电路板底层包括被配比为符合第二外设接口电路差分阻抗的底层接触线。

Description

外设部件互联总线
本申请要求在2016年3月31日提交中国专利局、申请号为201610196167.9、发明名称为“外设部件互联总线”的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，例如涉及一种外设部件互联总线。
背景技术
外设部件互连总线(Peripheral Component Interconnect，PCI)和PCI-E(PCI Express)是将周边设备与处理器高速结合起来的总线结构，以满足用户对于数据率越来越高的要求。使用PCI总线结构的设备，可以达到理论上峰值为132Mbytes/s的数据率。使用PCI总线一个突出的优点是中央处理器(Central Processing Unit，CPU)占用率极低，CPU和存储器之间的交互基本上通过直接内存存取(Direct Memory Access，DMA)方式，所以需要高数据率和低功耗的场合，都可以使用PCI总线设备。
PCI总线通常包括一个PCI接口芯片和一个配置芯片。在实现本申请过程中，发明人发现相关技术中至少存在如下问题：目前智能电视的设计趋向于扁平化，严重压缩了PCI总线的空间，如果将不同的外设接口电路通信的电路复合在同一个印刷电路板上，由于不同的外设接口电路所要求的差分阻抗不一致，会影响信号的完整性和时间延迟，进而降低通信质量。
发明内容
本申请实施例提供一种外设部件互联总线及智能电视，实现PCI总线复用。
第一方面，本申请实施例提供了一种外设部件互联总线，包括：用于与第一外设接口电路通信的印刷电路板表层和用于与第二外设接口电路通信的印刷电路板底层，其中，所述印刷电路板表层包括被配比为符合第一外设接口电路差分阻抗的表层接触线，以及所述印刷电路板底层包括被配比为符合第二外设接口电路差分阻抗的底层接触线。
可选的，所述总线还包括与所述印刷电路板配合的连接器插槽。
可选的，所述表层接触线包括：第一预设长度的接触线，所述第一预设长度根据第一外设接口电路差分阻抗确定；以及
所述底层接触线包括：第二预设长度的接触线，所述第二设长度根据第二外设接口电路差分阻抗确定。
可选的，所述表层接触线包括：等间距设置的多条接触线，所述间距根据第一外设接口电路差分阻抗确定；
所述底层接触线包括：等间距设置的多条接触线，所述间距根据第二外设接口电路差分阻抗确定。
可选的，所述表层接触线根据所述第一预设长度在印刷电路板表层弯曲排列；和/或所述底层接触线根据所述第二预设长度在印刷电路板表层弯曲排列。
可选的，所述印刷电路板表层包括：在所述表层接触线之间填充的第一材料，所述第一材料根据第一外设接口电路差分阻抗确定；以及
所述印刷电路板底层包括：在所述底层接触线之间填充的第二材料，所述第二材料根据第二外设接口电路差分阻抗确定，所述第二材料与第一材料不同。
可选的，所述第一材料为塑料，所述第二材料为树脂。
可选的，所述第一外设接口电路为通用串行总线USB接口电路。
更可选的，所述第二外设接口电路为高清晰度多媒体接口电路或通用异步收发传输器UART接口电路。
本申请实施例提供的外设部件互联总线，通过将PCI总线的表层和底层分别与不同的外设接口连接，同一PCI总线可以实现双接口复用。此外，通过将表层接触线和底层接触线配比为符合对应的接口电路差分阻抗，能够解决不同接口电路差分阻抗不同的问题，提高了通信质量。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1是本申请实施例一提供的外设部件互联总线的示意图；
图1a是本申请实施例一提供的外设部件互联总线的印刷电路板表层的结构示意图；
图1b是本申请实施例一提供的外设部件互联总线的印刷电路板底层的结构示意图；
图2是本申请实施例二提供的外设部件互联总线中一条表层接触线的微观形状示意图；
图3是本申请实施例二提供的外设部件互联总线中一条底层接触线的微观形状示意图；
图4是本申请实施例三提供的外设部件互联总线中印刷电路板表层的示意图；以及
图5是本申请实施例三提供的外设部件互联总线中印刷电路板底层的示意图。
图中的附图标记所分别指代的技术特征为：
1、印刷电路板；2、连接器插槽；3、表层接触线；4、底层接触线；5、接触线。
具体实施方式
下面结合附图和实施例对本申请进行详细说明。可以理解的是，此处所描述的实施例仅仅用于解释本申请，而非对本申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本申请相关的部分而非全部内容。在不冲突的情况下，本申请实施例中的特征可以任意组合。
在本申请实施例中，在未作相反说明的情况下，使用的方位词如“上、下、 顶、底”通常是针对附图所示的方向而言的或者是针对竖直、垂直或重力方向上而言的各部件相互位置关系描述用词。
实施例一
本申请实施例一提供了一种外设部件互联总线。图1是本申请实施例一提供的外设部件互联总线的示意图。如图1所示，外设部件互联总线包括：用于与第一外设接口电路通信的印刷电路板表层和用于与第二外设接口电路通信的印刷电路板底层。其中，所述印刷电路板表层包括被配比为符合第一外设接口电路差分阻抗的表层接触线，以及所述印刷电路板底层包括被配比为符合第二外设接口电路差分阻抗的底层接触线。接口复用的外设部件互连总线PCI总线可以分为印刷电路板表层和印刷电路板底层。
如图1所示，外设部件互联总线包括：印刷电路板1和连接器插槽2，在印刷电路板上设有接触线5，印刷电路板1通过接触线5和连接器插槽2配合连接。
图1a是本申请实施例一提供的外设部件互联总线的印刷电路板表层的结构示意图；图1b是本申请实施例一提供的外设部件互联总线的印刷电路板底层的结构示意图。印刷电路板表层和印刷电路板底层可以分别包括绝缘基板、在绝缘基板上的导电图形层和各种集成芯片，其中印刷电路板表层上和印刷电路板底层上的导电图形层及集成芯片分别用于接收不同的外设接口所传输的信号。在印刷电路板表层的下方设有接触线5，所述接触线5由众多的导电触片组成。通过接触线传送信号。由于印刷电路板表层和印刷电路板底层分别与不同的外设接口通信，信号在传输信道传播时，因电磁耦合会对相邻的传输线产生影响。为了避免串扰影响，保证信号的完整性，需要保证差分阻抗的匹配和一直连续性。由于不同的外设接口所要求的差分阻抗不同，因此需要将表层接触线3和底层接触线4配比为符合对应的连接的外设接口的差分阻抗。相应的，所述印刷电路板表层包括被配比为符合第一外设接口电路差分阻抗的表层接触线3，所述印刷电路板底层包括被配比为符合第二外设接口电路差分阻抗的底层接触线4。此外，外设部件互联总线还包括与印刷电路板对应配合连接的连接器插槽2。通过连接器插槽2的针脚，将信号传输给相应的通道。
在本实施例的一个可选实施方式中，所述印刷电路板表层用于与通用串行总线(Universal Serial Bus，USB)接口连接，此外，所述印刷电路板底层用于 与高清晰度多媒体接口(High Definition Multimedia Interface，HDMI)连接。USB接口和HDMI接口是智能电视中使用较多的接口。通过外设部件互联总线可以实现PCI总线即可实现传输USB接口数据或HDMI接口数据的目的。此外，第二外设接口电路也可以为通用异步收发传输器(Universal Asynchronous Receiver/Transmitter，UART)接口电路。接口电路可根据设计需求进行调整。
实施例二
图2是本申请实施例二提供的外设部件互联总线中一条表层接触线的微观形状示意图；图3是本申请实施例二提供的外设部件互联总线中一条底层接触线的微观形状示意图。本实施例以上述实施例为基础，表层接触线3可以设定为第一预设长度的接触线，所述第一预设长度根据第一外设接口电路差分阻抗确定；将底层接触线4可以设定为第二预设长度的接触线，所述第二预设长度根据第二外设接口电路差分阻抗确定。由于接触线的长度能够影响到差分阻抗，可以根据符合外设接口差分阻抗值通过实验确定接触线的长度。由于符合第一外设接口电路差分阻抗与符合第一外设接口电路差分阻抗不同，表层接触线3的长度与底层接触线4的长度也不相同。由图2可以看出，表层接触线3的微观形状呈近似于“F”形，这是由于在引述电路板上接触线的区域的长度是固定的，为了满足表层接触线3的长度要求，表层接触线3可以按照第一预设长度在印刷电路板表层中接触线区域弯曲排列后形成。同理，由图3可以看出，底层接触线4设定为第二预设长度，其微观形状呈近似于“弓”字形。表层接触线3的长度小于底层接触线4的长度。这是因为表层连接USB接口，底层连接HDMI接口。而USB接口差分阻抗为90Ω，HDMI接口差分阻抗为100Ω。接触线的长度与差分阻抗成正比关系，根据接口的差分阻抗值经过试验可以确定在印刷电路板1上接触线的长度。在印刷电路板上接触线的长度存在限制时，所述表层接触线3可根据所述第一预设长度在印刷电路板表层弯曲排列；和/或底层接触线4可根据所述第二预设长度在印刷电路板表层弯曲排列。
实施例三
图4是本申请实施例三提供的外设部件互联总线中印刷电路板表层的示意图；图5是本申请实施例三提供的外设部件互联总线中印刷电路板底层的示意 图。本实施例以上述实施例为基础，所述表层接触线3包括：等间距设置的多条接触线，所述间距根据第一外设接口电路差分阻抗确定；所述底层接触线4包括：等间距设置的多条接触线，所述间距根据第二外设接口电路差分阻抗确定。由于接触线之间的间距能够影响到差分阻抗，可以根据符合外设接口差分阻抗值通过实验确定接触线的之间的间距。由于符合第一外设接口电路差分阻抗与符合第一外设接口电路差分阻抗不同，表层接触线3的间距与底层接触线4的间距也不相同。由图2和图3可以看出，表层接触线3的间距大于底层接触线4的间距。因为表层连接USB接口，底层连接HDMI接口。而USB接口差分阻抗为90Ω，HDMI接口差分阻抗为100Ω。间距的大小与差分阻抗成反比关系，根据接口的差分阻抗值经过试验可以确定在印刷电路板1上接触线之间的间距。
此外，也可通过在接触线之间填充不同材料，调节差分阻抗。可以在所述表层接触线3之间填充的第一材料，所述第一材料根据第一外设接口电路差分阻抗确定；所述印刷电路板底层包括：在所述底层接触线4之间填充的第二材料，所述第二材料根据第二外设接口电路差分阻抗确定，所述第二材料与第一材料不同。其中，所述第一材料为塑料，所述第二材料为树脂。由于不同的材料对电磁波的传播有不同的吸收系数，从而影响接触线之间的电磁耦合，进而影响差分阻抗，利用材料的电磁吸收特性也可实现对差分阻抗的调制，示例性的，可以通过试验测定不同材料在同一印刷电路板1上对于差分阻抗的影响，进而选择在接触线之间填充材料。
此外，可以通过上述三种方式中的任意组合实现对差分阻抗的配比，例如调整接触线的长度，也调整接触线之间的间距，还同时在接触线之间填充材料。组合方式在此不做赘述。
注意，上述仅为本申请的较佳实施例及所运用技术原理。本领域技术人员会理解，本申请不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本申请的保护范围。因此，虽然通过以上实施例对本申请进行了较为详细的说明，但是本申请不仅仅限于以上实施例，在不脱离本申请构思的情况下，还可以包括更多其他等效实施例，而本申请的范围由所附的权利要求范围决定。
工业实用性
本申请实施例提供的外设部件互联总线，提高了通信质量。

Claims (9)

  1. 一种外设部件互联总线，包括：用于与第一外设接口电路通信的印刷电路板表层和用于与第二外设接口电路通信的印刷电路板底层，其中，所述印刷电路板表层包括被配比为符合第一外设接口电路差分阻抗的表层接触线，以及所述印刷电路板底层包括被配比为符合第二外设接口电路差分阻抗的底层接触线。
  2. 根据权利要求1所述的总线，所述总线还包括与所述印刷电路板配合的连接器插槽。
  3. 根据权利要求1所述的总线，其中，所述表层接触线包括：第一预设长度的接触线，所述第一预设长度根据第一外设接口电路差分阻抗确定；以及
    所述底层接触线包括：第二预设长度的接触线，所述第二预设长度根据第二外设接口电路差分阻抗确定。
  4. 根据权利要求3所述的总线，其中，所述表层接触线根据所述第一预设长度在印刷电路板表层弯曲排列；和/或
    所述底层接触线根据所述第二预设长度在印刷电路板表层弯曲排列。
  5. 根据权利要求1所述的总线，其中，所述表层接触线包括：等间距设置的多条接触线，所述间距根据第一外设接口电路差分阻抗确定；以及
    所述底层接触线包括：等间距设置的多条接触线，所述间距根据第二外设接口电路差分阻抗确定。
  6. 根据权利要求1所述的总线，其中，所述印刷电路板表层包括：在所述表层接触线之间填充的第一材料，所述第一材料根据第一外设接口电路差分阻抗确定；以及
    所述印刷电路板底层包括：在所述底层接触线之间填充的第二材料，所述第二材料根据第二外设接口电路差分阻抗确定，所述第二材料与第一材料不同。
  7. 根据权利要求6所述的总线，其中，所述第一材料为塑料，所述第二材料为树脂。
  8. 根据权利要求1-7任一所述的总线，其中，所述第一外设接口电路为通用串行总线USB接口电路。
  9. 根据权利要求1-7任一所述的总线，其中，所述第二外设接口电路为高清晰度多媒体接口电路或通用异步收发传输器UART接口电路。
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CN101400208A (zh) * 2007-09-28 2009-04-01 鸿富锦精密工业（深圳）有限公司 印刷电路板
CN201303458Y (zh) * 2008-10-31 2009-09-02 金哲虎 大容量信号传输载体用柔性印刷电路板
CN104752851A (zh) * 2015-02-09 2015-07-01 华为技术有限公司 一种系统
CN105843338A (zh) * 2016-03-31 2016-08-10 乐视控股（北京）有限公司 外设部件互联总线

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CN101400208A (zh) * 2007-09-28 2009-04-01 鸿富锦精密工业（深圳）有限公司 印刷电路板
CN201303458Y (zh) * 2008-10-31 2009-09-02 金哲虎 大容量信号传输载体用柔性印刷电路板
CN104752851A (zh) * 2015-02-09 2015-07-01 华为技术有限公司 一种系统
CN105843338A (zh) * 2016-03-31 2016-08-10 乐视控股（北京）有限公司 外设部件互联总线

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