WO2017166672A1 - 异步收发传输器和通用串行总线接口复用电路及电路板 - Google Patents

异步收发传输器和通用串行总线接口复用电路及电路板 Download PDF

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WO2017166672A1
WO2017166672A1 PCT/CN2016/097223 CN2016097223W WO2017166672A1 WO 2017166672 A1 WO2017166672 A1 WO 2017166672A1 CN 2016097223 W CN2016097223 W CN 2016097223W WO 2017166672 A1 WO2017166672 A1 WO 2017166672A1
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signal line
data signal
circuit
electrically connected
universal serial
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PCT/CN2016/097223
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English (en)
French (fr)
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潘硕
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乐视控股（北京）有限公司
乐视致新电子科技（天津）有限公司
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Publication of WO2017166672A1 publication Critical patent/WO2017166672A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/426—Internal components of the client ; Characteristics thereof

Definitions

  • the present application relates to the field of smart television technologies, for example, to an asynchronous transceiver transmitter and a universal serial bus interface multiplexing circuit and circuit board, and an electronic device.
  • USB Universal Serial Bus
  • UART is widely used in short-distance transmission interface, which adopts full-duplex mode and has low power consumption; USB supports medium-speed serial transmission speed, and each USB interface can connect up to 127 USB devices. With a large data transfer speed, you can establish a connection between the host and the MODEM, scanner, digital camera, USB keyboard, mouse and display.
  • a Universal Asynchronous Receiver/Transmitter (UART) interface or a Universal Serial Bus (USB) interface is generally used to implement information transmission between other devices and a smart TV, such as a command or The transmission of data.
  • UART Universal Asynchronous Receiver/Transmitter
  • USB Universal Serial Bus
  • smart TVs are developing in the direction of light, thin, miniaturized and multi-functional, and more and more stringent requirements are imposed on the number and design of their external interfaces.
  • the applicant found out how to implement many functions on a port with fewer pins, that is, the interface is properly reused, which is one of the factors that can not be ignored in product planning and product design of smart TV.
  • a common practice is to use a resistor to jumper and switch. The method is cumbersome to operate, requires multiple soldering of the PCB board, and the process is complicated, and it is easy to generate a high failure rate in mass production.
  • the embodiments of the present application provide an asynchronous transceiver transmitter, a universal serial bus interface multiplexing circuit and a circuit board, and an electronic device, which solves the technical problem of USB/UART interface multiplexing.
  • the embodiment of the present application provides an asynchronous transceiver transmitter and a universal serial bus interface multiplexing circuit, including:
  • the first end of the switch circuit is electrically connected to an external input data signal line, and the second end of the switch circuit is electrically connected to a data signal line of the asynchronous transceiver, or is connected to a data signal line of the universal serial bus. connection;
  • the first input end of the logic determining circuit is electrically connected to the power line
  • the second input end is electrically connected to the identification signal line
  • the output end of the logic determining circuit is electrically connected to the switch circuit for being used according to the power line
  • transmitting by the voltage value on the identification signal line, a control signal to the switch circuit to control a data signal line of the asynchronous transceiver to be electrically connected to the external input data signal line, or the universal serial
  • the data signal line of the bus is electrically connected to the external input data signal line.
  • the logic determining circuit is configured to send a first control signal to the switch circuit when the high voltage is output on the power line, so that the data signal line of the universal serial bus and the external input are The data signal line is turned on.
  • the logic determining circuit is configured to send a first control signal to the switch circuit when the low voltage is output on the identification signal line, so that the data signal line of the universal serial bus and the external The input data signal line is turned on.
  • the logic determining circuit is configured to send a second control signal to the switch circuit when the low voltage is output on the power line, so that the data signal line of the asynchronous transceiver is connected to the external input The data signal line is turned on.
  • the logic determining circuit is configured to send a first control signal to the switch circuit when the high voltage is output on the identification signal line, so that the data signal line of the asynchronous transceiver is connected to the external The input data signal line is turned on.
  • the high voltage is +5V
  • the low voltage is 0V
  • the switch circuit includes a first switch and a second switch
  • the external input data signal line includes a first external input data signal line and a second external input data signal line
  • the data signal of the asynchronous transceiver The line includes a receiving data signal line and a transmitting data signal line
  • the data signal line of the universal serial bus includes a first data signal line and a second data signal line;
  • the first end of the first switch is electrically connected to the first external input data signal line, and the second end of the first switch is electrically connected to the receiving data signal line or the first data signal line ;
  • the first end of the second switch is electrically connected to the second external input data signal line
  • the second The second end of the switch is electrically connected to the transmit data signal line or the second data signal line.
  • the embodiment of the present application further provides a circuit board, comprising: the asynchronous transceiver transmitter and the universal serial bus interface multiplexing circuit according to any one of the foregoing.
  • an embodiment of the present application further provides an electronic device, where the electronic device includes the foregoing circuit board.
  • the above electronic device may be a smart TV.
  • the switching circuit sends a control signal to control the data signal line of the asynchronous transceiver to be electrically connected to the external input data signal line, or the data signal line of the universal serial bus and the external input data signal line
  • FIG. 1 is a schematic diagram of a USB interface arrangement in the related art
  • FIG. 2 is a schematic diagram of a UART interface arrangement in the related art
  • FIG. 3 is a schematic structural diagram of an asynchronous transceiver and a universal serial bus interface multiplexing circuit according to Embodiment 1 of the present application;
  • FIG. 4 is a schematic structural diagram of an asynchronous transceiver and a universal serial bus interface multiplexing circuit according to Embodiment 2 of the present application.
  • switch circuit 11, switch circuit; 12, external input data signal line; 13, asynchronous transceiver transmitter;
  • the USB interface includes five signal lines: wherein D+ and D- are data signal lines D+ and D-; and VCC is a power line (VCC). GND is the ground line (GND) and the ID line is the identification signal line. When the USB interface is working normally, VCC is +5V and the ID line is left floating.
  • VCC is +5V and the ID line is left floating.
  • the UART interface includes five signal lines: VCC is the power line, GND is the ground line (GND), and the ID line is the identification signal line, RX is the receiving data line, and TX is the transmitting data line.
  • both the USB interface and the UART interface have a power line, a ground line, and an ID line and two data lines, except that the USB interface includes a D+ line and a D- line, and the UART interface includes a TX line and an RX line.
  • FIG. 3 is a schematic structural diagram of an asynchronous transceiver and a universal serial bus interface multiplexing circuit according to Embodiment 1 of the present application.
  • the asynchronous transceiver and the universal serial bus interface multiplexing circuit including:
  • a switching circuit 11 the first end of the switching circuit 11 is electrically connected to an external input data signal line 12, and the second end of the switching circuit 11 is electrically connected to a data signal line of the asynchronous transceiver 13 or The data signal lines of the serial bus 14 are electrically connected;
  • the first input end of the logic judging circuit 15 is electrically connected to the power line VCC, the second input end is electrically connected to the identification signal line ID, and the output end of the logic judging circuit is electrically connected to the switch circuit for a line and a voltage value on the identification signal line, and transmitting a control signal to the switch circuit to control a data signal line of the asynchronous transceiver 13 to be electrically connected to the external input data signal line 12, or
  • the data signal line of the universal serial bus 14 is electrically connected to the external input data signal line 12.
  • the logic judging circuit 15 in the embodiment of the present application can be implemented by a circuit or by a combination of a circuit and a software.
  • the logic judging circuit has two input terminals, one of which is electrically connected to the power line of the interface, and the other of which is electrically connected to the signal line.
  • the logic judging circuit 12 further has an output terminal connected to the switch circuit 11 for transmitting a control signal to the switch circuit 11 so that the switch circuit 11 controls the external selection input data signal line according to the input control signal.
  • a data signal line of the transceiving transmitter 13 or a data signal of the universal serial bus 14 The line is turned on.
  • the switch circuit 11 has two input terminals, wherein the input control terminal is connected to the logic judging circuit 15 for receiving the control signal of the logic judging circuit 15.
  • the external input data signal line 12 includes a first external input data signal line and a second external input data signal line. That is, the first end of the switch circuit 11 can be divided into D+ and D- lines that connect external devices.
  • the switch circuit 11 also has an output end, that is, the second end of the switch circuit 11, the second end of the switch circuit 11 is electrically connected to the data signal line of the asynchronous transceiver 13 or the universal serial bus 14
  • the data signal lines are electrically connected.
  • the second end of the switch circuit 11 can be connected to the data signal line of the asynchronous transceiver 13 or the data signal line of the universal serial bus 14 at different times, but cannot be simultaneously connected at the same time.
  • the switching circuit 11 selects the signal line that is turned on based on the control signal transmitted from the logic judging circuit 15.
  • a first control signal is sent to the switch circuit 11 to turn on the data signal line of the universal serial bus 14 and the external input data signal line 12.
  • a second control signal is sent to the switch circuit 11 to turn on the data signal line of the asynchronous transceiver 13 and the external input data signal line 12.
  • a first control signal is sent to the switch circuit 11 to turn on the data signal line of the asynchronous transceiver 13 and the external input data signal line 12.
  • a first control signal is sent to the switch circuit 11 to turn on the data signal line of the universal serial bus 14 and the external input data signal line 12.
  • the high voltage in the above embodiment of the present application is +5V, and the low voltage is 0V.
  • FIG. 4 is a schematic structural diagram of an asynchronous transceiver and a universal serial bus interface multiplexing circuit according to Embodiment 2 of the present application.
  • the second end of the switching circuit 11 is connected to the data signal line of the asynchronous transceiver 13 or to the data signal line of the universal serial bus 14.
  • the data signal line of the asynchronous transceiver 13 includes a reception data signal line and a transmission data signal line
  • the data signal line of the universal serial bus 14 includes the first data signal line and the second number. According to the signal line.
  • the above switching circuit 11 also includes a first switch 111 and a second switch 112.
  • the first end of the first switch 111 is electrically connected to the first external input data signal line, and the second end of the first switch 111 is electrically connected to the receiving data signal line or the first data signal line ;
  • the first end of the second switch 112 is electrically connected to the second external input data signal line, and the second end of the second switch 112 is electrically connected to the transmit data signal line or the second data signal line. .
  • the logic determining circuit 15 is based on the input power line VCC or the identification signal line.
  • the voltage of the ID is judged to be a USB device or a UART device.
  • one end of the external input data signal line 12 is electrically connected to the D+ signal line of the universal serial bus 14 through the switch circuit 11, and the other end of the external input data signal line 12 is connected to the universal string.
  • the D-signal line of the row bus 14 is turned on, enabling the interface circuit to transmit corresponding USB data.
  • one end of the external input data signal line 12 is connected to the TX signal line of the asynchronous transceiver transmitter 13 through the switch circuit, and the other end of the external input data signal line 12 is asynchronously transmitted and transmitted.
  • the RX signal line of the device 13 is turned on, enabling the interface circuit to transmit corresponding UART data.
  • the embodiment of the present application further provides a circuit board, which includes the asynchronous transceiver transmitter and the universal serial bus interface multiplexing circuit described in any of the above embodiments, and has the same functions as those of the foregoing embodiments, and can pass
  • the corresponding logic circuit implementation can also be realized by the corresponding chip and the corresponding connection.
  • the embodiment of the present application further provides an electronic device including the above circuit board.
  • the above electronic device may be a smart TV.
  • the embodiment of the present application achieves the purpose of receiving asynchronous transceiver or universal serial bus data by using the same interface, has a simple structure and is easy to implement, and is particularly suitable for mass production.

Abstract

一种异步收发传输器和通用串行总线接口复用电路及电路板，属于电子设备技术领域，其中，所述异步收发传输器和通用串行总线接口复用电路包括：开关电路和逻辑判断电路。通过利用电源线或标识信号线的电压高低，对异步收发传输器的数据信号线或者与所述通用串行总线的数据信号线对应的传输通道进行切换。

Description

异步收发传输器和通用串行总线接口复用电路及电路板
本申请要求在2016年3月31日提交中国专利局、申请号为2016101957404、发明名称为“一种异步收发传输器和通用串行总线接口复用电路及电路板”的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及智能电视技术领域，例如涉及一种异步收发传输器和通用串行总线接口复用电路及电路板，以及电子设备。
背景技术
随着科技的不断发展，智能电视机正在成为继计算机、手机之后的第三种信息访问终端，用户可随时访问自己需要的信息。并成为家庭娱乐中心，用户可以通过智能电视搜索电视频道、录制电视节目、能够播放卫星和有线电视节目以及网络视频。和通用串行总线(Universal Serial Bus，简称USB)。其中，UART广泛应用于短距离传输的接口，其采用全双工的方式，具有较低的功耗；USB支持中高速的串口传输速度，每个USB接口可最多连接至127个USB设备，其具有较大的数据传输速度，可以建立主机与MODEM、扫描仪、数字相机、USB键盘、鼠标和显示器等之间的连接。
相关技术中，一般单独采用异步收发传输器(Universal Asynchronous Receiver/Transmitter，UART)接口或者通用串行总线(Universal Serial Bus，USB)接口来实现其它装置与智能电视之间的信息传输，如命令或数据的传输。
目前，智能电视在向轻、薄、小型化、多功能方向发展，对其外部接口数目及设计也提出了越来越苛刻的要求。在实现本申请过程中，申请人发现如何将众多的功能在一个管脚较少的接口上实现，即接口合理复用，是智能电视在产品规划和产品设计中不可忽视的要素之一。常见的作法一种是用电阻进行跳线，进行切换。该方法操作比较麻烦，需要对PCB板进行多次焊接，工艺复杂，在大规模生产中极容易产生较高的不合格率。
发明内容
有鉴于此，本申请实施例提供一种异步收发传输器和通用串行总线接口复用电路及电路板，以及一种电子设备，解决了USB/UART接口复用的技术问题。
本申请实施例提供了一种异步收发传输器和通用串行总线接口复用电路，包括：
开关电路和逻辑判断电路；
所述开关电路的第一端与外部输入数据信号线电连接，所述开关电路的第二端与异步收发传输器的数据信号线电连接，或者与所述通用串行总线的数据信号线电连接；
所述逻辑判断电路的第一输入端与电源线电连接，第二输入端与标识信号线电连接，所述逻辑判断电路的输出端与所述开关电路电连接，用于根据所述电源线和所述标识信号线上的电压值，向所述开关电路发送控制信号，以控制所述异步收发传输器的数据信号线与所述外部输入数据信号线导通，或者，所述通用串行总线的数据信号线与所述外部输入数据信号线导通。
可选的，所述逻辑判断电路用于在所述电源线上输出高电压时，向所述开关电路发出第一控制信号，以使所述通用串行总线的数据信号线与所述外部输入数据信号线导通。
可选的，所述逻辑判断电路用于在所述标识信号线上输出低电压时，向所述开关电路发出第一控制信号，以使所述通用串行总线的数据信号线与所述外部输入数据信号线导通。
可选的，所述逻辑判断电路用于在所述电源线上输出低电压时，向所述开关电路发出第二控制信号，以使所述异步收发传输器的数据信号线与所述外部输入数据信号线导通。
可选的，所述逻辑判断电路用于在所述标识信号线上输出高电压时，向所述开关电路发出第一控制信号，以使所述异步收发传输器的数据信号线与所述外部输入数据信号线导通。
可选的，所述高电压为+5V，所述低电压为0V。
可选的，所述开关电路包括第一开关和第二开关，所述外部输入数据信号线包括第一外部输入数据信号线和第二外部输入数据信号线，所述异步收发传输器的数据信号线包括接收数据信号线和发送数据信号线，所述通用串行总线的数据信号线包括第一数据信号线和第二数据信号线；
所述第一开关的第一端与所述第一外部输入数据信号线电连接，所述第一开关的第二端，与所述接收数据信号线，或者所述第一数据信号线电连接；
所述第二开关的第一端与所述第二外部输入数据信号线电连接，所述第二 开关的第二端，与所述发送数据信号线，或者所述第二数据信号线电连接。
第二方面，本申请实施例还提供了一种电路板，包括：上述提供的任一所述的异步收发传输器和通用串行总线接口复用电路。
第三方面，本申请实施例还提供了一种电子设备，所述电子设备包括上述的电路板。
上述的电子设备可以是智能电视。
本申请实施例提供的异步收发传输器和通用串行总线接口复用电路及电路板，以及电子设备，通过利用逻辑判断电路根据所述电源线和所述标识信号线上的电压值，向所述开关电路发送控制信号，以控制所述异步收发传输器的数据信号线与所述外部输入数据信号线导通，或者，所述通用串行总线的数据信号线与所述外部输入数据信号线导通，实现了使用同一个接口可以接收异步收发传输器或通用串行总线数据的目的，结构简单，易于实现，特别适合大规模生产。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1是相关技术中USB接口布置示意图；
图2是相关技术中UART接口布置示意图；
图3是本申请实施例一提供的异步收发传输器和通用串行总线接口复用电路的结构示意图；
图4是本申请实施例二提供的异步收发传输器和通用串行总线接口复用电路的结构示意图。
图中的附图标记所分别指代的技术特征为：
11、开关电路；12、外部输入数据信号线；13、异步收发传输器；
14、通用串行总线；15、逻辑判断电路；111、第一开关；
112、第二开关。
实施方式
下面结合附图和实施例对本申请作详细说明。可以理解的是，此处所描述 的实施例仅仅用于解释本申请，而非对本申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本申请相关的部分而非全部内容。
实施例一
图1是相关技术中USB接口布置示意图，由图1可以看出，USB接口包括5条信号线：其中，其中D+、D-为数据信号线D+、D-；VCC为电源线(VCC)，GND为接地线(GND)、ID线为标识信号线，。在USB接口正常工作时，VCC为+5V，而ID线悬空。图2是相关技术中UART接口布置示意图。由图2可以看出，UART接口包括5条信号线：VCC为电源线，GND为接地线(GND)、ID线为标识信号线，，RX为接收数据线，TX为发送数据线。在UART接口正常工作时，VCC为悬空，而ID线为+5V。即USB接口和UART接口都具有电源线、接地线和ID线和两条数据线，区别在于USB接口包括D+线和D-线，而UART接口包括TX线和RX线。
图3是本申请实施例一提供的异步收发传输器和通用串行总线接口复用电路的结构示意图。所述异步收发传输器和通用串行总线接口复用电路，其中，包括：
开关电路11，所述开关电路11的第一端与外部输入数据信号线12电连接，所述开关电路11的第二端与异步收发传输器13的数据信号线电连接，或者与所述通用串行总线14的数据信号线电连接；
逻辑判断电路15的第一输入端与电源线VCC电连接，第二输入端与标识信号线ID电连接，所述逻辑判断电路的输出端与所述开关电路电连接，用于根据所述电源线和所述标识信号线上的电压值，向所述开关电路发送控制信号，以控制所述异步收发传输器13的数据信号线与所述外部输入数据信号线12导通，或者，所述通用串行总线14的数据信号线与所述外部输入数据信号线12导通。
本申请实施例中的逻辑判断电路15可以通过电路，或者是通过电路和软件结合的方式实现。
由图3可以看出，在本实施例中，逻辑判断电路有两个输入端，其中一个端口与接口的电源线电连接，另外一个输入端标识信号线电连接。此外，逻辑判断电路12还有一个输出端，该输出端与开关电路11连接，用于向开关电路11发送控制信号，以使得所述开关电路11根据输入的控制信号控制外部选择输入数据信号线与步收发传输器13的数据信号线或者通用串行总线14的数据信 号线导通。
相应的，开关电路11有两个输入端，其中，输入控制端与逻辑判断电路15相连接，用于接收逻辑判断电路15的控制信号。可选的，由于USB和UART端口相应的都有两条数据线。外部输入数据信号线12包括第一外部输入数据信号线和第二外部输入数据信号线。即开关电路11的第一端可以分为连接外部设备的D+和D-线。
此外，开关电路11对应也有一个输出端，即开关电路11的第二端，开关电路11的第二端与异步收发传输器13的数据信号线电连接，或者与所述通用串行总线14的数据信号线电连接。开关电路11的第二端可以与异步收发传输器13的数据信号线或者通用串行总线14的数据信号线可以在不同时间分别连接，但不可在同一时间同时连接。开关电路11根据逻辑判断电路15发送的控制信号选择接通的信号线。
由相关技术可知，在USB接口正常工作时，电源VCC线为+5V，而标识信号ID线悬空，为0V；而在UART接口正常工作时，VCC悬空，为0V；而ID线为+5V。由上述可以得出，对于逻辑判断电路，则存在以下几种工作情况：
在所述标识信号线上输出低电压时，向所述开关电路11发出第一控制信号，以使所述通用串行总线14的数据信号线与所述外部输入数据信号线12导通。
在所述电源线上输出低电压时，向所述开关电路11发出第二控制信号，以使所述异步收发传输器13的数据信号线与所述外部输入数据信号线12导通。
在所述标识信号线上输出高电压时，向所述开关电路11发出第一控制信号，以使所述异步收发传输器13的数据信号线与所述外部输入数据信号线12导通。
在所述电源线上输出高电压时，向所述开关电路11发出第一控制信号，以使所述通用串行总线14的数据信号线与所述外部输入数据信号线12导通。
可选的，本申请上述实施例中的高电压是为+5V，低电压为0V。
实施例二
图4是本申请实施例二提供的异步收发传输器和通用串行总线接口复用电路的结构示意图。从图4可以看出，开关电路11的第二端与异步收发传输器13的数据信号线连接，或者与通用串行总线14的数据信号线连接。根据UART和USB的接口规范，异步收发传输器13的数据信号线包括接收数据信号线和发送数据信号线，所述通用串行总线14的数据信号线包括第一数据信号线和第二数 据信号线。
相对应的，为了使异步收发传输器13和通用串行总线14接口复用电路能够正常工作，上述开关电路11也包括第一开关111和第二开关112。
第一开关111的第一端与所述第一外部输入数据信号线电连接，所述第一开关111的第二端，与所述接收数据信号线，或者所述第一数据信号线电连接；
第二开关112的第一端与所述第二外部输入数据信号线电连接，所述第二开关112的第二端，与所述发送数据信号线，或者所述第二数据信号线电连接。
下面结合本申请的工作过程对本申请做描述，在外部设备通过接口与异步收发传输器13和通用串行总线14接口复用电路连接时，逻辑判断电路15根据输入的电源线VCC或者标识信号线ID的电压判断是USB设备或者UART设备。在判断所述设备为USB设备时，通过开关电路11，将外部输入数据信号线12的一端与通用串行总线14的D+信号线导通，将外部输入数据信号线12的另一端与通用串行总线14的D-信号线导通，使所述接口电路能够传输相应的USB数据。
在判断所述设备为UART设备时，通过开关电路，将外部输入数据信号线12的一端与异步收发传输器13的TX信号线导通，将外部输入数据信号线12的另一端与异步收发传输器13的RX信号线导通，使所述接口电路能够传输相应的UART数据。
此外，本申请实施例还提供了一种电路板，该电路板包括上述任一实施例所描述的异步收发传输器和通用串行总线接口复用电路，具有上述实施例相同的功能，可以通过相应的逻辑电路实现，也可通过相应的芯片和对应的连线实现。
本申请实施例还提供了一种电子设备，该电子设备包括上述的电路板。可选的，上述的电子设备可以是智能电视。
注意，上述仅为本申请的可选实施例及所运用技术原理。在不冲突的情况下，以上实施例中的特征可以任意组合。本领域技术人员会理解，本申请不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本申请的保护范围。因此，虽然通过以上实施例对本申请进行了较为详细的说明，但是本申请不仅仅限于以上实施例，在不脱离本申请构思的情况下，还可以包括更多其他等效实施例，而本申请的范围由所附的权利要求范围决定。
工业实用性
本申请实施例实现了使用同一个接口可以接收异步收发传输器或通用串行总线数据的目的，结构简单，易于实现，特别适合大规模生产。

Claims (10)

  1. 一种异步收发传输器和通用串行总线接口复用电路，包括：
    开关电路和逻辑判断电路；
    其中，所述开关电路的第一端与外部输入数据信号线电连接，所述开关电路的第二端与异步收发传输器的数据信号线电连接，或者与所述通用串行总线的数据信号线电连接；
    所述逻辑判断电路的第一输入端与电源线电连接，第二输入端与标识信号线电连接，所述逻辑判断电路的输出端与所述开关电路电连接，用于根据所述电源线和所述标识信号线上的电压值，向所述开关电路发送控制信号，以控制所述异步收发传输器的数据信号线与所述外部输入数据信号线导通，或者，所述通用串行总线的数据信号线与所述外部输入数据信号线导通。
  2. 根据权利要求1所述的电路，其中，所述逻辑判断电路用于在所述电源线上输出高电压时，向所述开关电路发出第一控制信号，以使所述通用串行总线的数据信号线与所述外部输入数据信号线导通。
  3. 根据权利要求1所述的电路，其中，所述逻辑判断电路用于在所述标识信号线上输出低电压时，向所述开关电路发出第一控制信号，以使所述通用串行总线的数据信号线与所述外部输入数据信号线导通。
  4. 根据权利要求1所述的电路，其中，所述逻辑判断电路用于在所述电源线上输出低电压时，向所述开关电路发出第二控制信号，以使所述异步收发传输器的数据信号线与所述外部输入数据信号线导通。
  5. 根据权利要求1所述的电路，其中，所述逻辑判断电路用于在所述标识信号线上输出高电压时，向所述开关电路发出第一控制信号，以使所述异步收发传输器的数据信号线与所述外部输入数据信号线导通。
  6. 根据权利要求2-5任一所述的电路，其中，所述高电压为+5V，所述低电压为0V。
  7. 根据权利要求1所述的电路，其中，所述开关电路包括第一开关和第二开关，所述外部输入数据信号线包括第一外部输入数据信号线和第二外部输入数据信号线，所述异步收发传输器的数据信号线包括接收数据信号线和发送数据信号线，所述通用串行总线的数据信号线包括第一数据信号线和第二数据信号线；
    所述第一开关的第一端与所述第一外部输入数据信号线电连接，所述第一开关的第二端，与所述接收数据信号线，或者所述第一数据信号线电连接；
    所述第二开关的第一端与所述第二外部输入数据信号线电连接，所述第二开关的第二端，与所述发送数据信号线，或者所述第二数据信号线电连接。
  8. 一种电路板，包括权利要求1-7任一所述的异步收发传输器和通用串行总线接口复用电路。
  9. 一种电子设备，包括权利要求8所述的电路板。
  10. 根据权利要求9所述的电子设备，其中，所述电子设备为智能电视。
PCT/CN2016/097223 2016-03-31 2016-08-29 异步收发传输器和通用串行总线接口复用电路及电路板 WO2017166672A1 (zh)

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