WO2022183322A1 - 接口电路、电子设备、数据传输装置和数据传输系统 - Google Patents

接口电路、电子设备、数据传输装置和数据传输系统 Download PDF

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Publication number
WO2022183322A1
WO2022183322A1 PCT/CN2021/078479 CN2021078479W WO2022183322A1 WO 2022183322 A1 WO2022183322 A1 WO 2022183322A1 CN 2021078479 W CN2021078479 W CN 2021078479W WO 2022183322 A1 WO2022183322 A1 WO 2022183322A1
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WIPO (PCT)
Prior art keywords
interface
data transmission
coupled
interface circuit
mode controller
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PCT/CN2021/078479
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English (en)
French (fr)
Inventor
钱照华
柯建东
王晶晶
沈冬冬
Original Assignee
华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2021/078479 priority Critical patent/WO2022183322A1/zh
Priority to EP21928413.0A priority patent/EP4293480A4/en
Publication of WO2022183322A1 publication Critical patent/WO2022183322A1/zh
Priority to US18/240,139 priority patent/US20230409501A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4081—Live connection to bus, e.g. hot-plugging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4045—Coupling between buses using bus bridges where the bus bridge performs an extender function
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0042—Universal serial bus [USB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/38—Universal adapter
    • G06F2213/3812—USB port controller

Definitions

  • the embodiments of the present application relate to the field of circuits, and in particular, to an interface circuit, an electronic device, a data transmission device, and a data transmission system.
  • the electronic devices are usually provided with various types of interfaces.
  • a display device uses a high-definition multimedia interface (HDMI, High Definition Multimedia Interface) for data transmission
  • another display device uses a display interface (DP, DisplayPort) for data transmission.
  • the host device usually sets up various types of interfaces such as HDMI and DP.
  • the display device also provides multiple types of interfaces in order to perform data transmission with host devices of different interface types.
  • the coexistence of multiple interfaces greatly occupies the space of the electronic device and the layout area of the interface chip, which is not conducive to the realization of high-integration and small-volume electronic devices. Therefore, how to realize that the electronic device is compatible with various types of interfaces while reducing the space of the electronic device occupied by the interface becomes a problem that needs to be solved.
  • an embodiment of the present application provides an interface circuit, the interface circuit performs data transmission with a first device through a data transmission device, the interface circuit includes an interface indicating terminal and a data transmission terminal;
  • the interface instructing terminal obtains indication information from the indicator of the data transmission device, and the indication information is used to instruct the data transmission interface protocol of the first device;
  • the interface circuit is used for passing the data transmission terminal, using the The data transmission interface protocol of the first device indicated by the indication information transmits data to the first device.
  • the interface circuit shown in the embodiment of the present application determines the protocol type of the data transmission interface in the first device based on the indication information obtained from the indicator, and then uses the interface protocol of the same type as the first device to communicate with the first device. data transmission. Therefore, the interface circuit provided in the embodiments of the present application can multiplex one physical interface to implement multiple transmission interface protocols, and further implement data transmission with electronic devices of multiple different interface types. Compared with multiple types of interfaces provided in traditional electronic devices, the layout area of the electronic device occupied by the interfaces is reduced, thereby facilitating the realization of high-integration and small-volume electronic devices.
  • the interface circuit includes multiple interface controllers, multiplexers, port physical layers and mode controllers; each interface controller in the multiple interface controllers is respectively coupled to the multiplexer a plurality of input terminals of the multiplexer; the output terminal of the multiplexer is coupled to the first terminal of the port physical layer; the second terminal of the port physical layer is coupled to the data transmission terminal of the interface circuit; the mode control The input end of the controller is coupled to the interface indicating end of the interface circuit, the output end of the mode controller is coupled to the first control end of the multiplexer, and the mode controller controls the The multiplexer connects a first interface controller of the plurality of interface controllers with the port physical layer.
  • the output end of the mode controller is also coupled to the second control end of the port physical layer; the mode controller is further configured to: based on the indication information, adjust the transmitter and the port physical layer in the port physical layer. At least one of the following parameters in the receiver: the signal transmission rate or the amplitude of the transmitted signal.
  • mode 1 multiple interface controllers share the same interface physical layer. Based on the indication information provided by the indicator, the mode controller controls the multiplexer to select one of the multiple interface controllers to implement the same type of interface protocol as the first device.
  • the layout area of the electronic device occupied by the interface physical layer can be reduced, thereby facilitating the realization of high-integration and small-volume electronic devices.
  • the interface circuit includes multiple interface controllers, multiple port physical layers, switch groups and mode controllers; the multiple interface controllers are coupled to the first ends of the multiple port physical layers in a one-to-one correspondence ;
  • the second end of the physical layer of the plurality of ports is coupled to the data transmission end of the interface circuit through the one-to-one corresponding plurality of switches in the switch group;
  • the input end of the mode controller is coupled to the interface indication terminal, the output terminal of the mode controller is coupled to the control terminal of the switch group, and the mode controller is configured to control any switch in the switch group to turn on based on the indication information.
  • multiple interface controllers are connected to multiple port physical layers in one-to-one correspondence.
  • multiple interface controllers include HDMI controller, DP controller and USB interface controller
  • multiple port physical layers include HDMI port physical layer, DP port physical layer and USB port physical layer, HDMI controller and HDMI port physical layer
  • the first end of the DP controller is coupled to the first end of the DP port physical layer
  • the USB interface controller is coupled to the first end of the USB port physical layer.
  • the switch group includes a plurality of switches, the second end of the physical layer of each port is coupled to the data transmission end of the interface circuit through one of the switches, and the switches coupled to the physical layer of each port are different.
  • the mode controller controls any one of the switches in the switch group to be turned on, so as to connect the physical layer of one of the ports with the data transmission end of the interface circuit.
  • controlling any switch in the switch group to be turned on as described in the embodiments of the present application means that the switch is in an on state, and the other switches are in an off state.
  • controlling any switch in the switch group to turn on means turning on one of the switches and keeping the rest of the switches in the off state; for another example, when the switch group is in the off state
  • controlling any switch in the switch group to be turned on means keeping one of the switches in the on state and turning off the rest of the switches.
  • the mode controller described in the embodiments of the present application may be implemented in various manners.
  • the mode controller includes a comparator and a first resistor; a first input terminal of the comparator is coupled to a ground terminal, and a second input terminal of the comparator is coupled to the mode control terminal the input terminal of the comparator, the output terminal of the comparator is coupled to the output terminal of the mode controller; one end of the first resistor is coupled to the power supply terminal, and the other end of the first resistor is coupled to the comparator second input.
  • the mode controller includes a comparator and a current source; a first input terminal of the comparator is coupled to a ground terminal, and a second input terminal of the comparator is coupled to the mode
  • the input end of the controller, the output end of the comparator is coupled to the output end of the mode controller; one end of the current source is coupled to the power supply end, and the other end of the current source is coupled to the first end of the comparator Two input terminals.
  • the indication information is an analog signal
  • the mode controller includes an analog-to-digital converter and a first resistor; one end of the first resistor is coupled to a power supply end, and the first resistor The other end of the analog-to-digital converter is coupled to the input of the analog-to-digital converter; the first input of the analog-to-digital converter is coupled to the ground, and the second input of the analog-to-digital converter is coupled to the mode controller.
  • the analog-to-digital converter generates a digital signal based on the indication information and provides the digital signal to the output terminal of the mode controller.
  • the indication information is an analog signal
  • the mode controller includes an analog-to-digital converter and a current source; one end of the current source is coupled to a power supply end, and the other end of the current source is coupled to a power supply end coupled to an input of the analog-to-digital converter; a first input of the analog-to-digital converter is coupled to ground, a second input of the analog-to-digital converter is coupled to an input of the mode controller, The analog-to-digital converter generates a digital signal based on the indication information and provides the digital signal to the output terminal of the mode controller.
  • the indication information is a digital signal
  • the mode controller includes a reader; the reader is configured to read the indication information, and generate a control signal based on the indication information to provide to the input of the mode controller.
  • the port physical layer includes a transmitter, and the transmitter is configured to transmit data to the first device through the data transmission apparatus; and the interface
  • the circuit also includes a capacitor, a second resistor and a first switch; a first end of the capacitor is coupled to the output end of the transmitter, and a second end of the capacitor and one end of the second resistor are coupled to the interface the data transmission end of the circuit; the other end of the second resistor is coupled to the ground end through the first switch.
  • the number of capacitors, the number of second resistors and the number of first switches are the same as the number of transmitters.
  • the capacitor, the second resistor and the first switch in the embodiment of the present application, when the interface circuit is used as the data transmitting end, it can not only satisfy the regulations on the DC signal coupling mode in the interface protocol, but also meet the AC signal coupling mode in the interface protocol. Provisions.
  • the first switch when the first device uses an AC-coupling interface supported by the interface protocol (such as a DP, USB3 interface, USB4 interface or a new interface) for data transmission, the first switch can be turned off; The first switch may be closed when data transmission is performed on the supported DC-coupled interface (for example, HDMI or a new interface).
  • the port physical layer further includes a receiver, where the receiver is configured to receive data from the first device through the data transmission apparatus; and the The interface circuit further includes a third resistor, a second switch, a fourth resistor and a third switch; the first end of the third resistor is coupled to the power supply end through the second switch; the second end of the third resistor, The first end of the fourth resistor and the receiving end of the receiver are both coupled to the data transmission end of the interface circuit; the second end of the fourth resistor is coupled to the common ground through the third switch.
  • the number of third resistors, the number of second switches, the number of fourth resistors and the number of third switches are the same as the number of receivers.
  • the interface circuit can be used as a data receiving end to satisfy not only the provisions on the DC signal coupling mode in the interface protocol, but also the interface protocol.
  • Regulations on the AC signal coupling method in For example, when the first device uses an AC-coupling interface (such as DP, USB3 interface, USB4 interface or a new interface) supported by the interface protocol for data transmission, the second switch can be turned off and the third switch can be turned on; When a device uses a DC-coupled interface supported by the interface protocol (such as HDMI or a new interface) for data transmission, the second switch can be turned on and the third switch can be turned off.
  • the port physical layer includes at least one transmitter and at least one receiver; the first transmitter of the at least one transmitter and the at least one transmitter A first of the receivers is coupled to the same cable in the data transmission device.
  • an embodiment of the present application provides an electronic device, the electronic device includes a physical interface and the interface circuit according to the first aspect; the interface circuit communicates with the data transmission end in the data transmission device through the physical interface and Indicator coupling.
  • the interface includes a first connection end and a second connection end; a data transmission end of the interface circuit is coupled to the first connection end; an interface indication end of the interface circuit is coupled to the second connection end.
  • an embodiment of the present application provides a data transmission device, the data transmission device is coupled between a first device and a second device, and is used for data transmission between the first device and the second device, the data transmission device is
  • the data transmission apparatus includes: an indicator, coupled to an interface circuit in the first device, for providing indication information to the interface circuit, where the indication information is used to indicate a data transmission interface protocol of the second device.
  • the data transmission apparatus further includes: a plurality of cables for coupling the first device and the second device, so that the first device and the second device for data transmission through the plurality of cables.
  • the data transmission apparatus further includes a first adapter for coupling with the first device and a second adapter for coupling with the second device; the first adapter including a first data transmission end and an interface indication end, the first end of each cable in the plurality of cables is coupled to the first data transmission end, and the adapter is coupled to the interface indication end;
  • the second adapter includes a second data transmission end, and the second end of each of the plurality of cables is coupled to the second data transmission end.
  • the indication information is an analog signal
  • the indicator includes a fifth resistor, one end of the fifth resistor is coupled to the interface indication end of the first adapter, and the fifth resistor has an end. The other end is coupled to ground.
  • the indication information is a digital signal
  • the indicator includes a register; the register is used to store data, and the data is used to indicate the protocol type of the data transmission interface in the second device.
  • an embodiment of the present application provides a data transmission system, where the data transmission system includes the electronic device described in the second aspect and the data transmission device described in the third aspect.
  • an embodiment of the present application provides a data transmission method, the data transmission method is applied to an interface circuit, the interface circuit performs data transmission with a first device through a data transmission device, and the interface circuit includes an interface indicating terminal and a first device. a data transmission end, the method comprising: the interface circuit obtains indication information from an indicator of the data transmission device through the interface indication end, where the indication information is used to indicate a data transmission interface protocol of the first device; The interface circuit transmits data to the first device through the data transmission end using the data transmission interface protocol of the first device indicated by the indication information.
  • the interface circuit includes multiple interface controllers, multiplexers, port physical layers and mode controllers; and the interface circuit passes through the data transmission end,
  • Using the data transmission interface protocol of the first device indicated by the indication information to transmit data to the first device includes: the mode controller obtains from the indicator of the data transmission device through the interface indication terminal indication information, and based on the indication information, the multiplexer is controlled to communicate the first interface controller of the plurality of interface controllers with the port physical layer, wherein the first interface controller is connected to the port physical layer.
  • the first device has the same data transmission interface protocol; the interface controller controls the port physical layer to adopt the data transmission protocol, and transmits data to the first device through the data transmission end.
  • the method further includes: the mode controller, based on the indication information, adjusts at least one of the following parameters in the transmitter and the receiver in the physical layer of the port : The signal transmission rate or the amplitude of the transmitted signal.
  • the interface circuit includes multiple interface controllers, multiple port physical layers, switch groups and mode controllers, the multiple interface controllers, the multiple The physical layer of the port is coupled to the switches in the switch group in a one-to-one correspondence; and the interface circuit uses the data transmission interface protocol of the first device indicated by the indication information to transmit to the data transmission terminal through the data transmission end.
  • the first device transmits data, including: the mode controller obtains indication information from the indicator of the data transmission device through the interface indication terminal, and based on the indication information, controls the first switch in the switch group to conduct the switch.
  • the first interface controller corresponding to the first switch among the plurality of interface controllers controls the first interface controller in the physical layer of the plurality of ports, which is coupled to the first interface controller and the first switch.
  • a port physical layer using the data transmission protocol, transmits data to the first device through the data transmission end.
  • the indicator is a resistor
  • the indication information is an analog signal
  • the indicator is a register
  • the indication information is a digital signal
  • the method before the interface circuit transmits data to the first device, the method further includes: the interface circuit adopts a DC coupling manner or an AC coupling manner to communicate with the first device.
  • a device establishes a connection.
  • FIG. 1 is a schematic diagram of a system architecture provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of an interface circuit provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of an interface chip provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a mode controller provided by an embodiment of the present application.
  • FIG. 5 is another schematic structural diagram of a mode controller provided by an embodiment of the present application.
  • FIG. 6 is another schematic structural diagram of a mode controller provided by an embodiment of the present application.
  • FIG. 7 is another schematic structural diagram of a mode controller provided by an embodiment of the present application.
  • FIG. 8 is another schematic structural diagram of a mode controller provided by an embodiment of the present application.
  • FIG. 9 is another schematic structural diagram of an interface circuit provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a switch group in the interface circuit shown in FIG. 9 provided by an embodiment of the present application;
  • FIG. 11 is another schematic structural diagram of the switch group in the interface circuit shown in FIG. 9 provided by an embodiment of the present application.
  • FIG. 12 is a schematic diagram of a peripheral circuit of an interface circuit when an interface provided by an embodiment of the present application is used as a signal transmission interface;
  • FIG. 13 is a schematic diagram of an equivalent circuit when an interface provided by an embodiment of the present application is used as a signal transmission interface
  • FIG. 14 is another schematic diagram of an equivalent circuit when the interface provided by the embodiment of the present application is used as a signal transmission interface
  • 15 is a schematic diagram of a peripheral circuit of an interface circuit when an interface provided by an embodiment of the present application is used as a signal receiving interface;
  • 16 is a schematic diagram of an equivalent circuit when an interface provided by an embodiment of the present application is used as a signal receiving interface
  • 17 is another schematic diagram of an equivalent circuit when an interface provided by an embodiment of the present application is used as a signal receiving interface
  • 18a is another schematic diagram of a peripheral circuit of the interface circuit provided by the embodiment of the present application.
  • 18b is another schematic diagram of a peripheral circuit of the interface circuit provided by the embodiment of the present application.
  • FIG. 19 is another schematic diagram of the system architecture of the device 101 provided by the embodiment of the present application.
  • FIG. 20 is a flowchart of a data transmission method provided by an embodiment of the present application.
  • references herein to "first,” “second,” and similar terms do not denote any order, quantity, or importance, but are merely used to distinguish the various components. Likewise, words such as “a” or “an” do not denote a quantitative limitation, but rather denote the presence of at least one. Similar words “connected” or “connected” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect, equivalent to coupling or communicating in a broad sense.
  • words such as “exemplary” or “for example” are used to represent examples, illustrations or illustrations. Any embodiments or designs described in the embodiments of the present application as “exemplary” or “such as” should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as “exemplary” or “such as” is intended to present the related concepts in a specific manner.
  • the meaning of "plurality" refers to two or more. For example, multiple interface controllers refer to two or more interface controllers; multiple transmitters refer to two or more transmitters.
  • the interface described in the embodiment of the present application may be a physical interface, and the physical interface refers to a connector connected to an external device such as a transmission line or an adapter; the interface circuit described in the embodiment of the present application may include a circuit board or a chip .
  • the interface circuit is coupled to the interface and realizes data transmission with the external device through the interface.
  • FIG. 1 is a schematic diagram of a system architecture provided by an embodiment of the present application.
  • device 101 and device 102 are included.
  • the device 101 and the device 102 may include, but are not limited to, various electronic devices such as a host computer, a monitor, a television, a set-top box, an integrated computer (such as a notebook computer or an integrated desktop computer), a game console, a USB flash drive or a mobile hard disk.
  • the host here may be a device that integrates devices such as a processor and a memory but does not have a display function, which can drive the display to run.
  • the device 101 is provided with an interface A11, and the device 102 is provided with an interface A21, and the device 101 and the device 102 can communicate through the interface for data exchange.
  • the device 101 and the device 102 are different types of devices.
  • the device 101 is a host, and the device 102 is a display; for another example, the device 101 is a set-top box, and the device 102 is one of a television, a display, or an all-in-one computer.
  • the interface A21 of the device 102 may be a traditional interface.
  • the traditional interface includes but is not limited to one of the following: High Definition Multimedia Interface (HDMI, High Definition Multimedia Interface), Display Interface (DP, DisplayPort) or Universal Serial Bus (Universal Serial Bus, USB) interface.
  • the interface A21 of the device 102 may also be a newly specified interface. This type of interface is simply referred to as a new interface in this embodiment of the present application, and the new interface can communicate based on an interface protocol specified by the new interface.
  • the device 101 may configure the interface A11 as the interface matching the device 102 based on the type of the interface A21 of the device 102 .
  • such an interface that can match multiple protocol types is referred to as a multi-protocol interface.
  • the matching here can be understood as: using the same interface protocol as the interface A21 of the device 102 to communicate with the device 102 .
  • the device 101 and the device 102 can communicate based on the protocol specified by the new interface; when the interface A21 of the device 102 is HDMI, the device 101 can be based on the HDMI interface protocol.
  • the interface A11 communicates with the device 102; when the interface A21 of the device 102 is DP, the device 101 can communicate with the device 102 through the interface A11 based on the interface protocol of the DP.
  • the device 101 may be provided with an interface circuit 10, and the interface circuit 10 is coupled to the interface A11.
  • the interface circuit 10 can be implemented by software, hardware or a combination of the two.
  • the interface circuit 10 may include a controller, a programmable logic device (PLC, Programmable Logic Controller), a transistor device, or a discrete hardware component or the like.
  • the interface circuit 10 may be provided with various types of interface controllers such as HDMI, DP, USB interface or new interface.
  • the interface circuit 10 in the device 101 enables one of the interface controllers based on the interface type of the device 102, thereby Make the interface A11 match the interface A21.
  • the interface circuit 10 By setting the interface circuit 10 in the device 101 shown in the embodiment of the present application, it is realized that the same interface can perform data transmission with electronic devices of various interface types. Compared with multiple types of interfaces provided in traditional electronic devices, the layout area of the electronic device occupied by the interfaces is reduced, thereby facilitating the realization of high-integration and small-volume electronic devices.
  • the interface circuit 10 refer to the related description of the embodiments shown in FIG. 2-FIG. 18b below.
  • a data transmission device is also included, and the data transmission device may include, but is not limited to, a transmission line or an adapter.
  • the interface A11 of the device 101 and the interface A21 of the device 102 are connected through a data transmission device.
  • the difference between an adapter and a transmission line is that a cable for data transmission is provided in the transmission line, and no cable is provided in the adapter, and the other structures of the adapter and the transmission line are the same.
  • the data transmission device is taken as the transmission line 103 as an example for description.
  • FIG. 1 schematically shows a situation in which a device 101 and a device 102 are connected through a transmission line 103 .
  • the type of the adapter in the transmission line or the adapter described in the embodiments of the present application generally needs to match the type of the interface of the device to which the transmission line or the adapter is connected. Matching here means that one end of the adapter can be inserted into the device 101 .
  • the transmission line 103 shown in FIG. 1 the transmission line 103 includes an adapter C11 and an adapter C21.
  • the adapter C11 is used for connecting with the interface A11, which can be matched with the interface A11
  • the adapter C21 is used for connecting with the interface A21, which can be matched with the interface A21.
  • the connection between the transmission line 103 and the device 101 and the device 102 is described in more detail. Since the interface A11 of the device 101 is a multi-protocol interface, the physical appearance of the multi-protocol interface may be different from that of any conventional protocol interface. Therefore, the physical appearance of the adapter used to connect to the interface A11 in the transmission line 103 is different from the physical appearance of the adapter.
  • the adapter used for connecting with the interface A21 in the transmission line 103 needs to be designed to have a physical appearance of the HDMI type to be inserted into the device 102 to realize the connection with the interface A21. connect.
  • the device 101 can perform data transmission with the device 102 through the transmission line 103 .
  • the transmission line 103 described in the embodiments of the present application may be provided with a plurality of cables C for data transmission.
  • the number of cables C used for data transmission may be set based on the traditional interface transmission line protocol. For example, 4 cables are set based on the traditional interface transmission line protocol for 4-channel data transmission, or 8 cables are set based on the traditional interface transmission line protocol for 8-channel data transmission.
  • FIG. 1 schematically shows a case where four cables C are provided on the transmission line 103 .
  • an indicator Z is also provided, and the indicator Z is used to indicate the interface connected to the multi-protocol interface in the device 102 type.
  • the adapter C11 connected to the multi-protocol interface may include a data transmission end C111 and an interface indicating end C112, the data transmitting end C111 is coupled to one end of the cable C, and the interface indicating end C112 is connected to the indicator Z coupling;
  • the adapter C21 connected with the conventional interface may include a data transmission end C211 which is coupled with the other end of the cable C.
  • the cable C is coupled to the interface A11 through the data transmission end C111, and is coupled to the interface A21 through the data transmission end C211 to realize data transmission between the device 101 and the device 102.
  • the indicator Z is coupled to the interface circuit 10 in the device 101 through the interface indicating terminal C112 and the interface A11.
  • the interface circuit 10 can determine the interface type of the device 102 based on the signal output by the indicator Z to communicate with the device 102 using the same interface protocol as the device 102 .
  • the interface A11 shown in FIG. 1 may include a connection end A111 and a connection end A112, wherein the connection end A111 is used for coupling with the data transmission end C111 in the transmission line 103, and the connection end A112 is used for coupling with the interface indicating end C112 in the transmission line 103 coupling.
  • the interface A21 shown in FIG. 1 may include a data transmission end A211 , and the data transmission end A211 is used for coupling with the data transmission end C211 in the adapter C21 of the transmission line 103 .
  • the cable C and the indicator Z in the transmission line 103 can be wrapped inside by an insulating layer and not exposed to the outside;
  • the interface indicating terminal C112 can be integrated together, and similarly, the connecting terminal A111 and the connecting terminal A112 in the interface A11 can be integrated together. In this way, the user can directly insert the adapter C11 into the interface A11 without distinguishing the connection ends, which improves the convenience of the user.
  • FIG. 2 shows a schematic structural diagram of the interface circuit 10 provided by the embodiment of the present application.
  • the interface circuit 10 may be a module, a chip, a chip set, a circuit board or a component mounted with a chip or a chip set integrated in the device.
  • the interface circuit 10 includes a plurality of interface controllers (HDMI controller 01, DP controller 02, USB interface controller 03 and new interface controller 04), multiplexer 07, mode controller 05 and ports Physical layer (PHY, Port Physical Layer) 06.
  • the above-mentioned multiple interface controllers, multiplexers 07 and port physical layers 06 may be integrated into one or more chips.
  • the one or more chips can be considered as a chipset.
  • the above-mentioned multiple interface controllers, multiplexers 07 and port physical layers 06 can be integrated into the same chip, when multiple interface controllers, multiplexers 07 and port physical layers 06 are integrated into the same chip.
  • the chip is also called an interface chip.
  • the interface chip can be integrated into a system-on-chip (Soc, System on chip) in the electronic device 101 .
  • the mode controller 05 may be integrated in the interface chip, or may be provided outside the interface chip.
  • the interface circuit 10 may be packaged and sold separately.
  • the interface circuit 10 also includes a data transmission terminal J1 and an interface indicating terminal J2.
  • the signal connection terminal J1 is coupled to multiple cables in the transmission line 103 through the connection end A111 of the interface A11; the interface indicating terminal J2 is coupled to the indicator Z in the transmission line 103 through the connection end A112 of the interface A11.
  • the above-mentioned multiple interface controllers may include HDMI controller 01, DP controller 02, USB interface controller 03, new interface controller 04, and other known or unknown interface controllers as shown in FIG. 2 .
  • the interface circuit 10 may also be provided with a memory or a register (shown in the figure) to store the software programs or codes required for the operation of the above-mentioned interface controllers.
  • the above-mentioned interface controllers can call all or part of the computer programs stored in the memory or registers to implement corresponding types of interfaces. It should be noted that the computer programs run by each interface controller in the above-mentioned multiple interface controllers are different, and the computer programs run by each interface controller may be independently stored in a memory or a register.
  • the multiplexer 07 includes a first terminal Vi1, a second terminal Vi2, a third terminal Vi3 and a fourth terminal Vi4, the HDMI controller 01 is coupled to the first terminal Vi1, and the DP controller 02 is coupled to the second terminal Vi2 is coupled, the USB interface controller 03 is coupled with the third terminal Vi3, the new interface controller 04 is coupled with the fourth terminal Vi4; the fifth terminal Vo1 of the multiplexer 07 is coupled with the first terminal Vi5 of the port physical layer 06; the port The second terminal Vo2 of the physical layer 06 is coupled to the data transmission terminal J1 of the interface circuit 10, thereby being coupled to the connection terminal A111 of the interface A11.
  • the multiplexer 07 also includes a control terminal Vc1, and the port physical layer 06 also includes a control terminal Vc2.
  • the output terminal Vo3 of the mode controller 05 is respectively connected with the control terminal Vc1 of the multiplexer 07 and the control terminal of the port physical layer 06. Vc2 is coupled; the signal input terminal Vi6 of the mode controller 05 is coupled to the interface indicating terminal J2 of the interface circuit 10, and thus is coupled to the connection terminal A112 of the interface A11.
  • the multiplexer 07 can be a multi-select one digital selector.
  • the multiplexer 07 connects one of the plurality of interface controllers to the port physical layer 06 based on the control of the signal input from the mode controller 05 .
  • the above-mentioned multiplexer can be a four-to-one digital selector, and the control terminal Vc1 of the multiplexer is input.
  • the control signal can include 2-bit control bits. For example, "00" represents gating HDMI controller 01, "01” represents gating DP controller 02, "10” represents gating USB interface controller 03, and "11" represents gating new interface controller 04.
  • the port physical layer 06 is used to realize signal transmission and reception.
  • the port physical layer 06 may include multiple transmitters TX (or multiple receivers RX).
  • the port physical layer 06 can encode the data sent by one of the multiple controllers according to the interface protocol rules of the interface protocol adopted by the device 102, and convert the encoded data into analog signals for transmission (or transmit the data provided by the transmission line 103).
  • the analog signal is decoded according to the interface protocol rules of the interface protocol adopted by the device 102, and the decoded data is provided to one of the multiple controllers).
  • multiple interface controllers multiplex the transmitter TX (or the receiver RX) in the port physical layer 06 to implement a multi-protocol interface.
  • the port physical layer 06 can receive a control signal from the mode controller 05 through the control terminal Vc2, and adjust the parameters of the transmitter TX (or the receiver RX) based on the control signal.
  • the parameters of the transmitter TX (or the receiver RX) may include, but are not limited to, the signal transmission rate or the amplitude of the transmitted signal.
  • the adjustment method for the parameters of the transmitter TX (or the receiver RX) may be the same as the gating method of the multiplexer 07 .
  • the control signal input by the control terminal Vc2 of the port physical layer 06 may include 2-bit control bits.
  • “00” means to adjust the parameters of the transmitter TX (or receiver RX) to the parameters of the HDMI protocol
  • "01” to adjust the parameters of the transmitter TX (or the receiver RX) to the parameters of the DP protocol
  • "10” It represents adjusting the parameters of the transmitter TX (or the receiver RX) to the parameters of the USB interface protocol
  • “11” represents adjusting the parameters of the transmitter TX (or the receiver RX) to the parameters of the new interface protocol.
  • the traditional interface circuit is only provided with a controller of one interface protocol type
  • the port physical layer in the traditional interface circuit is only provided with physical hardware such as transmitters or receivers, and the physical hardware is only used to implement one type of interface protocol.
  • Interface protocol type there is no problem of multi-protocol multiplexing.
  • the port physical layer 06 described in the embodiments of this application may include hardware devices that are the same as or similar to physical hardware included in traditional interface circuits, for example, including transmitters, receivers, and discrete devices such as capacitors and resistors.
  • the port physical layer 06 described in the embodiments of the present application may be multiplexed by various types of interface protocols, in other possible implementations, the port physical layer 06 may further include a multiplexer 07 and a mode controller 06 . In this embodiment of the present application, the multiplexer 07 and the mode controller 06 are set outside the port physical layer 06 for description.
  • the mode controller 05 may be a programmable logic device or a discrete device.
  • the mode controller 05 controls the multiplexer 07 to couple one of the multiple interface controllers with the port physical layer 06 based on the signal input from the connection terminal A112 of the interface A11;
  • the signal input from the connection terminal A112 can also control the operation of the corresponding circuit unit in the physical layer 06 of the port.
  • the mode controller 05 described in the embodiment of the present application needs to cooperate with the indicator Z in the transmission line 103 as shown in FIG. 1 to detect the interface of the device 102 connected to the other end of the transmission line 103 type.
  • the structure of the mode controller 05 is linked to the structure of the indicator Z in the transmission line 103 .
  • the structure of the mode controller 05 and the structure of the indicator described in the embodiments of the present application will be described in detail below through several possible implementation manners.
  • FIG. 4 schematically shows a first structure diagram of the mode controller 05 and the indicator Z.
  • the indicator can be a resistor R1, wherein different resistance values are used to indicate different protocol interfaces.
  • the resistance value for indicating HDMI may be 100K ⁇
  • the resistance value for indicating DP may be 200K ⁇
  • the resistance value for indicating USB interface may be 800K ⁇
  • the resistance value for indicating new interface may be 1600K ⁇ .
  • the mode controller 05 may include a comparator B, the first input terminal of the comparator B is coupled to the common ground Gnd, the second input terminal of the comparator B is coupled to the signal input terminal Vi6 of the mode controller 05, and the output terminal of the comparator B is Coupled to the output Vo3 of the mode controller 05 .
  • the mode controller 05 shown in FIG. 4 also includes a resistor R2, and the resistance value of the resistor R2 can be, for example, 400K ⁇ . One end of the resistor R2 is coupled to the second input end of the comparator B, and the other end of the resistor R2 is used for connecting with the power supply terminal Vcc of the mode controller 05 .
  • Comparator B may be a multi-threshold comparator. That is to say, the comparator B may be provided with multiple thresholds, the comparator B compares the voltage value of the second input terminal with the multiple thresholds, and outputs a control signal based on the comparison result.
  • the device 101 can implement interfaces of four protocols, three thresholds can be set in the comparator B, and the output end of the comparator B outputs a two-bit signal. It can be understood that the number of thresholds set in the comparator B and the number of output bits may be determined based on the number of implemented protocol types, which is not limited in this embodiment of the present application.
  • the resistance value of the indicator Z used to indicate HDMI is 100K ⁇ and the resistance value used to indicate DP is 200K ⁇ .
  • the resistance value of the USB interface is 800K ⁇ , and the resistance value used to indicate the new interface may be 1600K ⁇ .
  • the working principle of the interface circuit 10 shown in FIG. 2 will be described in detail. At this time, three thresholds, 1/4*Vcc, 1/2*Vcc, and 3/4*Vcc, can be set in the mode controller 05 .
  • the comparator B can output Control signal "00".
  • the control signal "00" is respectively input to the control terminal Vc1 of the multiplexer 07 and the control terminal Vc2 of the port physical layer 06, so that a path is formed between the HDMI controller 01 and the port physical layer 06, and the port physical layer 06
  • the parameters of the transmitter TX (or the receiver RX) are set to the parameters of the HDMI protocol, so as to realize data transmission between the device 101 and the device 102 using the HDMI protocol.
  • the comparator B can output the control signal "01".
  • the control signal "01" is respectively input to the control terminal Vc1 of the multiplexer 07 and the control terminal Vc2 of the port physical layer 06, so that a path is formed between the DP controller 02 and the port physical layer 06, and the port physical layer 06.
  • the parameters of the transmitter TX (or the receiver RX) are set to the parameters of the DP protocol, so as to implement data transmission between the device 101 and the device 102 using the DP protocol.
  • the comparator B can output the control signal "10".
  • the control signal "10" is respectively input to the control terminal Vc1 of the multiplexer 07 and the control terminal Vc2 of the port physical layer 06, so that a path is formed between the USB interface controller 03 and the port physical layer 06, and the port physical layer 06
  • the parameters of the transmitter TX (or the receiver RX) in the device are set to the parameters of the USB interface protocol, thereby realizing data transmission between the device 101 and the device 102 using the USB interface protocol. Assuming that the resistor R1 is connected to the first input terminal and the second input terminal of the comparator B, the voltage of the second input terminal of the comparator B is 4/5*Vcc, and the voltage value is greater than 3/4*Vcc. At this time, the comparator B can output the control signal "11".
  • the control signal "11" is respectively input to the control terminal Vc1 of the multiplexer 07 and the control terminal Vc2 of the port physical layer 06, so that a path is formed between the new interface controller 04 and the port physical layer 06, and the port physical layer 06
  • the parameters of the transmitter TX (or the receiver RX) in the device are set to the parameters of the new interface protocol, so as to realize data transmission between the device 101 and the device 102 using the new interface protocol.
  • the structure of the mode controller 05 uses a resistor dividing method to make the voltage of the second input terminal of the comparator B different based on the resistance value of the resistor R1 .
  • a manner in which the output current of the fixed current source passes through the resistor may also be adopted, so that the voltage of the second input terminal is different based on the resistance value of the resistor R1 .
  • the indicator Z includes a resistor R1, wherein different resistance values are used to indicate different protocol interfaces. The specifics are the same as the resistance device R1 described in FIG. 4 , and are not repeated here. Different from the structure of the mode controller 05 shown in FIG. 4 , in FIG.
  • the mode controller 05 includes a current source I in addition to the comparator B. As shown in FIG. The input terminal of the current source I is coupled to the power supply terminal Vcc, and the output terminal is coupled to the second input terminal of the comparator B. That is to say, the resistor in FIG. 4 is replaced by a current source in FIG. 5 , and the remaining devices and the connection relationship between the devices are the same as those shown in FIG. 4 . It is not repeated here. In the specific operation, the current generated by the current source flows to the common ground Gnd through the resistor R1, and the voltage of the second input terminal of the comparator B at this time is R1*I.
  • the mode controller 05 can realize the control of the multiplexer 07 and the port physical layer 06 .
  • the conversion between the input signal and the output signal is realized by setting the comparator B.
  • the comparator B may be replaced by an analog-to-digital converter (ADC, Analog-to-Digital Converter).
  • ADC Analog-to-Digital Converter
  • FIG. 6 and FIG. 7 The circuit structure in which the comparator B is replaced with an ADC is shown in FIG. 6 and FIG. 7 .
  • the working principle of the mode controller 05 will be described below by taking the circuit structure of the mode controller 05 shown in FIG. 6 as an example.
  • the conversion relationship between the input analog signal and the output digital signal can be preset in the ADC, and the conversion relationship is realized based on the internal circuit design of the ADC.
  • the resistor R1 is connected to the first input terminal and the second input terminal of the ADC
  • the voltage of the second input terminal of the ADC is a certain voltage value
  • the voltage value is converted into a digital signal by the ADC to communicate with the multiplexer 07 and the port physical layer. 06 to take control.
  • the indicator Z adopts a resistance device, and the interface type of the peer device 102 is identified through the voltage division of the resistance device or through a fixed current.
  • the indicator Z may be a register in which a value for indicating the interface type is stored. Assuming that there are four types of interfaces, the indication of each interface type can be realized by using 2 bits in the register. For example, “00” stands for HDMI, "01” for DP, "10” for USB port, and "11” for new port. In addition, when more kinds of interfaces need to be set, more bits can be added to the register.
  • a reader may be provided in the mode controller 05 for reading the data stored in the register.
  • the reader may be a logic device, the ground terminal of the reader is coupled to the common ground Gnd, the signal reading terminal of the reader is coupled to the signal input terminal Vi6 of the mode controller 05, and the output terminal of the reader is coupled to The output terminal Vo3 of the mode controller 05 and the power supply terminal of the reader are coupled to the power supply terminal Vcc of the mode controller 05 .
  • the power supply terminal Vcc of the mode controller 05 is used to input the power supply voltage from the outside, the output terminal Vo3 of the mode controller 05 is coupled with the multiplexer 07 and the control terminal of the port physical layer 06, and the input terminal of the mode controller 05 is coupled Vi6 is coupled to the output terminal of the indicator Z through the connection terminal A112 , and the ground terminal of the indicator Z and the ground terminal of the indicator Z are jointly coupled to the common ground Gnd of the interface circuit 10 .
  • the mode controller 05 may pre-store the data-interface type-control signal correspondence table stored in the register.
  • the mode controller 05 can read the data stored in the indicator Z, and based on the above-mentioned correspondence table, convert the read data into a control signal and input it to the control terminal Vc1 of the multiplexer. Therefore, the multiplexer 07 forms a path between one of the interface controllers and the port physical layer 06 based on the control signal.
  • FIG. 9 shows another schematic structural diagram of the interface circuit 10 provided by the embodiment of the present application.
  • the interface circuit may be provided with multiple port physical layers 06, and each port physical layer 06 supports one protocol interface. The following will take an example of an interface where the interface circuit is used to implement the HDMI, DP and USB interface protocols for detailed description. Please continue to refer to FIG. 9.
  • FIG. 9 shows another schematic structural diagram of the interface circuit 10 provided by the embodiment of the present application. In FIG.
  • an HDMI controller 01 an HDMI controller 01 , a DP controller 02 , a USB interface controller 03 , an HDMI port physical layer 061 , a DP port physical layer 062 , and a USB port physical layer 063 are included.
  • the output of HDMI controller 01 is coupled to HDMI port physical layer 061
  • the output of DP controller 02 is coupled to DP port physical layer 062
  • the output of USB interface controller 03 is coupled to USB port physical layer 063 .
  • the switch group SW, the mode controller 05, and the interface A11 are also included. For the specific structure of the interface A11, reference is made to the related description of the interface A11 shown in FIG. 1 , and details are not repeated here.
  • the switch group SW includes a switch K1, a switch K2 and a switch K3.
  • the first end of the switch K1 is coupled to the output end of the HDMI port physical layer 061
  • the first end of the switch K2 is coupled to the output end of the DP port physical layer 062
  • the first end of the switch K3 is coupled to the USB port physical layer 063.
  • the output terminals, the second terminal of the switch K1, the second terminal of the switch K2 and the second terminal of the switch K3 are all coupled to the data transmission terminal J1 of the interface circuit 10 to be coupled to the connection terminal A111 of the interface A11.
  • the mode controller 05 includes a plurality of output terminals, wherein the output terminal Vo4 is used to control the turn-on or turn-off of the switch K1, the output terminal Vo5 is used to control the turn-on or turn-off of the switch K2, and the output terminal Vo6 is used to control the switch K3. turn-on or turn-off.
  • the input terminal Vi6 of the mode controller 05 is coupled to the interface indicating terminal J2 of the interface circuit 10 to be coupled to the connecting terminal A112 of the interface A11.
  • the structure of each port physical layer shown in FIG. 9 and the detailed structure of the port physical layer 06 shown in FIG. 2 are specifically referred to the relevant description of the port physical layer 06 shown in FIG. 2 , which will not be repeated here.
  • each port physical layer shown in FIG. 9 since each port physical layer shown in FIG. 9 is dedicated to one interface protocol, the parameters of the transmitter (or receiver) in each port physical layer correspond to one interface protocol parameter, and its parameters do not need to be Changes from time to time, therefore, each port physical layer shown in FIG. 9 does not need to be coupled to the output of the mode controller 05 .
  • the mode controller 05 shown in Figure 9 may include a digital to analog converter or reader based on the type of indicator Z in the cable C.
  • the mode controller 05 includes a digital-to-analog converter, the devices it includes and the connection relationship between the output terminal and each device are the same as the mode controller 05 shown in FIGS. 9-7 .
  • the digital-to-analog converter converts the analog voltage signal input from the input terminal into a three-bit digital signal, which is output through the output terminal Vo4, the output terminal Vo5 and the output terminal Vo6 respectively to control the switch K1, the switch K2 and the switch K3.
  • On-off state For example, "100” means that the switch K1 is turned on, "010” means that the switch K2 is turned on, and "001” means that the switch K3 is turned on.
  • the digital-to-analog converter can also be converted into a 2-bit digital signal based on the analog voltage signal input from the input terminal.
  • the mode controller 05 may only set the output terminal Vo4 and the output terminal Vo5, and not set the output terminal Vo6, which is not shown in the figure.
  • the mode controller 05 includes a reader
  • the devices it includes and the connection relationship between the output terminal and each device are the same as the mode controller 05 shown in FIG. 8 .
  • the reader converts the read data into a three-bit digital signal, which is output through the output end Vo4, the output end Vo5 and the output end Vo6 respectively, to control the on-off state of the switch K1, the switch K2 and the switch K3 .
  • FIG. 9 schematically shows a situation in which the controller includes three types, the port physical layer includes corresponding three types, and the switch group SW includes a switch K1, a switch K2, and a switch K3.
  • This embodiment of the present application does not specifically limit the type and number of controllers included in the interface circuit 10, which are set according to the needs of the application scenario.
  • the number of port physical layers and the number of switches included in the switch group SW are not specifically limited, and are set based on the type and number of controllers.
  • the number of bits of the digital signal output by the mode controller 05 is also determined based on the number of switches included in the switch group SW.
  • the interface circuit 10 may also include a new interface controller. At this time, a new interface port physical layer needs to be set in the interface circuit 10.
  • the switch group SW may also be provided with a switch K4.
  • the output of the mode controller 05 The digital signal can also be, for example, 4 bits.
  • the switches in the switch group SW as shown in FIG. 9 may be analog switches.
  • the switch group SW can be specifically implemented in the following three possible ways.
  • the switch K1 , the switch K2 and the switch K3 are single-pole single-throw switches, as shown in FIG. 9 .
  • each of the switch K1 , the switch K2 and the switch K3 is composed of a plurality of transistors, as shown in FIG. 10 .
  • each switch is provided with a transistor Q1 and a transistor Q2.
  • the transistor Q1 may be an NMOS transistor, and the transistor Q2 may be a PMOS transistor; or the transistor Q1 may be a PMOS transistor, and the transistor Q2 may be an NMOS transistor.
  • the transistor Q1 is an NMOS transistor and the transistor Q2 is a PMOS transistor
  • the connection relationship of the transistors included in each switch will be described.
  • the first pole of the transistor Q1, the first pole of the transistor Q2 and the output terminal of the HDMI port physical layer 06 are coupled together, and the second pole of the transistor Q1 and the second pole of the transistor Q2 are both coupled to the connection terminal A111 of the interface A11.
  • the first electrode of the transistor Q1 and the second electrode of the transistor Q2 may be the drain electrodes, and the second electrode of the transistor Q1 and the first electrode of the transistor Q2 may be the source electrodes.
  • the output terminal Vo4 of the mode controller 05 is coupled to the gate of the transistor Q1 in the switch K1, and the output terminal Vo4 of the mode controller 05 is coupled to the gate of the transistor Q2 in the switch K1 through an inverter (not shown in the figure) ;
  • the output terminal Vo5 of the mode controller 05 is coupled with the gate of the transistor Q1 in the switch K2, and the output terminal Vo5 of the mode controller 05 is coupled to the gate of the transistor Q2 in the switch K2 through an inverter (not shown in the figure) Coupling;
  • the output terminal Vo6 of the mode controller 05 is coupled with the gate of the transistor Q1 in the switch K3, and the output terminal Vo6 of the mode controller 05 is connected to the gate of the transistor Q2 in the switch K3 through an inverter (not shown in the figure).
  • the mode controller 05 is based on the information indicated by the indicator Z in the connected transmission line (wherein the method for determining the information indicated by the indicator Z refers to the relevant descriptions in the embodiments shown in FIGS. 4-8 )
  • the output terminal Vo4 of the mode controller 05 outputs a high-level signal
  • the output terminal Vo5 outputs a low-level signal
  • the output terminal Vo6 outputs a low-level signal.
  • the transistor Q1 and the transistor Q2 in the switch K1 are turned on, the output end of the HDMI port physical layer 06 is connected to the connection end A111 of the interface A11, and the device 101 can communicate with the device 201 through the HDMI protocol.
  • each of the switch K1 , the switch K2 and the switch K3 may be composed of more transistors, as shown in FIG. 11 .
  • each switch is provided with a transistor Q3, a transistor Q4, a transistor Q5, a transistor Q6 and a transistor Q7.
  • transistor Q3, transistor Q5 and crystal Q7 may be NMOS transistors, and transistor Q4 and transistor Q6 may be PMOS transistors; or, transistor Q3, transistor Q5 and crystal Q7 may be PMOS transistors, and transistor Q4 and transistor Q6 may be NMOS transistors.
  • transistor Q3, transistor Q5 and crystal Q7 as NMOS transistors, and transistor Q4 and transistor Q6 as PMOS transistors as examples the connection relationship of the transistors included in each switch will be described.
  • the first pole of transistor Q3, the first pole of transistor Q4 and the output terminal of the HDMI port physical layer 06 are coupled together, the second pole of transistor Q3, the second pole of transistor Q4, the first pole of transistor Q5, the The first electrode and the first electrode of the transistor Q7 are coupled together, the second electrode of the transistor Q5 and the first electrode of the transistor Q6 are both coupled to the connection terminal A111 of the interface A11, and the second electrode of the transistor Q7 is coupled to the common ground.
  • the first electrode of the transistor Q3, the second electrode of the transistor Q4, the first electrode of the transistor Q5, the second electrode of the transistor Q6 and the first electrode of the transistor Q7 may be drains, and the second electrode of the transistor Q3, the transistor Q4
  • the first pole of the transistor Q5, the second pole of the transistor Q5, the first pole of the transistor Q6 and the second pole of the transistor Q7 can be source stages;
  • One pole, the second pole of the transistor Q6 and the first pole of the transistor Q7 can be the source, the second pole of the transistor Q3, the first pole of the transistor Q4, the second pole of the transistor Q5, the first pole of the transistor Q6 and the transistor
  • the second pole of Q7 can be a drain.
  • the output terminal Vo4 of the mode controller 05 is coupled with the gate of the transistor Q3, the gate of the transistor Q5 and the gate of the transistor Q7 in the switch K1, and the output terminal Vo4 of the mode controller passes through an inverter (not shown in the figure) It is coupled with the gate of the transistor Q4 in the switch K1 and the gate of the transistor Q6; the output terminal Vo5 of the mode controller 05 is coupled with the gate of the transistor Q3 in the switch K2, the gate of the transistor Q5 and the gate of the transistor Q7, The output terminal Vo5 of the mode controller is coupled with the gate of the transistor Q4 in the switch K2 and the gate of the transistor Q6 through an inverter (not shown in the figure); the output terminal Vo6 of the mode controller 05 is coupled with the transistor in the switch K3 The gate of Q3, the gate of transistor Q5 and the gate of transistor Q7 are coupled, and the output terminal Vo6 of the mode controller 05 is coupled to the gate of the transistor Q4 and the transistor Q6 in the switch K3 through an inverter
  • the mode controller 05 When the mode controller 05 is based on the information indicated by the indicator Z in the connected transmission line (wherein the method for determining the information indicated by the indicator Z refers to the relevant descriptions in the embodiments shown in FIGS. 4-8 )
  • the output terminal Vo4 of the mode controller 05 When it is determined that the interface protocol type adopted by the peer device 102 is HDMI, the output terminal Vo4 of the mode controller 05 outputs a high-level signal, the output terminal Vo5 outputs a low-level signal, and the output terminal Vo6 outputs a low-level signal.
  • Each transistor in the switch K1 is turned on, the output end of the HDMI port physical layer 06 is connected to the connection end A111 of the interface A11, and the device 101 can communicate with the device 201 through the HDMI protocol.
  • the interface A11 shown in FIG. 1 and FIG. 2 may be a signal transmitting interface. At this time, the device 101 sends data to the device 102 through the interface A11. In addition, the interface A11 may also be a signal receiving interface. At this time, the device 101 receives data from the device 102 through the interface A11.
  • the peripheral circuits adopted by the signal transmitting interface and the signal receiving interface are different based on the protocol regulations.
  • interfaces of different protocol types support different signal coupling modes. For example, HDMI supports DC signal coupling, and DP supports AC signal coupling.
  • the interface circuit described in this embodiment of the present application further includes a peripheral circuit, so that the interface A11 can transmit both the DC signal specified by the HDMI protocol and the AC signal specified by the DP protocol, for example. Signal.
  • the peripheral circuits described here can be understood as circuits other than the above-mentioned multiple interface controllers, multiplexers 07, mode controllers 05 and port physical layer 06, which may include but are not limited to capacitors, switches and resistors, etc.
  • the peripheral circuit of the signal transmitting interface is different from that of the signal receiving interface.
  • FIGS. 12 to 17 show schematic diagrams of peripheral circuits when the interface A11 shown in FIG. 1 is used as the signal transmitting interface;
  • FIGS. 15-17 show the interface A11 shown in FIG. Schematic diagram of the peripheral circuit.
  • the interface circuit 10 further includes a plurality of capacitors C T1 , a plurality of resistors R T1 and a plurality of switches K T1 .
  • the number of capacitors C T1 , resistors R T1 and switches K T1 is the same as the number of transmitters TX included in the port physical layer 06 , and can also be said to be the same as the number of cables used to transmit data in the transmission line 103 .
  • the interface circuit 10 may include four capacitors C T1 , four resistors R T1 and four Switch K T1 .
  • a transmitter TX, a capacitor C T1 , a resistor R T1 and a switch K T1 can form a signal transmission channel, so the device 101 can include a plurality of signal transmission channels, the devices included in each signal transmission channel and the devices The connections between them are the same.
  • the following takes one of the signal transmission channels as an example to describe the connection relationship of each device.
  • one end of the capacitor C T1 is coupled to the output end of the transmitter TX, and the other end of the capacitor C T1 is coupled with one end of the resistor R T1 and the connection end A111 in the interface A11; the other end of the resistor R T1 is coupled through the switch K T1 Coupled to common ground Gnd.
  • the multiple capacitors C T1 , the multiple resistors R T1 and the multiple switches K T1 described in the embodiments of the present application may be disposed outside the interface chip as shown in FIG. 3 .
  • the mode controller 05 determines, based on the signal indicated by the indicator Z, that the interface of the peer device 102 is an interface that supports the AC signal coupling method ( For example, DP, USB3 interface, USB4 interface or new interface), based on the regulation of the AC signal coupling method in the interface protocol, the signal transmitter needs to be provided with a coupling capacitor C T1 , but does not need to be provided with a resistor R T1 .
  • the mode controller 05 can control the multiple switches K T1 to be turned off, as shown in FIG. 13 .
  • the mode controller 05 determines, based on the signal indicated by the indicator Z, that the interface of the peer device 102 is an interface that supports the DC signal coupling method ( For example, HDMI or new interface), based on the regulation of the DC signal coupling method in the interface protocol, the signal transmitter needs to provide a voltage of a certain voltage value, and because in order to meet the regulations on the AC signal coupling method in the interface protocol, the signal transmitter terminal needs to provide a voltage of a certain voltage value.
  • the DC signal coupling method For example, HDMI or new interface
  • a capacitor C T1 is provided, and the capacitor C T1 has the function of passing the alternating current and blocking the direct current.
  • the capacitor C T1 in the interface circuit 10 blocks the direct current signal output by the transmitter TX.
  • the mode controller 05 can control the multiple switches K T1 to be closed, so that the resistor R T1 is coupled between the common ground Gnd and the receiver RX of the opposite device 102 , as shown in FIG. 14 .
  • the input end of the receiver RX of the device 102 is provided with a pull-up resistor R R1 .
  • the resistor R T1 is used to divide the voltage input from the power supply end of the pull-up resistor R R1 , and by adjusting the resistance value of the resistor R T1 , the signal transmission interface can output a certain DC voltage specified by the interface protocol.
  • FIG. 15 is a schematic structural diagram of the interface circuit when the multi-protocol interface A11 is used as a signal receiving end.
  • the interface circuit 10 further includes a plurality of switches K R1 , a plurality of switches K R2 , a plurality of resistors R R2 and a plurality of resistors R R3 .
  • the number of switches K R1 , switches K R2 , resistors R R2 and resistors R R3 is the same as the number of receivers RX included in the port physical layer 06 , which can also be said to be the same as the number of cables used to transmit data in the transmission line 103 .
  • the interface circuit 10 may include four switches K R1 , four switches K R2 , four Resistor R R2 and four resistors R R3 .
  • a transmitter RX, a switch K R1 , a switch K R2 , a resistor R R2 and a resistor R R3 can form a signal receiving channel, so that the device 101 can include a plurality of signal receiving channels, each signal receiving channel includes The devices and the connection relationship between the devices are the same. The following takes one of the signal receiving channels as an example to describe the connection relationship of each device.
  • one end of the resistor R R2 and one end of the resistor R R3 are both coupled to the input end of the receiver RX, the other end of the resistor R R2 is coupled to the power supply terminal Vcc through the switch K R1 , and the other end of the resistor R R3 is connected through the switch K R2 Coupled to common ground Gnd. That is to say, the resistor R R2 is a pull-up resistor, and the resistor R R3 is a pull-down resistor.
  • the multiple switches K R1 , the multiple switches K R2 , the multiple resistors R R2 and the multiple resistors R R3 described in the embodiments of the present application may be integrated into the interface chip as shown in FIG. 3 .
  • the signal receiving end Based on the stipulation of the AC signal coupling method in the interface protocol, the signal receiving end needs to set the pull-down resistor RR3 , but does not need to set the pull-up resistor RR2 ; based on the stipulation on the DC signal coupling method in the interface protocol, the signal receiving end needs to set the upper Pull-up resistor R R2 , but does not need to set pull-down resistor R R3 .
  • the pull-up resistors R R2 and the pull-down resistors R R2 and pull-down The resistors R R3 are all integrated in the interface circuit 10, the on-off state between the pull-up resistor R R2 and the power supply terminal Vcc is controlled by the switch K R1 , and the on-off state between the pull-down resistor R R3 and the common ground Gnd is controlled by the switch K R2 state, so as to realize the signal transmission of various protocols.
  • the mode controller 05 determines, based on the signal indicated by the indicator Z, that the interface of the peer device 102 is an interface that supports the AC signal coupling method ( For example, DP, USB3 interface, USB4 interface or new interface in the future), based on the regulation of the AC signal coupling method in the interface protocol, the signal receiving end needs to be set with a pull-down resistor R R3 , but does not need to be set with a pull-up resistor R R2 .
  • the AC signal coupling method For example, DP, USB3 interface, USB4 interface or new interface in the future
  • the mode controller 05 can control the multiple switches K R1 to be turned off, and the multiple switches K R2 to be closed, as shown in FIG. 16 .
  • the mode controller 05 determines, based on the signal indicated by the indicator Z, that the interface of the peer device 102 is an interface that supports the DC signal coupling method ( For example, HDMI or a new interface in the future), based on the provisions of the DC signal coupling method in the interface protocol, the signal receiving end needs to be set with a pull-up resistor R R2 , but does not need to be set with a pull-down resistor R R3 .
  • the mode controller 05 can control the multiple switches K R2 to be turned off, and to control the multiple switches K R1 to be closed, as shown in FIG. 17 .
  • the interface A11 is schematically shown as the signal transmitting interface; in the implementations shown in FIGS. 15 to 17 , the interface A11 is schematically shown as the signal transmission interface.
  • the case of the signal receiving interface In other scenarios, based on the provisions of the interface protocol, the interface A11 can be a signal transceiving interface, which can transmit and receive signals in a time-sharing manner.
  • the interface A11 when the interface A11 performs signal transmission based on the DP protocol, within a communication cycle, the interface A11 is only used for transmitting signals or only for receiving signals; when the interface A11 performs signal transmission based on the USB interface protocol, in one communication In a period, the interface A11 is used for transmitting signals in the first period and for receiving signals in the second period.
  • the interface A11 may also have a structure as shown in FIG. 18 a and FIG. 18 b .
  • part of the receiver RX is also provided in the port physical layer 06.
  • the peripheral circuit of the transmitter TX and the connection relationship with other components are the same as the peripheral circuit of the transmitter TX and the connection relationship with other components shown in FIG. 12 , and are not repeated here.
  • the peripheral circuit of the receiver RX and the connection relationship with other components are the same as the peripheral circuit of the receiver RX and the connection relationship with other components shown in FIG. 15 , and are not repeated here.
  • four cables may be set in the transmission line 103, and at this time, the port physical layer 06 may be set with four transmitters TX and two receivers RX.
  • Two of the cables are only coupled to the two transmitters TX in the port physical layer 06, and the other two cables are coupled to the other two transmitters TX and the two receivers RX.
  • the interface A21 of the device 102 is a DP interface or an HDMI interface
  • the four transmitters TX in the port physical layer 06 are enabled, and the interface circuit 10 transmits signals to the device 102 through the interface A11 and the transmission line 103;
  • the interface A21 of the device 102 is When the USB interface is used, the two transmitters TX and the two receivers RX in the port physical layer 06 are enabled, and the two enabled transmitters TX and the two receivers RX are coupled with different cables.
  • the transmitter TX in the interface circuit 10 transmits signals to the device 102 through the interface A11 and two of the transmission lines 103 (or the receiver RX in the interface circuit 10 transmits signals through the interface A11 and two of the transmission lines 103 )
  • the cable receives the signal from the device 102
  • the receiver RX in the interface circuit 10 receives the signal from the device 102 through the interface A11 and the two cables in the transmission line 103 (or the transmitter TX in the interface circuit 10 passes through The interface A11 and two of the transmission lines 103 transmit signals to the device 102).
  • part of the transmitter TX is also provided in the port physical layer 06.
  • the peripheral circuit of the receiver RX and the connection relationship with other components are the same as the peripheral circuit of the receiver RX and the connection relationship with other components shown in FIG. 15 , and will not be repeated here.
  • the peripheral circuit of the transmitter TX and the connection relationship with other components are the same as the peripheral circuit of the transmitter TX and the connection relationship with other components shown in FIG. 12 , and will not be repeated here.
  • four cables may be set in the transmission line 103, and at this time, the port physical layer 06 may be set with four receivers RX and two transmitters TX.
  • Two of the cables are only coupled to the two receivers RX in the port physical layer 06, and the other two cables are coupled to the other two receivers RX and the two transmitters TX.
  • the interface A21 of the device 102 is a DP interface or an HDMI interface
  • the four receivers RX in the port physical layer 06 are enabled, and the interface circuit 10 receives signals from the device 102 through the interface A11 and the transmission line 103;
  • the interface A21 of the device 102 is When the USB interface is used, the two transmitters TX and the two receivers RX in the port physical layer 06 are enabled, and the two enabled transmitters TX and the two receivers RX are coupled with different cables.
  • the transmitter TX in the interface circuit 10 transmits signals to the device 102 through the interface A11 and two of the transmission lines 103 (or the receiver RX in the interface circuit 10 transmits signals through the interface A11 and two of the transmission lines 103 )
  • the cable receives the signal from the device 102
  • the receiver RX in the interface circuit 10 receives the signal from the device 102 through the interface A11 and the two cables in the transmission line 103 (or the transmitter TX in the interface circuit 10 passes through The interface A11 and two of the transmission lines 103 transmit signals to the device 102).
  • the device 101 includes an interface A11.
  • multiple interfaces can be set in the device 101, some of which are used to transmit signals to other devices, and the other The device receives the signal, as shown in Figure 18.
  • FIG. 18 schematically shows a situation where the device 101 includes an interface A12, an interface A13, an interface A14 and an interface A15.
  • Interface A12 is coupled to interface circuit 10A
  • interface A13 is coupled to interface circuit 10B
  • interface A14 is coupled to interface circuit 10C
  • interface A15 is coupled to interface circuit 10D.
  • Interface A12, interface A13, interface A14, and interface A15 may all be multi-protocol interfaces.
  • the interface A12 and the interface A13 may be signal transmitting interfaces, and the interface A14 and the interface A15 may be signal receiving interfaces.
  • the port physical layer 06 in the interface circuit 10A and the interface circuit 10B includes the transmitter TX
  • the port physical layer 06 in the interface circuit 10C and the interface circuit 10D includes the receiver RX.
  • the signal transmitting interface mentioned here refers to an interface based on such as HDMI protocol or DP protocol, which is only used for signal transmitting during the communication cycle; An interface used only for signal reception during a communication cycle.
  • some receivers TX may also be set to meet the requirements of the USB interface protocol.
  • some transmitters RX may also be set to meet the requirements of the USB interface protocol.
  • the structure of the interface circuit 10A and the interface circuit 10B, the coupling relationship between each interface and the corresponding interface circuit, and the interface circuit 10 and the coupling between the interface circuit 10 and the interface A11 described in any of the embodiments of FIG. 2-FIG. 14 and FIG. 18a The relationship is the same, and will not be repeated here; the structures of the interface circuit 10C and the interface circuit 10D, and the coupling relationship between each interface and the corresponding interface circuit are the same as those described in any of the embodiments in FIGS. 2-11, 15-17, and 18b.
  • the interface circuit 10 and the coupling relationship between the interface circuit 10 and the interface A11 are the same, and are not repeated here.
  • an embodiment of the present application further provides a data transmission method, and the data transmission method is applied to the data transmission system shown in FIG. 1 .
  • FIG. 19 shows a process 2000 of the data transmission method provided by the embodiment of the present application.
  • the process 2000 of the data transmission method includes the following steps:
  • step 2001 the interface circuit 10 obtains indication information from the indicator Z of the transmission line 103 through the interface indication terminal, and the indication information is used to instruct the data transmission interface protocol of the device 102 .
  • Step 2002 the interface circuit 10 transmits data to the device 102 through the data transmission end using the data transmission interface protocol of the device 102 indicated by the indication information.
  • the interface circuit 10 includes a plurality of interface controllers, multiplexers 07 , port physical layers 06 and mode controllers 05 as shown in FIG. 2 .
  • the above-mentioned step 2002 further includes: the mode controller 05 controls the multiplexer 07 to communicate with the port physical layer 06 based on the indication information, and one of the interface controllers in the plurality of interface controllers communicates with the port physical layer 06, wherein the interface communicated with the port physical layer 06
  • the controller has the same data transmission interface protocol as the device 102; the interface controller communicated with the port physical layer 06 controls the port physical layer 06 to adopt the same data transmission protocol as the device 102, and transmits the data to the device 102 through the data transmission end of the interface circuit. transfer data.
  • the data transmission method further includes: based on the indication information, the mode controller 05 adjusts at least one of the following parameters in the transmitter and the receiver in the port physical layer 06: a signal transmission rate or a transmitted signal Amplitude.
  • the interface circuit includes multiple interface controllers, multiple port physical layers, switch group SW and mode controller 05 as shown in FIG. 9 , multiple interface controllers, multiple port physical layers It is coupled to a plurality of switches in the switch group SW in a one-to-one correspondence.
  • the above step 2002 further includes: the mode controller 05 controls one of the switches in the switch group SW to be turned on based on the indication information; the interface controller corresponding to the turned-on switch controls the port physical layer coupled with the turned-on switch , using the same data transmission protocol as the device 102 to transmit data to the device 102 through the data transmission end of the interface circuit.
  • the indicator is a resistor
  • the indication information of the indicator is an analog signal
  • the indicator is a register, and the indication information of the indicator is a digital signal.
  • the data transmission method further includes: the interface circuit 10 establishes a connection with the device 102 in a DC coupling manner or an AC coupling manner.

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Abstract

本申请实施例提供了一种接口电路、电子设备和数据传输装置，该接口电路包括接口指示端和数据传输端；接口电路通过数据传输装置与第一设备进行数据传输，接口电路包括接口指示端和数据传输端；接口电路通过接口指示端从数据传输装置的指示器获取指示信息，指示信息用于指示第一设备的数据传输接口协议；接口电路用于通过数据传输端，采用指示信息指示的第一设备的数据传输接口协议，向第一设备传输数据。本申请提供的接口电路，可以复用一个物理接口实现多种传输接口协议，进而可以实现与多种不同接口类型的电子设备的数据传输。

Description

接口电路、电子设备、数据传输装置和数据传输系统 技术领域
本申请实施例涉及电路领域，尤其涉及一种接口电路、电子设备、数据传输装置和数据传输系统。
背景技术
伴随着科学技术发展，诸如平板电脑，手机、主机设备、机顶盒、超薄显示器以及虚拟现实(VR，Virtual Reality)显示器等各种类型的电子设备如雨后春笋般出现。此外，电子设备也朝着高集成度、小体积、大屏幕等多元化的方向发展。另外，对于不同的电子设备，其通常采用不同类型的接口协议进行数据传输。
当前技术中，为了与多种接口类型的电子设备进行数据传输，电子设备中通常设置有多种类型的接口。例如，某一显示设备采用高清多媒体接口(HDMI，High Definition Multimedia Interface)进行数据传输，另外一个显示设备采用显示接口(DP，DisplayPort)进行数据传输。主机设备为了能够与多种接口类型的显示设备进行数据传输，通常设置HDMI和DP等多种类型的接口。此外，显示设备为了与不同接口类型的主机设备进行数据传输，同样设置多种类型的接口。然而，多种接口并存极大占用电子设备的空间以及接口芯片的版图面积，不利于高集成度以及小体积的电子设备的实现。由此，如何在降低接口所占用的电子设备的空间的同时、实现电子设备兼容多种类型的接口成为需要解决的问题。
发明内容
为达到上述目的，本申请采用如下技术方案：
第一方面，本申请实施例提供一种接口电路，所述接口电路通过数据传输装置与第一设备进行数据传输，所述接口电路包括接口指示端和数据传输端；所述接口电路通过所述接口指示端从所述数据传输装置的指示器获取指示信息，所述指示信息用于指示所述第一设备的数据传输接口协议；所述接口电路用于通过所述数据传输端，采用所述指示信息指示的所述第一设备的数据传输接口协议，向所述第一设备传输数据。
本申请实施例所示的接口电路，基于从指示器获取到的指示信息来确定第一设备中数据传输接口的协议类型，然后采用与第一设备相同类型的接口协议与第一设备之间进行数据传输。从而，本申请实施例提供的接口电路可以复用一个物理接口实现多种传输接口协议，进而可以实现与多种不同接口类型的电子设备的数据传输。与传统电子设备中设置多种类型的接口相比，降低了接口所占用的电子设备的版图面积，从而有利于实现高集成度以及小体积的电子设备。
本申请实施例提供的接口电路可以包括多种可能的实现方式：
方式一：所述接口电路包括多个接口控制器、多路选择器、端口物理层和模式控制 器；所述多个接口控制器中的每一个接口控制器分别耦合至所述多路选择器的多个输入端；所述多路选择器的输出端耦合至所述端口物理层第一端；所述端口物理层的第二端耦合至所述接口电路的数据传输端；所述模式控制器的输入端耦合至所述接口电路的接口指示端，所述模式控制器的输出端耦合至所述多路选择器的第一控制端，所述模式控制器基于所述指示信息，控制所述多路选择器将所述多个接口控制器中的第一接口控制器与所述端口物理层连通。
进一步的，所述模式控制器的输出端还耦合于所述端口物理层的第二控制端；所述模式控制器还用于：基于所述指示信息，调整所述端口物理层中发射器和接收器中以下参数的至少一项：信号传输速率或者所传输的信号的幅度。
在方式一中，多个接口控制器共用同一个接口物理层。模式控制器基于指示器提供的指示信息，控制多路选择器选通多个接口控制器中的一个，实现与第一设备相同类型的接口协议。通过将多个接口控制器共用同一个接口物理层，可以减少接口物理层所占用的电子设备的版图面积，从而有利于实现高集成度以及小体积的电子设备。
方式二：所述接口电路包括多个接口控制器、多个端口物理层、开关组和模式控制器；所述多个接口控制器与所述多个端口物理层的第一端一一对应耦合；所述多个端口物理层的第二端通过所述开关组中一一对应的多个开关耦合至所述接口电路的数据传输端；所述模式控制器的输入端耦合至所述接口指示端，所述模式控制器的输出端耦合至所述开关组的控制端，所述模式控制器用于基于所述指示信息，控制所述开关组中的任一开关导通。
在方式二中，多个接口控制器与多个端口物理层一一对应连接。例如，多个接口控制器包括HDMI控制器、DP控制器和USB接口控制器，多个端口物理层包括HDM1端口物理层、DP端口物理层和USB端口物理层，HDMI控制器与HDMI端口物理层的第一端耦合，DP控制器与DP端口物理层的第一端耦合，USB接口控制器与USB端口物理层的第一端耦合。开关组中包括多个开关，每一个端口物理层的第二端通过其中一个开关耦合至接口电路的数据传输端，每一个端口物理层所耦合的开关不同。模式控制器基于指示器的指示信息，控制开关组中的任一个开关导通，从而实现将其中一个端口物理层与接口电路的数据传输端连通。
需要说明的是，本申请实施例中所述的控制所述开关组中的任一开关导通是指该开关处于导通状态，其余开关处于关断状态。例如，当开关组中的所有开关处于处于关断状态时，控制开关组中的任一开关导通是指将其中一个开关导通，保持其余开关处于关断状态；再例如，当开关组中的所有开关均处于导通状态时，控制控制开关组中的任一开关导通是指保持其中一个开关处于导通状态，关断其余开关。
基于上述方式一和方式二，本申请实施例所述的模式控制器可以由多种方式实现。
在第一种可能的实现方式中，模式控制器包括比较器和第一电阻；所述比较器的第一输入端耦合至地端，所述比较器的第二输入端耦合至所述模式控制器的输入端，所述比较器的输出端耦合至所述模式控制器的输出端；所述第一电阻的一端耦合至供电端，所述第一电阻的另一端耦合至所述比较器的第二输入端。
在第二种可能的实现方式中，所述模式控制器包括比较器和电流源；所述比较器的第一输入端耦合至地端，所述比较器的第二输入端耦合至所述模式控制器的输入端，所 述比较器的输出端耦合至所述模式控制器的输出端；所述电流源的一端耦合至供电端，所述电流源的另一端耦合至所述比较器的第二输入端。
在第三种可能的实现方式中，所述指示信息为模拟信号，所述模式控制器包括模数转换器和第一电阻；所述第一电阻的一端耦合至供电端，所述第一电阻的另一端耦合至所述模数转换器的输入端；所述模数转换器的第一输入端耦合至地端，所述模数转换器的第二输入端耦合至所述模式控制器的输入端，所述模数转换器基于所述指示信息，生成数字信号提供至所述模式控制器的输出端。
在第四种可能的实现方式中，所述指示信息为模拟信号，所述模式控制器包括模数转换器和电流源；所述电流源的一端耦合至供电端，所述电流源的另一端耦合至所述模数转换器的输入端；所述模数转换器的第一输入端耦合至地端，所述模数转换器的第二输入端耦合至所述模式控制器的输入端，所述模数转换器基于所述指示信息，生成数字信号提供至所述模式控制器的输出端。
在第五种可能的实现方式中，所述指示信息为数字信号，所述模式控制器包括读取器；所述读取器用于读取所述指示信息，基于所述指示信息生成控制信号提供至所述模式控制器的输入端。
基于上述方式一和方式二，在一种可能的实现方式中，所述端口物理层包括发射器，所述发射器用于通过所述数据传输装置向所述第一设备传输数据；以及所述接口电路还包括电容、第二电阻和第一开关；所述电容的第一端耦合至所述发射器的输出端，所述电容的第二端和所述第二电阻的一端耦合至所述接口电路的数据传输端；所述第二电阻的另一端通过所述第一开关耦合至地端。
可选的，电容的数目、第二电阻的数目和第一开关的数目与发射器的数目相同。
本申请实施例通过设置电容、第二电阻和第一开关，可以使得接口电路作为数据发射端时既可以满足接口协议中对直流信号耦合方式的规定，也可以满足接口协议中对交流信号耦合方式的规定。例如，当第一设备采用接口协议所支持的交流耦合方式的接口(例如DP、USB3接口、USB4接口或者新接口)进行数据传输时，可以断开第一开关；当第一设备采用接口协议所支持的直流耦合方式的接口(例如HDMI或者新接口)进行数据传输时，可以使得第一开关闭合。
基于上述方式一和方式二，在一种可能的实现方式中，所述端口物理层还包括接收器，所述接收器用于通过所述数据传输装置从所述第一设备接收数据；以及所述接口电路还包括第三电阻、第二开关、第四电阻和第三开关；所述第三电阻的第一端通过所述第二开关耦合至供电端；所述第三电阻的第二端、所述第四电阻的第一端、所述接收器的接收端均耦合至所述接口电路的数据传输端；所述第四电阻的第二端通过所述第三开关耦合至公共地。
可选的，第三电阻的数目、第二开关的数目、第四电阻的数目和第三开关的数目与接收器的数目相同。
本申请实施例通过设置第三电阻、第二开关、第四电阻和第三开关，可以使得接口电路作为数据接收端时既可以满足接口协议中对直流信号耦合方式的规定，也可以满足接口协议中对交流信号耦合方式的规定。例如，当第一设备采用接口协议所支持的交流耦合方式的接口(例如DP、USB3接口、USB4接口或者新接口)进行数据传输时，可 以断开第二开关、导通第三开关；当第一设备采用接口协议所支持的直流耦合方式的接口(例如HDMI或者新接口)进行数据传输时，可以导通第二开关、断开第三开关。
基于上述方式一和方式二，在一种可能的实现方式中，所述端口物理层包括至少一个发射器和至少一个接收器；所述至少一个发射器中的第一发射器和所述至少一个接收器中的第一接收器耦合至所述数据传输装置中的同一条线缆。
第二方面，本申请实施例提供一种电子设备，该电子设备包括物理接口以及如第一方面所述的接口电路；所述接口电路通过所述物理接口与数据传输装置中的数据传输端以及指示器耦合。
在一种可能的实现方式中，所述接口包括第一连接端和第二连接端；所述接口电路的数据传输端耦合至所述第一连接端；所述接口电路的接口指示端耦合至所述第二连接端。
第三方面，本申请实施例提供一种数据传输装置，所述数据传输装置耦合在第一设备和第二设备之间，用于在第一设备和第二设置之间进行数据传输，所述数据传输装置包括：指示器，与所述第一设备中的接口电路耦合，用于向所述接口电路提供指示信息，所述指示信息用于指示所述第二设备的数据传输接口协议。
在一种可能的实现方式中，所述数据传输装置还包括：多条线缆，所述多条线缆用于耦合所述第一设备和所述第二设备，以使所述第一设备和所述第二设备之间通过所述多条线缆进行数据传输。
在一种可能的实现方式中，所述数据传输装置还包括用于与所述第一设备耦合的第一转接头和与所述第二设备耦合的第二转接头；所述第一转接头包括第一数据传输端和接口指示端，所述多条线缆中的每条线缆的第一端耦合至所述第一数据传输端，所述转接器耦合至所述接口指示端；所述第二转接头包括第二数据传输端，所述多条线缆中的每条线缆的第二端耦合至所述第二数据传输端。
在一种可能的实现方式中，指示信息为模拟信号，所述指示器包括第五电阻，所述第五电阻的一端耦合至所述第一转接头的接口指示端，所述第五电阻的另一端耦合至地端。
在一种可能的实现方式中，指示信息为数字信号，所述指示器包括寄存器；所述寄存器用于存储数据，所述数据用于指示所述第二设备中数据传输接口的协议类型。
第四方面，本申请实施例提供一种数据传输系统，该数据传输系统包括如第二方面所述的电子设备以及如第三方面所述的数据传输装置。
第五方面，本申请实施例提供一种数据传输方法，所述数据传输方法应用于接口电路，所述接口电路通过数据传输装置与第一设备进行数据传输，所述接口电路包括接口指示端和数据传输端，所述方法包括：所述接口电路通过所述接口指示端从所述数据传输装置的指示器获取指示信息，所述指示信息用于指示所述第一设备的数据传输接口协议；所述接口电路通过所述数据传输端，采用所述指示信息指示的所述第一设备的数据传输接口协议，向所述第一设备传输数据。
基于第五方面，在一种可能的实现方式中，所述接口电路包括多个接口控制器、多路选择器、端口物理层和模式控制器；以及所述接口电路通过所述数据传输端，采用所述指示信息指示的所述第一设备的数据传输接口协议，向所述第一设备传输数据，包 括：所述模式控制器通过所述接口指示端从所述数据传输装置的指示器获取指示信息，基于所述指示信息，控制所述多路选择器将所述多个接口控制器中的第一接口控制器与所述端口物理层连通，其中，所述第一接口控制器与所述第一设备具有相同的所述数据传输接口协议；所述接口控制器控制所述端口物理层采用所述数据传输协议，通过所述数据传输端向所述第一设备传输数据。
基于第五方面，在一种可能的实现方式中，所述方法还包括：所述模式控制器基于所述指示信息，调整所述端口物理层中发射器和接收器中以下参数的至少一项：信号传输速率或者所传输的信号的幅度。
基于第五方面，在一种可能的实现方式中，所述接口电路包括多个接口控制器、多个端口物理层、开关组和模式控制器，所述多个接口控制器、所述多个端口物理层和所述开关组中的多个开关一一对应耦合；以及所述接口电路通过所述数据传输端，采用所述指示信息指示的所述第一设备的数据传输接口协议，向所述第一设备传输数据，包括：所述模式控制器通过所述接口指示端从所述数据传输装置的指示器获取指示信息，基于所述指示信息，控制所述开关组中的第一开关导通；所述多个接口控制器中与所述第一开关对应的第一接口控制器，控制所述多个端口物理层中与所述第一接口控制器和所述第一开关耦合的第一端口物理层，采用所述数据传输协议，通过所述数据传输端向所述第一设备传输数据。
基于第五方面，在一种可能的实现方式中，所述指示器为电阻，所述指示信息为模拟信号。
基于第五方面，在一种可能的实现方式中，所述指示器为寄存器，所述指示信息为数字信号。
基于第五方面，在一种可能的实现方式中，所述接口电路向所述第一设备传输数据之前，所述方法还包括：所述接口电路采用直流耦合方式或者交流耦合方式与所述第一设备建立连接。
应当理解的是，本申请的第二至五方面与本申请的第一方面的技术方案一致，各方面及对应的可行实施方式所取得的有益效果相似，不再赘述。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例的描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一个系统架构示意图；
图2是本申请实施例提供的接口电路的一个结构示意图；
图3是本申请实施例提供的接口芯片的一个结构示意图；
图4是本申请实施例提供的模式控制器的一个结构示意图；
图5是本申请实施例提供的模式控制器的又一个结构示意图；
图6是本申请实施例提供的模式控制器的又一个结构示意图；
图7是本申请实施例提供的模式控制器的又一个结构示意图；
图8是本申请实施例提供的模式控制器的又一个结构示意图；
图9是本申请实施例提供的接口电路的又一个结构示意图；
图10是本申请实施例提供的如图9所示的接口电路中开关组的一个结构示意图；
图11是本申请实施例提供的如图9所示的接口电路中开关组的又一个结构示意图；
图12是本申请实施例提供的接口作为信号发射接口时接口电路的外围电路示意图；
图13是本申请实施例提供的接口作为信号发射接口时的一个等效电路示意图；
图14是本申请实施例提供的接口作为信号发射接口时的又一个等效电路示意图；
图15是本申请实施例提供的接口作为信号接收接口时接口电路的外围电路示意图；
图16是本申请实施例提供的接口作为信号接收接口时的一个等效电路示意图；
图17是本申请实施例提供的接口作为信号接收接口时的又一个等效电路示意图；
图18a是本申请实施例提供的接口电路的又一个外围电路示意图；
图18b是本申请实施例提供的接口电路的又一个外围电路示意图；
图19是本申请实施例提供的设备101的又一个系统架构示意图
图20是本申请实施例提供的数据传输方法的一个流程图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本文所提及的"第一"、"第二"以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，"一个"或者"一"等类似词语也不表示数量限制，而是表示存在至少一个。"连接"或者"相连"等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的，等同于广义上的耦合或联通。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。在本申请实施例的描述中，除非另有说明，“多个”的含义是指两个或两个以上。例如，多个接口控制器是指两个或两个以上的接口控制器；多个发射器是指两个或两个以上的发射器。
本申请实施例中所述的接口可以为物理接口，该物理接口是指与传输线或者转接器等外部设备相连接的连接头；本申请实施例中所述的接口电路可以包括电路板或者芯片。接口电路耦合至接口，通过接口实现与外部设备的数据传输。
请参考图1，图1为本申请实施例提供的一个系统架构示意图。在图1中，包括设备101和设备102。其中，设备101和设备102可以包括但不限于：主机、显示器、电视机、机顶盒、一体化电脑(例如笔记本电脑或者一体化台式电脑)、游戏机、U盘或者移动硬盘等各种电子设备。这里的主机可以为集成有处理器和存储器等器件但不具有显示功能的设备，其可以驱动显示器运行。设备101设置有接口A11，设备102设置有 接口A21，设备101和设备102之间可以通过接口通信，以进行数据交换。在一种可能的实现方式中，设备101和设备102为不同类型的设备。例如，设备101为主机，设备102为显示器；再例如，设备101为机顶盒，设备102为电视机、显示器或者一体化电脑中的一种。
基于如图1所示的系统架构中，在本申请实施例中，设备102的接口A21可以为传统接口。该传统接口包括但不限于以下之一：高清多媒体接口(HDMI，High Definition Multimedia Interface)、显示接口(DP，DisplayPort)或者通用串行总线(Universal Serial Bus，USB)接口。此外，设备102的接口A21还可以为新规定的接口，本申请实施例中将此种类型的接口简称为新接口，该新接口可以基于新接口规定的接口协议通信。设备101可以基于设备102的接口A21的类型，将接口A11配置为与设备102相匹配的接口。本申请实施例中将该种可以匹配多种协议类型的接口称为多协议接口。这里的匹配可以理解为：采用与设备102的接口A21相同的接口协议与设备102通信。举例来说，当设备102的接口A21为新接口时，设备101和设备102可以基于新接口规定的协议进行通信；当设备102的接口A21为HDMI时，设备101可以基于HDMI的接口协议，通过接口A11与设备102通信；当设备102的接口A21为DP时，设备101可以基于DP的接口协议，通过接口A11与设备102通信。具体的，设备101中可以设置有接口电路10，接口电路10与接口A11耦合。该接口电路10可以通过软件、硬件或二者结合实现。该接口电路10可以包括控制器、可编程逻辑器件(PLC，Programmable Logic Controller)、晶体管器件、或者分立硬件组件等。接口电路10中可以设置有HDMI、DP、USB接口或者新接口等多种类型的接口控制器，设备101中的接口电路10基于设备102的接口类型，使得其中一种接口控制器使能，从而使得接口A11与接口A21相匹配。本申请实施例所示的设备101中通过设置接口电路10，实现同一个接口可以与多种接口类型的电子设备进行数据的传输。与传统电子设备中设置多种类型的接口相比，降低了接口所占用的电子设备的版图面积，从而有利于实现高集成度以及小体积的电子设备。关于接口电路10的具体描述参考下文中图2-图18b所示的实施例的相关描述。
如图1所示的系统架构中，还包括数据传输装置，该数据传输装置可以包括但不限于：传输线或者转接器。设备101的接口A11和设备102的接口A21之间通过数据传输装置连接。转接器与传输线的差别在于传输线中设置有用于进行数据传输的线缆，转接器中没有设置线缆，转接器与传输线的其余结构均相同。为了便于描述，本申请实施例中以数据传输装置为传输线103为例进行描述。图1示意性的示出了设备101与设备102通过传输线103连接的情况。本申请实施例中所述的传输线或转接器中转接头的类型，通常要与传输线或转接器所连接的设备的接口的类型匹配。这里的匹配，意思是指转接头的一端可以插入设备101中。以如图1所示的传输线103为例，传输线103包括转接头C11和转接头C21。转接头C11用于与接口A11连接，其可以与接口A11相匹配，转接头C21用于与接口A21连接，其可以与接口A21相匹配。以设备101为主机、设备102为显示器(其接口为HDMI)为例，对传输线103与设备101和设备102之间的连接更为详细的描述。由于设备101的接口A11为多协议接口，该多协议接口的物理外观可以不同于任意传统协议接口的物理外观，因此，传输线103中用于与接口A11连接的转接头，其转接头的物理外观可以设计成能够插入接口A11的物理外观，实现与接口A11的连接；传输线103 中用于与接口A21连接的转接头，需要设计成HDMI类型的物理外观以插入设备102中，实现与接口A21的连接。从而，设备101可以通过传输线103与设备102进行数据传输。
本申请实施例中所述的传输线103，可以设置有多条用于进行数据传输的线缆C。其用于进行数据传输的线缆C的数目，可以是基于传统的接口传输线协议设置的。例如，基于传统的接口传输线协议设置4条线缆以进行4路数据传输、或者基于传统的接口传输线协议设置8条线缆以进行8路数据传输。图1中示意性的示出了传输线103设置4条线缆C的情况。本申请实施例所述的传输线或者转接器中，除了设置有用于进行数据传输的线缆外，还设置有指示器Z，该指示器Z用于指示设备102中与多协议接口连接的接口的类型。
如图1所示的传输线103中，与多协议接口连接的转接头C11可以包括数据传输端C111和接口指示端C112，数据传输端C111与线缆C的一端耦合，接口指示端C112与指示器Z耦合；与传统接口连接的转接头C21可以包括数据传输端C211，该数据传输端C211与线缆C的另一端耦合。线缆C通过数据传输端C111与接口A11耦合、以及通过数据传输端C211与接口A21耦合，实现设备101和设备102之间的数据传输。指示器Z通过接口指示端C112和接口A11，与设备101中的接口电路10耦合。从而，接口电路10可以基于指示器Z输出的信号，确定设备102的接口类型，以采用与设备102相同的接口协议与设备102通信。如图1所示的接口A11可以包括连接端A111和连接端A112，其中，连接端A111用于与传输线103中的数据传输端C111耦合，连接端A112用于与传输线103中的接口指示端C112耦合。如图1所示的接口A21可以包括数据传输端A211，数据传输端A211用于与传输线103的转接头C21中的数据传输端C211耦合。实际产品的一种可能的实现方式中，传输线103中的线缆C和指示器Z可以被绝缘层包裹在内部，不裸露在外面；此外，传输线103的转接头C11中，数据传输端C111和接口指示端C112可以集成在一起，同样，接口A11中的连接端A111和连接端A112可以集成在一起。这样一来，用户在使用时，可以不需要分辨各连接端，直接将转接头C11插入接口A11即可，提高用户使用的便利性。
基于图1所示的系统架构，下面结合图2-图18b所示的实施例，对本申请实施例中所述的接口电路10的结构、传输线103中所设置的指示器的结构以及接口电路和指示器的工作原理进行详细描述。
请继续参考图2，图2示出了本申请实施例提供的接口电路10的结构示意图。接口电路10可以是集成于设备内的模组、芯片、芯片组、搭载有芯片或芯片组的电路板或部件。在图2中，接口电路10包括多个接口控制器(HDMI控制器01、DP控制器02、USB接口控制器03和新接口控制器04)、多路选择器07、模式控制器05和端口物理层(PHY，Port Physical Layer)06。在本申请实施例中，上述多个接口控制器、多路选择器07和端口物理层06可以集成于一个或多个芯片中。所述一个或多个芯片可以被视为是一个芯片组。可选的，上述多个接口控制器、多路选择器07和端口物理层06可以集成于同一个芯片中，当多个接口控制器、多路选择器07和端口物理层06集成于同一个芯片时，该芯片也叫接口芯片，如图3所示，该接口芯片可以集成于电子设备101中的系统级芯片(Soc，System on chip)中。此外，模式控制器05可以集成于接口芯片中，也可以设置于接口芯片之外。另外，接口电路10可以独立封装和销售。接口电路10还包括数据传输端J1和 接口指示端J2。信号连接端J1通过接口A11的连接端A111与传输线103中的多条线缆耦合；接口指示端J2通过接口A11的连接端A112与传输线103中的指示器Z耦合。上述多个接口控制器可以包括如图2所示的HDMI控制器01、DP控制器02、USB接口控制器03、新接口控制器04以及其他已知或未知的接口控制器。此外，接口电路10中还可以设置有存储器或寄存器(图中为示出)，以存储上述各接口控制器运行所需的软件程序或代码。上述各接口控制器可以调用存储器或寄存器中存储的全部或部分计算机程序，以实现相应类型的接口。需要说明的是，上述多个接口控制器中的每一个接口控制器所运行的计算机程序均不同，每一个接口控制器所运行的计算机程序在存储器或者寄存器中可以分别独立存储。
在图2中，多路选择器07包括第一端Vi1、第二端Vi2、第三端Vi3和第四端Vi4，HDMI控制器01与第一端Vi1耦合，DP控制器02与第二端Vi2耦合，USB接口控制器03与第三端Vi3耦合，新接口控制器04与第四端Vi4耦合；多路选择器07的第五端Vo1与端口物理层06的第一端Vi5耦合；端口物理层06的第二端Vo2耦合至接口电路10的数据传输端J1，从而与接口A11的连接端A111耦合。此外，多路选择器07还包括控制端Vc1，端口物理层06还包括控制端Vc2，模式控制器05的输出端Vo3分别与多路选择器07的控制端Vc1以及端口物理层06的控制端Vc2耦合；模式控制器05的信号输入端Vi6耦合至接口电路10的接口指示端J2，从而与接口A11的连接端A112耦合。
多路选择器07可以为多选一数字选择器。多路选择器07基于模式控制器05输入的信号的控制，将多个接口控制器的其中一个与端口物理层06连接。以接口控制器包括HDMI控制器、DP控制器、USB接口控制器以及新接口控制器为例，上述多路选择器可以为四选一数字选择器，此外该多路选择器的控制端Vc1输入的控制信号可以包括2位控制位。例如，“00”代表选通HDMI控制器01，“01”代表选通DP控制器02，“10”代表选通USB接口控制器03，“11”代表选通新接口控制器04。
端口物理层06用于实现信号收发。其中，端口物理层06可以包括多个发射器TX(或者多个接收器RX)。端口物理层06可以对多个控制器中的一个控制器发送的数据按照设备102所采用的接口协议的接口协议规则进行编码，将编码后的数据转换成模拟信号发射(或者对传输线103提供的模拟信号按照设备102所采用的接口协议的接口协议规则解码，将解码后的数据提供至多个控制器中的一个控制器)。如图2所示的接口电路10中，多个接口控制器复用端口物理层06中的发射器TX(或者接收器RX)以实现多协议接口。由于不同的接口协议，发射器TX(或者接收器RX)的参数设置不同。为了实现多协议接口，端口物理层06可以通过控制端Vc2从模式控制器05接收控制信号，基于该控制信号调整发射器TX(或者接收器RX)的参数。其中，发射器TX(或者接收器RX)的参数可以包括但不限于：信号传输速率或者所传输的信号的幅度。本申请实施例中，对发射器TX(或者接收器RX)的参数的调整方式可以与多路选择器07的选通方式相同。例如，当接口A11可以实现HDMI协议、DP协议、USB接口协议以及新接口协议时，端口物理层06的控制端Vc2输入的控制信号可以包括2位控制位。其中，“00”代表将发射器TX(或者接收器RX)的参数调整为HDMI协议的参数，“01”将发射器TX(或者接收器RX)的参数调整为DP协议的参数，“10”代表将发射器TX(或者接收器RX)的参数调整为USB接口协议的参数，“11”代表将发射器TX(或者接收器RX)的参数调整为新接口协 议的参数。需要说明的是，传统接口电路中仅设置一种接口协议类型的控制器，传统接口电路中的端口物理层仅设置有诸如发射器或者接收器等物理硬件，该物理硬件仅用于实现一种接口协议类型，不存在多协议复用的问题。本申请实施例中所述的端口物理层06，所包括的硬件设备可以与传统接口电路中所包括的物理硬件相同或类似，例如包括发射器、接收器以及诸如电容和电阻等分立器件。此外，由于本申请实施例所述的端口物理层06可以被多种类型的接口协议复用，在其他可能的实现方式中，端口物理层06还可以包括多路选择器07以及模式控制器06。本申请实施例中将多路选择器07和模式控制器06设置于端口物理层06之外进行描述。
模式控制器05可以为可编程逻辑器件或者分立器件。模式控制器05基于接口A11的连接端A112输入的信号，控制多路选择器07将多个接口控制器中的一个接口控制器与端口物理层06耦合；此外，模式控制器05基于接口A11的连接端A112输入的信号，还可以控制端口物理层06中相应电路单元工作。需要说明的是，由于本申请实施例中所述的模式控制器05需要与如图1所示的传输线103中的指示器Z相互配合，以检测传输线103的另一端所连接的设备102的接口类型。因此，模式控制器05的结构与传输线103中的指示器Z的结构相关联。下面通过几种可能的实现方式对本申请实施例中所述的模式控制器05的结构以及指示器的结构进行详细描述。
请参考图4，图4示意性的示出了模式控制器05和指示器Z的第一种结构示意图。在图4中，指示器可以为电阻R1，其中不同的电阻值用于指示不同的协议接口。例如，用于指示HDMI的电阻值可以为100KΩ，用于指示DP的电阻值可以为200KΩ，用于指示USB接口的电阻值可以为800KΩ，用于指示新接口的电阻值可以为1600KΩ。模式控制器05可以包括比较器B，比较器B的第一输入端耦合至公共地Gnd，比较器B的第二输入端耦合至模式控制器05的信号输入端Vi6，比较器B的输出端耦合至模式控制器05的输出端Vo3。在如图4所示的模式控制器05中还包括电阻R2，电阻R2的阻值例如可以为400KΩ。电阻R2的一端耦合至比较器B的第二输入端，电阻R2的另一端用于与模式控制器05的供电端Vcc连接。当传输线103的转接头C11插入接口A11中时，接口A11的连接端A112与转接头C11中的接口指示端C112耦合，电阻R1并联在比较器B的第一输入端和第二输入端之间。此时，比较器B的第二输入端的电压为Vcc*(R1/(R1+R2))。比较器B可以为多阈值比较器。也即是说，比较器B中可以设置有多个阈值，比较器B将第二输入端的电压值与多个阈值进行比较，基于比较结果，输出控制信号。假设设备101可以实现四种协议的接口，则比较器B中可以设置三个阈值，比较器B的输出端输出两比特位的信号。可以理解的是，比较器B中所设置的阈值的数目以及所输出的比特位的数目可以基于所实现的协议种类的数目确定，本申请实施例对此不做限定。
基于图4所示的模式控制器05和指示器Z的第一种结构示意图，下面以指示器Z中用于指示HDMI的电阻值为100KΩ、用于指示DP的电阻值为200KΩ，用于指示USB接口的电阻值为800KΩ、用于指示新接口的电阻值可以为1600KΩ为例，对如图2所示的接口电路10的工作原理进行详细描述。此时，模式控制器05中可以设置阈值1/4*Vcc，1/2*Vcc，3/4*Vcc该三个阈值。假设电阻R1接入比较器B的第一输入端和第二输入端后使得比较器B的第二输入端的电压为1/5*Vcc，该电压值小于任意阈值，此时比较器B可以输出控制信号“00”。该控制信号“00”分别输入至多路选择器07的控制端Vc1和端 口物理层06的控制端Vc2，以使得HDMI控制器01与端口物理层06之间形成通路，此外将端口物理层06中的发射器TX(或者接收器RX)的参数设置成HDMI协议的参数，从而实现设备101和设备102之间采用HDMI协议进行数据传输。假设电阻R1接入比较器B的第一输入端和第二输入端后使得比较器B的第二输入端的电压为1/3*Vcc，该电压值大于1/4*Vcc、且小于1/2*Vcc，此时比较器B可以输出控制信号“01”。该控制信号“01”分别输入至多路选择器07的控制端Vc1和端口物理层06的控制端Vc2，以使得DP控制器02与端口物理层06之间形成通路，此外将端口物理层06中的发射器TX(或者接收器RX)的参数设置成DP协议的参数，从而实现设备101和设备102之间采用DP协议进行数据传输。假设电阻R1接入比较器B的第一输入端和第二输入端后使得比较器B的第二输入端的电压为2/3*Vcc，该电压值大于1/2*Vcc、且小于3/4*Vcc，此时比较器B可以输出控制信号“10”。该控制信号“10”分别输入至多路选择器07的控制端Vc1和端口物理层06的控制端Vc2，以使得USB接口控制器03与端口物理层06之间形成通路，此外将端口物理层06中的发射器TX(或者接收器RX)的参数设置成USB接口协议的参数，从而实现设备101和设备102之间采用USB接口协议进行数据传输。假设电阻R1接入比较器B的第一输入端和第二输入端后使得比较器B的第二输入端的电压为4/5*Vcc，该电压值大于3/4*Vcc，此时比较器B可以输出控制信号“11”。该控制信号“11”分别输入至多路选择器07的控制端Vc1和端口物理层06的控制端Vc2，以使得新接口控制器04与端口物理层06之间形成通路，此外将端口物理层06中的发射器TX(或者接收器RX)的参数设置成新接口协议的参数，从而实现设备101和设备102之间采用新接口协议进行数据传输。
如图4所示的模式控制器05的结构，是采用电阻分压的方式使得比较器B的第二输入端的电压，基于电阻R1的阻值的不同而不同。在第二种可能的实现方式中，还可以采用固定电流源输出电流通过电阻的方式，使得第二输入端的电压基于电阻R1的阻值的不同而不同。具体如图5所示。在图5中，指示器Z包括电阻R1，其中不同的电阻值用于指示不同的协议接口。具体与图4所述的电阻器件R1相同，在此不再赘述。与图4所示的模式控制器05的结构不同的是，在图5中，模式控制器05除了包括比较器B外，还包括电流源I。电流源I的输入端耦合至供电端Vcc，输出端耦合至比较器B的第二输入端。也即是说，图4中的电阻在图5中被替换成电流源，其余器件以及各器件之间的连接关系与图4所示的各器件以及器件之间的连接关系相同。在此不再赘述。具体工作中，电流源产生的电流经电阻R1流至公共地Gnd，此时比较器B的第二输入端的电压即为R1*I。由于指示不同接口的电阻值不同，对于不同的接口类型，其输入至比较器B的第二输入端的电压不同。通过设置比较器B的参考电压值，即可实现模式控制器05对多路选择器07和端口物理层06的控制。
在图4和图5所示的模式控制器05中，是通过设置比较器B的方式实现输入信号和输出信号的转换。在其他可能的实现方式中，比较器B可以由模数转换器(ADC，Analog-to-Digital Converter)来替代。模式控制器05中所包括的其余各部件以及各部件之间的连接关系均可参考图4或图5所示的模式控制器05中的各部件以及各部件之间的连接关系，在此不再赘述。其中，比较器B被替换成ADC的电路结构如图6和图7所示。下面以图6所示的模式控制器05的电路结构为例，对模式控制器05的工作原理进行描述。首先可 以在ADC中预先设置输入模拟信号与输出数字信号之间的转换关系，该转换关系基于ADC的内部电路设计实现。电阻R1接入ADC的第一输入端和第二输入端后使得ADC的第二输入端的电压为某一电压值，该电压值通过ADC转换成数字信号以对多路选择器07和端口物理层06进行控制。
在如图4-图7所示的指示器Z的结构中，指示器Z均采用电阻器件，通过电阻器件的分压或者通过固定的电流来识别对端设备102的接口类型。在另外一种可能的实现方式中，指示器Z可以为寄存器，该寄存器中存储有用于指示接口类型的值。假设接口种类包括四种，则在寄存器中采用2比特位即可实现对各接口类型的指示。例如，“00”代表HDMI，“01”代表DP，“10”代表USB接口，“11”代表新接口。此外，当需要设置更多种类接口时，可以在寄存器中增加更多个比特位。当指示器Z为寄存器时，模式控制器05中可以设置有读取器，该读取器用于读取寄存器中存储的数据。其中，读取器可以为逻辑器件，读取器的接地端耦合至公共地Gnd，读取器的信号读取端耦合至模式控制器05的信号输入端Vi6，读取器的输出端耦合至模式控制器05的输出端Vo3，读取器的供电端耦合至模式控制器05的供电端Vcc。当传输线103的转接头C11插入接口A11时，指示器Z与模式控制器05之间的连接关系如图8所示。此时，模式控制器05的供电端Vcc用于从外部输入供电电压，模式控制器05的输出端Vo3与多路选择器07以及端口物理层06的控制端耦合，模式控制器05的输入端Vi6通过连接端A112与指示器Z的输出端耦合，指示器Z的接地端与指示器Z的接地端共同耦合至接口电路10的公共地Gnd。在如图8所示的实现方式中，模式控制器05中可以预先存储有寄存器中存储的数据-接口类型-控制信号三者之间的对应关系表，当传输线103的转接头C11插入接口A11时，模式控制器05可以读取指示器Z中存储的数据，基于上述对应关系表，将所读取的数据转换成控制信号输入至多路选择器的控制端Vc1。从而多路选择器07基于该控制信号，在其中一个接口控制器与端口物理层06之间形成通路。
如图2-图8所示的接口电路10中，设置有一个端口物理层06，多个控制器复用该一个端口物理层06。在其他可能的实现方式中，接口电路可以设置有多个端口物理层06，每一个端口物理层06支持一种协议接口。下面以接口电路用于实现HDMI、DP和USB接口协议的接口为例进行详细描述。请继续参看图9，图9示出了本申请实施例提供的接口电路10的又一种结构示意图。在图9中，包括HDMI控制器01、DP控制器02、USB接口控制器03、HDMI端口物理层061、DP端口物理层062和USB端口物理层063。其中，HDMI控制器01的输出端与HDMI端口物理层061耦合、DP控制器02的输出端与DP端口物理层062耦合、USB接口控制器03的输出端与USB端口物理层063耦合。此外，在图9中，还包括开关组SW、模式控制器05和接口A11。接口A11的具体结构参考图1中所述的接口A11的相关描述，在此不再赘述。开关组SW包括开关K1、开关K2和开关K3。其中，开关K1的第一端耦合于HDMI端口物理层061的输出端、开关K2的第一端耦合于DP端口物理层062的输出端、开关K3的第一端耦合于USB端口物理层063的输出端，开关K1的第二端、开关K2的第二端和开关K3的第二端均耦合至接口电路10的数据传输端J1，以与接口A11的连接端A111耦合。模式控制器05包括多个输出端，其中输出端Vo4用于控制开关K1的导通或者关断、输出端Vo5用于控制开关K2的导通或者关断、输出端V o6用于控制开关K3的导通或者关断。模式控制器05的输入端 Vi6耦合至接口电路10的接口指示端J2，以与接口A11的连接端A112耦合。如图9所示的每一个端口物理层的结构与如图2所示的端口物理层06的结构详图，具体参考图2所示的端口物理层06的相关描述，在此不再赘述。需要说明的是，由于图9所示的每一个端口物理层专用于一种接口协议，各端口物理层中发射器(或者接收器)的参数均对应于一种接口协议参数，其参数不需要时时改变，因此，图9所示的每一个端口物理层均不需要与模式控制器05的输出端耦合。此外，图9所示的模式控制器05基于线缆C中指示器Z的类型，可以包括数模转换器或者读取器。当模式控制器05包括数模转换器时，其所包括的器件以及输出端与各器件之间的连接关系与图9-图7所示的模式控制器05相同。此时，数模转换器基于输入端输入的模拟电压信号转换成三比特位的数字信号，分别通过输出端Vo4、输出端Vo5和输出端Vo6输出，以控制开关K1、开关K2和开关K3的通断状态。例如，“100”代表开关K1导通，“010”代表开关K2导通，“001”代表开关K3导通。另外，数模转换器基于输入端输入的模拟电压信号也可以转换成2比特位的数字信号，例如，“00”代表开关K1导通，“01”代表开关K2导通，“10”代表开关K3导通。此时，模式控制器05可以仅设置输出端Vo4和输出端Vo5，不设置输出端Vo6，图中未示出该种情况。当模式控制器05包括读取器时，其所包括的器件以及输出端与各器件之间的连接关系与图8所示的模式控制器05相同。此时，读取器将所读取数据的转换成三比特位的数字信号，分别通过输出端Vo4、输出端Vo5和输出端Vo6输出，以控制开关K1、开关K2和开关K3的通断状态。需要说明的是，图9示意性的示出了控制器包括三种、端口物理层包括相应的三种、开关组SW中包括开关K1、开关K2和开关K3的情况。本申请实施例对接口电路10所包括的控制器的类型以及数目不做具体限定，根据应用场景的需要设置。相应的，端口物理层的数目以及开关组SW所包括的开关的数目均不作具体限定，其基于控制器的类型以及数目进行设定。相应的，模式控制器05所输出的数字信号的比特位数也基于开关组SW所包括的开关的数目而定。例如，接口电路10中还可以包括新接口控制器，此时，接口电路10中还需要设置新接口端口物理层，同样，开关组SW中还可以设置有开关K4，模式控制器05所输出的数字信号例如还可以是4比特位。
如图9所示开关组SW中的开关可以为模拟开关。开关组SW具体可以通过如下三种可能的方式实现。
在第一种可能的实现方式中，开关K1、开关K2和开关K3为单刀单掷开关，如图9所示。
在第二种可能的实现方式中，开关K1、开关K2和开关K3中的每一个开关，是由多个晶体管组成，如图10所示。具体的，每一个开关均设置有晶体管Q1和晶体管Q2。其中，晶体管Q1可以为NMOS晶体管，晶体管Q2可以为PMOS晶体管；或者晶体管Q1可以为PMOS晶体管，晶体管Q2可以为NMOS晶体管。以晶体管Q1为NMOS晶体管和晶体管Q2为PMOS晶体管为例，对各开关所包括的晶体管的连接关系进行描述。晶体管Q1的第一极、晶体管Q2的第一极以及HDMI端口物理层06的输出端耦合在一起，晶体管Q1的第二极和晶体管Q2的第二极均耦合至接口A11的连接端A111。其中，晶体管Q1的第一极和晶体管Q2的第二极可以为漏极，晶体管Q1的第二极和晶体管Q2的第一极可以为源极。模式控制器05的输出端Vo4与开关K1中的晶体管Q1的栅极耦合，模式 控制器05的输出端Vo4通过反相器(图中未示出)与开关K1中的晶体管Q2的栅极耦合；模式控制器05的输出端Vo5与开关K2中的晶体管Q1的栅极耦合，模式控制器05的输出端Vo5通过反相器(图中未示出)与开关K2中的晶体管Q2的栅极耦合；模式控制器05的输出端Vo6与开关K3中的晶体管Q1的栅极耦合，模式控制器05的输出端Vo6通过反相器(图中未示出)与开关K3中的晶体管Q2的栅极耦合。当模式控制器05基于所接入的传输线中指示器Z所指示的信息(其中用于确定指示器Z所指示的信息的方式具体参考图4-图8所示的实施例中的相关描述)确定出对端设备102所采用的接口协议类型为HDMI时，模式控制器05的输出端Vo4输出高电平信号、输出端Vo5输出低电平信号、输出端Vo6输出低电平信号，此时开关K1中的晶体管Q1和晶体管Q2导通，HDMI端口物理层06的输出端与接口A11的连接端A111连通，设备101可以通过HDMI协议与设备201通信。
在第三种可能的实现方式中，开关K1、开关K2和开关K3中的每一个开关，可以是由更多个晶体管组成的，如图11所示。具体的，每一个开关均设置有晶体管Q3、晶体管Q4、晶体管Q5、晶体管Q6和晶体管Q7。其中，晶体管Q3、晶体管Q5和晶体Q7可以为NMOS晶体管，晶体管Q4和晶体管Q6可以为PMOS晶体管；或者，晶体管Q3、晶体管Q5和晶体Q7可以为PMOS晶体管，晶体管Q4和晶体管Q6可以为NMOS晶体管。以晶体管Q3、晶体管Q5和晶体Q7为NMOS晶体管、晶体管Q4和晶体管Q6为PMOS晶体管为例，对各开关所包括的晶体管的连接关系进行描述。晶体管Q3的第一极、晶体管Q4的第一极以及HDMI端口物理层06的输出端耦合在一起，晶体管Q3的第二极、晶体管Q4的第二极、晶体管Q5的第一极、晶体管Q6的第一极以及晶体管Q7的第一极耦合在一起，晶体管Q5的第二极和晶体管Q6的第一极均耦合至接口A11的连接端A111，晶体管Q7的第二极耦合至公共地。其中，晶体管Q3的第一极、晶体管Q4的第二极、晶体管Q5的第一极、晶体管Q6的第二极和晶体管Q7的第一极可以为漏极，晶体管Q3的第二极、晶体管Q4的第一极、晶体管Q5的第二极、晶体管Q6的第一极和晶体管Q7的第二极可以为源级；或者，晶体管Q3的第一极、晶体管Q4的第二极、晶体管Q5的第一极、晶体管Q6的第二极和晶体管Q7的第一极可以为源极，晶体管Q3的第二极、晶体管Q4的第一极、晶体管Q5的第二极、晶体管Q6的第一极和晶体管Q7的第二极可以为漏级。模式控制器05的输出端Vo4与开关K1中的晶体管Q3的栅极、晶体管Q5的栅极以及晶体管Q7的栅极耦合，模式控制器的输出端Vo4通过反相器(图中未示出)与开关K1中的晶体管Q4的栅极和晶体管Q6的栅极耦合；模式控制器05的输出端Vo5与开关K2中的晶体管Q3的栅极、晶体管Q5的栅极以及晶体管Q7的栅极耦合，模式控制器的输出端Vo5通过反相器(图中未示出)与开关K2中的晶体管Q4的栅极和晶体管Q6的栅极耦合；模式控制器05的输出端Vo6与开关K3中的晶体管Q3的栅极、晶体管Q5的栅极以及晶体管Q7的栅极耦合，模式控制器05的输出端Vo6通过反相器(图中未示出)与开关K3中的晶体管Q4的栅极和晶体管Q6的栅极耦合。当模式控制器05基于所接入的传输线中指示器Z所指示的信息(其中用于确定指示器Z所指示的信息的方式具体参考图4-图8所示的实施例中的相关描述)确定出对端设备102所采用的接口协议类型为HDMI时，模式控制器05的输出端Vo4输出高电平信号、输出端Vo5输出低电平信号、输出端Vo6输出低电平信号，此时开关K1中的各晶体管导通，HDMI端口物理层06的 输出端与接口A11的连接端A111连通，设备101可以通过HDMI协议与设备201通信。
基于如上所述的接口电路10中各电路部件的结构和工作原理，在本申请实施例中，如图1和图2所示的接口A11可以为信号发射接口。此时，设备101通过接口A11向设备102发送数据。此外，接口A11也可以为信号接收接口。此时，设备101通过接口A11从设备102接收数据。需要说明的是，对于某些协议类型的接口，基于协议规定，其信号发射接口和信号接收接口所采用的外围电路不同。另外，在本申请实施例中，不同协议类型的接口，其所支持的信号耦合方式不同。例如，HDMI支持直流信号耦合，DP支持交流信号耦合。为了实现同一个接口适配多种不同协议，本申请实施例所述的接口电路还包括外围电路，以实现接口A11既可以传输例如HDMI协议规定的直流信号，还可以传输例如DP协议规定的交流信号。需要说明的是，这里所述的外围电路，可以理解为除了上述多个接口控制器、多路选择器07、模式控制器05和端口物理层06之外的电路，可以包括但不限于电容、开关和电阻等。其中，信号发射接口的外围电路与信号接收接口的外围电路不同。下面，通过图12-图17所示的实施例进行详细描述。其中，图12-图14示出了如图1所示的接口A11作为信号发射接口时的外围电路示意图；图15-图17示出了如图1所示的接口A11作为信号接收接口时的外围电路示意图。
请参考图12，在图12中，接口电路10还包括多个电容C T1、多个电阻R T1和多个开关K T1。电容C T1、电阻R T1和开关K T1的数目与端口物理层06中所包括的发射器TX的数目相同，也可以说与传输线103中用于传输数据的线缆的数目相同。例如，端口物理层06包括4个发射器TX时，传输线103中用于进行信号传输的线缆的数目为四条，接口电路10中可以包括四个电容C T1、四个电阻R T1和四个开关K T1。一个发射器TX、一个电容C T1、一个电阻R T1和一个开关K T1可以形成一个信号发射通道，从而，设备101可以包括多个信号发射通道，每一个信号发射通道所包括的器件以及各器件之间的连接关系均相同。下面以其中一个信号发射通道为例，对各器件的连接关系进行描述。具体的，电容C T1的一端耦合至发射器TX的输出端，电容C T1的另一端与电阻R T1的其中一端以及接口A11中的连接端A111耦合；电阻R T1的另一端通过开关K T1耦合至公共地Gnd。需要说明的是，本申请实施例中所述的多个电容C T1、多个电阻R T1和多个开关K T1，可以设置于如图3所示接口芯片之外。基于图12所示的电路结构，传输线103的转接头C11插入接口A11后，假设模式控制器05基于指示器Z所指示的信号确定出对端设备102的接口为支持交流信号耦合方式的接口(例如DP、USB3接口、USB4接口或者新接口)，基于接口协议中对交流信号耦合方式的规定，信号发射端需要设置有耦合电容C T1，但不需要设置电阻R T1。此时，模式控制器05可以控制多个开关K T1均断开，如图13所示。基于图12所示的电路结构，传输线103的转接头C11插入接口A11后，假设模式控制器05基于指示器Z所指示的信号确定出对端设备102的接口为支持直流信号耦合方式的接口(例如HDMI或者新接口)，基于接口协议中对直流信号耦合方式的规定，信号发射端需要提供某一电压值的电压，而由于为了满足接口协议中对交流信号耦合方式的规定，在信号发射端设置有电容C T1，电容C T1具有通交流隔直流的作用，此时接口电路10中的电容C T1将发射器TX输出的直流信号阻隔。此时，模式控制器05可以控制多个开关K T1均闭合，以使得电阻R T1耦合在公共地Gnd和对端设备102的接收器RX之间，如图14所示。此外，基于接口协议对直流信号耦合方式的规定，在设备102的接收器RX的输入端设置有上拉 电阻R R1。从而，电阻R T1用于对上拉电阻R R1的供电端输入的电压进行分压，通过调整电阻R T1的阻值，可以使得信号发射接口输出接口协议所规定的某一直流电压。
请参考图15，图15为多协议接口A11作为信号接收端时、接口电路的结构示意图。在图15中，接口电路10还包括多个开关K R1、多个开关K R2、多个电阻R R2和多个电阻R R3。开关K R1、开关K R2、电阻R R2和电阻R R3的数目与端口物理层06中所包括的接收器RX的数目相同，也可以说与传输线103中用于传输数据的线缆的数目相同。例如，端口物理层06包括4个接收器RX时，传输线103中用于进行信号传输的线缆的数目为四条，接口电路10中可以包括四个开关K R1、四个开关K R2、四个电阻R R2和四个电阻R R3。一个发射器RX、一个开关K R1、一个开关K R2、一个电阻R R2和一个电阻R R3可以形成一个信号接收通道，从而，设备101可以包括多个信号接收通道，每一个信号接收通道所包括的器件以及各器件之间的连接关系均相同。下面以其中一个信号接收通道为例，对各器件的连接关系进行描述。具体的，电阻R R2的一端和电阻R R3的一端均耦合至接收器RX的输入端，电阻R R2的另一端通过开关K R1耦合至供电端Vcc，电阻R R3的另一端通过开关K R2耦合至公共地Gnd。也即是说，电阻R R2为上拉电阻，电阻R R3为下拉电阻。可选的，本申请实施例中所述的多个开关K R1、多个开关K R2、多个电阻R R2和多个电阻R R3，可以集成于如图3所示的接口芯片中。基于接口协议中对交流信号耦合方式的规定，信号接收端需要设置下拉电阻R R3，但不需要设置上拉电阻R R2；基于接口协议中对直流信号耦合方式的规定，信号接收端需要设置上拉电阻R R2，但不需要设置下拉电阻R R3。基于此，本申请实施例中，当多协议接口作为信号接收接口时，为了使得多协议接口同时满足接口协议中对交流信号耦合方式以及直流信号耦合方式的规定，将上拉电阻R R2和下拉电阻R R3均集成于接口电路10中，通过开关K R1控制上拉电阻R R2与供电端Vcc之间的通断状态，通过开关K R2控制下拉电阻R R3与公共地Gnd之间的通断状态，从而实现多种协议的信号传输。下面通过具体实施例进行更为详细的说明。基于图15所示的电路结构，传输线103的转接头C11插入接口A11后，假设模式控制器05基于指示器Z所指示的信号确定出对端设备102的接口为支持交流信号耦合方式的接口(例如DP、USB3接口、USB4接口或者未来新接口)，基于接口协议中对交流信号耦合方式的规定，信号接收端需要设置有下拉电阻R R3，但不需要设置上拉电阻R R2。此时，模式控制器05可以控制多个开关K R1均断开、控制多个开关K R2均闭合，如图16所示。基于图15所示的电路结构，传输线103的转接头C11插入接口A11后，假设模式控制器05基于指示器Z所指示的信号确定出对端设备102的接口为支持直流信号耦合方式的接口(例如HDMI或者未来新接口)，基于接口协议中对直流信号耦合方式的规定，信号接收端需要设置有上拉电阻R R2，但不需要设置下拉电阻R R3。此时，模式控制器05可以控制多个开关K R2均断开，控制多个开关K R1均闭合，如图17所示。
在图12-图14所示的实现方式中，示意性的示出了接口A11作为信号发射接口的情况；在图15-图17所示的实现方式中，示意性的示出了接口A11作为信号接收接口的情况。在其他场景中，基于接口协议的规定，接口A11可以为信号收发接口，其可以分时收发信号。举例来说，当接口A11基于DP协议进行信号传输时，在一个通信周期内，接口A11仅用于发射信号或者仅用于接收信号；当接口A11基于USB接口协议进行信号传输时，在一个通信周期内，接口A11在第一时段用于发射信号，在第二时段用于接收信号。 为了使得接口A11在一个通信周期内可以实现信号的收发，接口A11还可以为如图18a和图18b所示的结构。
在图18a中，在端口物理层06中除了设置发射器TX外，还设置有部分接收器RX。其中，发射器TX的外围电路以及与其他部件的连接关系，与图12所示的发射器TX的外围电路以及与其他部件的连接关系相同，在此不再赘述。接收器RX的外围电路以及与其他部件的连接关系与图15所示的接收器RX的外围电路以及与其他部件的连接关系相同，在此不再赘述。基于图18a所示的结构，在一个可能的场景中，传输线103中可以设置4条线缆，此时，端口物理层06可以设置四个发射器TX和两个接收器RX。其中两条线缆仅与端口物理层06中的两个发射器TX耦合，另外两条线缆与另外两个发射器TX和两个接收器RX耦合。当设备102的接口A21为DP接口或者HDMI接口时，端口物理层06中的四个发射器TX使能，接口电路10通过接口A11以及传输线103向设备102发射信号；当设备102的接口A21为USB接口时，端口物理层06中的两个发射器TX和两个接收器RX使能，所使能的两个发射器TX与两个接收器RX耦合不同的线缆。在第一时段，接口电路10中的发射器TX通过接口A11以及传输线103其中的两条线缆向设备102发射信号(或者接口电路10中的接收器RX通过接口A11以及传输线103其中的两条线缆从设备102接收信号)，在第二时段，接口电路10中的接收器RX通过接口A11以及传输线103其中的两条线缆从设备102接收信号(或者接口电路10中的发射器TX通过接口A11以及传输线103其中的两条线缆向设备102发射信号)。
在图18b中，在端口物理层06中除了设置接收器RX外，还设置有部分发射器TX。其中，接收器RX的外围电路以及与其他部件的连接关系，与图15所示的接收器RX的外围电路以及与其他部件的连接关系相同，在此不再赘述。发射器TX的外围电路以及与其他部件的连接关系与图12所示的发射器TX的外围电路以及与其他部件的连接关系相同，在此不再赘述。基于图18b所示的结构，在一个可能的场景中，传输线103中可以设置4条线缆，此时，端口物理层06可以设置四个接收器RX和两个发射器TX。其中两条线缆仅与端口物理层06中的两个接收器RX耦合，另外两条线缆与另外两个接收器RX以及两个发射器TX耦合。当设备102的接口A21为DP接口或者HDMI接口时，端口物理层06中的四个接收器RX使能，接口电路10通过接口A11以及传输线103从设备102接收信号；当设备102的接口A21为USB接口时，端口物理层06中的两个发射器TX和两个接收器RX使能，所使能的两个发射器TX与两个接收器RX耦合不同的线缆。在第一时段，接口电路10中的发射器TX通过接口A11以及传输线103其中的两条线缆向设备102发射信号(或者接口电路10中的接收器RX通过接口A11以及传输线103其中的两条线缆从设备102接收信号)，在第二时段，接口电路10中的接收器RX通过接口A11以及传输线103其中的两条线缆从设备102接收信号(或者接口电路10中的发射器TX通过接口A11以及传输线103其中的两条线缆向设备102发射信号)。
如图1所示的系统架构中，示意性的示出了设备101包括一个接口A11。当设备101需要满足既可以向其他设备发射信号，也可以从其他设备接收信号时，可以在设备101中设置多个接口，其中部分接口用于实现向其他设备发射信号，另外一部分接口实现从其他设备接收信号，如图18所示。图18示意性的示出了设备101包括接口A12、接口A13、接口A14和接口A15的情形。接口A12与接口电路10A耦合，接口A13与接口电路10B 耦合，接口A14与接口电路10C耦合，接口A15与接口电路10D耦合。接口A12、接口A13、接口A14和接口A15可以均为多协议接口。其中，接口A12和接口A13可以为信号发射接口，接口A14和接口A15可以为信号接收接口。此时，接口电路10A和接口电路10B中的端口物理层06包括发射器TX，接口电路10C和接口电路10D中的端口物理层06包括接收器RX。这里所述的信号发射接口，是指基于诸如HDMI协议或者DP协议，在通信周期内仅用于进行信号发射的接口；这里所述的信号接收接口，是指基于诸如HDMI协议或者DP协议，在通信周期内仅用于进行信号接收的接口。当然，在其他可能的实现方式中，在接口电路10A和接口电路10B的端口物理层06中，还可以设置有部分接收器TX，以满足USB接口协议要求，同样，在接口电路10C和接口电路10D的端口物理层06中，还可以设置有部分发射器RX，以满足USB接口协议要求。接口电路10A和接口电路10B的结构、各接口与相应接口电路之间的耦合关系与图2-图14、图18a任意实施例所述的接口电路10以及接口电路10与接口A11之间的耦合关系相同，在此不再赘述；接口电路10C和接口电路10D的结构、各接口与相应接口电路之间的耦合关系与图2-图11、图15-图17、图18b任意实施例所述的接口电路10以及接口电路10与接口A11之间的耦合关系相同，在此不再赘述。
基于同一发明构思，本申请实施例还提供了一种数据传输方法，该数据传输方法应用于如图1所示的数据传输系统。请继续参看图19，其示出了本申请实施例提供的数据传输方法的一个流程2000。该数据传输方法的流程2000包括如下所述的步骤：
步骤2001，接口电路10通过接口指示端从传输线103的指示器Z获取指示信息，指示信息用于指示设备102的数据传输接口协议。
步骤2002，接口电路10通过数据传输端，采用指示信息所指示的设备102的数据传输接口协议，向设备102传输数据。
在一种可能的实现方式中，接口电路10包括如图2所示的多个接口控制器、多路选择器07、端口物理层06和模式控制器05。上述步骤2002进一步包括：模式控制器05基于指示信息，控制多路选择器07将多个接口控制器中的其中一个接口控制器与端口物理层06连通，其中，与端口物理层06连通的接口控制器，与设备102具有相同的数据传输接口协议；与端口物理层06连通的接口控制器，控制端口物理层06采用与设备102相同的数据传输协议，通过接口电路的数据传输端向设备102传输数据。
在一种可能的实现方式中，数据传输方法还包括：模式控制器05基于指示信息，调整端口物理层06中发射器和接收器中以下参数的至少一项：信号传输速率或者所传输的信号的幅度。
在一种可能的实现方式中，接口电路包括如图9所示的多个接口控制器、多个端口物理层、开关组SW和模式控制器05，多个接口控制器、多个端口物理层和开关组SW中的多个开关一一对应耦合。上述步骤2002进一步包括：模式控制器05基于指示信息，控制开关组SW中的其中一个开关导通；与所导通的开关对应的接口控制器，控制与所导通的开关耦合的端口物理层，采用与设备102相同的数据传输协议，通过接口电路的数据传输端向设备102传输数据。
在一种可能的实现方式中，指示器为电阻，指示器的指示信息为模拟信号。
在一种可能的实现方式中，指示器为寄存器，指示器的指示信息为数字信号。
在一种可能的实现方式中，接口电路10向设备102传输数据之前，数据传输方法还包括：接口电路10采用直流耦合方式或者交流耦合方式与设备102建立连接。
以上，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (24)

  1. 一种接口电路，其特征在于，所述接口电路通过数据传输装置与第一设备进行数据传输，所述接口电路包括接口指示端和数据传输端；
    所述接口电路通过所述接口指示端从所述数据传输装置的指示器获取指示信息，所述指示信息用于指示所述第一设备的数据传输接口协议；
    所述接口电路用于通过所述数据传输端，采用所述指示信息指示的所述第一设备的数据传输接口协议，向所述第一设备传输数据。
  2. 根据权利要求1所述的接口电路，其特征在于，所述接口电路包括多个接口控制器、多路选择器、端口物理层和模式控制器；
    所述多个接口控制器中的每一个接口控制器分别耦合至所述多路选择器的多个输入端；
    所述多路选择器的输出端耦合至所述端口物理层第一端；
    所述端口物理层的第二端耦合至所述接口电路的数据传输端；
    所述模式控制器的输入端耦合至所述接口电路的接口指示端，所述模式控制器的输出端耦合至所述多路选择器的第一控制端，所述模式控制器基于所述指示信息，控制所述多路选择器将所述多个接口控制器中的第一接口控制器与所述端口物理层连通。
  3. 根据权利要求2所述的接口电路，其特征在于，所述模式控制器的输出端还耦合于所述端口物理层的第二控制端；所述模式控制器还用于：
    基于所述指示信息，调整所述端口物理层中发射器和接收器中以下参数的至少一项：信号传输速率或者所传输的信号的幅度。
  4. 根据权利要求1所述的接口电路，其特征在于，所述接口电路包括多个接口控制器、多个端口物理层、开关组和模式控制器；
    所述多个接口控制器与所述多个端口物理层的第一端一一对应耦合；
    所述多个端口物理层的第二端通过所述开关组中一一对应的多个开关耦合至所述接口电路的数据传输端；
    所述模式控制器的输入端耦合至所述接口指示端，所述模式控制器的输出端耦合至所述开关组的控制端，所述模式控制器用于基于所述指示信息，控制所述开关组中的任一个开关导通。
  5. 根据权利要求2-4任一项所述的接口电路，其特征在于，所述模式控制器包括比较器和第一电阻；
    所述比较器的第一输入端耦合至地端，所述比较器的第二输入端耦合至所述模式控制器的输入端，所述比较器的输出端耦合至所述模式控制器的输出端；
    所述第一电阻的一端耦合至供电端，所述第一电阻的另一端耦合至所述比较器的第二输入端。
  6. 根据权利要求2-4任一项所述的接口电路，其特征在于，所述模式控制器包括比较器和电流源；
    所述比较器的第一输入端耦合至地端，所述比较器的第二输入端耦合至所述模式控 制器的输入端，所述比较器的输出端耦合至所述模式控制器的输出端；
    所述电流源的一端耦合至供电端，所述电流源的另一端耦合至所述比较器的第二输入端。
  7. 根据权利要求2-4任一项所述的接口电路，其特征在于，所述指示信息为模拟信号，所述模式控制器包括模数转换器和第一电阻；
    所述第一电阻的一端耦合至供电端，所述第一电阻的另一端耦合至所述模数转换器的输入端；
    所述模数转换器的第一输入端耦合至地端，所述模数转换器的第二输入端耦合至所述模式控制器的输入端，所述模数转换器基于所述指示信息，生成数字信号提供至所述模式控制器的输出端。
  8. 根据权利要求2-4任一项所述的接口电路，其特征在于，所述指示信息为模拟信号，所述模式控制器包括模数转换器和电流源；
    所述电流源的一端耦合至供电端，所述电流源的另一端耦合至所述模数转换器的输入端；
    所述模数转换器的第一输入端耦合至地端，所述模数转换器的第二输入端耦合至所述模式控制器的输入端，所述模数转换器基于所述指示信息，生成数字信号提供至所述模式控制器的输出端。
  9. 根据权利要求2-4任一项所述的接口电路，其特征在于，所述指示信息为数字信号，所述模式控制器包括读取器；
    所述读取器用于读取所述指示信息，基于所述指示信息生成控制信号提供至所述模式控制器的输入端。
  10. 根据权利要求2-9任一项所述的接口电路，其特征在于，所述端口物理层包括发射器，所述发射器用于通过所述数据传输装置向所述第一设备传输数据；以及
    所述接口电路还包括电容、第二电阻和第一开关；
    所述电容的第一端耦合至所述发射器的输出端，所述电容的第二端和所述第二电阻的一端耦合至所述接口电路的数据传输端；
    所述第二电阻的另一端通过所述第一开关耦合至地端。
  11. 根据权利要求2-10任一项所述的接口电路，其特征在于，所述端口物理层还包括接收器，所述接收器用于通过所述数据传输装置从所述第一设备接收数据；以及
    所述接口电路还包括第三电阻、第二开关、第四电阻和第三开关；
    所述第三电阻的第一端通过所述第二开关耦合至供电端；
    所述第三电阻的第二端、所述第四电阻的第一端、所述接收器的接收端均耦合至所述接口电路的数据传输端；
    所述第四电阻的第二端通过所述第三开关耦合至地端。
  12. 一种电子设备，其特征在于，所述电子设备包括：
    物理接口；
    如权利要求1-11任一项所述的接口电路；
    所述接口电路通过所述物理接口与数据传输装置中的数据传输端以及指示器耦合。
  13. 根据权利要求12所述的电子设备，其特征在于，所述物理接口包括第一连接端和第二连接端；
    所述接口电路的数据传输端耦合至所述第一连接端；
    所述接口电路的接口指示端耦合至所述第二连接端。
  14. 一种数据传输装置，其特征在于，所述数据传输装置耦合在第一设备和第二设备之间，用于在第一设备和第二设置之间进行数据传输，所述数据传输装置包括：
    指示器，与所述第一设备中的接口电路耦合，用于向所述接口电路提供指示信息，所述指示信息用于指示所述第二设备的数据传输接口协议。
  15. 根据权利要求14所述的数据传输装置，其特征在于，所述数据传输装置还包括：
    多条线缆，所述多条线缆用于耦合所述第一设备和所述第二设备，以使所述第一设备和所述第二设备之间通过所述多条线缆进行数据传输。
  16. 根据权利要求15所述的数据传输装置，其特征在于，所述数据传输装置还包括用于与所述第一设备耦合的第一转接头和与所述第二设备耦合的第二转接头；
    所述第一转接头包括第一数据传输端和接口指示端，所述多条线缆中的每条线缆的第一端耦合至所述第一数据传输端，所述转接器耦合至所述接口指示端；
    所述第二转接头包括第二数据传输端，所述多条线缆中的每条线缆的第二端耦合至所述第二数据传输端。
  17. 根据权利要求14-16任一项所述的数据传输装置，其特征在于，所述指示信息为模拟信号，所述指示器包括第五电阻，所述第五电阻的一端耦合至所述第一转接头的接口指示端，所述第五电阻的另一端耦合至地端。
  18. 根据权利要求14-16任一项所述的数据传输装置，其特征在于，所述指示信息为数字信号，所述指示器包括寄存器；
    所述寄存器用于存储数据，所述数据用于指示所述第二设备中数据传输接口的协议类型。
  19. 一种数据传输系统，其特征在于，所述数据传输系统包括：
    如权利要求12或13所述的电子设备；
    如权利要求14-18任一项所述数据传输装置。
  20. 一种数据传输方法，其特征在于，应用于接口电路，所述接口电路通过数据传输装置与第一设备进行数据传输，所述接口电路包括接口指示端和数据传输端，所述方法包括：
    所述接口电路通过所述接口指示端从所述数据传输装置的指示器获取指示信息，所述指示信息用于指示所述第一设备的数据传输接口协议；
    所述接口电路通过所述数据传输端，采用所述指示信息指示的所述第一设备的数据传输接口协议，向所述第一设备传输数据。
  21. 根据权利要求20所述的方法，其特征在于，所述接口电路包括多个接口控制器、多路选择器、端口物理层和模式控制器；以及
    所述接口电路通过所述数据传输端，采用所述指示信息指示的所述第一设备的数据传输接口协议，向所述第一设备传输数据，包括：
    所述模式控制器基于所述指示信息，控制所述多路选择器将所述多个接口控制器中的第一接口控制器与所述端口物理层连通，其中，所述第一接口控制器与所述第一设备具有相同的所述数据传输接口协议；
    所述第一接口控制器控制所述端口物理层采用所述数据传输协议，通过所述数据传输端向所述第一设备传输数据。
  22. 根据权利要求21所述的方法，其特征在于，所述方法还包括：
    所述模式控制器基于所述指示信息，调整所述端口物理层中发射器和接收器中以下参数的至少一项：信号传输速率或者所传输的信号的幅度。
  23. 根据权利要求20所述的方法，其特征在于，所述接口电路包括多个接口控制器、多个端口物理层、开关组和模式控制器，所述多个接口控制器、所述多个端口物理层和所述开关组中的多个开关一一对应耦合；以及
    所述接口电路通过所述数据传输端，采用所述指示信息指示的所述第一设备的数据传输接口协议，向所述第一设备传输数据，包括：
    所述模式控制器基于所述指示信息，控制所述开关组中的第一开关导通；
    所述多个接口控制器中与所述第一开关对应的第一接口控制器，控制所述多个端口物理层中与所述第一接口控制器和所述第一开关耦合的第一端口物理层，采用所述数据传输协议，通过所述数据传输端向所述第一设备传输数据。
  24. 根据权利要求20-23任一项所述的方法，其特征在于，所述指示器为电阻，所述指示信息为模拟信号；或，
    所述指示器为寄存器，所述指示信息为数字信号。
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