WO2017166286A1 - 积分电路及信号处理模块 - Google Patents

积分电路及信号处理模块 Download PDF

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Publication number
WO2017166286A1
WO2017166286A1 PCT/CN2016/078308 CN2016078308W WO2017166286A1 WO 2017166286 A1 WO2017166286 A1 WO 2017166286A1 CN 2016078308 W CN2016078308 W CN 2016078308W WO 2017166286 A1 WO2017166286 A1 WO 2017166286A1
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Prior art keywords
capacitor
coupled
module
adjustable
resistor
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Application number
PCT/CN2016/078308
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English (en)
French (fr)
Inventor
杨富强
文亚南
梁颖思
Original Assignee
深圳市汇顶科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2016/078308 priority Critical patent/WO2017166286A1/zh
Priority to KR1020177024169A priority patent/KR20170131380A/ko
Priority to EP16889664.5A priority patent/EP3252581A4/en
Priority to CN201680000590.5A priority patent/CN107850970B/zh
Priority to KR1020177025951A priority patent/KR101965274B1/ko
Priority to CN201780000819.XA priority patent/CN107438951B/zh
Priority to EP17758788.8A priority patent/EP3267298B1/en
Priority to PCT/CN2017/079113 priority patent/WO2017167297A1/zh
Priority to US15/679,182 priority patent/US20180026608A1/en
Priority to US15/696,195 priority patent/US10367478B2/en
Publication of WO2017166286A1 publication Critical patent/WO2017166286A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H19/00—Networks using time-varying elements, e.g. N-path filters
    • H03H19/004—Switched capacitor networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
    • H03M1/52—Input signal integrated with linear return to datum
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/18—Arrangements for performing computing operations, e.g. operational amplifiers for integration or differentiation; for forming integrals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/11—Complex mathematical operations for solving equations, e.g. nonlinear equations, general mathematical optimization problems
    • G06F17/12—Simultaneous equations, e.g. systems of linear equations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G06F3/04182—Filtering of noise external to the device and not generated by digitiser components
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks
    • H03H11/12—Frequency selective two-port networks using amplifiers with feedback
    • H03H11/126—Frequency selective two-port networks using amplifiers with feedback using a single operational amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/38—Impedance-matching networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041—Functional aspects of demodulators
    • H03D2200/0086—Reduction or prevention of harmonic frequencies
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/264—An operational amplifier based integrator or transistor based integrator being used in an amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45526—Indexing scheme relating to differential amplifiers the FBC comprising a resistor-capacitor combination and being coupled between the LC and the IC
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45594—Indexing scheme relating to differential amplifiers the IC comprising one or more resistors, which are not biasing resistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45616—Indexing scheme relating to differential amplifiers the IC comprising more than one switch, which are not cross coupled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H2210/00—Indexing scheme relating to details of tunable filters
    • H03H2210/02—Variable filter component
    • H03H2210/028—Resistor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H2210/00—Indexing scheme relating to details of tunable filters
    • H03H2210/03—Type of tuning
    • H03H2210/036—Stepwise

Definitions

  • the invention relates to an integration circuit and a signal processing module, in particular to an integration circuit and a signal processing module capable of suppressing a sideband.
  • the mixer can be realized by a multiplier to generate a received signal and a The result of multiplication of the local signal.
  • the mixer can be realized by a switching mixer (High-linearity and low noise), which can be equivalent to multiplying the received signal by a square wave (ie, local signal). .
  • a square wave ie, local signal
  • SNR signal to noise ratio
  • a signal SIG1 represents a waveform diagram without a window function
  • a signal SIG2 represents a waveform that has been added to a window function e.
  • the window function e can be regarded as one of the envelopes (Envelop) of the signal SIG2, and the addition of the window function e can effectively suppress the noise introduced by the sideband, increase the resistance to interference near the band, and thereby improve System signal to noise ratio.
  • the function of the window function can be implemented using a digital integrator that can use different integral gains for different time segments to achieve the function of applying a window function.
  • the higher output frequency of the digital integrator is not conducive to the design of the Analog-to-Digital Converter (ADC).
  • ADC Analog-to-Digital Converter
  • the back-end analog-to-digital converter requires a higher sampling frequency. It can accurately sample the output signal of the digital integrator and increase the power consumption and complexity of the circuit. Therefore, the prior art is in need of improvement.
  • one of the objects of the present invention is to provide an integration circuit and a signal processing module, which can suppress A sideband is made to improve the shortcomings of the prior art.
  • the present invention discloses an integrating circuit including an operational amplifier; an integrating capacitor coupled to an output of the operational amplifier and a first input; and an adjustable resistor module coupled to the operation Between the first input end of the amplifier and an integral input end of the integrating circuit, the adjustable resistance module receives a plurality of first control signals to adjust a resistance value of the adjustable resistance module.
  • the invention further discloses an integrating circuit, the integrating circuit includes an operational amplifier, an integrating capacitor coupled to an output end of the operational amplifier and a first input end, and a switching capacitor module coupled to the operation Between the first input end of the amplifier and the integral input end of the integrating circuit, the switching capacitor module includes an adjustable capacitor module, and receives a plurality of second control signals to adjust a first end of the adjustable capacitor module a first switch is coupled to the first end of the adjustable capacitor module; a second switch coupled between the first end and a ground end; The third switch is coupled between the second end and the first input end of the operational amplifier; and a fourth switch coupled between the second end and the ground end.
  • the switching capacitor module includes an adjustable capacitor module, and receives a plurality of second control signals to adjust a first end of the adjustable capacitor module a first switch is coupled to the first end of the adjustable capacitor module; a second switch coupled between the first end and a ground end; The third switch is coupled between the second end and the first input end of the operational amplifier; and a fourth switch
  • the invention further discloses a signal processing module, comprising a switching type mixer; an analog to digital converter; an integrating circuit coupled between the switching type mixer and the analog to digital converter, the integrating circuit
  • An integrating amplifier is coupled to an output end of the operational amplifier and a first input end, and an adjustable module coupled to the first input end of the operational amplifier and one of the integrating circuits Between the integral inputs, the adjustable module is controlled by a number of signals to adjust the resistance value or a capacitance value of the adjustable module.
  • the present invention discloses an integrating circuit including a first operational amplifier; an adjustable integrated capacitor module coupled between a first input end and an output end of the first operational amplifier, the adjustable
  • the integrating capacitor module includes a plurality of integrating capacitor selecting units, each integrating capacitor selecting unit includes an integrating capacitor and at least one switch; and a voltage following module coupled to the plurality of capacitor selecting units of the adjustable integrating capacitor module;
  • the adjustable integrated capacitor module receives a plurality of control signals to adjust a capacitance value between the first input end and the output end.
  • the adjustable resistance module can be controlled by the control signal to Adjusting the resistance between the first end and the second end of the adjustable resistor module in different time segments, thereby changing the integral gain of the integrating circuit in different time segments; or controlling the adjustable capacitor module through the control signal
  • the present invention utilizes an analog integrating circuit to implement The function of the window function is to adjust the integral gain corresponding to each time segment in different time segments, thereby reducing the noise introduced by the sideband and improving the signal to noise ratio.
  • the integrator circuit of the present invention can reduce the sampling frequency requirement of the analog to digital converter, thereby reducing the power consumption and circuit complexity of the overall circuit.
  • Figure 1 shows several waveforms.
  • FIG. 2 is a schematic diagram of an integrating circuit according to an embodiment of the present invention.
  • FIG. 3 is a waveform diagram of an output signal of the integrating circuit of FIG. 1.
  • FIG. 4 is a schematic diagram of an integrating circuit according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of an integrating circuit according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of an integrating circuit according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of an integrating circuit according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a switched capacitor module according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of an integrating circuit according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of a signal processing module according to an embodiment of the present invention.
  • Figure 11 is a schematic diagram of an integrating circuit in accordance with an embodiment of the present invention.
  • Figure 12 is a schematic diagram of an integrating circuit in accordance with an embodiment of the present invention.
  • FIG. 2 is an integrating circuit according to an embodiment of the present invention.
  • the integration circuit 20 is a resistor-capacitor integrator (RC Integrator), which includes an operational amplifier Amp, an integrating capacitor CI, and an adjustable resistor module VR.
  • the operational amplifier Amp includes a negative input terminal (labeled with a "-" sign), a positive input terminal (labeled with a "+” sign), and an output terminal coupled to the negative input terminal and the output terminal of the operational amplifier Amp. between.
  • the adjustable resistor module VR is coupled between the negative input terminal of the operational amplifier Amp and an integral input terminal NIN of the integrating circuit 20.
  • the adjustable resistor module VR includes a resistor selecting unit RU1 RUMM, and the adjustable resistor module VR is selected by a resistor.
  • the unit RU1 - RUM are connected in parallel with each other, wherein any one of the resistor selection units RU1 - RUM includes a resistor Rm and a control switch SRm, and the control switch SRm is controlled by a control signal ctrl_R_m
  • the resistor selection unit RUm is formed by connecting the resistor Rm and the control-resistance switch SRm in series (Connected in Series).
  • control signals ctrl_R_1 ⁇ ctrl_R_M can control the adjustable resistor module VR to adjust the resistance between a first end NR1 and a second end NR2 of the adjustable resistor module VR in different time segments.
  • the integral gain of the integrating circuit 20 is varied in different time segments.
  • FIG. 3 illustrates the integration circuit 20 when an input signal VIN of the integrating circuit 20 is a direct current (DC) signal.
  • the resistance value between the first terminal NR1 and the second terminal NR2 of the adjustable resistor module VR can be adjusted by the control signals ctrl_R_1 to ctrl_R_M, so that the integration circuit 20 is in time.
  • the segments T1 to T7 have different integral gains.
  • the time segments T1, T7 may have the smallest integral gain
  • the time segments T2, T6 may have the second smallest integral gain
  • the centrally located time segment T4 may have the largest integral gain. .
  • FIG. 4 is a schematic diagram of an integrating circuit 40 according to an embodiment of the present invention.
  • the integrating circuit 40 is similar to the integrating circuit 20, so the same components follow the same symbols.
  • the integration circuit 40 is a switched capacitor integrator (Switched-Capacitor Integrator), the integration circuit 40 includes a switching capacitor module SCM, and the switching capacitor module SCM is coupled to the negative input terminal and integral of the operational amplifier Amp.
  • Switchched-Capacitor Integrator switched capacitor integrator
  • SCM switching capacitor module
  • the switching capacitor module SCM is coupled to the negative input terminal and integral of the operational amplifier Amp.
  • the switched capacitor module SCM includes a The modulating capacitor module VC and the switches SW1 ⁇ SW4, the switches SW1 and SW2 are coupled to a first end NC1 of the adjustable resistor module VC, and the switches SW3 and SW4 are coupled to a second end NC2 of the adjustable resistor module VC, the switch SW2 The SW4 is coupled to a ground.
  • the adjustable capacitor module VC includes capacitor selection units CU1 to CUN, and the adjustable capacitor module VC is formed by connecting capacitor selection units CU1 to CUN in parallel with each other, wherein any of the capacitor selection units CU1 to CUN includes a capacitor Cn and A control capacitor switch SCn, the control capacitor switch SCn is controlled by a control signal ctrl_C_n, and the capacitor selection unit CUn is formed by connecting the capacitor Cn and the control capacitor switch SCn in series.
  • the control signals ctrl_C_1 to ctrl_C_N can be used to control the adjustable capacitor module VC to adjust the capacitance between the first end NC1 and the second end NC2 of the adjustable capacitor module VC in different time segments.
  • the integral gain of the integrating circuit 40 is changed in different time segments.
  • the switches SW1, SW2, SW3, and SW4 can be controlled by the frequency control signals ph1, ph2, wherein the frequency control signals ph1, ph2 are mutually orthogonal frequency control signals (ie, the time when the frequency control signals ph1, ph2 are high)
  • the frequency control signal ph1 can be used to control the on state of the switches SW1 and SW3, and the frequency control signal ph2 can be used to control the on state of the switches SW2 and SW4.
  • the frequency control signal ph1 can be used to control the conduction state of the switches SW1, SW4, and the frequency control signal ph2 can be used to control the conduction state of the switches SW2, SW3. It is in accordance with the requirements of the present invention and is within the scope of the present invention as long as the conduction states of the switches SW1, SW2, SW3, and SW4 are controlled by mutually orthogonal frequency control signals ph1, ph2.
  • the integrating circuit 20 and the integrating circuit 40 can adjust the resistance value of the adjustable resistor module VR and the capacitance value of the adjustable capacitor module VC in different time sections through the adjustable resistor module VR and the adjustable capacitor module VC, respectively.
  • the integrating circuit 20 and the integrating circuit 40 can change the integral gain of the integrating circuit 20 and the integrating circuit 40 in different time segments, thereby achieving the effect of the window function.
  • the integrating circuit 20 and the integrating circuit 40 can reduce the noise introduced by the sideband, thereby improving the overall signal to noise ratio (SNR).
  • FIG. 5 is a schematic diagram of an integrating circuit 50 according to an embodiment of the present invention.
  • the integrating circuit 50 is similar to the integrating circuit 20, so the same components follow the same symbols.
  • the integration circuit 50 includes an adjustable resistance module VR', the adjustable resistance module VR' includes a resistance selection unit RU1'-RUM', and the adjustable resistance module VR' is composed of a resistance selection unit RU1' ⁇ RUM' is formed in series with each other, wherein any one of the resistor selection units RU1'-RUM' includes a resistor Rm' and a control switch SRm', and the control switch SRm' is controlled by a control signal ctrl_R_m'
  • the resistance selecting unit RUm' is formed by connecting the resistor Rm' and the control-resistance switch SRm' in parallel with each other.
  • FIG. 6 is a schematic diagram of an integrating circuit 60 according to an embodiment of the present invention.
  • the integrating circuit 60 is similar to the integrating circuit 20, so the same components follow the same symbols.
  • the integration circuit 60 includes a switched capacitor module SCM', the switched capacitor module SCM' includes a tunable capacitor module VC', and the tunable capacitor module VC' includes capacitor selection units CU1'-CUN'.
  • the adjustable capacitor module VC' is formed by connecting capacitor selection units CU1'-CUN' in series with each other, wherein any one of the capacitor selection units CU1'-CUN' includes a capacitor Cn' and a control switch SCn'.
  • the control capacitor switch SCn' is controlled by a control signal ctrl_C_n', and the capacitor selection unit CUn' is formed by connecting the capacitor Cn' and the control capacitor switch SCn' in parallel with each other.
  • FIG. 7 is a schematic diagram of an integrating circuit 70 according to an embodiment of the present invention.
  • the integrating circuit 70 is similar to the integrating circuit 20, so the same components follow the same symbols.
  • the integrating circuit 70 includes an adjustable resistor module 700 and a switched capacitor module 702.
  • the adjustable resistor module 700 and the switched capacitor module 702 are both coupled between the negative input terminal of the operational amplifier Amp and the integral input terminal NIN of the integrating circuit 70.
  • the adjustable resistor module 700 can be implemented by the adjustable resistor module VR or the adjustable resistor module VR′, and the switched capacitor module 702 can be implemented by the switched capacitor module SCM or the switched capacitor module SCM′, without being limited thereto.
  • the switched capacitor module is not limited to the aforementioned switched capacitor module SCM or switched capacitor module
  • the SCM' can be implemented, and the switched capacitor module can further include a resistor coupled between the switches SW1 and SW3.
  • FIG. 8 is a schematic diagram of a switched capacitor module 80 according to an embodiment of the present invention.
  • the switching capacitor module 80 is different from the switching capacitor modules SCM and SCM.
  • the switching capacitor module 80 further includes a resistor unit R coupled between the switches SW1 and SW3.
  • the resistor unit R can be a single resistor component or a Modulated resistor modules are also within the scope of the invention.
  • FIG. 9 is a schematic diagram of a fully differential integration circuit 90 according to an embodiment of the present invention.
  • the integrating circuit 90 receives the differential input signals VI+, VI- and generates differential output signals VO+, VO-.
  • the integrating circuit 90 includes a fully differential operational amplifier FOP, integrating capacitors CI, CI', and adjustable modules 900, 900', the adjustable module Both the 900 and the adjustable module 900' can be implemented by one of an adjustable resistor module VR, an adjustable resistor module VR', a switched capacitor module SCM or a switched capacitor module SCM', in addition to the adjustable module 900 and the adjustable type
  • the module 900' can also be implemented by a series connection switching capacitor module SCM (or a switching capacitor module SCM') through an adjustable resistor module VR (or an adjustable resistor module VR'), without being limited thereto.
  • the controllable module 900 and the adjustable module 900' have the same resistance value or capacitance value to maintain the balance of the differential signals, thereby improving the performance of the fully differential integration circuit 90.
  • FIG. 10 is a schematic diagram of a signal processing module 12 according to an embodiment of the present invention.
  • the signal processing module 12 includes a switching mixer 120, an integrating circuit 90, and an analog-to-digital converter ADC.
  • the switching mixer 120 receives the differential signals VIN+, VIN- and generates differential input signals VI+, VI- to the integrating circuit 90.
  • the analog-to-digital converter ADC receives the differential output signals VO+, VO- generated by the integrating circuit 90, and converts the analog differential output signals VO+, VO- into digital signals for operation by the back-end circuit.
  • the switching mixer 120 can include switches S1 to S4, the switches S1 and S2 are used to receive the differential signal VIN-, the switches S3 and S4 are used to receive the differential signal VIN+, and the switches S1 and S4 are coupled to the first of the integrating circuit 90.
  • the input terminal transmits a differential input signal VI- to the integrating circuit 90, and the switches S2 and S3 are coupled to a second input of the integrating circuit 90.
  • the terminal transmits the differential input signal VI+ to the integrating circuit 90.
  • FIG. 11 is a schematic diagram of an integrating circuit 14 according to an embodiment of the present invention.
  • the integrating circuit 14 includes an adjustable integrating capacitor module 140, a voltage following module 142, and an operational amplifier Amp.
  • the adjustable integrator capacitor module 140 is coupled between the positive and negative input terminals and the output terminal of the operational amplifier Amp, and the voltage following module 142 is coupled to the adjustable integrating capacitor module 140.
  • the adjustable integrating capacitor module 140 includes integral capacitor selecting units CIU1 CICIUN, and the adjustable integrating capacitor module 140 can be regarded as being formed by connecting the integrating capacitor selecting units CU1 to CUN in parallel, and the integrating capacitor selecting units CIU1 to CIUN
  • An integrating capacitor selection unit CIUn includes an integrating capacitor CIn and switches Mn, Jn, the integrating capacitor CIn and the switches Mn, Jn are connected in series, and the integrating capacitor CIn is coupled to the positive and negative inputs of the operational amplifier Amp through the switch Mn, and the integral The capacitor CIn is coupled to the output of the operational amplifier Amp through the switch Jn.
  • the voltage following module 142 includes switches H1 HH1, K1 KKN and a voltage follower circuit 144.
  • the voltage follower circuit 144 includes an operational amplifier OP, and a negative input terminal (labeled with a "-" sign) of the operational amplifier OP. Connected to an output of the operational amplifier OP, the output of the operational amplifier OP is coupled to the switches K1 - KN, and a positive input of the operational amplifier OP (labeled "+”) is coupled to the switches H1 - HN.
  • the voltage following module 142 has nodes ND1 - NDN, and the switches H1 - HN are respectively coupled to the switches K1 - KN at the nodes ND1 - NDN.
  • any one of the switches H1 to HN is coupled to the node NDn, and the other end of the switch Hn is coupled to the positive input terminal of the operational amplifier OP, and one end of any one of the switches K1 to KN is coupled.
  • the node NDn the other end of the switch Kn is coupled to the output terminal of the operational amplifier OP, and each of the nodes ND1 to NDN is coupled between the integrating capacitor CIn and the switch Jn.
  • the switches M1 to MN, J1 to JN, H1 to HN, and K1 to KN can receive and control a plurality of control signals (not shown in FIG. 11) for performing an integration operation, and the plurality of control signals can be in different time segments.
  • the integral gain of the integrating circuit 14 is changed to adjust a capacitance value between the negative input terminal and the output terminal of the operational amplifier Amp, thereby implementing the function of the window function.
  • the integrating circuit 14 integrates an integrating capacitor CIp of the integrating capacitors CI1 to CIN
  • the plurality of control signal control switches H1 to HN, K1 to KN are all open (Cutoff), and in addition, the switches J1 to JN correspond to In addition to a switch Jp of the integral capacitor CIp-, the plurality of control signals control the remaining switches J1 to Jp-1 and Jp+1 to JN to be open, and the plurality of control signals control the switch M1 to A switch Mp corresponding to the integrating capacitor CIp- turns on the connection between the integrating capacitor CIp- and the negative input terminal of the operational amplifier Amp.
  • the plurality of control signals control the remaining switches M1 to Mp-1.
  • Mp+1 ⁇ MN both turn on the connection between the integrating capacitor and the positive input terminal of the operational amplifier Amp.
  • the plurality of control signals will correspond to the switch Hp of the integrating capacitor CIp and the switch Kq corresponding to the integrating capacitor CIq. Closed (ie, switches Hp and Kq are turned on), and the remaining switches H1 to Hp-1, Hp+1 to HN, K1 to Kq-1, and Kq+1 to KN are all open. In this way, in different time segments, the capacitance value between the negative input terminal and the output terminal of the operational amplifier Amp can be adjusted, so that the integration circuit 14 has different integral gains, thereby realizing the function of the window function.
  • FIG. 12 is a schematic diagram of an integrating circuit 24 according to an embodiment of the present invention.
  • the integrating circuit 24 is similar to the integrating circuit 14, so that the same components follow the same symbols.
  • the integrating circuit 24 includes an adjustable integrating capacitor module 240, the adjustable integrating capacitor module 240 includes an integrating capacitor selecting unit CIU1'-CIUN', and the adjustable integrating capacitor module 240 is composed of an integrating capacitor selecting unit CIU1' ⁇ CIUN' is connected in series.
  • any one of the integrating capacitor selecting units CIU1' to CIUN' includes an integrating capacitor CIn' and switches Mn', Ln', Jn', and the integrating capacitor CIn' is connected in series with the switches Mn', Ln', that is, The integrating capacitor CIn' forms a sequence with the switches Mn', Ln', and the series formed by the switch Jn' and the integrating capacitor CIn' and the switches Mn', Ln' are connected in parallel.
  • the integrating circuit 24 integrates an integrating capacitor CIp' of the integrating capacitors CI1' to CIN', the switches H1 to HN, K1 to KN are all open, and the switch J1' ⁇ In JN', except for the switch Jp' corresponding to the integral capacitor CIp'-, the other switches J1'-Jp-1', Jp+1'-JN' are all turned on, and the switches L1'-LN' are turned on.
  • the switch Lp' corresponding to the integrating capacitor CIp'- is turned on, and a switch Mp' corresponding to the integrating capacitor CIp-' of the switch M1'-MN' turns on the integrating capacitor CIp-' and the negative input terminal of the operational amplifier Amp The link between.
  • the switch Hp corresponding to the integrating capacitor CIp' and the switch corresponding to the integrating capacitor CIq' are used.
  • Kq is closed (ie, switches Hp and Kq are turned on), and the remaining switches H1 to Hp-1, Hp+1 to HN, K1 to Kq-1, and Kq+1 to KN are all open.
  • a switch Mq' corresponding to the integrating capacitor CIq' of the switches M1' to MN' turns on the connection between the integrating capacitor CIq-' and the positive input terminal of the operational amplifier Amp. In this way, in different time segments, the capacitance value between the negative input terminal and the output terminal of the operational amplifier Amp can be adjusted, so that the integration circuit 24 has different integral gains, thereby realizing the function of the window function.
  • the present invention changes the integral gain of the integrating circuit in different time segments through the adjustable resistor module or the adjustable capacitor module to realize the function of the window function, thereby reducing the noise introduced by the sideband and improving Signal to noise ratio.
  • the integrator circuit of the present invention can reduce the sampling frequency requirement of the analog to digital converter, thereby reducing the power consumption and circuit complexity of the overall circuit.

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Abstract

一种积分电路（20），包含有：一运算放大器；一积分电容，耦接于该运算放大器的一输出端及一第一输入端；以及一可调式电阻模块，耦接于该运算放大器的该第一输入端与该积分电路的一积分输入端之间，该可调式电阻模块接收若干个控阻信号第一控制信号，以调整该可调式电阻模块的电阻值。提高了信噪比。

Description

积分电路及信号处理模块 【技术领域】
本发明涉及一种积分电路及信号处理模块，尤指一种可抑制旁波带(Sidelobe)的积分电路及信号处理模块。
【背景技术】
匹配滤波器(Match Filter)与混频器(Mixer)已广泛地应用于通讯系统与电容式触控系统中，一般来说，混频器可通过一乘法器实现，而产生一接收信号与一本地信号的相乘结果。另外，混频器另可通过具有高线性度及低噪声的一切换式混波器(Switching Mixer)来实现，切换式混波器可等效于将接收信号乘以一方波(即本地信号)。然而，无论是方波或正弦波在频谱上都具有较高的旁波带(Sidelobe)而引入额外噪声，而使得系统的信噪比(Signal to Noise Ratio，SNR)降低。为了解决旁波带引入噪声的问题，可于积分器前加入窗函数，如图1所示，一信号SIG1代表未加入窗函数之波形图，而一信号SIG2代表已加入一窗函数e之波形图，由图1可知，窗函数e可视为信号SIG2之一包迹(Envelop)，而加入窗函数e可有效抑制旁波带所引入之噪声，增加对频带附近干扰的抵抗能力，进而提高系统信噪比。
窗函数的功能可利用数字积分器来实现，数字积分器可于不同时间区段使用不同的积分增益，以达到施加窗函数的功能。然而，数字积分器的输出频率较高，反倒不利于后端模拟数字转换器(Analog-to-Digital Converter，ADC)的设计，换句话说，后端模拟数字转换器需要更高的采样频率，始能精准地对数字积分器的输出信号进行采样，而增加电路的功耗以及复杂度。因此，现有技术实有改善之必要。
【发明内容】
因此，本发明的目的之一在于提供一种积分电路及信号处理模块，其可抑 制旁波带，以改善现有技术的缺点。
本发明公开了一种积分电路，该积分电路包含有一运算放大器；一积分电容，耦接于该运算放大器的一输出端及一第一输入端；以及一可调式电阻模块，耦接于该运算放大器的该第一输入端与该积分电路的一积分输入端之间，该可调式电阻模块接收若干个第一控制信號，以调整该可调式电阻模块的电阻值。
本发明另公开了一种积分电路，该积分电路包含有一运算放大器；一积分电容，耦接于该运算放大器的一输出端及一第一输入端；以及一切换电容模块，耦接于该运算放大器的该第一输入端与该积分电路的该积分输入端之间，该切换电容模块包含有一可调式电容模块，接收若干个第二控制信號，以调整该可调式电容模块的一第一端与一第二端之间之一电容值；一第一开关，耦接于该可调式电容模块的第一端；一第二开关，耦接于该第一端与一接地端之间；一第三开关，耦接于该第二端与该运算放大器的该第一输入端之间；以及一第四开关，耦接于该第二端与该接地端之间。
本发明另公开了一种信号处理模块，包含有一切换式混波器；一模拟数字转换器；一积分电路，耦接于该切换式混波器与该模拟数字转换器之间，该积分电路包含有一运算放大器；一积分电容，耦接于该运算放大器的一输出端及一第一输入端；以及一可调式模块，耦接于该运算放大器的该第一输入端与该积分电路的一积分输入端之间，该可调式模块受控于若干个信号，以调整该可调式模块的电阻值或一电容值。
本发明公开了一种积分电路，该积分电路包含有一第一运算放大器；一可调式积分电容模块，耦接于该第一运算放大器的一第一输入端与一输出端之间，该可调式积分电容模块包含有若干个积分电容选择单元，每一积分电容选择单元包含有一积分电容及至少一开关；以及一电压跟随模块，耦接于该可调式积分电容模块的该若干个电容选择单元；其中，该可调式积分电容模块接收若干个控制信号，以调整该第一输入端与该输出端之间的一电容值。
通过本发明提供的积分电路，其通过控制信号可控制可调式电阻模块，以 于不同时间区段中，调整可调式电阻模块的第一端与第二端之间的电阻值，进而于不同时间区段中，改变积分电路的积分增益；或者通过控制信号控制可调式电容模块，以于不同时间区段中，调整可调式电容模块的第一端与第二端之间的电容值，进而于不同时间区段中，改变积分电路的积分增益；本发明利用模拟积分电路实现窗函数的功能，其可于不同时间区段调整对应于各个时间区段的积分增益，进而实现降低旁波带所引入的噪声而提高信噪比。相较于现有技术，本发明之积分电路可降低模拟数字转换器对采样频率的需求，进而减低整体电路的功耗以及电路复杂度。
【附图说明】
图1为若干个波形图。
图2为本发明实施例一积分电路的示意图。
图3为图1的积分电路的一输出信号的波形图。
图4为本发明实施例一积分电路的示意图。
图5为本发明实施例一积分电路的示意图。
图6为本发明实施例一积分电路的示意图。
图7为本发明实施例一积分电路的示意图。
图8为本发明实施例一切换电容模块的示意图。
图9为本发明实施例一积分电路的示意图。
图10为本发明实施例一信号处理模块的示意图。
图11为本发明实施例一积分电路的示意图。
图12为本发明实施例一积分电路的示意图。
【具体实施方式】
本发明利用模拟积分电路实现窗函数的功能，其可于不同时间区段调整对应于各个时间区段的积分增益。请参考图2，图2为本发明实施例一积分电路 20的示意图，积分电路20为一电阻电容积分器(RC Integrator)，其包含有一运算放大器Amp、一积分电容CI以及一可调式电阻模块VR。运算放大器Amp包含有一负输入端(标示有「－」号)、一正输入端(标示有「+」号)及一输出端，积分电容CI耦接于运算放大器Amp的负输入端与输出端之间。可调式电阻模块VR耦接于运算放大器Amp的负输入端与积分电路20的一积分输入端NIN之间，可调式电阻模块VR包含有电阻选择单元RU1～RUM，可调式电阻模块VR由电阻选择单元RU1～RUM相互并联(Connected in Parallel)而成，其中电阻选择单元RU1～RUM中任一电阻选择单元RUm包含有一电阻Rm以及一控阻开关SRm，控阻开关SRm受控于一控制信号ctrl_R_m，电阻选择单元RUm由电阻Rm与控阻开关SRm相互串联(Connected in Series)而成。换句话说，控制信号ctrl_R_1～ctrl_R_M可控制可调式电阻模块VR，以于不同时间区段中，调整可调式电阻模块VR的一第一端NR1与一第二端NR2之间之电阻值，进而于不同时间区段中，改变积分电路20的积分增益。
关于不同时间区段中积分电路20的积分增益的改变情况可进一步参考图3，图3绘示当积分电路20的一输入信号VIN为一直流(Direct Current，DC)信号时，积分电路20的一输出信号VOUT的波形图。由图3可知，对应于时间区段T1～T7，可藉由控制信号ctrl_R_1～ctrl_R_M调整可调式电阻模块VR的第一端NR1与第二端NR2之间之电阻值，使得积分电路20于时间区段T1～T7中具有不同的积分增益。为了实现窗函数，较佳地，时间区段T1、T7可具有最小的积分增益，时间区段T2、T6可具有次小的积分增益，而位于中央的时间区段T4可具有最大的积分增益。
另外，请参考图4，图4为本发明实施例一积分电路40的示意图，积分电路40与积分电路20相似，故相同组件沿用相同符号。与积分电路20不同的是，积分电路40为一切换电容积分器(Switched-Capacitor Integrator)，积分电路40包含有一切换电容模块SCM，切换电容模块SCM耦接于运算放大器Amp的负输入端与积分电路40的积分输入端NIN之间，切换电容模块SCM包含有一可 调式电容模块VC以及开关SW1～SW4，开关SW1、SW2耦接于可调式电阻模块VC的一第一端NC1，开关SW3、SW4耦接于可调式电阻模块VC的一第二端NC2，开关SW2、SW4耦接于一接地端。可调式电容模块VC包含有电容选择单元CU1～CUN，可调式电容模块VC由电容选择单元CU1～CUN相互并联而成，其中电容选择单元CU1～CUN中任一电容选择单元CUn包含有一电容Cn以及一控容开关SCn，控容开关SCn受控于一控制信号ctrl_C_n，电容选择单元CUn由电容Cn与控容开关SCn相互串联而成。换句话说，控制信号ctrl_C_1～ctrl_C_N可用来控制可调式电容模块VC，以于不同时间区段中，调整可调式电容模块VC的第一端NC1与第二端NC2之间之电容值，进而于不同时间区段中，改变积分电路40的积分增益。
另外，开关SW1、SW2、SW3、SW4可受控于频率控制信号ph1、ph2，其中频率控制信号ph1、ph2为相互正交之频率控制信号(即频率控制信号ph1、ph2为高电位的时间不相互重迭)，具体来说，于一实施例中，频率控制信号ph1可用来控制开关SW1、SW3的导通状态，而频率控制信号ph2可用来控制开关SW2、SW4的导通状态；于另一实施例中，频率控制信号ph1可用来控制开关SW1、SW4的导通状态，而频率控制信号ph2可用来控制开关SW2、SW3的导通状态。只要利用相互正交之频率控制信号ph1、ph2控制开关SW1、SW2、SW3、SW4的导通状态，皆符合本发明之要求且属于本发明之范畴。
由上述可知，积分电路20及积分电路40可分别通过可调式电阻模块VR及可调式电容模块VC，于不同时间区段调整可调式电阻模块VR的电阻值及可调式电容模块VC的电容值，换句话说，积分电路20及积分电路40可于不同时间区段中，改变积分电路20及积分电路40的积分增益，进而实现窗函数的效果。如此一来，积分电路20及积分电路40可降低旁波带(Sidelobe)所引入的噪声，进而提高整体信噪比(Signal to Noise Ratio，SNR)。
需注意的是，前述实施例系用以说明本发明之概念，本领域具通常知识者当可据以做不同之修饰，而不限于此。举例来说，于可调式电阻模块VR中，电 阻选择单元RU1～RUM以并联的方式相互连接，而电阻Rm与控阻开关SRm以串联的方式相互连接，于可调式电容模块VC中，电容选择单元CU1～CUN以并联的方式相互连接，而电容Cn与控容开关SCn以串联的方式相互连接，而不限于此。请参考图5，图5为本发明实施例一积分电路50的示意图。积分电路50与积分电路20相似，故相同组件沿用相同符号。与积分电路20不同的是，积分电路50包含一可调式电阻模块VR’，可调式电阻模块VR’包含有电阻选择单元RU1’～RUM’，可调式电阻模块VR’由电阻选择单元RU1’～RUM’相互串联而成，其中电阻选择单元RU1’～RUM’中任一电阻选择单元RUm’包含有一电阻Rm’以及一控阻开关SRm’，控阻开关SRm’受控于一控制信号ctrl_R_m’，电阻选择单元RUm’由电阻Rm’与控阻开关SRm’相互并联而成。同样地，请参考图6，图6为本发明实施例一积分电路60的示意图，积分电路60与积分电路20相似，故相同组件沿用相同符号。与积分电路20不同的是，积分电路60包含一切换电容模块SCM’，切换电容模块SCM’包含一可调式电容模块VC’，可调式电容模块VC’包含有电容选择单元CU1’～CUN’，可调式电容模块VC’由电容选择单元CU1’～CUN’相互串联而成，其中电容选择单元CU1’～CUN’中任一电容选择单元CUn’包含有一电容Cn’以及一控容开关SCn’，控容开关SCn’受控于一控制信号ctrl_C_n’，电容选择单元CUn’由电容Cn’与控容开关SCn’相互并联而成。
另外，积分电路可同时包含可调式电阻模块与可调式电容模块。举例来说，请参考图7，图7为本发明实施例一积分电路70的示意图。积分电路70与积分电路20相似，故相同组件沿用相同符号。积分电路70包含一可调式电阻模块700及一切换电容模块702，可调式电阻模块700及切换电容模块702皆耦接于运算放大器Amp的负输入端与积分电路70的积分输入端NIN之间，其中可调式电阻模块700可由可调式电阻模块VR或可调式电阻模块VR’来实现，切换电容模块702可由切换电容模块SCM或切换电容模块SCM’来实现，而不限于此。
另外，切换电容模块不限于以前述切换电容模块SCM或切换电容模块 SCM’来实现，切换电容模块可另包含一电阻耦接于开关SW1、SW3之间。举例来说，请参考图8，图8为本发明实施例一切换电容模块80的示意图。切换电容模块80与切换电容模块SCM、SCM’不同的是，切换电容模块80另包含一电阻单元R耦接于开关SW1、SW3之间，其中电阻单元R可为一单一电阻组件或是一可调式电阻模块，亦属于本发明之范畴。
另外，前述可调式电阻模块或切换电容模块皆应用于单端(Single-Ended)输入的积分电路，而不限于此，可调式电阻模块或切换电容模块亦可应用于差分(Diffferential)输入的积分电路。举例来说，请参考图9，图9为本发明实施例一全差分积分电路90的示意图。积分电路90接收差分输入信号VI+、VI-并产生差分输出信号VO+、VO-，积分电路90包含一全差分运算放大器FOP、积分电容CI、CI’以及可调式模块900、900’，可调式模块900与可调式模块900’皆可由可调式电阻模块VR、可调式电阻模块VR’、切换电容模块SCM或切换电容模块SCM’其中之一来实现，除此之外，可调式模块900与可调式模块900’亦可通过可调式电阻模块VR(或可调式电阻模块VR’)串接切换电容模块SCM(或切换电容模块SCM’)来实现，而不限于此。较佳地，可控制可调式模块900与可调式模块900’的电阻值或电容值为一致，以维持差分信号之平衡，进而增进全差分积分电路90的效能。
另外，积分电路90可应用于一信号处理模块中，请参考图10，图10为本发明实施例一信号处理模块12的示意图。信号处理模块12包含有一切换式混波器120、积分电路90以及一模拟数字转换器ADC，切换式混波器120接收差分信号VIN+、VIN-并产生差分输入信号VI+、VI-至积分电路90，模拟数字转换器ADC接收积分电路90所产生的差分输出信号VO+、VO-，并将模拟的差分输出信号VO+、VO-转换成数字信号供后端电路进行运算。切换式混波器120可包含开关S1～S4，开关S1、S2用来接收差分信号VIN-，开关S3、S4用来接收差分信号VIN+，开关S1、S4耦接于积分电路90的一第一输入端以传递差分输入信号VI-至积分电路90，开关S2、S3耦接于积分电路90的一第二输入 端以传递差分输入信号VI+至积分电路90。
另外，前述积分电路中耦接于运算放大器Amp输入端与输出端之间的积分电容均以单一电容组件来实现，而不限于此，亦可利用可调式电容模块来实现耦接于运算放大器Amp输入端与输出端之间的积分电容。请参考图11，图11为本发明实施例一积分电路14之示意图，积分电路14包含一可调式积分电容模块140、一电压跟随模块142以及运算放大器Amp。可调式积分电容模块140耦接于运算放大器Amp的正、负输入端与输出端之间，电压跟随模块142耦接于可调式积分电容模块140。详细来说，可调式积分电容模块140包含积分电容选择单元CIU1～CIUN，可调式积分电容模块140可视为由积分电容选择单元CU1～CUN相互并联而成，积分电容选择单元CIU1～CIUN中任一积分电容选择单元CIUn包含有一积分电容CIn以及开关Mn、Jn，积分电容CIn与开关Mn、Jn相互串连，积分电容CIn透过开关Mn耦接于运算放大器Amp的正、负输入端，积分电容CIn透过开关Jn耦接于运算放大器Amp的输出端。
另外，电压跟随模块142包含有开关H1～HN、K1～KN以及一电压跟随电路144，电压跟随电路144包含一运算放大器OP，运算放大器OP的一负输入端(标示有「－」号)耦接于运算放大器OP的一输出端，运算放大器OP的输出端耦接于开关K1～KN，而运算放大器OP的一正输入端(标示有「+」号)耦接于开关H1～HN。另外，电压跟随模块142具有节点ND1～NDN，开关H1～HN分别耦接于开关K1～KN于节点ND1～NDN。换句话说，开关H1～HN中任一开关Hn的一端耦接于节点NDn，开关Hn的另一端耦接于运算放大器OP的正输入端，开关K1～KN中任一开关Kn的一端耦接于节点NDn，开关Kn的另一端耦接于运算放大器OP的输出端，节点ND1～NDN中每一节点NDn耦接于积分电容CIn与开关Jn之间。开关M1～MN、J1～JN、H1～HN、K1～KN可接收并受控于若干个控制信号(未绘示于图11)而进行积分操作，该若干个控制信号可于不同时间区段中改变积分电路14的积分增益，以调整运算放大器Amp的负输入端与输出端之间的一电容值，进而以实现窗函数的功能。
积分电路14的操作细节简述如下。当积分电路14对积分电容CI1～CIN中一积分电容CIp进行积分时，该若干个控制信号控制开关H1～HN、K1～KN皆为断路(Cutoff)，另外，开关J1～JN中除了对应于积分电容CIp-的一开关Jp为导通(Conducted)之外，该若干个控制信号控制其余开关J1～Jp-1、Jp+1～JN为断路，另外，该若干个控制信号控制开关M1～MN中对应于积分电容CIp-的一开关Mp导通积分电容CIp-与运算放大器Amp的负输入端之间的连结，除了开关Mp之外，该若干个控制信号控制其余开关M1～Mp-1、Mp+1～MN皆导通积分电容与运算放大器Amp的正输入端之间的连结。当积分电路14即将由积分电容CIp切换至对积分电容CI1～CIN中另一积分电容CIq进行积分之前，该若干个控制信号将对应于积分电容CIp的开关Hp以及对应于积分电容CIq的开关Kq闭合(即开关Hp、Kq为导通)，其余开关H1～Hp-1、Hp+1～HN、K1～Kq-1、Kq+1～KN皆为断路。如此一来，于不同时间区段中，可调整运算放大器Amp的负输入端与输出端之间的电容值，而使积分电路14具有不同的积分增益，进而实现窗函数的功能。
另外，积分电路14中，可调式积分电容模块140可视为由积分电容选择单元CIU1～CIUN相互并联而成，而不限于此。请参考图12，图12为本发明实施例一积分电路24之示意图，积分电路24与积分电路14相似，故相同组件沿用相同符号。与积分电路14不同的是，积分电路24包含一可调式积分电容模块240，可调式积分电容模块240包含积分电容选择单元CIU1’～CIUN’，可调式积分电容模块240由积分电容选择单元CIU1’～CIUN’相互串联而成。积分电容选择单元CIU1’～CIUN’中任一积分电容选择单元CIUn’包含有一积分电容CIn’以及开关Mn’、Ln’、Jn’，积分电容CIn’与开关Mn’、Ln’相互串联，即积分电容CIn’与开关Mn’、Ln’形成一串行，而开关Jn’与积分电容CIn’、开关Mn’、Ln’所形成的串行相互并联。
积分电路24的操作细节简述如下。当积分电路24对积分电容CI1’～CIN’中一积分电容CIp’进行积分时，开关H1～HN、K1～KN皆为断路，开关J1’～ JN’中除了对应于积分电容CIp’-的开关Jp’为断路之外，其余开关J1’～Jp-1’、Jp+1’～JN’皆为导通，另外，开关L1’～LN’中对应于积分电容CIp’-的开关Lp’为导通，开关M1’～MN’中对应于积分电容CIp-’的一开关Mp’导通积分电容CIp-’与运算放大器Amp的负输入端之间的连结。当积分电路24即将由积分电容CIp’切换至对积分电容CI1’～CIN’中另一积分电容CIq’进行积分之前，将对应于积分电容CIp’的开关Hp以及对应于积分电容CIq’的开关Kq闭合(即开关Hp、Kq为导通)，其余开关H1～Hp-1、Hp+1～HN、K1～Kq-1、Kq+1～KN皆为断路。另外，开关M1’～MN’中对应于积分电容CIq’的一开关Mq’导通积分电容CIq-’与运算放大器Amp的正输入端之间的连结。如此一来，于不同时间区段中，可调整运算放大器Amp的负输入端与输出端之间的电容值，而使积分电路24具有不同的积分增益，进而实现窗函数的功能。
需注意的是，前述实施例系用以说明本发明之优选实施例，但不限于此。举例来说，图11中当积分电容CIq没有进行积分时，其对应开关Mq耦接于运算放大器Amp的正输入端。另一实施例中(未绘出)，Mq可耦接于任意参考电压，而此参考电压不需要与运算放大器Amp的正输入端相同，也可积分电路14具有不同的积分增益，进而实现窗函数的功能。同理，图12中的开关M1’～MN’在其对应积分电容没有进行积分时，也可耦接于任意参考电压，利用积分电路24实现窗函数的功能。
综上所述，本发明透过可调式电阻模块或可调式电容模块，于不同时间区段中改变积分电路的积分增益，以实现窗函数的功能，进而降低旁波带所引入的噪声而提高信噪比。相较于现有技术，本发明之积分电路可降低模拟数字转换器对采样频率的需求，进而减低整体电路的功耗以及电路复杂度。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (26)

  1. 一种积分电路，包含有：
    一运算放大器；
    一积分电容，耦接于该运算放大器的一输出端及一第一输入端；以及
    一可调式电阻模块，耦接于该运算放大器的该第一输入端与该积分电路的一积分输入端之间，该可调式电阻模块接收若干个第一控制信号，以调整该可调式电阻模块的电阻值。
  2. 如权利要求1所述的积分电路，其中该可调式电阻模块包含有若干个电阻选择单元，分别受控于该若干个第一控制信号，每一电阻选择单元包含有：
    一电阻；以及
    一控阻开关，耦接于该电阻。
  3. 如权利要求2所述的积分电路，其中该若干个电阻选择单元之间以并联的方式相互耦接，每一电阻选择单元中的该电阻与该控阻开关串联。
  4. 如权利要求2所述的积分电路，其中该若干个电阻选择单元之间以串联的方式相互耦接，该每一电阻选择单元中的该电阻与该控阻开关相互并联。
  5. 如权利要求1所述的积分电路，另包含一切换电容模块，耦接于该运算放大器的该第一输入端与该积分电路的该积分输入端之间，该切换电容模块包含有：
    一可调式电容模块，接收若干个第二控制信号，以调整该可调式电容模块的第一端与第二端之间的电容值；
    一第一开关，耦接于該可调式电容模块的该第一端；
    一第二开关，耦接于該可调式电容模块的该第一端与一接地端之间；
    一第三开关，耦接于該可调式电容模块的该第二端与该运算放大器的该第一输入端之间；以及
    一第四开关，耦接于該可调式电容模块的该第二端与该接地端之间。
  6. 如权利要求5所述的积分电路，其中该可调式电容模块包含有若干个电容选择单元，分别受控于若干个第二控制信号，以调整该可调式电容模块的电容值；
    每一电容选择单元包含有：
    一电容；以及
    一控容开关，耦接于该电容。
  7. 如权利要求6所述的积分电路，其中所述若干个电容选择单元之间以并联的方式相互耦接，该每一电容选择单元中的该电容与该控容开关串联；或者其中所述若干个电容选择单元之间以串联的方式相互耦接，该每一电容选择单元中的该电容与该控阻开关相互并联。
  8. 如权利要求5所述的积分电路，其中该切换电容模块另包含：
    至少一电阻单元，耦接于该第一开关与该第三开关之间。
  9. 一种积分电路，包含有：
    一运算放大器；
    一积分电容，耦接于该运算放大器的一输出端及一第一输入端；以及
    一切换电容模块，耦接于该运算放大器的该第一输入端与该积分电路的该积分输入端之间，该切换电容模块包含有：
    一可调式电容模块，接收若干个控制信号，以调整该可调式电容模块的一第一端与一第二端之间之一电容值；
    一第一开关，耦接于該可调式电容模块的该第一端；
    一第二开关，耦接于該可调式电容模块的该第一端与一接地端之间；
    一第三开关，耦接于該可调式电容模块的该第二端与该运算放大器的该第一输入端之间；以及
    一第四开关，耦接于該可调式电容模块的该第二端与该接地端之间。
  10. 如权利要求9所述的积分电路，其中该可调式电容模块包含有若干个电容选择单元，分别受控于该若干个控制信号，每一电容选择单元包含有：
    一电容；以及
    一控容开关，耦接于该电容。
  11. 如权利要求10所述的积分电路，其中所述若干个电容选择单元之间以并联的方式相互耦接，该每一电容选择单元中的该电容与该控容开关串联；或者其中所述若干个电容选择单元之间以串联的方式相互耦接，该每一电容选择单元中的该电容与该控阻开关相互并联。
  12. 如权利要求9所述的积分电路，其中该切换电容模块另包含：
    至少一电阻单元，耦接于该第一开关与该第三开关之间。
  13. 一种信号处理模块，包含有：
    一切换式混波器；
    一模拟数字转换器；
    一积分电路，耦接于该切换式混波器与该模拟数字转换器之间，该积分电路包含有：
    一运算放大器；
    一积分电容单元，耦接于该运算放大器的一输出端及一第一输入端；以及
    一可调式模块，耦接于该运算放大器的该第一输入端与该积分电路的一积分输入端之间，该可调式模块受控于若干个信号，以调整该可调式模块的电阻值或电容值。
  14. 如权利要求13所述的信号处理模块，其中该可调式模块包含一可调式电阻模块，该可调式电阻模块接收若干个第一控制信号，以调整该可调式电阻模块的电阻值。
  15. 如权利要求14所述的信号处理模块，其中该可调式电阻模块包含有若干个电阻选择单元，分别受控于该若干个第一控制信号，每一电阻选择单元包含有：
    一电阻；以及
    一控阻开关，耦接于该电阻。
  16. 如权利要求15所述的信号处理模块，其中所述若干个电阻选择单元之间以并联的方式相互耦接，每一电阻选择单元中的该电阻与该控阻开关串联信号；或者所述若干个电阻选择单元之间以串联的方式相互耦接，该每一电阻选择单元中的该电阻与该控阻开关相互并联。
  17. 如权利要求13所述的信号处理模块，其中该可调式模块包含一切换电容模块，耦接于该运算放大器的该第一输入端与该积分电路的该积分输入端之间，该切换电容模块包含有：
    一可调式电容模块，接收若干个第二控制信号，以调整该可调式电容模块的一第一端与一第二端之间之一电容值；
    一第一开关，耦接于该第一端；
    一第二开关，耦接于该第一端与一接地端之间；
    一第三开关，耦接于该第二端与该运算放大器的该第一输入端之间；以及
    一第四开关，耦接于该第二端与该接地端之间。
  18. 如权利要求17所述的信号处理模块，其中该可调式电容模块包含有若干个电容选择单元，分别受控于该若干个第二控制信号，每一电容选择单元包含有：
    一电容；以及
    一控容开关，耦接于该电容。
  19. 如权利要求18所述的信号处理模块，其中所述若干个电容选择单元之间以并联的方式相互耦接，该每一电容选择单元中的该电容与该控容开关串联信号；或者其中所述若干个电容选择单元之间以串联的方式相互耦接，该每一电容选择单元中的该电容与该控阻开关相互并联。
  20. 如权利要求17所述的信号处理模块，其中该切换电容模块另包含：
    至少一电阻单元，耦接于该第一开关与该第三开关之间。
  21. 一种积分电路，包含有：
    一第一运算放大器；
    一可调式积分电容模块，耦接于该第一运算放大器的一第一输入端与一输出端之间，该可调式积分电容模块包含有若干个积分电容选择单元，每一积分电容选择单元包含有一积分电容及至少一开关；以及
    一电压跟随模块，耦接于该可调式积分电容模块的该若干个电容选择单元；
    其中，该可调式积分电容模块接收若干个控制信号，以调整该第一输入端与该输出端之间的一电容值。
  22. 如权利要求21所述的积分电路，其中该电压跟随模块具有若干个节点，该若干个节点分别电性连接于该若干个电容选择单元的该积分电容。
  23. 如权利要求22所述的积分电路，其中该电压跟随模块包含一电压跟随电路，该若干个节点的每一节点通过一第一开关耦接至该电压跟随电路的一输入端并且通过一第二开关耦接至该电压跟随电路的一输出端。
  24. 如权利要求23所述的积分电路，其中该电压跟随电路包含一第二运算放大器，其中该第二运算放大器的一第一输入端电性连接于该第二运算放大器的一输出端，该运算放大器的一第二输入端为该电压跟随电路的该输入端，该运算放大器的一输出端为该电压跟随电路的该输出端。
  25. 如权利要求21所述的积分电路，其中该若干个积分电容选择单元之间以并联的方式相互耦接。
  26. 如权利要求21所述的积分电路，其中该若干个积分电容选择单元之间以串联的方式相互耦接。
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