WO2017158725A1 - 対数尤度比算出回路、受信装置および対数尤度比算出方法 - Google Patents
対数尤度比算出回路、受信装置および対数尤度比算出方法 Download PDFInfo
- Publication number
- WO2017158725A1 WO2017158725A1 PCT/JP2016/058156 JP2016058156W WO2017158725A1 WO 2017158725 A1 WO2017158725 A1 WO 2017158725A1 JP 2016058156 W JP2016058156 W JP 2016058156W WO 2017158725 A1 WO2017158725 A1 WO 2017158725A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- signal
- modulo
- likelihood ratio
- calculation
- llr
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/38—Demodulator circuits; Receiver circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/45—Soft decoding, i.e. using symbol reliability information
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
- H04L25/067—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing soft decisions, i.e. decisions together with an estimate of reliability
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/497—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems
- H04L25/4975—Correlative coding using Tomlinson precoding, Harashima precoding, Trellis precoding or GPRS
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/0413—MIMO systems
Definitions
- the present invention relates to a log likelihood ratio calculation circuit, a receiver, and a log likelihood ratio calculation method in a digital communication system.
- DPC Densty Paper Coding
- Non-Patent Document 2 and Non-Patent Document 3 disclose a technique for performing waveform shaping by applying a non-linear operation called a modulo operation to a transmission signal. DPC in which this calculation is applied to the transmission signal after interference subtraction is called THP (Tomlinson-Harashima Precoding).
- a modulo operation is applied to each of a real part and an imaginary part of a complex signal, and is used to fit the signal within a certain complex region.
- a boundary value called a modulo boundary value is used.
- LLR Log-Likelihood Ratio
- Non-Patent Document 4 As an LLR calculation method, as disclosed in Non-Patent Document 4, among signal point candidates of which the target bit is 0, a signal point having a minimum Euclidean distance from the received signal (hereinafter referred to as a received signal) The signal point candidate having the smallest Euclidean distance is referred to as the maximum likelihood signal point) and the maximum likelihood signal point searched from the signal point candidate having a bit of 1, respectively, find the square of the Euclidean distance with the received signal, There is a method in which a value obtained by taking the difference between the squares of the Euclidean distance is set to LLR. When this method is theoretically analyzed, as disclosed in Non-Patent Document 5, it is possible to express mathematically according to the range of the received signal, and the LLR can be uniquely calculated from the value of the received signal.
- Non-Patent Document 6 the signal point space before the modulo operation is applied is assumed after the signal point space is expanded using the modulo boundary as a repetitive reference. Then, a technique for obtaining an LLR for signal point candidates in the expanded signal point space is disclosed as in Non-Patent Document 4. Further, in Non-Patent Document 7, in the case of a specific modulo boundary value, similarly to Non-Patent Document 5, a mathematical expression for calculating the LLR of a QAM (Quadrature Amplitude Modulation) modulation signal uniquely from the value of the received signal. An expression has been derived.
- QAM Quadrature Amplitude Modulation
- MAX H.M.COSTA “Writing on Dirty Paper,” IEEE TRANSACTIONS ON INFORMATION THEORY, VOL.IT-29, NO.3, pp.439-441, May 1983.
- M. TOMLINSON “NEW AUTOMATIC EQUALISER EMPLOYING MODULO ARITHMETIC,” ELECTRONICS LETTERS, Vol.7, pp.138-139, March 1971.
- H. HARASHIMA and H. MIYAKAWA “Matched-Transmission Technology for Channels With Intersymbol Interference,” IEEE TRANSACTIONS ON COMMUNICATIONS, VOL.COM-20, NO.4, pp.774-779, Aug. 1972.
- H. MATSUOKA S. Sampei, N.
- Non-Patent Document 6 can cope with an arbitrary modulo boundary value, it is necessary to search for a maximum likelihood signal point from among signal point candidates extended with reference to the modulo boundary. There is a problem that the amount of calculation required for the search and the hardware scale increase compared to the case where the modulo calculation is not performed.
- Non-Patent Document 7 can easily calculate the LLR of the QAM modulation signal even when performing a modulo operation, but an LLR calculation formula is derived for a specific modulo boundary value ⁇ , There is a problem that it cannot cope with an arbitrary modulo boundary value. Although the communication quality deteriorates as the modulo boundary value is smaller, an increase in the amplitude of the transmission signal can be suppressed. Therefore, in order to improve the design flexibility of the communication apparatus, a simple LLR corresponding to an arbitrary modulo boundary value. A calculation method is desired.
- the present invention has been made in view of the above, and a logarithmic likelihood ratio corresponding to an arbitrary modulo boundary value is calculated by suppressing a calculation amount and a hardware scale in a receiving device that performs a modulo operation. It is an object to obtain a log likelihood ratio calculation circuit capable of
- the log-likelihood ratio calculation circuit provides a received signal after modulo calculation, which of a plurality of ranges determined based on a boundary value in modulo calculation. Based on the detection result by the range detector and the detection result by the range detector, the coefficient used to calculate the log likelihood ratio of the most significant bit in the quadrature phase amplitude modulation of the received signal after the modulo operation is determined A coefficient determination unit.
- the log likelihood ratio calculation circuit includes a calculation unit that calculates the log likelihood ratio of the most significant bit using the received signal after the modulo operation and the determined coefficient.
- the log-likelihood ratio calculation circuit can calculate a log-likelihood ratio corresponding to an arbitrary modulo boundary value while suppressing a calculation amount and a hardware scale in a receiving apparatus that performs a modulo calculation. There is an effect.
- the figure which shows an example of the signal point before the modulo calculation in THP The figure which shows an example of the signal point after the modulo calculation in THP
- the figure which shows the signal point candidate of 3 bits corresponding to I axis The figure which shows the multiplication coefficient and addition value for every object bit when not performing a modulo operation
- the figure which shows an example of the signal point candidate before and behind the modulo calculation at the time of extending a signal point space The figure which shows the structural example of the LLR calculation part of Embodiment 1.
- FIG. 3 is a diagram illustrating a configuration example of a control circuit according to the first embodiment.
- FIG. 1 is a diagram of a configuration example of a communication system according to the first embodiment of the present invention.
- the communication system according to the present embodiment includes a transmission device 10 and a reception device 20.
- a signal transmitted from the transmission device 10 is received by the reception device 20 via the transmission path 30.
- interference that is, an interference signal and noise are added to the signal received by the receiving device 20 in the transmission path 30.
- the transmission device 10 includes an error correction encoding unit 11, a QAM modulation unit 12, an interference subtraction unit 13, and a modulo calculation unit 14.
- the error correction encoding unit 11 performs error correction encoding on transmission bits that are information to be transmitted. Any code may be used as the error correction code. For example, a convolutional code, a turbo code, an LDPC (Low Density Parity Check) code, or an RS (Reed Solomon) code can be used.
- a convolutional code a turbo code
- LDPC Low Density Parity Check
- RS Raster Solomon
- the QAM modulation unit 12 QAM modulates the error-corrected encoded signal.
- the interference subtracting unit 13 subtracts the interference signal from the QAM modulated signal.
- the process performed by the interference subtraction unit 13 is a process called DPC.
- the interference signal in the transmission line 30 is known or can be estimated, and the interference subtraction unit 13 removes the interference signal that is known or estimated. Any method may be used as a method of estimating the interference signal when the interference signal is estimated and used. As a specific estimation method, for example, if the interference signal is a fixed signal sequence that is generated periodically, the reception device detects the interference signal and notifies the interference signal information from the reception device to the transmission device using another line. Thus, the transmission device can also estimate.
- the transmission apparatus can cooperate with the transmission station of the interference source, the transmission apparatus can also infer the target signal that causes interference from the transmission station in advance.
- the modulo calculation unit 14 performs a modulo calculation on the signal processed by the interference subtraction unit 13.
- the process performed by the interference subtraction unit 13 and the modulo calculation unit 14 is a process called THP.
- the signal on which the modulo operation is performed by the modulo operation unit 14 is sent to the transmission line 30 as a transmission signal.
- the transmission signal may be a radio signal or a signal transmitted by wire.
- the receiving device 20 includes a detection unit 4, a modulo calculation unit 3, an LLR calculation unit 2, and an error correction decoding unit 1.
- the detection unit 4 performs a synchronization process and a transmission path fluctuation compensation process as a detection process on a signal received from the transmission device 10 via the transmission path 30.
- a specific synchronization process for example, a correlation calculation is performed on a received signal sequence to perform timing detection.
- the present invention is not limited to this, and any synchronization process may be performed.
- a specific transmission path fluctuation compensation process for example, a transmission path value between transmission and reception is estimated, and a detection axis rotated due to transmission path fluctuation is corrected correctly by multiplying the reception signal sequence by the complex conjugate of that value.
- the modulo calculation unit 3 performs I / Q separation on the complex signal after the detection processing, and performs modulo calculation on each real signal of I / Q.
- the LLR calculation unit 2 that is a log likelihood ratio calculation circuit calculates an LLR using a real number signal after a modulo calculation.
- the error correction decoding unit 1 performs soft decision error correction decoding using the LLR and calculates an estimated value of transmission bits.
- the modulo operation and THP will be described.
- the operator shown in the following formula (1) is an operator that gives the maximum integer not exceeding a.
- x is an input signal to the modulo operation
- y is an output signal of the modulo operation
- ⁇ is a modulo boundary value
- x and y are real numbers
- the modulo operation can be expressed by the following equation (2).
- Expression (2) the input / output of the modulo operation is a real number.
- the modulo operation is an operation that fits an input signal into a signal within a certain range, and a value that defines this range is a modulo boundary value.
- the signal after applying the modulo operation is limited to a range of [ ⁇ , + ⁇ ], and 2 ⁇ ⁇ is also called a modulo width.
- the output signal y is output as a range-limited value with ⁇ 1 as a boundary so as to be in the range of [ ⁇ 1, +1].
- the modulo calculation in THP performed by the transmission apparatus 10 is used to keep a signal obtained by removing an interference signal from a complex signal generated by modulation within a certain range.
- 3 and 4 are diagrams illustrating an example of signal points before and after a modulo calculation in THP.
- FIG. 3 shows an example of signal points when an interference signal is removed from a QPSK (Quadrature Phase Shift Keying) modulated signal.
- FIG. 4 is a diagram illustrating an example of signal points when a modulo operation is applied to the signal illustrated in FIG. 3.
- the original signal of QPSK is ( ⁇ 1 / ⁇ (2), ⁇ 1 / ⁇ (2)), and the modulo boundary value ⁇ is 1.225.
- Receiving device 20 of the present embodiment receives a signal subjected to THP as described above in transmitting device 10.
- QPSK modulation has been described as an example for explaining the modulo operation.
- FIG. 5 is a diagram illustrating 3-bit signal point candidates corresponding to the I axis. As shown in FIG. 5, the signal point candidates on the I axis are ⁇ 2 m +1, ⁇ 2 m +3,..., 2 m ⁇ 3, 2 m ⁇ 1, that is, ⁇ 7, ⁇ 5, ⁇ 3, ⁇ 1.
- b 0 is a bit distinguished by positive and negative on the I axis and is defined as MSB (Most Significant Bit). Although the description is omitted, the same applies to the Q axis. If the 3 bits corresponding to the Q axis are b 3 , b 4 , and b 5 , the 3 bits b 0 , b 1 , b corresponding to the I axis respectively. Signal point candidates can be determined as in 2 .
- the MSB on the Q axis is b 3 .
- the received signal has a signal scale with an average power of 1, the received signal is multiplied by ⁇ (2 ⁇ (M ⁇ 1) / 3) to obtain ⁇ 2 m +1, ⁇ 2 m +3. ..., it is corrected so as to be 2 m-3,2 m -1 the same scale and the signal point candidates.
- ⁇ 3
- M 64
- ⁇ (42) is multiplied by the received signal.
- the modulo boundary value ⁇ in the present embodiment is a value that includes the outermost point of the QAM modulated signal. That is, it is assumed that 2 m ⁇ 1 ⁇ .
- the receiving device 20 needs to calculate the LLR when performing soft decision error correction decoding.
- the LLR calculation method for a QAM modulation signal when the modulo operation is not applied that is, the techniques disclosed in Non-Patent Documents 4 and 5 will be described.
- ⁇ (bar) bi (y c ) which is an LLR in which the fixed coefficient is omitted, is defined by the following expression (4).
- the LLR will be discussed according to the definition formula of Formula (4).
- the LLR of the QAM modulated signal is the received complex signal y c and the maximum likelihood signal point where the bit b i of interest is 0 and the maximum likelihood signal point where the bit b i is 1, respectively.
- the square of the Euclidean distance is obtained and the difference is obtained. This is the principle of LLR calculation disclosed in Non-Patent Document 4.
- the received complex signal y c is I / Q independent, it is divided into two real signals of I / Q, and when equation (4) is solved by applying a specific maximum likelihood signal point, it corresponds to the I axis.
- (4) can be expressed as a linear expression of the received signal y by dividing the case within the range of the received real signal y. For example, ⁇ (bar) b0 (y) (L (y)), ⁇ (bar) b1 (y) and ⁇ (bar) which are LLRs for 3 bits b 0 , b 1 and b 2 on the I axis of 64QAM
- the theoretical formula of b2 (y) can be expressed by the following formula (5), formula (6) and formula (7), respectively.
- the LLR is determined by determining the case in the range of the received signal y and determining the multiplication coefficient and the addition value according to the corresponding range. It can be calculated by applying the multiplication coefficient and the added value to the received signal y. This is a mathematical expression of the LLR calculation method disclosed in Non-Patent Document 5.
- FIG. 6 is a diagram illustrating a multiplication coefficient and an addition value for each target bit when the modulo operation is not performed.
- Non-Patent Document 6 describes a technique for extending a signal point space using a modulo boundary as a repetitive reference.
- FIG. 7 is a diagram illustrating an example of signal point candidates before and after the modulo calculation when the signal point space is expanded.
- an image of an extended signal point candidate in a 16QAM modulated signal is illustrated.
- a range 500 surrounded by a thick line in the center of FIG. 7 indicates a signal point space in the 16QAM modulated signal before expansion, and 16 signal point candidates are included in this range 500.
- Non-Patent Document 6 can cope with an arbitrary modulo boundary value, it is necessary to search for a maximum likelihood signal point from among QAM modulation signal point candidates extended with reference to the modulo boundary. As a result, there is a problem that the amount of calculation required for the search and the hardware scale increase compared to the case where the modulo calculation is not performed.
- the LLR calculation unit 2 that can cope with the modulo boundary value while suppressing the calculation amount and the hardware scale of the reception apparatus 20. The configuration and operation will be described.
- FIG. 8 is a diagram illustrating a configuration example of the LLR calculation unit 2 of the present embodiment.
- the LLR calculation unit 2 of the present embodiment includes a b 0 LLR calculation unit 21, a b 1 LLR calculation unit 22, and a b 2 LLR calculation unit 23.
- the LLR calculation unit 2 receives either the signal c0 indicating the modulo boundary value ⁇ from the modulo calculation unit 3 in the previous stage, and either the I axis or the Q axis after the reception complex signal is subjected to detection processing and modulo calculation.
- a real signal is input.
- a signal on the I-axis or a real signal on the Q-axis that is an object of LLR calculation is d0.
- Output signal output from the LLR calculating section 2 includes a d10 output from and b 0 for LLR calculation unit 21 a LLR corresponding to b 0, from b 1 for LLR calculation unit 22 a LLR corresponding to b 1
- the output d11 is the LLR corresponding to b 2 and d12 output from the b 2 LLR calculation unit 23.
- modulo boundary value c0 is input to b 0 for LLR calculation unit 21.
- FIG. 9 is a diagram illustrating a configuration example of the b 0 LLR calculation unit 21.
- b 0 for LLR calculation unit 21 includes a range detector 211, coefficient determination section 212 and the LLR calculation section 213.
- the range detection unit 211 performs positive / negative determination and absolute value range detection on the input d0. That is, the range detection unit 211 detects which range of the plurality of ranges determined based on the boundary value in the modulo calculation is within the received signal after the modulo calculation. Specifically, the range detection unit 211 determines whether d0 is equal to or greater than 0 , and in which range the absolute value of d0 is within a plurality of ranges corresponding to b0 described later. Determine. Note that the plurality of ranges corresponding to b 0 are determined depending on c 0, that is, ⁇ .
- the determination result as to which range of the plurality of ranges the absolute value of d0 is called a range detection value.
- the range detection unit 211 calculates sign (y) and the range detection value.
- the range detection unit 211 outputs the calculated sign (y) and the range detection value to the coefficient determination unit 212.
- the coefficient determining unit 212 uses the multiplication coefficient ⁇ 0 (y) and the added value ⁇ 0 based on the sign (y) and the range detection value received from the range detection unit 211 and c0, that is, ⁇ input from the modulo calculation unit 3. (Y) is obtained and output to the LLR calculator 213.
- the multiplication coefficient ⁇ 0 (y) and the addition value ⁇ 0 (y) are coefficients for calculating the LLR.
- the coefficient here includes a multiplication coefficient ⁇ 0 (y) and a constant term, that is, an addition value ⁇ 0 (y). That is, coefficient determination section 212 determines a coefficient used for calculating the LLR of the most significant bit in the quadrature phase amplitude modulation of the received signal after the modulo calculation based on the detection result by range detection section 211.
- the LLR calculation unit 213 uses the multiplication coefficient ⁇ 0 (y) and the addition value ⁇ 0 (y) received from the coefficient determination unit 212 and d0 received from the modulo calculation unit 3 according to the above-described equation (8).
- the LLR is calculated, and the LLR for the bit b 0 is output to the subsequent error correction decoding unit 1 as d10. That is, the LLR calculation unit 213 is a calculation unit that calculates the log likelihood ratio of the most significant bit using the received signal after the modulo calculation and the coefficient determined by the coefficient determination unit 212.
- the LLR calculation unit 213 multiplies the reception signal after the modulo calculation by the multiplication coefficient ⁇ 0 (y), and adds the addition value ⁇ 0 (y) to the result obtained by the multiplication, thereby obtaining the highest order. Calculate the LLR of the bit.
- FIG. 10 is a diagram illustrating a configuration example of the b 1 LLR calculation unit 22.
- the configuration of the b 1 LLR calculation unit 22 is the same as that of the b 0 LLR calculation unit 21 except that the modulo boundary value c0 is not input as shown in FIG.
- the b 1 LLR calculation unit 22 includes a range detection unit 221, a coefficient determination unit 222, and an LLR calculation unit 223.
- the range detection unit 221 performs positive / negative sign determination and range detection on d0 input from the modulo calculation unit 3. In the range detection in the range detection unit 221, it is determined which range of the plurality of ranges corresponding to the predetermined b 1 is the absolute value of d0.
- the range detection unit 221 outputs the obtained range detection value to the coefficient determination unit 222.
- Coefficient determination unit 222 obtains multiplication coefficient ⁇ 1 (y) and addition value ⁇ 1 (y) based on sign (y) and range detection value received from range detection unit 221, and outputs them to LLR calculation unit 223.
- the LLR calculation unit 223 uses the multiplication coefficient ⁇ 1 (y) and the addition value ⁇ 1 (y) received from the coefficient determination unit 222 and d0 received from the modulo calculation unit 3 according to the above equation (8). calculating the LLR, the LLR for bit b 1, and outputs to the subsequent error correction decoding unit 1 as d11.
- the range detection unit in the b 2 LLR calculation unit 23 performs positive / negative sign determination and range detection on d0 input from the modulo calculation unit 3. In the range detection by the range detection unit in the b 2 LLR calculation unit 23, it is determined which range of the plurality of ranges corresponding to the predetermined b 2 is the absolute value of d0.
- range detection unit b 2 for LLR calculation unit 23 outputs the range detection value obtained to the coefficient determining unit of b 2 for LLR calculation unit 23.
- the coefficient determination unit of the b 2 LLR calculation unit 23 obtains the multiplication coefficient ⁇ 2 (y) and the addition value ⁇ 2 (y) based on the sign (y) and the range detection value received from the range detection unit, and performs the LLR calculation. Output to the section.
- the LLR calculation unit uses the multiplication coefficient ⁇ 2 (y) and the addition value ⁇ 2 (y) received from the coefficient determination unit and d0 received from the modulo calculation unit 3 to calculate the LLR according to the above-described equation (8).
- the LLR for the bit b 1 is calculated and output to the subsequent error correction decoding unit 1 as d12.
- FIG. 11 is a diagram illustrating an example of signal candidate points on the I axis when a modulo operation is applied in 64QAM modulation.
- ⁇ > 2 m ⁇ 1 7 here.
- the received signal y is limited to the region
- x can be a value in a region where
- 8 points of ⁇ 2 ⁇ + 1, ⁇ 2 ⁇ + 3, ⁇ 2 ⁇ + 5, ⁇ 2 ⁇ + 7 and 2 ⁇ 7, 2 ⁇ 5, 2 ⁇ 3, and 2 ⁇ 1 are added as assumed signal candidate points before the modulo calculation.
- 8 points of ⁇ 2 ⁇ + 1, ⁇ 2 ⁇ + 3, ⁇ 2 ⁇ + 5, ⁇ 2 ⁇ + 7 and 2 ⁇ 7, 2 ⁇ 5, 2 ⁇ 3, and 2 ⁇ 1 are added as assumed signal candidate points before the modulo calculation.
- An added signal point region that is, a region where
- ⁇ 2 ⁇ + 1, ⁇ 2 ⁇ + 3, ⁇ 2 ⁇ + 5, ⁇ 2 ⁇ + 7 correspond to the original signal points +1, +3, +5, and +7, respectively.
- the original signal point is a signal point before adding a signal point of the modulo repetitive virtual region.
- the LLR of the MSB is considered in a range that can be taken by y.
- the case of y ⁇ 0 will be described, but the case of y ⁇ 0 can be considered similarly.
- Condition (a): 2n ⁇ y ⁇ 2 (n + 1); (n 0, 1, 2)
- the LLR of b 0 which is the MSB can be obtained as the following equation (11).
- the integer n satisfying 2 ⁇ n ⁇ y ⁇ 2 ⁇ (n + 1) is equal to or larger than the maximum integer not exceeding ( ⁇ 4) / 2 by ⁇ > 7 and the condition (d).
- Bits other than the MSB are the same as when the modulo operation is not applied, that is, when the signal point of the modulo repetitive virtual area is not added.
- the LLRs of b 1 and b 2 in the case of 64QAM can be calculated by equations (6) and (7), respectively. This is because, in a Gray-coded QAM modulation signal point, a signal point candidate in the modulo repetitive virtual region does not become a maximum likelihood signal point for bits other than the MSB.
- the range detection unit 211 calculates sign (y) and performs range detection corresponding to the four case classifications in the above equation (14).
- the coefficient determination unit 212 calculates the multiplication coefficient ⁇ 0 (y) and the addition value ⁇ 0 (y) according to the equation (14) based on the sign (y) and the range detection result.
- FIG. 12 is a diagram illustrating an example of setting values set in the range detection unit 211 and the coefficient determination unit 212 of the present embodiment.
- a table or a calculation formula for determining seven ranges from (R1) to (R7) is set in the range detection unit 211.
- the coefficient determination unit 212 sets correspondence between the determination result of the range detection unit 211 and a table or calculation formula for calculating a multiplication coefficient and an addition value.
- the LLR calculation unit 213 uses the multiplication coefficient ⁇ 0 (y), the addition value ⁇ 0 (y), and d0 received from the modulo calculation unit 3, that is, y according to the above equation (8). to calculate the LLR of b 0.
- the range detection unit and the coefficient setting unit are set according to the values corresponding to the target bits corresponding to those in FIG. . That is, the table or calculation formula for determining the three ranges shown in FIG. 6 is set in the range detecting unit of the b 1 LLR calculating unit 22.
- the coefficient setting unit of b 1 for LLR calculation unit 22, the correspondence between a table or calculation formula for calculating the multiplication factor and the added value for the judgment result and b 1 by range detector of b 1 for LLR calculation unit 22 Is set in advance.
- the range detection unit of the b 2 LLR calculation unit 23 is set with a table or a calculation formula for determining the two ranges shown in FIG.
- the coefficient setting unit of b 2 for LLR calculation unit 23, the correspondence between a table or calculation formula for calculating the multiplication factor and the added value for the judgment result and b 2 by the range detector of b 2 for LLR calculation unit 23 Is set in advance.
- the detector 4 is an equalizer or a demodulator.
- the modulation processing includes discrete Fourier transform processing
- the detection unit 4 is added with a discrete Fourier transform processing circuit.
- the modulo calculation unit 3 is a processing circuit that performs a modulo calculation
- the LLR calculation unit 2 is a processing circuit that calculates an LLR as described above.
- the error correction decoding unit 1 is a processing circuit that performs error correction decoding. When bit interleaving is performed in the transmission apparatus 10, a deinterleaver is added.
- the processing circuit that realizes the LLR calculation unit 2 is a dedicated hardware, a CPU (Central Processing Unit, a central processing unit, a processing unit, an arithmetic unit, a microprocessor, and a CPU that executes a program stored in the memory. It may be a control circuit including a microcomputer, a processor, and a DSP (Digital Signal Processor).
- the memory is, for example, a RAM (Random Access Memory), a ROM (Read Only Memory), a flash memory, an EPROM (Erasable Programmable Read Only Memory), an EEPROM (Electrically Portable Memory), or the like. Volatile semiconductor memories, magnetic disks, flexible disks, optical disks, compact disks, mini disks, DVDs (Digital Versatile Disks), and the like are applicable.
- the LLR calculation unit 2 When the LLR calculation unit 2 is realized by dedicated hardware, these include, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field). Programmable Gate Array), or a combination of these.
- this processing circuit is, for example, the processing circuit 300 shown in FIG. FIG. 13 is a diagram illustrating the processing circuit 300.
- the control circuit is, for example, a control circuit 400 having a configuration shown in FIG.
- the control circuit 400 includes a processor 401 that is a CPU and a memory 402.
- FIG. 14 is a diagram illustrating a configuration example of the control circuit 400.
- the processor 401 is realized by reading and executing a program stored in the memory 402 and corresponding to the processing of the LLR calculation unit 2.
- the memory 402 is also used as a temporary memory in each process executed by the processor 401.
- the detection unit 4, the modulo calculation unit 3, and the error correction decoding unit 1 may be realized by the processing circuit 300 that is dedicated hardware, like the LLR calculation unit 2 described above.
- the control circuit 400 may implement
- each component constituting the transmission device 10 shown in FIG. 1 can be realized as an electronic circuit.
- the error correction encoding unit 11, the QAM modulation unit 12, the interference subtraction unit 13, and the modulo calculation unit 14 in the transmission apparatus 10 may be realized by the processing circuit 300 that is dedicated hardware or realized by the control circuit 400. May be.
- the LLR for b 0 that is the MSB is easily obtained for any modulo boundary value by the above-described range detection unit 211, coefficient determination unit 212, and LLR calculation unit 213. It can be calculated.
- the LLR calculation units 22 and 23 for b 1 and the bit b 2 do not need to use a modulo boundary value in the calculation of the LLR, and thus are the same as the LLR calculation in the QAM modulation without using the modulo operation. Detailed description of the specific operation is omitted.
- the processing performed by the LLR calculation unit 213 described in the present embodiment does not include multiplication of the coefficient 1 / (2 ⁇ 2 ) for reflecting the noise power defined by Expression (2).
- the processing performed by the LLR calculation unit 213 may include multiplication by a coefficient 1 / (2 ⁇ 2 ). For example, when a plurality of LLRs having different noise powers are simultaneously processed by the error correction decoding unit 1 in the subsequent stage and ⁇ 2 is known or can be estimated, the LLR calculation unit 213 adds a coefficient 1 to the calculated value of the LLR. / (2 ⁇ 2 ) may be multiplied.
- the LLR calculation unit 213 may multiply the calculated value of the LLR by the SNR. That is, the LLR calculation unit 2 may further calculate the LLR based on the noise power or the signal-to-noise power ratio.
- the LLR calculation unit 213 uses 2 (M ⁇ 1) / 3 which is the square of the coefficient for correcting the signal scale. Each LLR may be divided. That is, the LLR calculation unit 213 may correct the signal scale by dividing the LLR of the most significant bit calculated using the multiplication coefficient and the addition value by 2 (2 2m ⁇ 1) / 3.
- communication performed in the communication system of the present embodiment may be wired communication or wireless communication. Further, communication performed in the communication system of the present embodiment may be multicarrier communication or single carrier communication. In the communication system shown in FIG. 1, one transmission system and one reception system are illustrated, but the present invention is not limited to this, and there may be a plurality of signal systems for both transmission and reception.
- a transmission method including a plurality of antennas (input / output systems) for transmission and reception called MIMO (Multiple-Input Multiple-Output) is used. Spatial multiplex transmission may be performed.
- the LLR calculation unit 2 of the present embodiment is a simple process based on a range detection process, a coefficient determination process, and an LLR calculation process on a received signal that has been subjected to a modulo operation for an arbitrary modulo boundary value.
- LLR can be calculated. That is, the LLR calculation unit 2 of the present embodiment can calculate the log likelihood ratio corresponding to an arbitrary modulo boundary value while suppressing the amount of calculation and the hardware scale.
- the configuration described in the above embodiment shows an example of the contents of the present invention, and can be combined with another known technique, and can be combined with other configurations without departing from the gist of the present invention. It is also possible to omit or change the part.
Abstract
Description
図1は、本発明の実施の形態1にかかる通信システムの構成例を示す図である。図1に示すように、本実施の形態の通信システムは、送信装置10および受信装置20を備える。送信装置10から送信される信号は伝送路30を介して受信装置20により受信される。受信装置20により受信される信号には、一般に、伝送路30において、干渉すなわち干渉信号、および雑音が付加される。
条件(a):2n≦y<2(n+1);(n=0,1,2)
条件(b):6≦y
条件(c):y<τ-4
条件(d):τ-4≦y
Claims (7)
- モジュロ演算後の受信信号が、モジュロ演算における境界値に基づいて定まる複数の範囲のうちのどの範囲内であるかを検出する範囲検出部と、
前記範囲検出部による検出結果に基づいて、前記モジュロ演算後の受信信号の直交位相振幅変調における最上位ビットの対数尤度比の計算に用いる係数を決定する係数決定部と、
前記モジュロ演算後の受信信号および決定された前記係数を用いて前記最上位ビットの対数尤度比を計算する計算部と、
を備えることを特徴とする対数尤度比算出回路。 - 前記係数は、乗算係数および加算値を含み、
前記計算部は、前記モジュロ演算後の受信信号に前記乗算係数を乗算し、乗算により得られた結果に前記加算値を加算することにより前記最上位ビットの対数尤度比を計算することを特徴とする請求項1に記載の対数尤度比算出回路。 - 前記計算部は、さらに雑音電力または信号対雑音電力比に基づいて前記最上位ビットの対数尤度比を計算することを特徴とする請求項1から3のいずれか1つに記載の対数尤度比算出回路。
- 前記計算部は、前記係数を用いて計算された前記最上位ビットの対数尤度比を2×(22m-1)/3で除算することにより信号スケールの補正を行うことを特徴とする請求項3に記載の対数尤度比算出回路。
- 請求項1から5のいずれか1つに記載の対数尤度比算出回路を備えることを特徴とする受信装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2016/058156 WO2017158725A1 (ja) | 2016-03-15 | 2016-03-15 | 対数尤度比算出回路、受信装置および対数尤度比算出方法 |
US16/082,517 US20190081846A1 (en) | 2016-03-15 | 2016-03-15 | Log-likelihood ratio calculation circuit, reception device, and log-likelihood ratio calculation method |
JP2018505109A JPWO2017158725A1 (ja) | 2016-03-15 | 2016-03-15 | 対数尤度比算出回路、受信装置および対数尤度比算出方法 |
CN201680083321.XA CN108781129A (zh) | 2016-03-15 | 2016-03-15 | 对数似然比计算电路、接收装置及对数似然比计算方法 |
EP16894347.0A EP3432496A4 (en) | 2016-03-15 | 2016-03-15 | CIRCUIT FOR THE CALCULATION OF THE LOG PROPERTY RATIO, RECEIVER AND METHOD FOR CALCULATING THE LOG PROPERTY RATIO |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2016/058156 WO2017158725A1 (ja) | 2016-03-15 | 2016-03-15 | 対数尤度比算出回路、受信装置および対数尤度比算出方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2017158725A1 true WO2017158725A1 (ja) | 2017-09-21 |
Family
ID=59851146
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2016/058156 WO2017158725A1 (ja) | 2016-03-15 | 2016-03-15 | 対数尤度比算出回路、受信装置および対数尤度比算出方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20190081846A1 (ja) |
EP (1) | EP3432496A4 (ja) |
JP (1) | JPWO2017158725A1 (ja) |
CN (1) | CN108781129A (ja) |
WO (1) | WO2017158725A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2020048414A1 (zh) * | 2018-09-03 | 2020-03-12 | 华为技术有限公司 | 参数配置方法和装置 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113519126A (zh) * | 2019-03-11 | 2021-10-19 | 三菱电机株式会社 | 光传输装置和似然度生成电路 |
US11387935B2 (en) * | 2021-02-19 | 2022-07-12 | Ultralogic 6G, Llc | Error detection and correction by modulation quality in 5G/6G |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7451361B2 (en) * | 2005-01-27 | 2008-11-11 | General Instrument Corporation | Method and apparatus for forward error correction in a content distribution system |
WO2012070369A1 (ja) * | 2010-11-26 | 2012-05-31 | 三菱電機株式会社 | 軟判定値生成回路 |
CN102185824B (zh) * | 2011-04-25 | 2014-04-16 | 武汉邮电科学研究院 | 一种适用于高阶qam的载波相位纠偏方法 |
JP5847335B2 (ja) * | 2012-12-14 | 2016-01-20 | 三菱電機株式会社 | Qam変調通信システムの多値差動復号装置および方法 |
-
2016
- 2016-03-15 JP JP2018505109A patent/JPWO2017158725A1/ja active Pending
- 2016-03-15 EP EP16894347.0A patent/EP3432496A4/en not_active Withdrawn
- 2016-03-15 CN CN201680083321.XA patent/CN108781129A/zh not_active Withdrawn
- 2016-03-15 US US16/082,517 patent/US20190081846A1/en not_active Abandoned
- 2016-03-15 WO PCT/JP2016/058156 patent/WO2017158725A1/ja active Application Filing
Non-Patent Citations (11)
Title |
---|
AKINORI OHASHI ET AL.: "A Study on Low- Complexity Calculation of Log Likelihood Ratio for Quardrature Amplitude Modulation", 2013 NEN IEICE COMMUNICATIONS SOCIETY CONFERENCE TSUSHIN KOEN RONBUNSHU 1 , IEICE, 20 September 2013 (2013-09-20), pages 368, XP000990996 * |
E.C.Y. PEH; Y.-C. LIANG: "Power and Modulo Loss Tradeoff with Expanded Soft Demapper for LDPC Coded GMD-THP MIMO Systems", IEEE TRANSACTIONS ON WIRELESS COMMUNICATIONS, vol. 8, no. 2, February 2009 (2009-02-01), pages 714 - 724, XP011252004 |
H. HARASHIMA; H. MIYAKAWA: "Matched-Transmission Technique for Channels With Intersymbol Interference", IEEE TRANSACTIONS ON COMMUNICATIONS, vol. 20, no. 4, August 1972 (1972-08-01), pages 774 - 779, XP000990996 |
H. MATSUOKA; S. SAMPEI; N. MORINAGA; Y. KAMIO: "Adaptive Modulation System with Punctured Convolutional Code for High Quality Personal Communication Systems", IEICE TRANS. COMMUN., vol. E79-B, no. 3, March 1996 (1996-03-01), pages 328 - 334, XP000588456 |
M. TOMLINSON: "NEW AUTOMATIC EQUALISER EMPLOYING MODULO ARITHMETIC", ELECTRONICS LETTERS, vol. 7, March 1971 (1971-03-01), pages 138 - 139, XP000761097 |
MAX H. M. COSTA: "Writing on Dirty Paper", IEEE TRANSACTIONS ON INFORMATION THEORY, vol. 29, no. 3, May 1983 (1983-05-01), pages 439 - 441 |
R. PYNDIAH; A. PICART; A. GLAVIEUX: "PERFORMANCE OF BLOCK TURBO CODED 16-QAM AND 64-QAM MODULATIONS", PROC. GLOBECOM'95, vol. 2, November 1995 (1995-11-01), pages 1039 - 1043, XP010164530, DOI: doi:10.1109/GLOCOM.1995.502563 |
S. KINJO: "An efficient soft demapper for Tomlinson-Harashima precoded systems", IEICE COMMUNICATIONS EXPRESS, vol. 4, no. 3, March 2015 (2015-03-01), pages 89 - 94 |
See also references of EP3432496A4 * |
SHIGENORI KINJO: "A low complexity soft demapping method for expanded M-QAM constellations", CIRCUITS AND SYSTEMS (APCCAS) , 2014 IEEE ASIA PACIFIC CONFERENCE ON, 17 November 2014 (2014-11-17) - 24 November 2014 (2014-11-24), pages 137 - 140, XP055537489, Retrieved from the Internet <URL:DOI:10.1109/APCCAS.2014.7032738> * |
YASUHIKO TANABE ET AL.: "An Error Reduction Method of Modulo Operation for a MIMO Broadcast Channel Using Tomlinson-Harashima Precoding in Low SNR Region", 2008 NEN IEICE COMMUNICATIONS SOCIETY CONFERENCE KOEN RONBUNSHU 1, 2 September 2008 (2008-09-02), pages S-1 - S-2, XP000761097 * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2020048414A1 (zh) * | 2018-09-03 | 2020-03-12 | 华为技术有限公司 | 参数配置方法和装置 |
Also Published As
Publication number | Publication date |
---|---|
EP3432496A4 (en) | 2019-10-23 |
US20190081846A1 (en) | 2019-03-14 |
JPWO2017158725A1 (ja) | 2019-01-17 |
CN108781129A (zh) | 2018-11-09 |
EP3432496A1 (en) | 2019-01-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8737458B2 (en) | Highly-spectrally-efficient reception using orthogonal frequency division multiplexing | |
KR101124863B1 (ko) | 다중 소스로부터의 통신신호를 처리하는 장치 및 방법 | |
US9319182B2 (en) | Near maximum likelihood spatial multiplexing receiver | |
US20160065275A1 (en) | Multiple input multiple output communications over nonlinear channels using orthogonal frequency division multiplexing | |
EP2200240A1 (en) | Method and apparatus for near-optimal computation of bit soft information in multiple antenna communication systems with iterative detection and decoding | |
US20090041165A1 (en) | Receiver apparatus | |
JP2004509521A (ja) | 適応アルゴリズムを用いて適応チャネル等化器の重みベクトルのスパーシティを活用する装置および方法 | |
US9634879B2 (en) | Demodulator apparatus and demodulation method | |
WO2014034676A1 (ja) | 受信機、送信機、および通信方法 | |
EP3193453B1 (en) | Wireless communication device and method | |
US9083499B1 (en) | Decision feedback solution for channels with low signal to noise ratio | |
WO2017158725A1 (ja) | 対数尤度比算出回路、受信装置および対数尤度比算出方法 | |
US8711958B2 (en) | Method for decoding a spatially multiplexed data signal using a maximum likelihood detection | |
EP2680520B1 (en) | Method and apparatus for efficient MIMO reception with reduced complexity | |
JP4380407B2 (ja) | ブランチメトリック演算方法 | |
US8428169B1 (en) | MIMO soft demodulation using hard-decision candidate selection | |
US9531577B2 (en) | Bit-likelihood calculating apparatus and bit-likelihood calculating method | |
JP4611271B2 (ja) | 受信装置 | |
JP5700644B2 (ja) | 無線通信システム、無線通信方法及び無線端末 | |
JP2013162312A (ja) | 受信装置及びプログラム | |
JP2008263366A (ja) | 受信装置 | |
US9917723B2 (en) | Efficient methods and recursive/scalable circuit architectures for QAM symbol mean and variance estimations | |
JP6731771B2 (ja) | デマッピング処理回路、チップ、及び受信装置 | |
JP5581967B2 (ja) | 分散推定方法、分散推定装置、変調信号生成方法、変調信号生成装置、および、コンピュータ・プログラム | |
KR101351577B1 (ko) | 다중 입력 다중 출력 통신 시스템의 심볼 검파 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ENP | Entry into the national phase |
Ref document number: 2018505109 Country of ref document: JP Kind code of ref document: A |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2016894347 Country of ref document: EP |
|
ENP | Entry into the national phase |
Ref document number: 2016894347 Country of ref document: EP Effective date: 20181015 |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 16894347 Country of ref document: EP Kind code of ref document: A1 |