WO2017156914A1 - 金属化叠层及包括其的半导体器件和电子设备 - Google Patents

金属化叠层及包括其的半导体器件和电子设备 Download PDF

Info

Publication number
WO2017156914A1
WO2017156914A1 PCT/CN2016/087253 CN2016087253W WO2017156914A1 WO 2017156914 A1 WO2017156914 A1 WO 2017156914A1 CN 2016087253 W CN2016087253 W CN 2016087253W WO 2017156914 A1 WO2017156914 A1 WO 2017156914A1
Authority
WO
WIPO (PCT)
Prior art keywords
metallization stack
negative capacitance
conductive interconnect
dielectric material
interlayer dielectric
Prior art date
Application number
PCT/CN2016/087253
Other languages
English (en)
French (fr)
Inventor
朱慧珑
Original Assignee
中国科学院微电子研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Publication of WO2017156914A1 publication Critical patent/WO2017156914A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors

Definitions

  • the present disclosure relates to semiconductor technology and, more particularly, to a metallization stack capable of reducing capacitance between conductive interconnect members and semiconductor devices and electronic devices including such metallization stacks.
  • a metallization stack includes an interlayer dielectric layer that includes a dielectric material and a negative capacitance material. At least one pair of first conductive interconnect members formed in the interlayer dielectric layer at least partially opposite each other includes both a dielectric material and a negative capacitance material between their opposing portions, and/or the interlayer dielectric layer At least one second conductive interconnect member formed in the upper layer and at least one third conductive interconnect member formed in the lower layer of the interlayer dielectric layer at least partially opposite the second conductive interconnect member between their opposite portions Including dielectric Both materials and negative capacitance materials.
  • a semiconductor device including the metallization stack described above.
  • an electronic device including an integrated circuit formed by the above semiconductor device is provided.
  • both a dielectric material and a negative capacitance material may be included between a pair of electrically conductive interconnect members that are at least partially opposite each other such that both positive and negative capacitances may be generated between the pair of electrically conductive interconnection members.
  • both positive and negative capacitances may be generated between the pair of electrically conductive interconnection members. Due to the presence of a negative capacitance (especially where both positive and negative capacitances are connected in parallel), the total capacitance between the pair of electrically conductive interconnect members can be reduced.
  • FIG. 1 is a schematic circuit diagram showing capacitance between a pair of electrically conductive interconnect members in accordance with an embodiment of the present disclosure
  • FIGS. 2(a)-2(g) are cross-sectional views showing partial stages in a process of fabricating a metallization stack in accordance with an embodiment of the present disclosure
  • 3(a)-3(e') are cross-sectional views showing portions of a process for fabricating a metallization stack in accordance with another embodiment of the present disclosure.
  • a layer/element when referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be a central layer between them/ element. In addition, if a layer/element is "on” another layer/element, the layer/element may be "under” the other layer/element when the orientation is reversed.
  • FIG. 1 is a schematic circuit diagram showing capacitance between a pair of electrically conductive interconnect members in accordance with an embodiment of the present disclosure.
  • a conductive interconnection member may be formed M 1 and M 2.
  • a conductive interconnect member may be a contact that contacts a terminal (eg, a gate, a source, or a drain terminal) of a semiconductor device formed in the substrate, and may be a conductive via that communicates with the upper and lower layers (via It may be a conductive interconnection or wiring that travels in a certain path in the IL to connect the contacts/conducting channels to each other or to a certain terminal (eg, a pad).
  • the contact portion is substantially identical in form to the conductive via, typically a conductive material (eg, a metal such as Cu, Al, or W) embedded in a via extending through the IL; the conductive interconnect is typically embedded in the through IL And a conductive material (for example, a metal such as Cu, Al or W, etc.) in the groove extending in the IL according to the design line.
  • a diffusion barrier layer may be formed on the walls of the through holes or grooves (for example, the bottom wall, the side walls, and the like).
  • the metallization stack may comprise a stack of a plurality of ILs (eg, IL0, IL1, IL2, IL3, IL4, ... from the IL closest to the side of the device), forming contacts, conductive vias, and / or conductive interconnection.
  • ILs eg, IL0, IL1, IL2, IL3, IL4, ... from the IL closest to the side of the device
  • contacts eg. IL0, IL1, IL2, IL3, IL4, ... from the IL closest to the side of the device
  • contacts eg, IL0, IL1, IL2, IL3, IL4, ... from the IL closest to the side of the device
  • contacts eg., IL0, IL1, IL2, IL3, IL4, ... from the IL closest to the side of the device
  • contacts e.g, IL0, IL1, IL2, IL3, IL4, ... from the IL closest to the side of the
  • conductive interconnect features Due to the presence of numerous conductive interconnect features in the metallization stack, it is inevitable that certain conductive interconnect features are at least partially opposite each other. For example, there may be portions that oppose each other between two conductive interconnect members in the same IL; portions that are opposite each other may also exist between two conductive interconnect members that are in different ILs. Due to the dielectric material (the body of the IL) between each other, a (positive) capacitance is formed between such conductive interconnect members.
  • the capacitor comprises a plate-dielectric material-plate configuration in which the dielectric material can store charge.
  • Conventional capacitors have a "positive" capacitance characteristic, that is, as the charge stored in the dielectric material increases, the voltage between the two plates increases.
  • a dielectric material is referred to as a conventional dielectric material, or simply referred to as a dielectric material, as the term is conventional in the art.
  • certain materials can exhibit a "negative" capacitance characteristic under certain conditions, that is, as the charge stored therein increases, the voltage between the plates decreases.
  • This material is called a "negative capacitance material.”
  • certain ferroelectric materials eg, materials containing Hf, Zr, Ba, or Sr, such as HfZrO 2 , BaTiO 3 , KH 2 PO 4 , or NBT, or any combination thereof
  • Polarization causes a large amount of bound charge to accumulate instantaneously on the surface of the material, causing the voltage across the ferroelectric material to decrease.
  • such a positive capacitance may be compensated for with a negative capacitance to reduce the total capacitance between the conductive interconnect members.
  • Figure 1 shows the positive capacitance C 1 , ..., C m ' between the conductive interconnect members M 1 and M 2 due to the dielectric material as the IL body and the negative capacitance C n_1 for compensating for this , ..., C n_m , where m is a positive integer greater than or equal to 1, and m' is a positive integer greater than or equal to 1.
  • This negative capacitance for example, by introducing a negative capacitance material between the conductive interconnection member M 1 and M 2 (e.g., negative capacitance by embedding in a dielectric material as a material of the body) is obtained.
  • these capacitances are shown as configurations that are connected in parallel.
  • the total capacitance C t can be reduced, even close to 0 (zero), compared to the case where the conductive interconnect members M 1 and M 2 are completely dielectric materials.
  • C t ⁇ 0 to keep the device electrically stable.
  • the positive capacitance and the negative capacitance are preferably connected in parallel with each other.
  • a negative capacitance material may extend from the surface of M 1 to the opposite surface of M 2 such that the resulting negative capacitance is M 1 and M 2 as plates.
  • the positive capacitance caused by the dielectric material of the IL body is also the plate with M 1 and M 2 . That is, the positive and negative capacitors can share the same plates and thus be connected in parallel with each other.
  • the techniques of the present disclosure may be presented in various ways, some of which are described below. Due to the general The extension of the ground conductive interconnection or wiring is long, resulting in a relatively large capacitance, and thus exemplified below by compensating for the capacitance between the conductive interconnections or the wiring. Of course, the techniques of the present disclosure may be applicable to other applications where capacitance reduction is required.
  • FIGS. 2(a)-2(g) are cross-sectional views showing portions of a process for fabricating a metallization stack in accordance with an embodiment of the present disclosure.
  • a substrate 1001 is provided.
  • a silicon wafer will be described as an example.
  • the present disclosure is not limited thereto, but can be applied to other various forms of substrates such as a germanium substrate, a semiconductor-on-insulator (SOI) substrate, a compound semiconductor substrate, and the like.
  • a shallow trench isolation (STI) 1003 for defining an active region may be formed in the substrate 1001.
  • Desired devices such as transistors T1 and T2 and the like can be formed on the substrate 1001.
  • the transistor T1 may include a gate (G1) and a source and a drain (S/D1-1, S/D1-2).
  • the transistor T2 may include a gate (G2) and a source and a drain (S/D2-1, S/D2-2).
  • Transistor T1 can be an n-type device and transistor T2 can be a p-type device. Accordingly, a p-type well and an n-type well can be formed in the substrate 1001 to form T1 and T2 therein, respectively.
  • CMOS process is taken as an example here, the present disclosure is not limited thereto.
  • Devices T1 and T2 can be various types of devices such as metal oxide semiconductor field effect transistors (MOSFETs), fin field effect transistors (FinFETs), bipolar junction transistors, and the like.
  • MOSFETs metal oxide semiconductor field effect transistors
  • FinFETs fin field effect transistors
  • bipolar junction transistors and the like.
  • the device formed is not limited to a transistor, but may include various devices such as diodes, capacitors, resistors, and the like that may be formed on or in a substrate.
  • a metallization stack can be formed over the substrate to effect interconnection of the devices and/or connections to the outside.
  • the metallization stack can be formed by sequentially forming interlayer dielectric layers (IL) on the substrate 1001 and forming conductive interconnection members such as contacts, conductive vias, conductive interconnections or wirings therein.
  • IL interlayer dielectric layers
  • an interlayer dielectric layer IL0 1005 may be formed on the substrate.
  • IL0 1005 can be formed by depositing, for example, chemical vapor deposition (CVD) or the like, forming an oxide (for example, silicon oxide) on the substrate 1001, and planarizing it such as chemical mechanical polishing (CMP).
  • CVD chemical vapor deposition
  • CMP chemical mechanical polishing
  • the contact portion 1007 may be formed in the IL0 1005, specifically, the contact portion may include the contact portions CT11, CT12, CT13, CT21, CT22 corresponding to the respective terminals of the devices T1 and T2, in this example, CT23.
  • the contact portion 1007 can be formed in a variety of ways.
  • a through hole penetrating through the IL0 1005 may be formed at a position corresponding to each terminal of the devices T1 and T2 in the IL0 1005, and a conductive material such as a metal such as Cu, Al, or W may be filled therein to form each contact portion 1007. .
  • a diffusion barrier layer such as TiN may be formed on the inner wall of the via hole, and then the via hole may be filled with metal.
  • the next interlayer dielectric layer IL1 can be formed on the IL0.
  • IL1 includes a dielectric material such as an oxide (eg, silicon oxide), a nitride (eg, silicon nitride), or other sub-layers of low-k dielectric material 1009-2, 1009-4 and a negative capacitance material such as HfZrO 2 , a laminate of sub-layers 1009-1, 1009-3 of BaTiO 3 , KH 2 PO 4 or NBT or any combination thereof. These laminates are stacked along the stacking direction of the metallization stack (vertical direction in the drawing).
  • the materials, thicknesses, and the like of the respective sub-layers are not necessarily the same.
  • the number of dielectric material sub-layers 1009-2, 1009-4 is not limited to 2 shown in the drawing, but may be 1 or any other positive integer; likewise, the negative capacitance material sub-layers 1009-1, 1009-3 The number is not limited to 2 shown in the figure, but may be 1 or any other positive integer.
  • a first metal layer (Metal 1) 1011 may be formed in the interlayer dielectric layer IL1.
  • the first metal layer 1011 may include conductive interconnections M1-1, M1-2 that electrically contact the respective contact portions CT11, CT12, CT13, CT21, CT22, CT23, respectively. M1-3, M1-4, M1-5, M1-6. These conductive interconnections may follow a circuit design and travel in a certain line in IL1 to interconnect the respective contact portions CT11, CT12, CT13, CT21, CT22, CT23 with each other and to the terminals of other devices.
  • the contacts are connected to other conductive interconnects such as conductive vias in the upper layer (IL2 described below), and the like.
  • Such a conductive interconnection can be formed by forming a trench extending in the IL1 according to the design line (the trench penetrates IL1) and filling the trench with a conductive material such as a metal such as Cu, Al or W or the like.
  • a diffusion barrier such as TiN may be formed on the inner wall of the trench, and then the trench is filled with metal.
  • an adjacent pair of conductive interconnections M1-3 and M1-5 are considered. Since they are opposite each other and there is a dielectric material and a negative capacitance material between them, a capacitance C t will be generated between them.
  • the capacitance C t includes a negative capacitance C n_1 caused by a portion of the negative capacitance material sub-layer 1009-1 between the conductive interconnections M1-3 and M1-5, and the dielectric material sub-layer 1009-2 is electrically interconnected M1-3 and positive portion between the capacitor C caused a M1-5, partial negative capacitance material sublayer between the conductive interconnects 1009-3 M1-3 and M1-5 results in the negative and the capacitance C and n_2
  • the positive capacitance C 2 caused by the portion of dielectric material sub-layer 1009-4 between conductive interconnects M1-3 and M1-5.
  • each capacitance can be adjusted by adjusting the thickness of one or more sub-layers (dimensions in the vertical direction in the figure) such that Ct is close to zero (but preferably greater than zero).
  • a material having an appropriate (positive/negative) dielectric constant for each sublayer to adjust the capacitance value. The same is true between other conductive interconnects that are opposite each other.
  • the alternating laminated structure of the dielectric material and the negative capacitance material may be limited to a partial region of the interlayer dielectric layer IL1, for example, disposed between the conductive interconnections opposite to each other; in the remaining regions, It consists entirely of dielectric material as is the case with conventional interlayer dielectric layers.
  • the next interlayer dielectric layer IL2 can be formed on the IL1.
  • IL2 includes a body 1013-1 of dielectric material and a negative capacitance material 1013-2 embedded in the body.
  • a dielectric layer may be, for example, about 10 to 500 nm
  • trenches may be formed at desired positions in the body, and in the trenches.
  • a negative capacitance material is filled to form the interlayer dielectric layer IL2.
  • the location in which the negative capacitance material is embedded may be set according to the layout of the conductive interconnects in the metallization stack, such as between conductive interconnects that are opposite each other (but not electrically connected to each other).
  • each of the conductive vias 1015 can be formed by forming a via hole penetrating through the IL 2 at a corresponding position in the IL 2 and filling a conductive material such as a metal such as Cu, Al, or W therein.
  • a diffusion barrier layer such as TiN may be formed on the inner wall of the via hole, and then the via hole may be filled with metal.
  • the next interlayer dielectric layer IL3 can be formed on the IL2.
  • the interlayer dielectric layer IL3 may comprise a stack of sub-layers 1017-2, 1017-4 of dielectric material and sub-layers 1017-1, 1017-3 of a negative capacitance material. These laminates are stacked along the stacking direction of the metallization stack (vertical direction in the drawing).
  • the interlayer dielectric layer IL3 reference may be made to the above description for the interlayer dielectric layer IL1.
  • a second metal layer (Metal 2) 1019 can be formed in the interlayer dielectric layer IL3.
  • the second metal layer 1019 can include conductive interconnects M2-1, M2-2, M2-3 that electrically contact the respective conductive vias V13, V22, V23, respectively.
  • conductive interconnects reference may be made to the above description of conductive interconnects in IL1.
  • a conductive interconnection in which the upper and lower layers are opposed to each other is considered, for example, M2-1 in IL3 and M1-2 in IL1 are considered here. Since they are opposite each other and there is a dielectric material and a negative capacitance material between them, a capacitance C' t will be generated between them.
  • the capacitor C' t includes a negative capacitance C' n_1 caused by a portion of the negative capacitance material 1013-2 in IL2 between the conductive interconnections M2-1 and M1-2, and a dielectric material 1013-1 in the IL2.
  • the positive capacitance C' 1 caused by the portion between the conductive interconnections M2-1 and M1-2.
  • each capacitance can be adjusted by adjusting the width of the negative capacitance material 1013-2 (the dimension in the horizontal direction in the figure) such that C' t is close to zero (but preferably greater than zero).
  • IL2 may comprise a body of negatively charged material and a dielectric material embedded in the body.
  • 1013-1 shown in Figure 2(f) may indicate a negative capacitive material and 1013-2 may indicate a dielectric material. In this case, the same can be reduced C 't of.
  • FIG. 3(a)-3(e') are cross-sectional views showing a partial stage in a process of manufacturing a metallized laminate according to another embodiment of the present disclosure, wherein, and FIG. 2(a)-2(g) The same reference numerals are used to denote the same components.
  • a substrate 1001 is provided on which devices T1, T2 are formed. For details of them, reference can be made to the above description in conjunction with FIG. 2(a). Next, a metallization stack can be formed.
  • An interlayer dielectric layer IL0 1005 may be formed on the substrate. Further, in the IL0 1005, the contact portion 1007 can be formed. Regarding their materials and manner of formation, reference can be made to the description above in connection with Figure 2(b). In this embodiment, unlike the above embodiment, the formation positions of the contact portions CT11, CT21 corresponding to the gate electrodes G1, G2 are deviated from the formation positions of the contact portions corresponding to the source and drain regions to avoid each other. Interference; in addition, two contact portions are formed on each of the source and drain regions.
  • a lower inter-layer dielectric layer IL1 1009 may be formed on IL0, and In the interlayer dielectric layer IL1, a first metal layer (Metal 1) 1011 may be formed.
  • IL1 may only include a dielectric material.
  • a conductive interconnect M1-1/M1-4 that electrically connects the respective gates G1, G2 of the devices T1 and T2 to each other, one of the source and drain of T1, S/D1-2 and T2, is shown.
  • a conductive interconnection M1-3/M1-5 in which one of the source and drain electrodes S/D2-1 is electrically connected to each other, and a conductive interconnection M1-2 electrically connected to the other of the source/drain S/D1-1 of T1, And a conductive interconnect M1-6 electrically coupled to another S/D 2-2 in the source drain of T2.
  • the manner of connection between the devices is not limited thereto, but may be determined according to the circuit design.
  • a trench R may be formed in the interlayer dielectric layer IL1 1009.
  • a trench R may be formed between the respective opposite surfaces of the first metal layer 1011 by photolithography.
  • the bottom surface of the trench R is lower than the bottom surface of the first metal layer 1011.
  • the negative capacitance material 1021 may be filled in the trench R.
  • the respective conductive interconnections for example between M1-1/M1-4 and M1-2, between M1-1/M1-4 and M1-3/M1-5, at M1- Between 1/M1-4 and M1-6, the dielectric material and the negative capacitance material are disposed adjacent to each other along the in-plane direction of the metallization stack, thereby forming a parallel arrangement of positive and negative capacitances between the conductive interconnections.
  • this capacitance setting can reduce the total capacitance between the conductive interconnects.
  • the capacitance value can be adjusted such that the total capacitance is close to zero (but preferably greater than zero) by adjusting the shape, size, type of negative capacitance material, and the like of the trench.
  • a semiconductor device comprising the above metallization stack.
  • a metallization stack can connect various components formed on a substrate such as transistors to each other and to external terminals.
  • a semiconductor device can be applied to various electronic devices. For example, through the set A plurality of such semiconductor devices, as well as other devices (eg, other forms of transistors, etc.), may form an integrated circuit (IC) and thereby construct an electronic device. Accordingly, the present disclosure also provides an electronic device including the above semiconductor device.
  • the electronic device can also include a display screen that mates with the integrated circuit and a wireless transceiver that mates with the integrated circuit.
  • Such electronic devices are, for example, smart phones, tablet computers (PCs), personal digital assistants (PDAs), and the like.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

公开了一种金属化叠层及包括该金属化叠层的半导体器件和电子设备。根据实施例，金属化叠层可以包括：层间电介质层，包括电介质材料和负电容材料，其中，该层间电介质层中形成的至少一对彼此之间至少部分相对的第一导电互连部件在它们的相对部分之间包括电介质材料和负电容材料二者，和/或该层间电介质层的上层中形成的至少一个第二导电互连部件与该层间电介质层的下层中形成的与该第二导电互连部件至少部分相对的至少一个第三导电互连部件在它们的相对部分之间包括电介质材料和负电容材料二者。

Description

金属化叠层及包括其的半导体器件和电子设备
相关申请的引用
本申请要求于2016年3月17日递交的题为“金属化叠层及包括其的半导体器件和电子设备”的中国专利申请201610153583.0的优先权，其内容一并于此用作参考。
技术领域
本公开涉及半导体技术，更具体地，涉及一种能够降低导电互连部件之间电容的金属化(metallization)叠层以及包括这种金属化叠层的半导体器件和电子设备。
背景技术
随着集成电路(IC)中器件密度的不断增加，部件间的间隔越来越小。这使得IC中各导电互连部件特别是互连配线之间的电容增加，并因此使IC性能劣化。另一方面，即便对于性能要求不高的器件，也期望获得低功耗，并因此希望降低电容。抑制这种电容增加的一种方法是在互连部件之间使用气隙，但是其机械和电学等稳定性存在着问题。
因此，需要能够在互连部件之间不断地减小电容。
发明内容
本公开的目的至少部分地在于提供一种能够降低导电互连部件之间电容的金属化叠层以及包括这种金属化叠层的半导体器件和电子设备。
根据本公开的一个方面，提供了一种金属化叠层，包括层间电介质层，层间电介质层包括电介质材料和负电容材料。该层间电介质层中形成的至少一对彼此之间至少部分相对的第一导电互连部件在它们的相对部分之间包括电介质材料和负电容材料二者，和/或该层间电介质层的上层中形成的至少一个第二导电互连部件与该层间电介质层的下层中形成的与该第二导电互连部件至少部分相对的至少一个第三导电互连部件在它们的相对部分之间包括电介质 材料和负电容材料二者。
根据本公开的另一方面，提供了一种半导体器件，包括上述金属化叠层。
根据本公开的又一方面，提供了一种电子设备，包括上述半导体器件形成的集成电路。
根据本公开的实施例，彼此至少部分相对的一对导电互连部件之间可以包括电介质材料和负电容材料二者，从而在该对导电互连部件之间可以产生正电容和负电容二者。由于负电容的存在(特别是正电容与负电容二者并联的情况下)，可以降低该对导电互连部件之间的总电容。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1是示出了根据本公开实施例的一对导电互连部件之间的电容的示意电路图；
图2(a)-2(g)是示出了根据本公开实施例的制造金属化叠层的流程中部分阶段的截面图；
图3(a)-3(e′)是示出了根据本公开另一实施例的制造金属化叠层的流程中部分阶段的截面图。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
图1是示出了根据本公开实施例的一对导电互连部件之间的电容的示意电路图。
如图1所示，在层间电介质层(IL)中，可以形成导电互连部件M1和M2。这种导电互连部件可以是与衬底中形成的半导体器件的端子(例如，栅极、源极或漏极端子)相接触的接触部(contact)，可以是连通上下层的导电通道(via)，可以是在IL中按一定路线行进以便将接触部/导电通道彼此连接或将之连接到一定端子(例如，焊盘)的导电互连(interconnect)或配线(wiring)。通常，接触部与导电通道的形式基本上相同，一般地是嵌入于贯穿IL的通孔中的导电材料(例如，金属如Cu、Al或W等)；导电互连一般地是嵌入于贯穿IL且在IL中按设计线路延伸的槽中的导电材料(例如，金属如Cu、Al或W等)。此外，在通孔或槽的壁(例如，底壁、侧壁等)上，还可以形成扩散阻挡层。
金属化叠层可以包括多个IL的叠层(例如，从最靠近器件一侧的IL开始分别是IL0、IL1、IL2、IL3、IL4...)，各IL中形成接触部、导电通道和/或导电互连。一般地，在最靠近器件的IL0中可以形成与器件端子相对应的接触部，在接下来一层IL1中可以形成导电互连，在再上一层IL2中可以形成导电通道，在IL3中又可以形成导电互连，在IL4中又可以形成导电通道，以此类推。这样，可以实现所需的连接。注意，这仅仅是示例，金属化叠层的数目和配置不限于此。这种金属化叠层可以用多种方法来制造，例如大马士革工艺。
由于金属化叠层中存在众多导电互连部件，因此不可避免某些导电互连部件至少部分地彼此相对。例如，同一IL中的两个导电互连部件之间可能存在彼此相对的部分；分处于不同IL中的两个导电互连部件之间也可能存在彼此相对的部分。由于彼此之间的电介质材料(IL的本体)，在这种导电互连部件之间形成了(正)电容。
一般地，电容器包括极板-电介质材料-极板的配置，电介质材料可以储存 电荷。常规的电容器呈“正”电容特性，即，当电介质材料中储存的电荷增多时，两个极板间的电压增大。在本公开中，将这种电介质材料称作常规电介质材料，或者直接简称为电介质材料，这与该术语在本领域的常规含义相同。与此不同，某些材料在一定状态下，可以呈现“负”电容特性，即，随着其中储存的电荷增多，极板间的电压反而表现为降低。这种材料称作“负电容材料”。例如，某些铁电材料(例如含Hf、Zr、Ba或Sr的材料，如HfZrO2、BaTiO3、KH2PO4或NBT或其任意组合等)在到达某一临界电场时，可发生极化现象。极化使得大量的束缚电荷瞬间积累在材料的表面，使铁电材料两端的电压减小。
根据本公开的实施例，可以负电容来补偿这种正电容，以降低导电互连部件之间的总电容。图1示出了导电互连部件M1和M2之间由于作为IL本体的电介质材料而导致的正电容C1、...、Cm′以及用于对此进行补偿的负电容Cn_1、...、Cn_m，其中，m是大于等于1的正整数，m′是大于等于1的正整数。这种负电容例如可以通过在导电互连部件M1和M2之间引入负电容材料(例如，通过在作为本体的电介质材料中嵌入负电容材料)而得到。在该示例中，将这些电容示出为并联连接的配置。
由于并联关系，导电互连部件M1和M2之间的总电容Ct可以表示为：
Figure PCTCN2016087253-appb-000001
可以看出，由于负电容的存在，相比于导电互连部件M1和M2之间完全是电介质材料的情况，总电容Ct可以降低，甚至可以接近0(零)。优选地，Ct≥0以保持器件在电学上稳定。
根据以上分析可以看出，通过在作为IL本体的电介质材料中引入负电容材料，可以抑制导电互连部件之间的电容。为了有效确保这种电容抑制效果，正电容与负电容优选地彼此并联。例如，负电容材料可以从M1的表面延伸到M2的相对表面，从而由此导致的负电容以M1和M2为极板。另一方面，作为IL本体的电介质材料所导致的正电容也是以M1和M2为极板。也即，正电容和负电容可以共享相同的极板，从而彼此并联。
本公开的技术可以各种方式来呈现，以下将描述其中一些示例。由于一般 地导电互连或配线的延伸较长，从而导致的电容相对较大，因此在下文中以补偿导电互连或配线之间的电容为例来进行描述。当然，本公开的技术可以适用于需要降低电容的其他场合。
图2(a)-2(g)是示出了根据本公开实施例的制造金属化叠层的流程中部分阶段的截面图。
如图2(a)所示，提供衬底1001。在此，以硅晶片为例进行描述。但是，本公开不限于此，而是可以适用于其他各种形式的衬底，例如，锗衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底等。在衬底1001中可以形成有用于限定有源区的浅沟槽隔离(STI)1003。
在衬底1001上可以形成所需的器件，如晶体管T1和T2等。晶体管T1可以包括栅极(G1)以及源、漏极(S/D1-1，S/D1-2)。同样地，晶体管T2可以包括栅极(G2)以及源、漏极(S/D2-1，S/D2-2)。晶体管T1可以是n型器件，晶体管T2可以是p型器件。相应地，可以在衬底1001中形成p型阱和n型阱，用以分别在其中形成T1和T2。需要指出的是，尽管在此以CMOS工艺为例，但是本公开不限于此。
器件T1和T2可以是各种类型的器件，例如金属氧化物半导体场效应晶体管(MOSFET)、鳍式场效应晶体管(FinFET)、双极结型晶体管等。本领域技术人员知道多种方式来在衬底中形成多种器件。此外，所形成的器件不限于晶体管，而是可以包括各种可以形成于衬底上或衬底中的器件，如二极管、电容器、电阻器等。
在形成器件如T1和T2之后，可以在衬底上形成金属化叠层，以实现器件的互连和/或与外部的连接。如上所述，金属化叠层可以通过在衬底1001上依次形成各层间电介质层(IL)并在其中形成导电互连部件如接触部、导电通道、导电互连或配线等来形成。
具体地，如图2(b)所示，可以在衬底上形成层间电介质层IL0 1005。例如，可以通过淀积如化学气相淀积(CVD)等，在衬底1001上形成氧化物(例如，氧化硅)，并对其进行平坦化如化学机械抛光(CMP)，来形成IL0 1005。然后，可以在IL0 1005中形成接触部1007，具体地，在该示例中接触部可以包括与器件T1和T2的各端子相对应的接触部CT11、CT12、CT13、CT21、CT22、 CT23。可以有多种方式来形成接触部1007。例如，可以在IL0 1005中与器件T1和T2的各端子相对应的位置处形成贯穿IL0 1005的通孔，并在其中填充导电材料例如金属如Cu、Al或W等，来形成各接触部1007。备选地，可以先在通孔的内壁上形成扩散阻挡层如TiN，然后再向通孔中填充金属。
接着，如图2(c)所示，可以在IL0上形成下一层间电介质层IL1。在该示例中，IL1包括电介质材料如氧化物(例如，氧化硅)、氮化物(例如，氮化硅)或其他低k电介质材料的子层1009-2、1009-4与负电容材料如HfZrO2、BaTiO3、KH2PO4或NBT或其任意组合等的子层1009-1、1009-3的叠层。这些叠层沿着金属化叠层的堆叠方向(图中竖直方向)叠置。在此需要指出的是，各子层的材料、厚度等不必相同。另外，电介质材料子层1009-2、1009-4的数目不限于图中所示的2，而是可以为1或任意其他正整数；同样，负电容材料子层1009-1、1009-3的数目不限于图中所示的2，而是可以为1或任意其他正整数。
在该层间电介质层IL1中，可以形成第一金属层(Metal 1)1011。在该示例中，如图2(d)所示，第一金属层1011可以包括分别电接触相应接触部CT11、CT12、CT13、CT21、CT22、CT23的导电互连M1-1、M1-2、M1-3、M1-4、M1-5、M1-6。这些导电互连可以按照电路设计，在IL1中按一定的线路行进，以便将各接触部CT11、CT12、CT13、CT21、CT22、CT23彼此之间互相连接、连接到与其他器件的端子相对应的接触部、连接到上一层(下述IL2)中的其他导电互连部件如导电通道，等等。这种导电互连可以通过在IL1中形成按照设计线路延伸的沟槽(该沟槽贯穿IL1)，并在沟槽中填充导电材料例如金属如Cu、Al或W等，来形成。备选地，可以先在沟槽的内壁上形成扩散阻挡层如TiN，然后再向沟槽中填充金属。
在此，考虑相邻的一对导电互连M1-3和M1-5。由于它们彼此相对且彼此之间存在电介质材料和负电容材料，从而在它们之间将产生电容Ct。在此，该电容Ct包括负电容材料子层1009-1在导电互连M1-3和M1-5之间的部分所导致的负电容Cn_1、电介质材料子层1009-2在导电互连M1-3和M1-5之间的部分所导致的正电容C1、负电容材料子层1009-3在导电互连M1-3和M1-5之间的部分所导致的负电容Cn_2和电介质材料子层1009-4在导电互连M1-3 和M1-5之间的部分所导致的正电容C2。而且，由于这些电容均共享相同的极板M1-3和M1-5，所以它们呈并联关系。因此，如上所述，总电容Ct＝C1+C2-|Cn_1|-|Cn_2|，相比于M1-3和M1-5之间全部为电介质材料的情况，得以降低。在该示例中，可以通过调节一个或更多子层的厚度(图中竖直方向上的维度)，来调节各电容的值，使得Ct接近于零(但优选地大于零)。当然，也可以为各子层选择具有适当(正/负)介电常数的材料，来调节电容值。在其他彼此相对的导电互连之间，同样如此。
在此需要指出的是，电介质材料和负电容材料的交替叠层结构可以限于层间电介质层IL1的局部区域中，例如，设置在彼此相对的导电互连之间；在其余区域中，仍然可以如常规层间电介质层那样完全由电介质材料构成。
接着，如图2(e)所示，可以在IL1上形成下一层间电介质层IL2。在该示例中，IL2包括电介质材料的本体1013-1以及嵌于本体中的负电容材料1013-2。例如，可以在IL1上通过淀积并进行平坦化处理来形成作为本体的电介质层(厚度可以为例如约10～500nm)，然后在该本体中所需位置处形成沟槽，并在沟槽中填充负电容材料，来形成层间电介质层IL2。嵌入负电容材料的位置可以根据金属化叠层中的导电互连的布局来设定，例如处于彼此相对(但并不彼此电连接)的导电互连之间。
此外，在该IL2中，还可以形成所需的导电互连部件，例如导电通道1015，如图2(f)所示。在该示例中，与导电互连M1-3、M1-5、M1-6相对应形成导电通道V13、V22、V23，这些导电通道V13、V22、V23可以将相应的导电互连M1-3、M1-5、M1-6电连接到上层。例如，可以通过在IL2中相应位置处形成贯穿IL2的通孔，并在其中填充导电材料例如金属如Cu、Al或W等，来形成各导电通道1015。备选地，可以先在通孔的内壁上形成扩散阻挡层如TiN，然后再向通孔中填充金属。
接着，如图2(g)所示，可以在IL2上形成下一层间电介质层IL3。与IL1类似，该层间电介质层IL3可以包括电介质材料的子层1017-2、1017-4与负电容材料的子层1017-1、1017-3的叠层。这些叠层沿着金属化叠层的堆叠方向(图中竖直方向)叠置。关于该层间电介质层IL3，可以参见以上针对层间电介质层IL1的描述。
同样地，在层间电介质层IL3中，可以形成第二金属层(Metal 2)1019。在该示例中，第二金属层1019可以包括分别电接触相应导电通道V13、V22、V23的导电互连M2-1、M2-2、M2-3。关于这些导电互连，可以参见以上针对IL1中导电互连的描述。
如上所述，在相对的导电互连之间，例如M2-1与M2-2之间、M2-2与M2-3之间，由于存在电介质材料子层和负电容材料子层的叠层，总电容可以得以降低。
另一方面，考虑上下层之间彼此相对的导电互连，例如在此考虑IL3中的M2-1与IL1中的M1-2。由于它们彼此相对且彼此之间存在电介质材料和负电容材料，从而在它们之间将产生电容C′t。在此，该电容C′t包括IL2中的负电容材料1013-2在导电互连M2-1和M1-2之间的部分所导致的负电容C′n_1以及IL2中的电介质材料1013-1在导电互连M2-1和M1-2之间的部分所导致的正电容C′1。而且，由于这些电容各自的电介质材料或负电容材料沿着金属化叠层的面内方向相邻设置，从而共享相同的极板M2-1和M1-2，所以它们呈并联关系。因此，如上所述，总电容C′t＝C′1-|C′n_1|，相比于M2-1和M1-2之间全部为电介质材料的情况，得以降低。在该示例中，可以通过调节负电容材料1013-2的宽度(图中水平方向上的维度)，来调节各电容的值，使得C′t接近于零(但优选地大于零)。当然，也可以选择具有适当(正/负)介电常数的材料，来调节电容值。IL3和IL1中其他彼此相对(但并不彼此电连接)的导电互连之间同样如此。
备选地，IL2可以包括由负电容材料构成的本体以及嵌入该本体中的电介质材料。例如，图2(f)中所示的1013-1可以指示负电容材料，而1013-2可以指示电介质材料。这种情况下，同样可以实现C′t的降低。
图3(a)-3(e′)是示出了根据本公开另一实施例的制造金属化叠层的流程中部分阶段的截面图，其中，与图2(a)-2(g)中相同的附图标记用以表示相同的部件。
如图3(a)所示，提供衬底1001，衬底1001上形成有器件T1、T2。关于它们的详情，可以参见以上结合图2(a)的描述。接着，可以形成金属化叠层。
具体地，如图3(b)(俯视图)和3(b′)(沿图3(b)中AA′线的截面图)所示， 可以在衬底上形成层间电介质层IL0 1005。此外，在IL0 1005中，可以形成接触部1007。关于它们的材料和形成方式，可以参见以上结合图2(b)的描述。在该实施例中，与上述实施例不同的是，与栅极G1、G2相对应的接触部CT11、CT21的形成位置偏离了与源漏区相对应的接触部的形成位置，以避免彼此之间的干扰；此外，在各源、漏区上分别形成了两个接触部。
接着，如图3(c)(俯视图)和3(c′)(沿图3(c)中AA′线的截面图)所示，可以在IL0上形成下一层间电介质层IL1 1009，并在层间电介质层IL1中，可以形成第一金属层(Metal 1)1011。在该示例中，IL1可以仅包括电介质材料。在该示例中，示出了将器件T1和T2各自的栅极G1、G2彼此电连接的导电互连M1-1/M1-4，将T1的源漏极之一S/D1-2和T2的源漏极之一S/D2-1彼此电连接的导电互连M1-3/M1-5，与T1的源漏极S/D1-1中另一个电连接的导电互连M1-2，以及与T2的源漏极中另一个S/D2-2电连接的导电互连M1-6。但是，器件之间的连接方式不限于此，而是可以根据电路设计而定。
接着，如图3(d)(俯视图)和3(d′)(沿图3(d)中BB′线的截面图)所示，可以在层间电介质层IL1 1009中形成沟槽R。例如，可以通过光刻，在第一金属层(Metal 1)1011的各相对表面之间形成沟槽R。在此，优选地，沟槽R的底面低于第一金属层1011的底面。
然后，如图3(e)(俯视图)和3(e′)(沿图3(e)中BB′线的截面图)所示，可以在沟槽R中填充负电容材料1021。于是，在各相对的导电互连之间，例如在M1-1/M1-4与M1-2之间、在M1-1/M1-4与M1-3/M1-5之间、在M1-1/M1-4与M1-6之间，电介质材料、负电容材料沿着金属化叠层的面内方向相邻设置，从而在这些导电互连之间形成正电容与负电容的并联设置。如上所述，这种电容设置可以降低导电互连之间的总电容。在此，可以通过调整沟槽的形状、尺寸、负电容材料的类型等，来调整电容值使得总电容接近于零(但优选地大于零)。
根据本公开的实施例，还提供了一种半导体器件，包括上述金属化叠层。例如，这种金属化叠层可以将衬底上形成的各种部件如晶体管相互连接并连接到外部端子。
根据本公开实施例的半导体器件可以应用于各种电子设备。例如，通过集 成多个这样的半导体器件以及其他器件(例如，其他形式的晶体管等)，可以形成集成电路(IC)，并由此构建电子设备。因此，本公开还提供了一种包括上述半导体器件的电子设备。电子设备还可以包括与集成电路配合的显示屏幕以及与集成电路配合的无线收发器等部件。这种电子设备例如智能电话、平板电脑(PC)、个人数字助手(PDA)等。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (15)

  1. 一种金属化叠层，包括：
    层间电介质层，包括电介质材料和负电容材料，
    其中，该层间电介质层中形成的至少一对彼此之间至少部分相对的第一导电互连部件在它们的相对部分之间包括电介质材料和负电容材料二者，和/或该层间电介质层的上层中形成的至少一个第二导电互连部件与该层间电介质层的下层中形成的与该第二导电互连部件至少部分相对的至少一个第三导电互连部件在它们的相对部分之间包括电介质材料和负电容材料二者。
  2. 根据权利要求1所述的金属化叠层，其中，在该对第一导电互连部件之间的相对部分之间，电介质材料和负电容材料实质上沿着金属化叠层的堆叠方向叠置。
  3. 根据权利要求1或2所述的金属化叠层，其中，层间电介质层包括电介质材料的子层与负电容材料的子层沿着金属化叠层的堆叠方向叠置的叠层。
  4. 根据权利要求3所述的金属化叠层，其中，层间电介质层包括电介质材料的子层与负电容材料的子层的交替叠层。
  5. 根据权利要求1所述的金属化叠层，其中，在该对第一导电互连部件之间的相对部分之间，电介质材料和负电容材料沿着金属化叠层的面内方向相邻设置。
  6. 根据权利要求5所述的金属化叠层，其中，电介质材料构成该层间电介质层的本体，负电容材料嵌于本体中形成的沟槽中。
  7. 根据权利要求6所述的金属化叠层，其中，沟槽从该对第一导电互连部件之一延伸至该对第一导电互连部件中另一个。
  8. 根据权利要求6或7所述的金属化叠层，其中，在该对第一导电互连部件之间的相对部分之间，形成有多个这种沟槽。
  9. 根据权利要求6所述的金属化叠层，其中，负电容材料的底面低于第一导电互连部件的底面。
  10. 根据权利要求1所述的金属化叠层，其中，在该第二导电互连部件与该第三导电互连部件之间的相对部分之间，电介质材料和负电容材料沿着金属 化叠层的面内方向相邻设置。
  11. 根据权利要求10所述的金属化叠层，其中，电介质材料构成该层间电介质层的本体，负电容材料嵌于本体中形成的沟槽中；或者，负电容材料构成该层间电介质层的本体，电介质材料嵌于本体中形成的沟槽中。
  12. 根据权利要求1所述的金属化叠层，其中，在所述相对部分之间，电介质材料和/或负电容材料的尺度被设置为使得它们在所述相对部分之间导致的总电容小于仅由电介质材料填充在所述相对部分之间而导致的电容，且不小于零。
  13. 一种半导体器件，包括如权利要求1-12中任一项所述的金属化叠层。
  14. 一种电子设备，包括如权利要求13所述的半导体器件形成的集成电路。
  15. 根据权利要求14所述的电子设备，还包括：与所述集成电路配合的显示器以及与所述集成电路配合的无线收发器。
PCT/CN2016/087253 2016-03-17 2016-06-27 金属化叠层及包括其的半导体器件和电子设备 WO2017156914A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610153583.0 2016-03-17
CN201610153583.0A CN105679742B (zh) 2016-03-17 2016-03-17 金属化叠层及包括其的半导体器件和电子设备

Publications (1)

Publication Number Publication Date
WO2017156914A1 true WO2017156914A1 (zh) 2017-09-21

Family

ID=56310733

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/087253 WO2017156914A1 (zh) 2016-03-17 2016-06-27 金属化叠层及包括其的半导体器件和电子设备

Country Status (3)

Country Link
US (1) US9953923B2 (zh)
CN (1) CN105679742B (zh)
WO (1) WO2017156914A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105679742B (zh) * 2016-03-17 2019-02-15 中国科学院微电子研究所 金属化叠层及包括其的半导体器件和电子设备
US10290632B2 (en) * 2016-11-21 2019-05-14 Qorvo Us, Inc. AC-coupled switch and metal capacitor structure for nanometer or low metal layer count processes
US10566413B2 (en) 2017-10-03 2020-02-18 Qualcomm Incorporated MIM capacitor containing negative capacitance material
CN116169118A (zh) * 2019-12-06 2023-05-26 中国科学院微电子研究所 金属化叠层及其制造方法及包括金属化叠层的电子设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7148535B2 (en) * 2003-08-25 2006-12-12 Lsi Logic Corporation Zero capacitance bondpad utilizing active negative capacitance
CN1959976A (zh) * 2005-11-03 2007-05-09 国际商业机器公司 后端金属化结构及其制造方法
KR20140004855A (ko) * 2012-07-03 2014-01-14 서울대학교산학협력단 음의 커패시턴스를 가지는 강유전체를 이용한 커패시터 소자
CN104299956A (zh) * 2013-07-15 2015-01-21 格罗方德半导体公司 使用cmos兼容反铁电高k材料的复杂电路组件及电容器
US20150318285A1 (en) * 2014-04-30 2015-11-05 Stmicroelectronics, Inc. Dram interconnect structure having ferroelectric capacitors
CN105679742A (zh) * 2016-03-17 2016-06-15 中国科学院微电子研究所 金属化叠层及包括其的半导体器件和电子设备

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7148535B2 (en) * 2003-08-25 2006-12-12 Lsi Logic Corporation Zero capacitance bondpad utilizing active negative capacitance
CN1959976A (zh) * 2005-11-03 2007-05-09 国际商业机器公司 后端金属化结构及其制造方法
KR20140004855A (ko) * 2012-07-03 2014-01-14 서울대학교산학협력단 음의 커패시턴스를 가지는 강유전체를 이용한 커패시터 소자
CN104299956A (zh) * 2013-07-15 2015-01-21 格罗方德半导体公司 使用cmos兼容反铁电高k材料的复杂电路组件及电容器
US20150318285A1 (en) * 2014-04-30 2015-11-05 Stmicroelectronics, Inc. Dram interconnect structure having ferroelectric capacitors
CN105679742A (zh) * 2016-03-17 2016-06-15 中国科学院微电子研究所 金属化叠层及包括其的半导体器件和电子设备

Also Published As

Publication number Publication date
US20170271257A1 (en) 2017-09-21
US9953923B2 (en) 2018-04-24
CN105679742A (zh) 2016-06-15
CN105679742B (zh) 2019-02-15

Similar Documents

Publication Publication Date Title
TWI693704B (zh) 三維記憶體元件的混和鍵合接觸結構
US10475772B2 (en) Seal-ring structure for stacking integrated circuits
US10693019B2 (en) Film scheme for a high density trench capacitor
US11114414B2 (en) Wafer structure with capacitive chip interconnection, method for manufacturing the same, and chip structure with capacitive chip interconnection
KR102404490B1 (ko) 후면 커패시터 기법
US9917030B2 (en) Semiconductor structure and fabrication method thereof
WO2017156914A1 (zh) 金属化叠层及包括其的半导体器件和电子设备
TW201913966A (zh) 三維記憶體裝置及其製造方法
TWI540725B (zh) 半導體裝置及半導體裝置之製造方法
US9721951B2 (en) Semiconductor device using Ge channel and manufacturing method thereof
CN110364507B (zh) 半导体元件
JP7272426B2 (ja) 半導体装置
US10074606B2 (en) Via, trench or contact structure in the metallization, prematallization dielectric or interlevel dielectric layers of an integrated circuit
JP2012248582A (ja) 半導体装置及び半導体装置の製造方法
JP7315016B2 (ja) 半導体装置
JP2009111013A (ja) 半導体装置
WO2013168354A1 (ja) 電源電圧の安定化構造を持つ三次元集積回路、及びその製造方法
US20230053433A1 (en) Semiconductor device and semiconductor device manufacturing method
TW201735181A (zh) 用以改善崩潰電壓及減小寄生電容的多層堆疊場板氮化鎵電晶體及層間電介質
US8026612B2 (en) Semiconductor device and method of manufacturing semiconductor device
JP2024001284A (ja) 半導体装置
US10410946B2 (en) Semiconductor device
TWI751896B (zh) 半導體元件及其形成方法
US10903305B2 (en) Ultra high density metal-oxide-metal capacitor
US11610993B2 (en) 3D semiconductor apparatus manufactured with a plurality of substrates and method of manufacture thereof

Legal Events

Date Code Title Description
NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16894076

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 16894076

Country of ref document: EP

Kind code of ref document: A1