WO2017148899A1 - Module pour dispositif d'éclairage - Google Patents

Module pour dispositif d'éclairage Download PDF

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Publication number
WO2017148899A1
WO2017148899A1 PCT/EP2017/054573 EP2017054573W WO2017148899A1 WO 2017148899 A1 WO2017148899 A1 WO 2017148899A1 EP 2017054573 W EP2017054573 W EP 2017054573W WO 2017148899 A1 WO2017148899 A1 WO 2017148899A1
Authority
WO
WIPO (PCT)
Prior art keywords
carrier
semiconductor chips
contacts
module according
layer
Prior art date
Application number
PCT/EP2017/054573
Other languages
German (de)
English (en)
Inventor
Frank Singer
Stefan GRÖTSCH
Thomas Schwarz
Jürgen Moosburger
Original Assignee
Osram Opto Semiconductors Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram Opto Semiconductors Gmbh filed Critical Osram Opto Semiconductors Gmbh
Publication of WO2017148899A1 publication Critical patent/WO2017148899A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21S—NON-PORTABLE LIGHTING DEVICES; SYSTEMS THEREOF; VEHICLE LIGHTING DEVICES SPECIALLY ADAPTED FOR VEHICLE EXTERIORS
    • F21S41/00—Illuminating devices specially adapted for vehicle exteriors, e.g. headlamps
    • F21S41/10—Illuminating devices specially adapted for vehicle exteriors, e.g. headlamps characterised by the light source
    • F21S41/14—Illuminating devices specially adapted for vehicle exteriors, e.g. headlamps characterised by the light source characterised by the type of light source
    • F21S41/141—Light emitting diodes [LED]
    • F21S41/151—Light emitting diodes [LED] arranged in one or more lines
    • F21S41/153—Light emitting diodes [LED] arranged in one or more lines arranged in a matrix
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21S—NON-PORTABLE LIGHTING DEVICES; SYSTEMS THEREOF; VEHICLE LIGHTING DEVICES SPECIALLY ADAPTED FOR VEHICLE EXTERIORS
    • F21S41/00—Illuminating devices specially adapted for vehicle exteriors, e.g. headlamps
    • F21S41/60—Illuminating devices specially adapted for vehicle exteriors, e.g. headlamps characterised by a variable light distribution
    • F21S41/65—Illuminating devices specially adapted for vehicle exteriors, e.g. headlamps characterised by a variable light distribution by acting on light sources
    • F21S41/663—Illuminating devices specially adapted for vehicle exteriors, e.g. headlamps characterised by a variable light distribution by acting on light sources by switching light sources
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21Y—INDEXING SCHEME ASSOCIATED WITH SUBCLASSES F21K, F21L, F21S and F21V, RELATING TO THE FORM OR THE KIND OF THE LIGHT SOURCES OR OF THE COLOUR OF THE LIGHT EMITTED
    • F21Y2105/00—Planar light sources
    • F21Y2105/10—Planar light sources comprising a two-dimensional array of point-like light-generating elements
    • F21Y2105/12—Planar light sources comprising a two-dimensional array of point-like light-generating elements characterised by the geometrical disposition of the light-generating elements, e.g. arranging light-generating elements in differing patterns or densities
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21Y—INDEXING SCHEME ASSOCIATED WITH SUBCLASSES F21K, F21L, F21S and F21V, RELATING TO THE FORM OR THE KIND OF THE LIGHT SOURCES OR OF THE COLOUR OF THE LIGHT EMITTED
    • F21Y2113/00—Combination of light sources
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21Y—INDEXING SCHEME ASSOCIATED WITH SUBCLASSES F21K, F21L, F21S and F21V, RELATING TO THE FORM OR THE KIND OF THE LIGHT SOURCES OR OF THE COLOUR OF THE LIGHT EMITTED
    • F21Y2113/00—Combination of light sources
    • F21Y2113/20—Combination of light sources of different form
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09681—Mesh conductors, e.g. as a ground plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10106—Light emitting diode [LED]

Definitions

  • the invention relates to a module for a luminaire, insbeson ⁇ particular for a headlight according to Claim. 1
  • the object of the invention is to provide an improved Mo ⁇ dul for a luminaire, in particular for a headlight ei ⁇ nes vehicle.
  • the object of the invention is achieved by the module according to Pa ⁇ tent screw 1.
  • a module for a luminaire in particular for a headlight of a vehicle, with a carrier provided schla ⁇ gene, said semiconductor light-emitting chips are arranged on said carrier, said first planar electrical lines are arranged on the support, wherein first terminals of the semiconductor chip with the first electrical lines are connected, wherein the first lines are guided to an edge region of the arrangement of the semiconductor chips, wherein a connecting line is arranged next to the arrangement of the semiconductor chips on the carrier, wherein the connecting line is electrically conductively connected to at least one electrical line, wherein on the carrier further carrier contacts are ⁇ assigned , wherein the semiconductor chips on the other carrier gerbiten are arranged, wherein a semiconductor chip has a second terminal contact on a bottom, where ⁇ are electrically connected at the second terminal contacts with the other carrier contacts, the other carrier contacts via at least one electrical line, which is arranged in the carrier, connected to carrier contacts are, wherein the carrier contacts and the connecting line for a power supply of the semiconductor chips, in particular for connection to contacts, where
  • the connection line is designed as a planar line.
  • the first lines and the connecting line can be produced in one method.
  • the radiation is hardly or little affected by the connecting cable.
  • the carrier contacts are connected to planar wei ⁇ mon connecting lines, which are provided for a power supply, in particular for an electrical connection with contacts of a control unit. Thus shading by the further connection lines is avoided.
  • the lines in the carrier are guided laterally beyond the arrangement of the semiconductor chips and connected to the carrier contacts, wherein the carrier contacts are arranged on an upper side of the carrier. In this way, a compact structure of the module is obtained.
  • the semiconductor chips are connected to side surfaces embedded in an electrically insulating material, where ⁇ formed in the electrically insulating material between the semi-conductor chips ⁇ webs, wherein the first planar electrical lines are arranged on the webs.
  • ⁇ formed in the electrically insulating material between the semi-conductor chips ⁇ webs, wherein the first planar electrical lines are arranged on the webs.
  • the semiconductor chips are surrounded on four sides by webs of the electrically insulating material. As a result, a protected arrangement of the semiconductor chips is achieved.
  • the webs extend slightly beyond an edge region of an upper side and / or slightly beyond an edge region of an underside of a semiconductor chip and mechanically hold the semiconductor chip on the carrier.
  • the semiconductor chip a cover layer ⁇ listed introduced from an electrically insulating material, and wherein the cover layer has in particular a Konversi ⁇ onsmaterial.
  • At least one control device for the semiconductor chips is provided on the carrier, wherein contacts of the control device with the connecting line and with the carrier contacts are electrically connected.
  • a layer of an electrically insulating material is provided between the region with the semiconductor chips and the control device on the carrier, wherein the connecting line is arranged as a planar line on the layer.
  • the carrier is arranged on a second carrier, wherein a control device is arranged next to the carrier on the second carrier, wherein a layer of an electrically insulating material between the carrier and the controller is provided on the second carrier, wherein on the compensation layer the connection line is arranged.
  • the carrier can be made smaller.
  • the second carrier may be made of a thermally conductive material, the waste heat of the control unit better abdate ⁇ ren, as the material of the carrier.
  • second connection lines are arranged on the layer and routed to the control unit, wherein the second connection lines are connected to carrier contacts via third plated-through holes.
  • the semiconductor chips have differing ⁇ che area sizes. As a result, different semiconductor chips can be used flexibly.
  • no semiconductor chips are arranged at least in a predetermined subregion adjacent to an upper side and adjacent to a narrow first side. As a result, semiconductor chips can be saved.
  • the first lines form a grid structure, which surrounds the individual semiconductor chips.
  • a large-area wiring layer can be provided despite the small space.
  • At least a portion of the semiconductor chips are arranged in such a way that adjacent half ⁇ chip chips have a distance of 250 microns or less, in particular a distance 150ym or smaller, in particular all semiconductor chips are arranged in such a way that adjacent Semiconductor chips have a spacing of 250 microns or smaller, in particular a distance of 150 microns or smaller.
  • the ers ⁇ th connection contacts are connected electrically conductively connected at least by a part of the semiconductor chips, in particular of all the semiconductor chips. This way can be a simple power supply and a simple control of the semiconductor chips achieved ⁇ who.
  • FIG. 1 is a schematic representation of a first embodiment of a module with a first carrier
  • Fig. 2 is a schematic representation of a partial cross-section through the module of Fig. 1,
  • Fig. 3 is a schematic representation of a second embodiment of a module with a carrier, wherein the carrier is arranged on a second carrier
  • FIG. 4 shows a schematic representation of a cross section through the second embodiment of the module according to FIG. 3,
  • Fig. 5 is a schematic representation of a second cross section through the second embodiment of the Mo ⁇ duls of Fig.3, Fig. 6 is a schematic representation of another embodiment of a module with differently sized semiconductor chip,
  • Fig. 7 is a schematic representation of a further exemplary form of a module with different sizes of semiconductor chips and having free surface preparation ⁇ chen in the array of Hableiterchips,
  • FIG. 8 is a schematic representation of a further embodiment of a module with an asymmetric
  • FIG. 9 is a plan view of another embodiment of a module with two carriers
  • Fig. 10 is a plan view of another embodiment of a module with two carriers, and
  • Fig. 11 is a plan view of an additional embodiment ⁇ form of a module with two carriers.
  • 1 shows a schematic representation of a plan view of a module 1, which has a carrier 2, wherein light-emitting semiconductor chips 4 are arranged on the carrier 2 in a predetermined region 3.
  • the area 3 has a rectangular shape. Depending on the chosen embodiment, the area 3 may also have other shapes.
  • the semiconductor chips 4 are designed to generate electromagnetic radiation and in particular to emit it via an upper side.
  • the semiconductor chips 4 are arranged in a predetermined grid in rows and columns within the rectangular area 3.
  • the semiconductor chips 4 are the same size and have, for example, the same structure. Depending on the selected embodiment, the semiconductor chips may also have different sizes, a different structure and different properties.
  • the semiconductor chips 4 emit electromagnetic radiation at different wavelengths.
  • the semiconductor chips 4 have first connection contacts 5 which are arranged on an upper side of the semiconductor chips 4 and which are each connected to a first electrical line 6.
  • the first electrical lines 6 are designed as planar lines, ie PI (planar interconnect) line surfaces.
  • the first electrical leads 6 are arranged between the semiconductor chips 4 and form a grid structure. In the illustrated embodiment, the planar form
  • electrical lines 6 an electrically conductive grid structure, which framing each semiconductor chip 4.
  • the first electrical connection contacts 5 of the semiconductor chips 4 are thus all electrically connected to each other.
  • the semiconductor chips 4 are arranged at a small distance from each other. Thus, the distances between the edges of two ⁇ be nachbarter semiconductor chip 4 in the range of 250 ym or less, in particular in the range of 150ym or be made smaller.
  • a connecting line 7 is provided, which is formed for example as a planar electrical line.
  • the connecting line 7 is connected to a first electrical line 6.
  • the connection line 7 may also be directly connected to a plurality of first electrical lines.
  • the connection line 7 is arranged next to the region 3 on the support 2 and led to two connection regions 9, 10.
  • a control device 11, 12 is arranged in the first and the second connection region 9, 10.
  • the Steuerge ⁇ devices 11,12 on a variety of electrical contacts 8.
  • the connection line 7 is connected at least to a contact 8 of the first and the second control device 11, 12 in order to supply the first connection contacts 5 of the semiconductor chips with an electrical voltage.
  • only one connection area or a control unit can be provided.
  • a further connection line 7 is provided, which is formed for example as a planar electrical line.
  • the further connection line 7 is connected to a first electrical line 6.
  • the further connection line 7 can also be directly connected to a plurality of first electrical lines 6.
  • the further connection line 7 is arranged next to the region 3 on the carrier 2 and guided to a third and a fourth connection region 15, 16 for a third and fifth control device.
  • a control unit 41, 42 is arranged in the third and the fifth connection area 15, 16.
  • the control units 41, 42 have a large number of electrical contacts 8.
  • the further connecting line 7 is connected to a terminal contact 8 of the third and the fourth control device 11,12 to to supply the first connection contacts 5 of the semiconductor chips with an electrical voltage.
  • only one connection area or only one control unit can be provided.
  • 2 carrier contacts 13 are provided on the carrier.
  • the carrier contacts 13 are connected via further connecting lines 14 with first contacts 8 of the control units 11,12 electrically conductive.
  • second terminal contacts of the semiconductor chips are supplied with an electrical voltage.
  • the further connection lines 14 may be formed in the form of planar electrical lines.
  • connection areas 9, 10, 15, 16 are provided for the control units on each longitudinal side of the area 3. Between the Anschlußberei ⁇ surfaces 9, 10, 15, 16 and the area 3 two rows of carrier contacts 13 are provided in each case. In addition, two rows of carrier contacts 13 are provided between the two terminal regions 9, 10, 15, 16 and the corresponding edges of the carrier 2. Furthermore, 2 contact pads 17 are arranged on the carrier, wherein two contact pads are arranged in a corner region of the carrier 2 in each case. However, the contact pads can also be arranged in other areas of the carrier 2. The contact pads are connected to unillustrated electrical leads with contacts 8 of the controllers 11,12,41,42 to provide the controllers with power or data.
  • the further connecting lines 14 which connect the carrier contacts 13 to the contacts 8 of the control devices 11, 12, 41, 42.
  • the electrically conductive connection can take place directly between the further connection lines 14 and the contacts 8 of the control devices 11, 12 or via further contacts on the carrier 2.
  • the carrier 2 may, for example, in the form of a printed circuit board, in the form of a silicon layer, in the form of a sapphire layer and / or be formed in the form of a silicon carbide layer.
  • the carrier 2 may be formed as a ceramic substrate.
  • the carrier 2 may be formed of an Al 2 O 3 / AIN ceramic substrate (two or more layers).
  • a planar electrical conductor layer is made of a metal ⁇ metallic material, said metallic material is locally applied, for example in the form of a metallic paste or a silver-containing paste.
  • processes such as a stencil printing process, a screen printing process, a dispensing process or a droplet-shaped application can be carried out with the aid of a printing device (jetting).
  • Another contemplated process for forming the electrically conductive planar conductive layer is electrochemical deposition together with a photographic technique.
  • a start layer can be deposited large area ⁇ .
  • the starting layer may, for example, comprise TiCu and be produced by sputtering.
  • a structured photoresist layer serving for masking can subsequently be formed.
  • the photoresist layer has a layer exposing the start opening portion, which is tuned to the trainees planar Lei ⁇ tung layer. Subsequently, the electrochemical deposition ⁇ mix can be done. In this case, the starting layer is used as a deposition electrode on which a metallic material, for example copper, is applied in the opening region of the photoresist layer. Subsequently, the photoresist ⁇ layer can be removed, and it can be Runaway ⁇ performs an etching process to remove the seed layer outside the area of the planar conductor layer.
  • Fig. 2 shows a schematic representation of a partial cross-section through the module 1 of FIG. 1.
  • electrically insulating material 18 are embedded.
  • semiconductor chips 4 rest with a bottom 19 on further electrical carrier contacts 20.
  • the further carrier contacts 20 are arranged on an upper side of the carrier 2.
  • the semiconductor chips 4 on the bottom 19 on second connection contacts 21 which are in communication with the other carrier ⁇ contacts 20.
  • the further carrier contacts 20 can in particular be in the form of solder surfaces.
  • As a solder material AuSn, SnAgCu, or SnAg ent ⁇ speaking suitable materials may be used.
  • Ag sinter pastes can also be used as solder material.
  • each semiconductor chip 4 has a first connection contact 5 on the upper side.
  • the first connection contact 5 is arranged in each case in a corner region of the upper side of the semiconductor chip 4.
  • a first electric line 6 is arranged as a planar line.
  • the material 18 forms ellektrisch insulating webs 23 Zvi ⁇ rule the semiconductor chips 4.
  • the electric material 18 extends over the top of the semiconductor chip 4 and thus on the upper ⁇ side of the first connection contact 5 addition.
  • the first planar line 6 is brought to the first connection contact 5 on ⁇ and extends, starting from the top of the first connection contact 5 to a top side of Mate ⁇ rials 18 in a central region between two semiconductor chips 4. Further, in the illustrated embodiment, the top side the semiconductor chip 4 and the material 18 and the first planar lines 6 covered with a cover layer 22 of an electrically insulating material.
  • the cover layer 22 is permeable to the electromagnetic radiation generated by the semiconductor chip 4.
  • the cover layer 22 Konversionsmate ⁇ rial for shifting the wavelength of the semiconductor chip 4 generated electromagnetic radiation.
  • phosphorus may be disposed in the cover layer 22.
  • the cover layer 22 may comprise, for example, a polymer material, for example silicone.
  • the phosphor material may be arranged only in the region of the emission side of the semiconductor chips 4.
  • the electrically insulating material 18 forms webs 23 between the semiconductor chips 4. In this way, the
  • a ridge 23 in a region adjacent to a semiconductor chip 4 covers the top of the semiconductor chip 4.
  • a ridge 23 adjacent to the semiconductor chip 4 covers a bottom 19 of the semiconductor chip 4.
  • second plated-through holes 26 are provided, which connect the second line level 25 to a third line level 27.
  • the second line level 25 and / or the third line level 27 led out laterally over the region 3 of the semiconductor chips 4 and guided up to the top of the carrier 2 and connected to carrier ⁇ contacts 13.
  • the carrier shown in FIG. 2 illustrates a multi-layer substrate is at least one line ⁇ planar for electrical rewiring. As a result, a separate electrical conduction from the second terminal contact 21 to a substrate contact 13 (Fig.l) may be prepared for each semiconductor chip 4.
  • the carrier contacts 13 (FIG. 1) are formed on an upper side and / or on an underside of the carrier 2.
  • every second is to ⁇ -circuit terminal 21 of a semiconductor chip 4 can be controlled individually by ei ⁇ nem control unit.
  • the carrier 2 can dispense with the second plated-through holes 26 and the third wire level 27.
  • more than two line levels may be provided in the carrier 2 in order to lead the second terminal contacts 21 laterally over the area 3 and to connect them to further carrier contacts 13.
  • only first plated-through holes 24 can be provided which are guided to a lower side of the carrier 2.
  • FIG. 3 shows a schematic view of a further embodiment of a module, which is designed substantially in accordance with FIG. 1, wherein, however, the carrier 2 is arranged on a second carrier 28.
  • the connection areas 9, 10, 15, 16 and the control devices 11, 12, 41, 42 are arranged on the second carrier 28.
  • the carrier contacts 13 are arranged adjacent to the region 3 between the region 3 and the connection regions 9, 10, 15, 16.
  • the carrier has two line levels according to FIG. 2, so that the second terminal regions of the semiconductor chips 4 are each electrically conductively connected to a carrier contact 13.
  • the contact pads 17 are arranged on the second carrier 28 ⁇ .
  • the contact pads 17 are surfaces between the Ranberei- 9, 10, 15, 16 and arranged ⁇ the edge of the second carrier 28th
  • connection lines 7 are electrically conductively connected to a first line 6 of the area 3 and electrically conductively connected to at least one contact 8 of a control unit 11, 12, 41, 42.
  • the semiconductor chips 4 and the region 3 and the carrier 2 are constructed according to FIGS. 1 and 2.
  • the control units 11, 12, 41, 42 are formed according to Fig.l.
  • FIG. 4 shows a partial cross section through the module of FIG. 3 in the region of a connection line 7.
  • the semiconductor chips 4 have on the top side first connection contacts, which are electrically conductively connected to first planar lines 6.
  • the semiconductor chips 4 are embedded in an electrically insulating material 18.
  • the carrier 2 is arranged on a second carrier 28.
  • the second carrier 28 may for example serve as a heat sink and having metal, may be formed into ⁇ particular as a metal plate.
  • a first control device 11 is arranged on the second carrier 28 next to the carrier 2.
  • the layer 44 is disposed of the electrically insulating material, so that the connecting line 7 can be performed as a planar line on top of the layer 44 to the contact 8 of the first control unit 11.
  • FIG. 5 shows a second cross section through the arrangement of FIG. 3 in the region of a further connecting line 14.
  • the connecting line 14 is designed as a planar line and arranged on the layer 44.
  • the connecting line 14 is connected via a third electrically conductive through-connection 43 to a carrier contact 13 of the carrier 2.
  • the connecting line 14 is connected to a contact 8 of the control unit 11.
  • a layer of an electrically insulating material 18 can be formed on the carrier 2 between the region 3 and the control devices 11, 12, 41, 42 ,
  • the control units 11, 12, 41, 42 are arranged on the carrier 2 in the exporting ⁇ tion in FIG. 1.
  • the layer of the material 18 can adjoin the region 3 and the control units 11, 12, 41, 42.
  • the layer of the insulating material 18 may have the same height as the control units 11, 12, 41, 42 and / or as the semiconductor chips 4 or as the webs 23.
  • the planar connection cables 7 can be performed on the layer of the insulating material 18 in a plane almost from the region 3 to the STEU ⁇ erellan 11, 12, 41, 42nd
  • height differences between upper sides of the semiconductor chips 4 and upper sides of the control devices 11, 12, 41, 42 on the carrier 2 can be compensated by means of the layer of the electrically insulating material 18.
  • the layer of the electrically insulating material 18 between the region of the carrier contacts 13 and the control units 11, 12, 41, 42 may be formed.
  • Characterized the further Ranlei ⁇ inter- faces can be formed as a planar lines 14 on the layer of the electrically insulating material 18th
  • the further connecting lines 14 may be electrically conductively connected to the carrier contacts 13 of the carrier 2 via corresponding third electrically conductive plated-through holes.
  • the planar further connection lines 14 are connected to contacts 8 of the control unit 11.
  • the planar white ⁇ additional connection lines 14 can thus be formed substantially in one plane.
  • FIG. 6 shows a plan view of a further embodiment of a module 1, which is formed essentially in accordance with the embodiment of FIG. 1.
  • this embodiment has different-sized semiconductor chips 4, 30.
  • the second semiconductor chips 30, which have a larger surface area than the semiconductor chips 4, are arranged in opposite narrow side regions 31, 32 of the region 3.
  • the second semiconductor chips 30 are also embedded in the material 18.
  • 30 have the second semiconductor chip has the same structure as the half ⁇ semiconductor chip 4, and are connected with the first connection contacts 5 to the first electrical lines.
  • each second semiconductor chip 30 has a second connection contact 21, which is connected via a further carrier contact 20 and a rewiring with a carrier contacts 13.
  • the carrier contacts 13 are connected to contacts 8 of the control units.
  • FIG. 7 shows a further embodiment of the module according to FIG. 6, but in this embodiment subareas 33, 34 of the region 3 which adjoin the first and second side regions 31, 32 are free of semiconductor chips. Thus, semiconductor chips, which are not required for a desired beam ⁇ shaping, can be saved.
  • FIG. 8 shows a further embodiment of a module 1 which is essentially constructed in accordance with the embodiment of FIG. 6.
  • a first partial region 33 is provided on the first narrow side region 31, in which no semiconductor chips are arranged.
  • second semiconductor chips 30 having a larger area are arranged adjacent to the first subarea 33.
  • semiconductor chip 4 are arranged, which have a smaller area than the second semiconductor chip 30 on ⁇ .
  • the arrangement of the semiconductor chips 4 and the second semiconductor chips 30 is formed asymmetrically with respect to a center axis of the region 3.
  • second semiconductor chips 30 are arranged only in an upper second subregion 34. In this way An asymmetrical configuration of the arrangement of the semiconductor chips 4, 30 in the region 3 is achieved.
  • a layer of an electrically insulating material 18 on the carrier 2 between the region 3 of the semiconductor chips 4 and the control units 11, 12, 41, 42 may be formed.
  • the control units 11, 12, 41, 42 are arranged in the embodiment of FIGS. 6 to 8 on the carrier 2.
  • the layer of the material 18 can adjoin the region 3 and the control units 11, 12, 41, 42.
  • the layer of the insulating material 18 may have the same height as the control units 11, 12, 41, 42 and / or as the semiconductor chips 4 or as the webs 23 on ⁇ .
  • the planar connection lines 7 on the layer of the insulating material 18 can be guided in almost one plane from the region 3 to the control devices 11, 12, 41, 42.
  • the layer of the electrically insulating material 18 height differences Zvi ⁇ rule tops of the semiconductor chips 4 and upper sides of the control units 11, 12, 41, are compensated for on the carrier 2 42nd.
  • the layer of the electrically insulating material 18 between the region of the carrier contacts 13 and the control units 11, 12, 41, 42 may be formed.
  • the further connection lines 14 can be formed as planar lines on the layer of the electrically insulating material 18.
  • the further connecting lines 14 may be electrically conductively connected to the carrier contacts 13 of the carrier 2 via corresponding third electrically conductive plated-through holes.
  • the planar further connection lines 14 are connected to contacts 8 of the control unit 11.
  • the planar white ⁇ additional connection lines 14 can thus be formed substantially in one plane.
  • 9 shows a plan view of a further embodiment of a module 1, in which area 3 is formed substantially in accordance with the embodiment of FIG. 6, but two carriers 2, 28 according to FIGS. 3-5 are provided.
  • the control devices are on the second carrier and the region 3 with the semiconductor chips and the carrier contacts 13 are arranged on the carrier 2.
  • a layer 44 of an electrically insulating material 18 is formed adjacent to the first carrier 2 in a dashed region of the second carrier 28, a layer 44 of an electrically insulating material 18 is formed.
  • the connecting lines 7 and the further connecting lines 14 are arranged in this embodiment on the layer 44 and in particular formed as a planar lines.
  • the semiconductor chips 4 are arranged at a small distance from each other.
  • the spacings of the edges of two adjacent semiconductor chips 4 can be in the range of 250 ym or smaller, in particular in the range of 150 ym or smaller.
  • FIG. 10 shows a plan view of a further embodiment of a module 1, in which area 3 is formed substantially in accordance with the embodiment of FIG. 7, but two carriers 2, 8 according to FIGS. 3-5 are provided.
  • the control devices are arranged on the second carrier and the region 3 with the semiconductor chips and the carrier contacts 13 are arranged on the carrier 2.
  • a layer 44 of an electrically insulating material 18 is formed in a dashed region of the second carrier 28.
  • the ⁇ -circuit lines 7 and the further connection lines 14 are arranged in this embodiment on the layer 44 and is formed in particular as a planar lines.
  • the half ⁇ semiconductor chip 4 are arranged at a small distance from each other.
  • Fig. 11 shows a plan view of a further execution ⁇ form of a module 1, in the region 3 substantially in accordance with the embodiment of FIG. 8 is formed, but with two carriers are provided 2.28 as shown in FIGS. 3-5.
  • the control devices are arranged on the second carrier and the region 3 with the semiconductor chips and the carrier contacts 13 are arranged on the carrier 2.
  • a layer 44 of an electrically insulating material 18 is formed in a dashed region of the second carrier 28.
  • connection lines 7 and the further connection lines 14 are arranged in this embodiment on the layer 44 and is formed in particular as a planar lines.
  • the half ⁇ semiconductor chip 4 are arranged with a small distance to each other Toggle.
  • the distances of the edges of two adjacent semiconductor chips 4 in the range of 250 ym or smaller, in particular in the range of 150ym or smaller may be formed. Also in the embodiments of FIGS. 6 to 11 are the
  • the distances of the edges of two adjacent semiconductor chips 4 and the edges of two adjacent second semiconductor chips 30 may be in the range of 250 ym or smaller, in particular in the range of 150 ym or smaller.
  • the distance between an edge of a semiconductor chip 4 and an edge of a second semiconductor chip 30 can also be formed in the range of 250 ⁇ m or smaller, in particular in the range of 150 ⁇ m or smaller.
  • the first connection contacts 5 of the semiconductor chips 4 and, if present, the second semiconductor chips 30 are connected to one another
  • the semiconductor chips 4, 30 can, for example, be designed as a thin-film LED chips.
  • the semiconductor chips ⁇ may have a square area having a size of for example 335 ym edge length.
  • the semi ⁇ conductor chips may have an anode contact on the top.
  • the semiconductor chips are arranged by soldering onto the Trä ⁇ ger 2, fixed and bottom sides electrically joined ⁇ .
  • the semiconductor chips are mounted as close as possible to each other, wherein, for example, a distance between two semiconductor chips in the range of 50 ym may be.
  • Each semiconductor chip may be connected via the bottom via the cathode connection with its own constant current source.
  • the anode contacts of the semiconductor chips are connected to each other by a planar Interconnect contact, so that one hand, no or hardly any light obscuration in contrast to the use of wire contacts formed and simultaneously a op ⁇ diagram channel separation between the individual pixels, that is arises the individual semiconductor chips.
  • the light from the semiconductor chip may for example be converted into white light by a thin spray-coating layer converter.
  • the Kon ⁇ verter für may have a thickness of 50 ym or smaller sen.
  • the smallest possible distance between the individual optical channels, ie, individual semiconductor chips, so that no Lich ⁇ tabfall between adjacent semiconductor chips can be seen.
  • This is achieved by the frame structure of the electrically insulating material 18 and by the first planar lines 6, which are formed in the form of a grid structure.
  • the lattice structure of the planar lines 6 of the described embodiments of the module 1 respectively surrounds a semi-conductor chip ⁇ 4, ie in the illustrated embodiments on four sides.
  • connection lines 14 are arranged as planar lines on the layer 44 of the electrically insulating material 18, the connecting lines 14, third electrically conductive vias 43 are connected to the carrier contacts 13 of the carrier 2. In addition, the connection lines 14 are connected to contacts 8 of the control unit 11.
  • the control devices can be designed as unhoused electronic circuits or as cased circuits (eg BGA).
  • the electrical contacts of the controllers are on the top and / or bottom.
  • the controllers may be disposed on the top, inside the carrier or on the back of the carrier or on the layer of electrically insulating material 18 or on a planar line.
  • the arrangement of the control device on a planar contact on a layer of insulating material has the advantage that in a final step, after a test of the functions of the modules ABILITY only the modules having a Steuerge ⁇ advises be fitted that are functional.
  • the cathode terminals of the semiconductor chips are individually connected via a rewiring in the carrier with the corresponding contacts of the control units and can also be connected in the case of a CoB assembly with a PI contact on the carrier with the electrical contacts of the control units.
  • Standard semiconductor chips such as UX: 3, ThinGaN, thin-film chips can be used for the described arrangements. This allows a high-precision chip-to-chip
  • Placement with an accuracy of e.g. + -50 ym can be achieved by using chip die bonders including HBH contacts.
  • chip die bonders including HBH contacts can be achieved by using chip die bonders including HBH contacts.
  • a carrier 2 may for example have a size of 10 x 16 mm and be formed for example in the form of a multilayer ceramic. For example, 320 chips may be arranged in the 8 ⁇ 40 array on the carrier 2.
  • the contact pads 17 represent an electrical module interface for the power supply and a module interface for the data lines to the control units.
  • the control units contain a constant current source and optionally further electronics for calibrating the current and voltage supply of the semiconductor chips for each semiconductor chip.
  • the control device may have memory for a temporary pixel brightness and a Businter ⁇ face.
  • control units can be attached ⁇ orders outside of the module.
  • the second carrier 28 may be made of an electrically conductive material such as copper or aluminum, wherein between the carrier 2 and the second carrier 28, an electrically insulating layer, for example with solder mask or ceramic layer is provided to the carrier 2 from the second carrier 28 electrically to isolate.
  • an electrically insulating layer for example with solder mask or ceramic layer is provided to the carrier 2 from the second carrier 28 electrically to isolate.
  • a mounting plane approximately at the level of the emission level of the semiconductor chips is advantageous.
  • the assembly ⁇ plane may for example by a casting of a fo- to Modellierbaren material (for example, SINR, ormocers), a highly filled epoxy or silicone, which has been applied with FAM molding or Dam & Fill and laser-patterned.
  • the planar leads may be titanium, platinum, gold, copper, silver, nickel, aluminum, vanadium, chromium, tungsten, tin oxide, zinc oxide, ITO, conductive polymer, graphenes, etc. Furthermore, on the upper side of the planar lines 6, a reflective terminating metal such as silver may be provided for reasons of efficiency.
  • the conversion layer may be partially structured or unstructured.
  • the conversion layer may have a thickness of greater or less than 50 ⁇ m.
  • the conversion layer may consist of converter particles and silicone, glass particles or ceramic matrix.
  • the conversion layer can be applied by layer transfer, spray coating, Dam & Fill, EPD, film lamination etc. The arrangement of Fig.
  • control devices are not attached to the carrier 2 ⁇ arranged and thereby the carrier 2 can be made smaller.
  • support material in particular a teu ⁇ re ceramics, can be saved.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Device Packages (AREA)

Abstract

L'invention concerne un module destiné à un dispositif d'éclairage, en particulier un phare d'un véhicule, comprenant un support. Des puces semi-conductrices photoémettrices sont disposées sur le support. Des premières lignes électriques planes sont disposées sur le support. Des premiers contacts de connexion des puces semi-conductrices sont reliés aux premières lignes électriques. Les premières lignes sont amenées à une zone de bord de l'ensemble des puces semi-conductrices. Une ligne de connexion est disposée sur le support à côté de l'ensemble de puces semi-conductrices. La ligne de connexion est reliée électriquement à au moins une ligne électrique. D'autres contacts de support sont disposés sur le support. Les puces semi-conductrices sont disposées sur les autres contacts de support. Un puce semi-conductrice comporte un second contact de connexion sur un côté inférieur. Les seconds contacts de connexion sont reliés électriquement aux autres contacts de support. Les autres contacts de support sont reliés à des contacts de support sur au moins une ligne électrique disposé dans le support. Les contacts de support et la ligne de connexion sont destinés à alimenter en énergie les puces semi-conductrices.
PCT/EP2017/054573 2016-02-29 2017-02-28 Module pour dispositif d'éclairage WO2017148899A1 (fr)

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DE102016103552.1 2016-02-29
DE102016103552.1A DE102016103552A1 (de) 2016-02-29 2016-02-29 Modul für eine Leuchte

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Cited By (2)

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WO2021165073A1 (fr) * 2020-02-20 2021-08-26 Osram Opto Semiconductors Gmbh Module optoélectronique et projecteur équipé de celui-ci
WO2022017047A1 (fr) * 2020-07-24 2022-01-27 华域视觉科技(上海)有限公司 Module de phare de véhicule, phare de véhicule et véhicule

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DE102018132691A1 (de) * 2018-12-18 2020-06-18 Osram Opto Semiconductors Gmbh Leuchtvorrichtung
DE102020130540A1 (de) 2020-11-19 2022-05-19 Marelli Automotive Lighting Reutlingen (Germany) GmbH Projektionsmodul, Scheinwerfer, Kraftfahrzeug

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US20120018745A1 (en) * 2010-07-20 2012-01-26 Epistar Corporation Integrated lighting apparatus and method of manufacturing the same
DE102010046254A1 (de) * 2010-09-22 2012-04-19 Osram Opto Semiconductors Gmbh Optoelektronisches Halbleiterbauelement
DE102013104273A1 (de) * 2013-04-26 2014-10-30 Osram Opto Semiconductors Gmbh Anordnung mit säulenartiger Struktur und einer aktiven Zone
US20150362165A1 (en) * 2014-06-14 2015-12-17 Hiphoton Co., Ltd. Light Engine Array

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DE102008021402A1 (de) * 2008-04-29 2009-11-05 Osram Opto Semiconductors Gmbh Oberflächenmontierbares Leuchtdioden-Modul und Verfahren zur Herstellung eines oberflächenmontierbaren Leuchtdioden-Moduls
US20120018745A1 (en) * 2010-07-20 2012-01-26 Epistar Corporation Integrated lighting apparatus and method of manufacturing the same
DE102010046254A1 (de) * 2010-09-22 2012-04-19 Osram Opto Semiconductors Gmbh Optoelektronisches Halbleiterbauelement
DE102013104273A1 (de) * 2013-04-26 2014-10-30 Osram Opto Semiconductors Gmbh Anordnung mit säulenartiger Struktur und einer aktiven Zone
US20150362165A1 (en) * 2014-06-14 2015-12-17 Hiphoton Co., Ltd. Light Engine Array

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021165073A1 (fr) * 2020-02-20 2021-08-26 Osram Opto Semiconductors Gmbh Module optoélectronique et projecteur équipé de celui-ci
WO2022017047A1 (fr) * 2020-07-24 2022-01-27 华域视觉科技(上海)有限公司 Module de phare de véhicule, phare de véhicule et véhicule

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