WO2017148215A1 - 一种压力计芯片及其制造工艺 - Google Patents

一种压力计芯片及其制造工艺 Download PDF

Info

Publication number
WO2017148215A1
WO2017148215A1 PCT/CN2017/000198 CN2017000198W WO2017148215A1 WO 2017148215 A1 WO2017148215 A1 WO 2017148215A1 CN 2017000198 W CN2017000198 W CN 2017000198W WO 2017148215 A1 WO2017148215 A1 WO 2017148215A1
Authority
WO
WIPO (PCT)
Prior art keywords
pressure gauge
silicon
piezoresistive
substrate
chip
Prior art date
Application number
PCT/CN2017/000198
Other languages
English (en)
French (fr)
Inventor
王文
周显良
Original Assignee
中国科学院地质与地球物理研究所
王文
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院地质与地球物理研究所, 王文 filed Critical 中国科学院地质与地球物理研究所
Priority to US16/073,732 priority Critical patent/US11255740B2/en
Publication of WO2017148215A1 publication Critical patent/WO2017148215A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L1/00—Measuring force or stress, in general
    • G01L1/18—Measuring force or stress, in general using properties of piezo-resistive materials, i.e. materials of which the ohmic resistance varies according to changes in magnitude or direction of force applied to the material
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L9/00—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
    • G01L9/0041—Transmitting or indicating the displacement of flexible diaphragms
    • G01L9/0051—Transmitting or indicating the displacement of flexible diaphragms using variations in ohmic resistance
    • G01L9/0052—Transmitting or indicating the displacement of flexible diaphragms using variations in ohmic resistance of piezoresistive elements
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0009—Structural features, others than packages, for protecting a device against environmental influences
    • E—FIXED CONSTRUCTIONS
    • E21—EARTH OR ROCK DRILLING; MINING
    • E21B—EARTH OR ROCK DRILLING; OBTAINING OIL, GAS, WATER, SOLUBLE OR MELTABLE MATERIALS OR A SLURRY OF MINERALS FROM WELLS
    • E21B47/00—Survey of boreholes or wells
    • E21B47/01—Devices for supporting measuring instruments on drill bits, pipes, rods or wirelines; Protecting measuring instruments in boreholes against heat, shock, pressure or the like
    • E21B47/017—Protecting measuring instruments
    • E—FIXED CONSTRUCTIONS
    • E21—EARTH OR ROCK DRILLING; MINING
    • E21B—EARTH OR ROCK DRILLING; OBTAINING OIL, GAS, WATER, SOLUBLE OR MELTABLE MATERIALS OR A SLURRY OF MINERALS FROM WELLS
    • E21B47/00—Survey of boreholes or wells
    • E21B47/06—Measuring temperature or pressure
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L9/00—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
    • G01L9/0041—Transmitting or indicating the displacement of flexible diaphragms
    • G01L9/0042—Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms
    • G01L9/0048—Details about the mounting of the diaphragm to its support or about the diaphragm edges, e.g. notches, round shapes for stress relief
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L9/00—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
    • G01L9/02—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means by making use of variations in ohmic resistance, e.g. of potentiometers, electric circuits therefor, e.g. bridges, amplifiers or signal conditioning
    • G01L9/06—Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means by making use of variations in ohmic resistance, e.g. of potentiometers, electric circuits therefor, e.g. bridges, amplifiers or signal conditioning of piezo-resistive devices

Definitions

  • the present invention relates to a sensor, and more particularly to a pressure gauge for detecting pressure changes in a mine.
  • the measurement of downhole pressure is critical in the exploration and production of hydrocarbon mines.
  • the pressure data collected during drilling will be used to set the parameters of the drill bit and to establish the structure of the mine.
  • pressure data is used for oil and gas storage management. So pressure data is critical throughout the life of a hydrocarbon mine, especially in optimizing mining and reducing risk. To this end, there is a need for a pressure measuring device that is accurate and cost effective.
  • Pressure sensors for downhole hydrocarbons must be able to maintain accuracy, stability and reliability during harsh conditions for many weeks of measurement. Usually the sensor must be able to withstand temperatures from -50 to 250 degrees Celsius and pressures up to 200 MPa (approximately 2000 atmospheres) with accuracy that must maintain the error within 0.1% of the pressure range, preferably at 0.01%. Within the scope.
  • a quartz-based pressure gauge in which a quartz resonator is immersed in a liquid and the outside pressure is measured by a metal isolating diaphragm or bellows.
  • a quartz resonator is described in U.S. Patent No. 3,617,780, in which a quartz resonator component is placed in a vacuum-sealed cavity formed of a quartz casing and forms the main support component of the cavity structure.
  • the resonant component resonates by electrical excitation and the piezoelectric effect of quartz, and its resonant frequency changes according to changes in pressure on the walls of the cavity.
  • quartz pressure gauge Since quartz resonance is already a very mature technology, and all components of the quartz resonator are basically made of quartz, the quartz pressure gauge has high precision, stability and reliability, and has become the highest standard of today's downhole pressure gauges. . However, the cost of quartz pressure gauges is very high. expensive.
  • a sapphire pressure gauge is described in U.S. Patent No. 5,024,098, in which a sapphire component is immersed in a liquid and is passed through an isolating diaphragm to measure external pressure.
  • the sapphire element is deformed when subjected to pressure, and the pressure value can be derived from the strain measured by a film strain gauge disposed on the surface of the sapphire element.
  • sapphire pressure gauges are highly reliable and suitable for downhole applications, they are not as accurate and stable as quartz pressure gauges, and are also very expensive to manufacture.
  • the film strain gauge used is a silicon material
  • the accuracy will be affected by the temperature coefficient of resistance of silicon and the temperature coefficient of the piezoresistive effect.
  • a silicon strain gauge is not used and a metal alloy film strain gauge is used, there is a problem of low sensitivity, which also causes a problem that temperature and other measurement errors are amplified.
  • no matter which material the film strain gauge is used there will be an error caused by the mismatch between the sapphire thermal expansion and contraction coefficient.
  • MEMS sensors are Micro-Electro-Mechanical Systems (MEMS) type sensors. Similar to integrated chips, MEMS sensors are typically fabricated by micromachining silicon wafers. In view of the structure of MEMS sensors, there are also some special manufacturing processes for fabricating three-dimensional microstructures, such as double-sided lithography, deep reactive ion etching (Ion Etching Etching), silicon wafer bonding, and the like. Compared to quartz and sapphire, silicon has very good mechanical properties, such as high hardness, high modulus of elasticity, high ultimate strength, and is completely elastic before the breaking point. In addition, single crystal silicon has a strong piezoresistive effect and can effectively convert stress changes into resistance changes.
  • Ion Etching Etching deep reactive ion etching
  • silicon MEMS piezoresistive pressure gauges have been widely used in automotive, medical, industrial and electronic products.
  • MEMS pressure gauges have not been widely used in mine applications. There are several issues that must be addressed, especially when measuring particularly high pressures, an improved mechanical design that is different from conventional silicon film gauges. This is because the conventional silicon film gauge chip uses a silicon film to amplify the pressure into stress, and in order to be suitable for measuring a high voltage of up to 200 MPa, the film must be narrowed and thickened. However, if the film is designed too narrow, the piezoresistive measuring element will not be placed; The film is greatly thickened, which causes a non-ideal deformation of the entire chip. In addition, MEMS pressure gauges need to overcome various temperature coefficients and instability to increase measurement accuracy in high temperature environments. To this end, there is a need for a silicon-based pressure gauge that is capable of high precision and cost-effectiveness in high temperature and high pressure environments downhole.
  • the object of the present invention is to overcome the deficiencies of the prior art and to provide a pressure gauge which has high accuracy, large detection range, and low environmental impact, and can accurately output pressure data in such a high temperature and high pressure environment under the mine.
  • a pressure gauge includes a cavity, and a pressure gauge chip disposed within the cavity, the pressure gauge chip being uniformly compressed within the cavity by the detected external pressure and capable of freely deforming.
  • the pressure gauge chip is basically made of single crystal silicon, and includes a substrate and a cover plate connected to each other, wherein the cover plate is formed with a recessed portion and forms a sealed cavity with the substrate, the substrate A silicon oxide layer is formed between the cover plate and the cover plate; the substrate includes a piezoresistive measurement element, and the piezoresistive measurement element is located within the cavity.
  • the pressure gauge of the present invention also has the following optional accessory features:
  • the sealed cavity is a vacuum sealed cavity.
  • the end of the piezoresistive measuring element is formed with a metal contact.
  • the substrate includes at least two pairs of the piezoresistive measurement elements that are perpendicular to each other.
  • the piezoresistive measuring elements are electrically connected to each other in a Wheatstone bridge manner.
  • the substrate is P-type silicon disposed on a ⁇ 110 ⁇ crystal plane
  • the piezoresistive measurement element is an N-type doped region disposed on the substrate and arranged in a ⁇ 100> or ⁇ 110> crystal direction.
  • the substrate is N-type silicon disposed on a ⁇ 110 ⁇ crystal plane
  • the piezoresistive measurement element is a P-type doped region disposed on the substrate and arranged in a ⁇ 100> or ⁇ 110> crystal direction.
  • the cover plate and the substrate are rectangular parallelepiped, and the cover plate is monocrystalline silicon disposed on a ⁇ 110 ⁇ crystal plane; on the bonding surface of the cover plate and the substrate, each of the cover plates The direction of the crystal along which each edge of one side corresponds to the substrate is uniform.
  • the pressure gauge chip substrate is a silicon-on-insulator (SOI) structure, including a substrate, a device layer, and a silicon oxide buried layer disposed between the substrate and the device layer; the piezoresistive measurement element is disposed on the device layer.
  • SOI silicon-on-insulator
  • a silicon oxide isolation layer is formed on each of the top end, the bottom end, and the sidewall of the piezoresistive measuring element.
  • the device layer is P-type silicon disposed on a ⁇ 110 ⁇ crystal plane
  • the piezoresistive measurement element is a P-type silicon disposed on the device layer and arranged in a ⁇ 100> or ⁇ 110> crystal direction.
  • the device layer is N-type silicon disposed on a ⁇ 110 ⁇ crystal plane
  • the piezoresistive measurement element is N-type silicon disposed on the device layer and arranged in a ⁇ 100> or ⁇ 110> crystal direction.
  • the substrate is monocrystalline silicon disposed on a ⁇ 110 ⁇ crystal plane, the substrate being aligned with the crystal direction of each of the corresponding sides of the device layer.
  • the cover plate is monocrystalline silicon disposed on a ⁇ 110 ⁇ crystal plane, and the cover plate is aligned with the crystal direction of each of the corresponding sides of the device layer.
  • the cavity is made of metal, the cavity is filled with an electrically insulating liquid, and the gauge chip is immersed in the electrically insulating liquid.
  • the pressure gauge is further provided with a metal diaphragm for sealing the electrically insulating liquid and the pressure gauge chip.
  • the pressure gauge chip detects external pressure through the metal diaphragm.
  • the first manufacturing process of the pressure gauge chip includes the following steps:
  • a silicon oxide layer is grown or deposited on the top and bottom surfaces of the single crystal silicon wafer;
  • the top surface of the single crystal silicon wafer is partially doped by photolithography and ion implantation; and a plurality of piezoresistive measurement elements opposite to the doping type of the single crystal silicon wafer are formed;
  • the top surface of the single crystal silicon wafer is partially heavily doped by photolithography and ion implantation; and a high conductive region opposite to the doping type of the single crystal silicon wafer is formed;
  • the top surface of the single crystal silicon wafer is partially heavily doped by photolithography and ion implantation; and a high conductive region of the same type as the single crystal silicon wafer is formed. And then depositing or depositing a silicon oxide layer on the top and bottom surfaces of the single crystal silicon wafer, and activating the various introduced doping;
  • a plurality of holes deep in the concentrated doped region are etched in the top silicon oxide layer of the high conductive region by photolithography and etching; and metal is deposited in the hole and extracted electrode;
  • the single crystal silicon cap wafer wafer pre-processed with the depressed portion is bonded to the top surface of the single crystal silicon wafer;
  • the bonded silicon wafer is divided by dicing to form a complete pressure gauge chip.
  • the second manufacturing process of the pressure gauge chip includes the following steps:
  • a silicon oxide layer is grown or deposited on the top and bottom surfaces of the silicon wafer on the insulator;
  • the device layer of the silicon-on-insulator wafer is locally heavily doped by photolithography and ion implantation; and a high-conductivity region of the same type as the device layer is formed;
  • a plurality of trenches deep into the silicon oxide buried layer are etched on the device layer by photolithography and etching; and a plurality of piezoresistive measuring elements are formed;
  • a silicon oxide layer is grown or deposited in the trench, and the introduced rich doping is activated;
  • a plurality of holes deep into the heavily doped region of the device layer are etched through the top silicon oxide layer of the high conductive region by photolithography and etching; and deposited in the hole Metal and lead out the electrode;
  • the single crystal silicon cap wafer wafer pre-processed with the depressed portion is bonded to the top surface of the silicon wafer on the insulator;
  • the bonded silicon wafer is divided by dicing to form a complete pressure gauge chip.
  • the processing step of the recess of the cap plate includes etching a recess on the cap plate by photolithography and etching.
  • the etching method is one or more of the following methods: dry etching or wet etching, the dry etching includes: deep reactive ions of silicon, reactive ions, and gaseous difluoride Reactive etch and silicon oxide reactive ions, plasma, and gaseous hydrogen fluoride etching.
  • the etchant for wet etching the silicon layer is a combination of one or more of the following etchants: hydrogen Potassium oxide, tetramethylammonium hydroxide, or ethylenediamine catechol etching solution.
  • the etchant for wet etching the silicon oxide layer is a combination of one or more of the following etchants: hydrofluoric acid and buffered hydrofluoric acid.
  • the pressure gauge of the present invention has the following advantages: First, the cost of a silicon based pressure gauge is much lower than that of a quartz or sapphire pressure gauge, but conventional silicon
  • the membrane type pressure gauge cannot be applied to the measurement of the pressure environment of the mine up to 200 MPa, and the invention is different from the conventional silicon film type pressure gauge.
  • the pressure gauge of the invention is applied to the upper and lower sides of the pressure gauge chip by using the high pressure downhole and directly It is transformed into the internal stress of the chip, so that the pressure gauge does not need to pass through the silicon film to amplify the external pressure into stress.
  • the piezoresistive measurement elements in traditional MEMS piezoresistive pressure gauges are isolated by PN junction, the relationship between the current and the temperature is exponential. When the temperature is raised to 150 degrees Celsius, the PN junction is isolated. Will be invalid.
  • a silicon oxide buried layer is disposed between the piezoresistive measuring element and the substrate, and silicon oxide is also provided between each piezoresistive measuring element for insulation, and further, the piezoresistive measuring element is on top
  • a silicon oxide layer is also grown or deposited.
  • each piezoresistive measuring element is in a state of being completely insulated from the upper and lower sides, and the electrical isolation in the embodiment of the present invention does not fail even if the temperature rises.
  • the resistance of the two pairs of mutually perpendicular piezoresistive measuring elements varies with the external pressure, and the connection of the four piezoresistive measuring elements in the manner of the Wheatstone bridge can eliminate many Common mode error. Therefore, the pressure gauge has higher detection accuracy.
  • the cavity formed by the mutual connection of the substrate and the cover is a vacuum sealed cavity. The main part of the piezoresistive measuring element is disposed in the cavity.
  • the pressure gauge chip basically uses silicon as a raw material, on the one hand, it solves the mismatch problem caused by different thermal expansion and contraction coefficients of various materials, and on the other hand, the cost is far more than quartz or sapphire through the MEMS manufacturing process. The pressure gauge is low.
  • FIG. 1 is a three-dimensional perspective view of a first embodiment of a pressure gauge chip.
  • FIG. 2 is a three-dimensional perspective view showing the opening of the cover plate of the first embodiment of the pressure gauge chip of FIG. 1 and the removal of the silicon oxide layer on the top surface.
  • Figure 3 is a top plan view of a first embodiment of a pressure gauge chip.
  • FIG. 4 is a three-dimensional perspective view of a second embodiment of the pressure gauge chip.
  • FIG. 5 is a three-dimensional perspective view showing the opening of the cover plate of the second embodiment of the pressure gauge chip of FIG. 4 and the removal of the silicon oxide layer on the top surface.
  • Figure 6 is a three-dimensional perspective view taken along line AA' of Figure 5.
  • Figure 7 is a top plan view of a second embodiment of a pressure gauge chip.
  • Figure 8 is a schematic diagram showing the circuit connection of the piezoresistive measuring element in the pressure gauge chip.
  • Figure 9 is a schematic view of the pressure gauge.
  • Fig. 10A is a graph showing changes in the piezoresistive coefficient of ⁇ 11 + ⁇ 12 in the crystal direction on the plane of the P-type silicon ⁇ 110 ⁇ crystal.
  • Fig. 10B is a graph showing changes in the piezoresistive coefficient of ⁇ 11 + ⁇ 12 in the crystal direction on the plane of the N-type silicon ⁇ 110 ⁇ crystal.
  • Figure 11 is a schematic diagram showing the first and second steps of the manufacturing process of the first embodiment of the pressure gauge chip.
  • Figure 12 is a schematic view showing the third and fourth steps of the manufacturing process of the first embodiment of the pressure gauge chip.
  • Figure 13 is a schematic view showing the fifth and sixth steps of the manufacturing process of the first embodiment of the pressure gauge chip.
  • Figure 14 is a seventh step view showing the manufacturing process of the first embodiment of the pressure gauge chip.
  • Figure 15 is a schematic diagram showing the first and second steps of the manufacturing process of the second embodiment of the pressure gauge chip.
  • Figure 16 is a schematic view showing the third and fourth steps of the manufacturing process of the second embodiment of the pressure gauge chip.
  • Figure 17 is a schematic view showing the fifth and sixth steps of the manufacturing process of the second embodiment of the pressure gauge chip.
  • Figure 18 is a seventh step view showing the manufacturing process of the second embodiment of the pressure gauge chip.
  • Substrate 1 device layer 2, cover plate 3, silicon oxide layer 4, recess 5, substrate 6, metal contact 8, Class A concentrated doped region 9, Class B concentrated doped region 10, slot 11, piezoresistive measuring element 23, constant current source 24;
  • the pressure gauge chip is basically made of single crystal silicon, including the substrate 6 and the cover plate 3 connected to each other, and the silicon structure is used to remove errors caused by different thermal expansion and contraction coefficients of various materials.
  • the cover plate 3 is formed with a recess 5 and is bonded to the substrate 6 to form a sealed cavity.
  • the connecting surface of the cover plate and the substrate is indicated by a broken line.
  • the substrate comprises a piezoresistive measuring element 23, the main part of which is located within the sealed cavity.
  • the sealed cavity is a vacuum sealed cavity, thereby preventing external foreign matter and temperature fluctuations from affecting the piezoresistive measuring element 23.
  • a silicon oxide layer 4 is formed between the substrate 6 and the cap plate 3, and the silicon oxide layer 4 is provided with a metal contact 8 which is opposite to the piezoresistive measuring element 23 in the substrate 6. Electrical connections, while external circuitry and other electronic components are also electrically coupled only to the electrical contacts 8, further reducing interference with the piezoresistive measurement component 23.
  • the substrate 6 is provided with four piezoresistive measuring elements 23 of the same shape and size, respectively R1 to R4, wherein R1, R3 and R2, R4 are perpendicular to each other.
  • Each piezoresistive measuring element employs a U-shaped bent design.
  • the piezoresistive measuring element 23 includes a plurality of interconnected U-shaped bent structures.
  • the piezoresistive measuring element 23 is a diffusion resistor fabricated by locally doping on the substrate 6, and is insulated from each other by a reverse biased PN junction. The doping is determined to be P-type doped or N-type doped depending on the properties of the substrate 6.
  • each piezoresistive measuring element 23 is also formed with a type A concentrated doping region 9 for the purpose of locally increasing the piezoresistive resistance.
  • the doping concentration of the measuring element 23 is measured, and therefore, the type A concentrated doping region 9 and the piezoresistive measuring element 23 must have the same non-rich doping type. Since the sheet resistance of the non-dense doped region is about 100 ⁇ /square, and the sheet resistance of the heavily doped region is only about 15 ⁇ /square, a type A concentrated doping region 9 is provided in each piezoresistive measuring element 23 to locally reduce the voltage.
  • the resistance value of the resistance measuring element 23 forms a highly conductive region such that the total resistance value of each piezoresistive measuring element 23 is only slightly more than the sum of the remaining partial resistance values of the non-concentrated doped regions.
  • the changes in the partial resistances disposed in the sealed cavity and arranged in the same direction are the largest, by setting the Class A concentrated doping region. 9 to lower the resistance value of the partial region, the percentage change of the resistance of the piezoresistive measuring element 23 can be increased, thereby improving the detection accuracy of the pressure gauge.
  • a Class B concentrated doped region 10 and an electronic contact 8 connected thereto are provided for use as an external circuit to the other portion of the substrate 6 outside the piezoresistive measuring element 23 to provide the desired reverse for each PN junction. Offset.
  • the doping type of the B-type heavily doped region 10 and the substrate 6 must be the same in order to ensure good electrical contact between the electronic contact 8 and the substrate 6.
  • the resistance values of the four piezoresistive measuring elements R1 to R4 should be substantially the same without the pressure gauge chip being subjected to external pressure. Since the piezoresistive effect of the single crystal silicon is anisotropic, preferably, two pairs of mutually perpendicular piezoresistive measuring elements R1, R3 and R2, R4 may be arranged in different crystal directions for the purpose of detecting the gauge chip. When the external pressure is uniformly compressed and the deformation can be freely generated, the difference between the piezoresistive effects of the two pairs of piezoresistive measuring elements R1, R3 and R2 and R4 is maximized. If so, it will produce different resistance changes.
  • the factor that affects the resistance value of the piezoresistive measuring element 23 is not limited to stress, and other factors such as changes in ambient temperature may also cause changes in the resistance value of the piezoresistive measuring element 23.
  • the piezoresistive measuring elements R1 to R4 are electrically connected in the form of a Wheatstone bridge and are powered by a constant current source 24.
  • the measured external pressure can be calculated by measuring the voltage between the two points of the point V+ and the point V-.
  • the resistance values of the piezoresistive measuring elements R1 to R4 are substantially the same, and the voltage between the measuring points V+ and V- is substantially zero.
  • connection of the Wheatstone bridge mainly eliminates the common mode error. For example, when the temperature changes, the resistance changes produced by the four piezoresistive measuring elements R1 to R4 are the same, so that there is no external voltage, and the voltage between the two points V+ and V- is still zero.
  • the Wheatstone bridge can be driven by a constant voltage power source or a constant current power source, but preferably, the Wheatstone bridge excited by the constant current power source has the following advantages: the negative temperature coefficient of the piezoresistive effect of silicon Part of it is offset by the positive temperature coefficient of the resistor, thereby reducing the overall error ratio factor caused by temperature. By measuring the bridge voltage of the measuring point Vb, the corresponding temperature information can be calculated, and the error caused by the ambient temperature can be further compensated.
  • the present invention provides a piezoresistive measuring element in two perpendicular directions, so that the pressure collected by the piezoresistive measuring element when detecting the pressure is The information is more comprehensive.
  • a conventional silicon MEMS film gauge chip generates a detection signal by detecting two sets (two per group) of piezoresistive measurement elements disposed in a single direction, which are limited by the edge of the film.
  • the shape design of the two sets of piezoresistive measuring components often cannot be consistent, and the difference in shape or size of the two sets of piezoresistive measuring components themselves may cause the resistance or temperature coefficient between the piezoresistive measuring components to be mismatched, so that the Wheatstone The common mode error after bridge processing cannot be completely eliminated. Although analog or digital compensation can still be performed later, certain detection accuracy will still be sacrificed. However, the present invention performs differential processing on signals of two sets of piezoresistive measuring elements having the same shape and size, so that the detection accuracy of the present invention is higher.
  • the gauge chip has a size of approximately 1.6 mm long, 1.6 mm wide, and 1 mm thick, and the size of the sealed cavity is approximately 0.4 mm long, 0.4 mm wide, and 0.2 mm. high.
  • an ordinary 8-inch silicon wafer can produce thousands to 10,000 pressure gauge chips, making the manufacturing cost of the pressure gauge chip very low.
  • the above size data is only an example of the present invention, and is not intended to limit the scope of the present invention. Those skilled in the art can modify the size according to their specific needs.
  • the piezoresistive measuring elements 23 are isolated by the PN junction, their interception The relationship between current and temperature is exponential. When the temperature is raised to 150 degrees Celsius, the PN junction isolation will fail, so this embodiment is only suitable for applications below 150 degrees Celsius.
  • a second embodiment of a pressure gauge chip is provided in accordance with the present invention.
  • the working principle, the size, the external circuit and the like of the embodiment are the same as those of the first embodiment, except that the substrate 6 in the embodiment is a silicon-on-insulator structure, including the substrate 1 and the device layer 2 connected to each other. And a silicon oxide layer 4 between the substrate 1 and the device layer 2.
  • This silicon oxide layer 4 is also referred to as a silicon oxide buried layer for electrically isolating the substrate 1 and the device layer 2.
  • the piezoresistive measuring element 23 of the present embodiment is disposed on the device layer 2, and a silicon oxide layer 4 is formed on the side walls of each of the piezoresistive measuring elements 23.
  • the silicon oxide layer 4 is isolated on the upper and lower sides of each piezoresistive measuring element, which not only prevents electrical crosstalk between the piezoresistive measuring elements 23, but also allows the pressure gauge chip to operate at high temperatures of up to 250 degrees Celsius. It is not limited by the failure of the PN junction isolation in the first embodiment at high temperatures.
  • the type A concentrated doping region 9 located at both ends of the piezoresistive measuring element 23 and the U-turn is intended to locally increase the doping concentration of the piezoresistive measuring element 23 to form a highly conductive region, and its function and first implementation The examples are the same.
  • the piezoresistive measuring element 23 itself is a resistor formed by the single crystal silicon material of the device layer 2, the doping type of the class A doped region 9 and the doping type of the device layer 2 must be the same.
  • the device layer 2 has a thickness of about 2 ⁇ m and the silicon oxide layer 4 has a thickness of about 1 ⁇ m.
  • the above size data is only an example of the present invention, and is not intended to limit the scope of the present invention. Those skilled in the art can modify the size according to their specific needs.
  • Figure 9 shows a schematic view of the present pressure gauge for use in the first and second embodiments of the above-described pressure gauge chip.
  • the pressure gauge chip 31 is mounted in the pressure gauge cavity 33.
  • the cavity is made of metal, internally filled with an electrically insulating liquid 37, and the gauge chip 31 is immersed in the electrically insulating liquid 37.
  • the cavity 33 is further provided with a metal diaphragm 38, and the electrically insulating liquid 37 and the gauge chip 31 are sealed within the cavity 33.
  • the metal diaphragm 38 is connected to an external pressure 39 and transmits the external pressure 39 to the electrically insulating liquid 37.
  • the metal diaphragm 38 is designed as a corrugated metal diaphragm, and its own pressure resistance is extremely small, so that the external pressure is 39. All of this is transferred to the manometer chip 31 by the electrically insulating liquid 37.
  • the connection point of the pressure gauge chip 31 and the cavity 33 is relatively small.
  • the pressure gauge chip 31 passes through the chip adhesive 32 of one side or even one point to the cavity 33.
  • Connected, and the die attach adhesive 32 is flexible such that the gauge chip 31 is uniformly compressed and free to deform when subjected to the ambient pressure 39 transmitted by the electrically insulating liquid 37. This flexible mounting also avoids the fact that the manometer chip 31 may be affected by the deformation of the cavity 33 due to external forces or temperature.
  • the cavity formed between the substrate 6 and the cap plate 3 in the pressure gauge chip 31 is in a vacuum state, so the absolute pressure is measured by the pressure gauge.
  • the metal contacts 8 on the manometer chip 31 are connected to the metal cylinder 35 by wire bonds 34 and are carried out of the manometer cavity 33, with external circuitry. Connected. The metal cylinder 35 is electrically isolated from the sealed insulator 36 between the pressure gauge cavity 33.
  • the resistivity of single crystal silicon is closely related to the type of dopant ions and the concentration of dopant ions, wherein the type of dopant ions includes P type or N type. Since the piezoresistive effect of single crystal silicon is anisotropic, the difference in crystal orientation also causes the difference in resistivity with stress. The factors that cause the magnitude of the change in resistivity are published in Y. Kanda in the IEEE Transactions on Electron Devices, vol. ED-29, no. 1, pp. 64-70, 1982. A detailed explanation of the graph of the piezoresistive coefficient of silicon is given. Among them, the relationship between resistivity change and stress and piezoresistive coefficient is
  • 1, 2, and 3 are the three vertical directions of the Cartesian coordinates; ⁇ 11 / ⁇ is the change of the resistivity when the electric field and the current are both in the 1 direction; ⁇ 11 , ⁇ 22 , and ⁇ 33 are along the 1, 2 Normal stress in 3 directions; ⁇ 23 , ⁇ 13 , ⁇ 12 are shear stresses in the directions 2-3, 1-3, 1-2, respectively; and ⁇ 11 , ⁇ 12 , ⁇ 13 , ⁇ 14 , ⁇ 15 , ⁇ 16 is a piezoresistive coefficient that expresses the relationship between the change in resistivity and various stresses, respectively.
  • the top surface of the substrate 6 of the manometer chip 31 is a 1-2 plane perpendicular to the three directions, and the piezoresistive measuring element 23 is located above the plane.
  • the main (non-densely doped) portions of the four piezoresistive measuring elements 23 are all facing the vacuum sealed cavity, so that the 1-2 plane in which it is located is a free surface, so all The stresses related to the 3 directions, that is, ⁇ 13 , ⁇ 23 , and ⁇ 33 , are all zero.
  • the manometer chip 31 is mounted in the manometer cavity 33 to be uniformly compressed and free to deform.
  • the normal stress of each of the upper and lower surfaces of the manometer chip 31 is equivalent to the external pressure 39, and the shear stress is almost zero.
  • ⁇ 12 is still about zero, and ⁇ 11 and ⁇ 22 are equal to each other and the value of the external pressure 39 is set.
  • the thickness of the substrate 6 should be larger than the width of the sealing cavity. Otherwise, the substrate 6 may be recessed toward the sealing cavity due to the external pressure 39, and the result is ⁇ 11 and ⁇ .
  • k is a constant that is usually less than one.
  • the resistance is proportional to the resistivity, it is known from the formula (2) that the resistance change of the piezoresistive measuring element 23 is close to the external pressure 39, and the sensitivity is substantially the same as the ⁇ 11 + ⁇ 12 piezoresistive coefficient. In direct proportion.
  • the piezoresistive effect of single crystal silicon is anisotropic, the size of ⁇ 11 + ⁇ 12 changes due to the orientation of the 1-2 plane and the 1 direction. For example, when the 1-2 plane is a silicon ⁇ 110 ⁇ crystal plane, referring to FIG. 10, when the 1 direction is rotated from 0 to 360 degrees, the ⁇ 11 + ⁇ 12 piezoresistive coefficient changes as shown in FIG.
  • ⁇ 11 + ⁇ 12 reaches a maximum value in the ⁇ 110> direction, and reaches a ⁇ 100> direction perpendicular to the ⁇ 110> direction. Minimum value.
  • the two pairs of piezoresistive measuring elements R1, R3 and R2, R4 may be arranged in different crystal directions, for the purpose of When the pressure gauge chip 31 is uniformly compressed by the detected external pressure 39 and can be freely deformed, the piezoresistive effect of the two pairs of piezoresistive measuring elements R1, R3 and R2, R4, that is, ⁇ 11 + The ⁇ 12 piezoresistive coefficient has the largest difference. If so, a different resistance change will occur, which is processed by the Wheatstone bridge to form a voltage output.
  • the substrate 6 in the first embodiment and the substrate 1 and the device layer 2 in the second embodiment are each single crystal silicon disposed on a ⁇ 110 ⁇ crystal plane, and
  • the directions along which the two pairs of piezoresistive measuring elements are located are two mutually perpendicular crystal directions of ⁇ 100> and ⁇ 110>, respectively.
  • the portions of the two piezoresistive measuring elements R1 and R3 which are not densely doped are in the ⁇ 100> direction, so their resistance changes are the same; meanwhile, the two piezoresistive measuring elements R2 and R4 are not The heavily doped regions are all in the ⁇ 110> direction, so their resistance changes are the same but the difference from R1 and R3 is the largest.
  • the cover plate 3 is also a single crystal disposed on the ⁇ 110 ⁇ crystal plane. Silicon, the crystal direction of the cover plate 3 and the substrate 6 on the bonding surface of the cover plate 3 corresponding to the substrate 6 is uniform. Or the cover plate 3 is aligned with the crystal direction of each of the sides of the substrate 1 and the device layer 2.
  • the skilled person can also preferably select the crystal face of the substrate 6 or the device layer 2 and the arrangement direction of the piezoresistive measuring element 23 according to the description of Y. Kanda.
  • the process is applicable to the structure shown in the first embodiment of the pressure gauge chip.
  • the raw material of the substrate 6 is a single crystal silicon wafer, and then the following processing steps are included:
  • the single crystal silicon wafer is subjected to high temperature oxidation treatment, a silicon oxide layer 4 is formed on the top surface and the bottom surface thereof, or a silicon oxide layer is deposited by chemical vapor deposition (Chemical Vapor Deposition). .
  • a photoresist is coated on the top surface of the single crystal silicon wafer, and then the top surface is exposed according to a specific pattern, and the exposed photoresist is removed by a developer, and The exposed photoresist is baked. The pattern thus exposed will appear. Then using ion implantation technology, and by energy control, the ions have sufficient energy to pass through the top silicon oxide layer not covered by the photoresist to be injected into the single crystal silicon wafer, and at the same time, covered by the photoresist. Whereas, the ions are trapped in the photoresist layer.
  • the substrate 6 of the single crystal silicon wafer can be partially doped to form the piezoresistive measuring element 23 opposite to the type of the substrate 6.
  • the substrate 6 is of a P type, an N-type dopant ion such as phosphorus is used; and if the substrate 6 is of an N type, a P-type dopant ion such as boron is used. Finally, all lithography Glue removal. In addition to the ion implantation techniques described above, impurity high temperature diffusion techniques can also be used for local doping.
  • the top surface of the single crystal silicon wafer is locally heavily doped by photolithography and ion implantation to form the type A concentrated doping region 9 of the same type as the piezoresistive measuring element 23. Thereby reducing the resistance value of the region to form a highly conductive region.
  • the substrate 6 is of a P type, an N-type dopant ion such as phosphorus is used; and if the substrate 6 is of an N type, a P-type dopant ion such as boron is used.
  • the top surface of the single crystal silicon wafer is partially heavily doped by photolithography and ion implantation to form the B-type heavily doped region 10 of the same type as the substrate 6, thereby reducing The resistance value of this region forms a highly conductive region.
  • a P-type dopant ion such as boron
  • an N-type dopant ion such as phosphorus
  • the top silicon oxide layer 4 of the single crystal silicon wafer is partially etched by photolithography, reactive ion or plasma dry etching, or hydrofluoric acid etching, thereby Forming a plurality of holes deep into the type A concentrated doped region 9 and the B-type densely doped region 10 of the substrate 6, and depositing metal in the holes and the top surface of the entire silicon wafer, and then utilizing light
  • the metal contacts 8 and the electrode patterns are extracted by etching and metal etching.
  • the pre-cavity-processed single crystal silicon cap wafer is vacuum bonded to the top surface of the single crystal silicon wafer to form a sealed vacuum cavity.
  • the bonding technique may be silicon-silicon direct bonding, eutectic bonding, solder bonding, or anodic bonding.
  • the bonded silicon wafer is divided by dicing to form a complete pressure gauge chip.
  • the raw material used is a silicon-on-insulator wafer, including a substrate 1, a device layer 2, and the substrate and the device.
  • the silicon oxide buried layer 4 between the layers is then subjected to the following processing steps:
  • the silicon wafer on the insulator is subjected to high temperature oxidation treatment, a silicon oxide layer 4 is formed on the top surface and the bottom surface thereof, or a silicon oxide layer is deposited by chemical vapor deposition (Chemical Vapor Deposition). .
  • a photoresist is coated on the top surface of the silicon-on-insulator wafer, and then the top surface is exposed in a specific pattern, and the exposed photoresist is removed by a developer, and The exposed photoresist is baked. The pattern thus exposed will appear. Then using ion implantation technology, and through energy control, the ions have enough energy to pass through the top silicon oxide layer not covered by the photoresist and implanted into the device layer. At the same time, the ions are blocked in the place covered by the photoresist. In the photoresist layer.
  • the device layer 2 of the silicon-on-insulator wafer can be locally heavily doped to form a type A densely doped region 9 of the same type as the device layer 2, thereby reducing the resistance value of the region and forming a high A conductive region; wherein, if device layer 2 is P-type, a P-type dopant ion, such as boron, is used. If device layer 2 is N-type, an N-type dopant ion, such as phosphorus, is used. Finally all the photoresist is removed. In addition to the ion implantation techniques described above, high concentration diffusion of impurities can also be used for local concentrated doping.
  • the third step photolithography is performed on the top surface of the silicon wafer on the insulator, and the top silicon oxide layer 4 is locally etched by reactive ion or plasma dry etching or hydrofluoric acid etching. A plurality of grooves 11 deep to the device layer 2 are formed on the top surface. Thereafter, the device layer 2 in the trench 11 is further etched into the silicon oxide buried layer 4 by deep reactive ion etching or other dry or wet etching. Thereby, a plurality of piezoresistive measuring elements 23 are formed.
  • a silicon oxide spacer layer 4 is grown or deposited in the trench 11 by high temperature oxidation or chemical vapor deposition, and the introduced rich doping is activated. At this point, all the upper and lower sides of the piezoresistive measuring element are wrapped by the silicon oxide insulating layer.
  • the top surface silicon oxide layer 4 of the high conductive region is locally etched by photolithography, reactive ion or plasma dry etching, or hydrofluoric acid etching, thereby forming a plurality of top surfaces.
  • a hole deep into the heavily doped region 9 of the class A of the device layer 2, and deposited in the hole and on the top surface of the entire silicon wafer The metal is then etched by photolithography and metal etching to extract the metal contacts 8 and the electrode patterns.
  • the pre-cavity-processed single crystal silicon cap wafer is vacuum bonded to the top surface of the silicon-on-insulator wafer to form a sealed vacuum cavity.
  • the bonding technique may be silicon-silicon direct bonding, eutectic bonding, solder bonding, or anodic bonding.
  • the bonded silicon wafer is divided by dicing to form a complete pressure gauge chip.
  • the etching method is one or more of the following methods: dry etching or wet etching, the dry etching includes: deep reactive ions of silicon, reactive ions, and gaseous states.
  • the etchant for wet etching the silicon layer is a combination of one or more of the following etchants: potassium hydroxide, tetramethylammonium hydroxide, or ethylenediamine catechol etching solution.
  • the etchant for wet etching the silicon oxide layer is hydrofluoric acid or buffered hydrofluoric acid.
  • the pressure gauge chip of the invention adopts a non-film type novel structure, and the internal stress generated when the chip is uniformly pressed is converted into the resistance value change of the piezoresistive measuring component 23 by the piezoresistive effect of the single crystal silicon. Moreover, the anisotropy of the piezoresistive effect of the single crystal silicon is utilized, and the crystal faces of the two pairs of piezoresistive measuring elements 23 and the direction of the crystals are optimized, so that the difference in resistance value between the two pairs is maximized, thereby detecting up to 200 MPa. pressure.
  • each piezoresistive measuring element 23 is disposed in the cavity of the vacuum, which greatly reduces external environmental factors and the influence of foreign matter on the pressure gauge chip, and also enhances the reliability and detection accuracy of the pressure gauge.
  • each piezoresistive measuring element 23 is completely wrapped in a layer of silicon oxide 4 such that each piezoresistive measuring element 23 is isolated from each other. This isolation by means of an insulator also makes the manometer It can be tested in a high temperature environment.
  • electrically connecting the piezoresistive measuring element in the manner of a Wheatstone bridge can reduce the common mode error caused by external factors and reduce the influence of temperature on the accuracy of the pressure gauge detection.
  • the use of a silicon MEMS process to produce the pressure gauge chip is mature technology and low in cost. As mentioned above, an ordinary 8-inch silicon wafer can produce thousands to 10,000 of this pressure gauge chip, and it can be seen that the pressure gauge has a low manufacturing cost.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mining & Mineral Resources (AREA)
  • Geology (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • General Life Sciences & Earth Sciences (AREA)
  • Environmental & Geological Engineering (AREA)
  • Fluid Mechanics (AREA)
  • Geophysics (AREA)
  • Geochemistry & Mineralogy (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • General Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Measuring Fluid Pressure (AREA)
  • Pressure Sensors (AREA)

Abstract

一种压力计芯片（31）以及其制造方法。一种压力计，包括腔体（33）、以及设置在腔体（33）内的压力计芯片（31）；压力计芯片（31）在腔体（33）内受被检测的外界压力均匀压缩并且能够自由的产生形变。压力计芯片（31）基本由单晶硅制成，包括相互连接的基板（6）及盖板（3）；盖板（3）上形成有凹陷部（5），并与基板（6）形成一个密封空腔，基板（6）与盖板（3）之间形成有氧化硅层（4）；基板（6）包括压阻测量元件（23），压阻测量元件（23）位于空腔之内。本压力计芯片（31）适合测量超高压力，受温度影响较小，可以在高温的环境中使用，而且具有检测精度高、可靠性高、制造成本低等特点。

Description

一种压力计芯片及其制造工艺 技术领域
本发明涉及一种传感器，特别是一种用于检测矿井下压力变化的压力计。
背景技术
在碳氢化合物矿井的勘探与开采过程中，井下压力的测量是至关重要的。在钻井时所采集的压力数据将用于设置钻头的各项参数以及建立矿井的结构。当钻好矿井并开始开采后，油气储存量管理上又要用到压力数据。所以在碳氢化合物矿井的整个周期中，压力数据是至为关键的，尤其是在优化开采和降低风险上。为此，人们需要一种能精确，性价比又高的压力测量装置。
而用于碳氢化合物井下的压力传感器必须在恶劣的工作环境中，于长达数周的测量期间依旧能够保持精准度、稳定性和可靠性。通常传感器必须能够承受-50至250摄氏度的温度，以及高至200MPa的压力(约2000个大气压)，其精准度必须将误差保持在压力量程的0.1％的范围内，最好是在0.01％的范围内。
用于井下的压力计通常包括两种：第一种是石英类压力计，其中的石英谐振器被浸在液体中，并通过一个金属隔离膜片或者波纹管来测量外界的压力。在美国3617780号专利中描述了一种石英谐振器，其中的石英谐振部件被置于一个由石英外壳构成、真空密封的腔体内并形成了该腔体结构的主要支撑部件。该谐振部件通过电激励及石英的压电效应而产生谐振，其谐振频率会根据腔体壁上的压力变化而变化。由于石英共振已经是非常成熟的技术，而石英谐振器的全部部件基本都由石英制成，所以石英压力计有着很高的精准度、稳定性和可靠性，并成为当今井下压力计的最高标准。然而，石英压力计的造价非常的 昂贵。
另一种用于井下的压力计为蓝宝石类压力计。在美国5024098号专利中描述了一种蓝宝石压力计，其中，蓝宝石元件被浸在液体中并通过隔离膜片来测量外界的压力。蓝宝石元件在受到压力时产生形变，通过设置在蓝宝石元件表面上的薄膜应变计所测量的应变则可以推算出压力值。虽然蓝宝石压力计的可靠性很高，并且适用于井下应用，但其精准度和稳定性并不如石英压力计，而且其造价也非常昂贵。主要原因是：如果使用的薄膜应变计是硅材料的话，则精确度会受到硅的电阻温度系数以及压阻效应的温度系数的影响。然而，如果不使用硅应变计，而采用金属合金类薄膜应变计的话，则会有灵敏度低的问题，也会带来温度和其他测量误差被放大的问题。此外，无论使用哪种材料的薄膜应变计，都会有和蓝宝石热胀冷缩系数不匹配所带来的误差。
现如今，大多数传感器均为微机电系统(Micro-Electro-Mechanical Systems-MEMS)类型的传感器。与集成芯片类似，MEMS传感器通常是通过对硅晶圆片进行微加工而制成的。鉴于MEMS传感器的结构，也有一些用来制造三维细微结构的特殊的制造工艺，例如双面光刻，深度反应离子刻蚀(Deep Reactive Ion Etching)，硅晶圆片键合等等。与石英和蓝宝石相比，硅具有很好的机械特性，例如，高硬度，高弹性模量，高极限强度，并且在断裂点之前都是完全弹性的。此外，单晶硅具有很强的压阻效应，能有效地将应力变化转化为电阻变化。况且，在硅上制作精确的微结构要比在石英或者蓝宝石上制作容易的多。鉴于其成本低、尺寸小、精度高、可靠性高以及稳定性高等诸多优点，硅MEMS压阻式压力计已经广泛应用于汽车、医疗、工业以及电子产品中。
虽然有如此多的优点，MEMS压力计仍没有被广泛的用于矿井应用领域。其中有几个必须要解决的问题，特别是在测量特别高压力的时候，需要一种有别于常规硅薄膜式压力计的改进型机械设计。这是因为常规的硅薄膜式压力计芯片是利用硅薄膜来将压力放大为应力，为了适合测量高达200MPa的高压，必须将薄膜弄窄和弄厚。但若薄膜设计得太窄就会放不下压阻测量元件；若将 薄膜大大加厚，则会导致整个芯片产生非理想性的形变。此外，MEMS压力计还需要克服各种温度系数以及不稳定性来增加在高温环境中的测量精准度。为此，现在需要一种能够在井下高温高压环境中仍然能够具有高精准度并且性价比高的硅基压力计。
发明内容
本发明的目的在于克服现有技术的不足，提供一种准确度高、检测范围大、并且受环境影响小，能够在矿井下这种高温、高压环境中仍然能够准确输出压力数据的压力计。
一种压力计，包括腔体、以及设置在所述腔体内的压力计芯片，所述压力计芯片在所述腔体内受被检测的外界压力均匀压缩并且能够自由的产生形变。所述压力计芯片基本由单晶硅制成，包括相互连接的基板及盖板，其特征在于：所述盖板上形成有凹陷部，并与所述基板形成一个密封空腔，所述基板与所述盖板之间形成有氧化硅层；所述基板包括压阻测量元件，所述压阻测量元件位于所述空腔之内。本发明中的压力计还具有以下可选的附属特征：
所述密封空腔为真空密封空腔。
所述压阻测量元件的末端形成有金属触点。
所述基板包括至少两对相互垂直的所述压阻测量元件。
所述压阻测量元件相互之间以惠斯登电桥方式相电连接。
所述基板是设置在{110}晶体平面上的P型硅，所述压阻测量元件是设置在所述基板上并沿<100>或<110>晶体方向布置的N型掺杂区。
所述基板是设置在{110}晶体平面上的N型硅，所述压阻测量元件是设置在所述基板上并沿<100>或<110>晶体方向布置的P型掺杂区。
所述盖板以及所述基板为长方体，所述盖板是设置在{110}晶体平面上的单晶硅；在所述盖板与所述基板的键合面上，所述盖板的每一条边与所述基板相对应的每一条边所沿的晶体方向一致。
所述压力计芯片基板为绝缘体上硅(Silicon On Insulator-SOI)结构，包括 衬底、器件层以及设置在所述衬底与器件层之间的氧化硅埋层；所述压阻测量元件设置于所述器件层上。
所述压阻测量元件的顶端、底端及侧壁上分别形成有氧化硅隔离层。
所述器件层是设置在{110}晶体平面上的P型硅，所述压阻测量元件是设置在所述器件层上并沿<100>或<110>晶体方向布置的P型硅。
所述器件层是设置在{110}晶体平面上的N型硅，所述压阻测量元件是设置在所述器件层上并沿<100>或<110>晶体方向上布置的N型硅。
所述衬底是设置在{110}晶体平面上的单晶硅，所述衬底与所述器件层相应的每一条边所沿的晶体方向一致。
所述盖板是设置在{110}晶体平面上的单晶硅，所述盖板与所述器件层相应的每一条边所沿的晶体方向一致。
所述腔体由金属制成，所述腔体内填充有电绝缘液体，所述压力计芯片浸入在所述电绝缘液体中。
所述压力计上还设置有金属膜片，所述金属膜片用于密封所述电绝缘液体以及所述压力计芯片。
所述压力计芯片通过所述金属膜片来检测外界压力。
所述压力计芯片的第一种制造工艺，包括以下步骤：
第一步，在单晶硅晶圆片的顶面及底面生长或淀积一层氧化硅层；
第二步，通过光刻及离子注入，对所述单晶硅晶圆片的顶面进行局部掺杂；形成多个与所述单晶硅晶圆片掺杂类型相反的压阻测量元件；
第三步，通过光刻及离子注入，对所述单晶硅晶圆片的顶面进行局部浓掺杂；形成与所述单晶硅晶圆片掺杂类型相反的高导电区域；
第四步，通过光刻及离子注入，对所述单晶硅晶圆片的顶面进行局部浓掺杂；形成与所述单晶硅晶圆片掺杂类型相同的高导电区域。之后再在所述单晶硅晶圆片的顶面及底面生长或淀积一层氧化硅层，并将所述各种已引入的掺杂激活；
第五步，通过光刻和刻蚀，在所述高导电区域的顶面氧化硅层刻蚀出多个深至所述浓掺杂区的孔；并在所述孔内淀积金属并引出电极；
第六步，将预先加工有凹陷部的单晶硅盖板晶圆片与所述单晶硅晶圆片的顶面进行键合；
第七步，通过划片，将所述已键合的硅晶圆片分割，形成完整的压力计芯片。
所述压力计芯片的第二种制造工艺，包括以下步骤：
第一步，在绝缘体上硅晶圆片的顶面及底面生长或淀积一层氧化硅层；
第二步，通过光刻及离子注入，对所述绝缘体上硅晶圆片的器件层进行局部浓掺杂；形成与所述器件层掺杂类型相同的高导电区域；
第三步，通过光刻以及刻蚀，在所述器件层上刻蚀出多个深至氧化硅埋层的槽；形成多个压阻测量元件；
第四步，在所述槽内生长或淀积一层氧化硅层，并将所述已引入的浓掺杂激活；
第五步，通过光刻和刻蚀，在所述高导电区域的顶面氧化硅层刻蚀出多个深至所述器件层中浓掺杂区的孔；并在所述孔内淀积金属并引出电极；
第六步，将预先加工有凹陷部的单晶硅盖板晶圆片与所述绝缘体上硅晶圆片的顶面进行键合；
第七步，通过划片，将所述已键合的硅晶圆片分割，形成完整的压力计芯片。
对所述盖板的凹陷部的加工步骤包括：通过光刻和刻蚀，在所述盖板上刻蚀出凹陷部。
所述刻蚀的方法为以下方法中的一种或多种方法：干法刻蚀或湿法刻蚀，所述干法刻蚀包括：硅的深度反应离子、反应离子、以及气态的二氟化氙刻蚀和氧化硅的反应离子、等离子、以及气态的氟化氢刻蚀。
所述用于湿法腐蚀硅层的腐蚀剂为以下腐蚀剂中的一种或多种的组合：氢 氧化钾、四甲基氢氧化铵、或乙二胺邻苯二酚腐蚀液。
所述用于湿法腐蚀氧化硅层的腐蚀剂为以下腐蚀剂中的一种或多种的组合：氢氟酸以及缓冲氢氟酸。
相对于背景技术中所提到的两种不同的井下应用的压力计，本发明的压力计具有以下优点：首先，硅基压力计的造价远远低于石英或者蓝宝石压力计，但常规的硅薄膜式压力计并不能应用于测量矿井高达200MPa的压力环境中，而本发明有别于常规硅薄膜式压力计，本发明的压力计利用井下的高压力施加于压力计芯片的上下四方并直接转化为芯片内部的应力，以至于本压力计无需通过硅薄膜来将外界压力放大为应力，一方面解决了硅薄膜式压力计在高压应用设计上的困难，同时亦保留硅MEMS传感器的优点。另一方面，由于传统MEMS压阻式压力计中压阻测量元件之间是依靠PN结隔离的，其截流电流与温度之间的关系为指数关系，当温度提高至150摄氏度时，PN结隔离将会失效。而本发明的其中一个实施例中的压阻测量元件与衬底之间设置有氧化硅埋层，每个压阻测量元件之间也设置氧化硅来进行绝缘，此外，压阻测量元件顶部上也生长或淀积有氧化硅层。因此，每个压阻测量元件是处于上下四周完全绝缘的状态，即使温度升高，本发明所述的实施例中的电隔离也不会失效。其次，在本压力计芯片中，两对相互垂直的压阻测量元件其电阻随外界压力呈不一样变化，而将四个压阻测量元件以惠斯登电桥的方式进行连接可以消除许多的共模误差。因此本压力计的检测精准度更高。再次，优选地，由基板和盖板相互连接后形成的空腔为真空的密封空腔。而压阻测量元件的主要部分均设置在该空腔中。所以外界温度的波动对本压力计芯片的影响较小，而且外部异物也无法接触到测量元件。进一步的增加了本压力计的可靠性。此外，压力计芯片整体基本采用硅作为原料，一方面解决了各种材料之间因热胀冷缩系数不同而导致的失配问题，另一方面通过MEMS制造流程也使得成本远较石英或者蓝宝石压力计为低。
附图说明
图1为压力计芯片中第一实施例的三维立体示意图。
图2为将图1的压力计芯片中第一实施例的盖板打开及顶面的氧化硅层移除后的三维立体示意图。
图3为压力计芯片中第一实施例的俯视图。
图4为压力计芯片中第二实施例的三维立体示意图。
图5为将图4的压力计芯片中第二实施例的盖板打开及顶面的氧化硅层移除后的三维立体示意图。
图6为沿图5中AA’线剖视的三维立体图。
图7为压力计芯片中第二实施例的俯视图。
图8为压力计芯片中压阻测量元件电路连接示意图。
图9为本压力计的示意图。
图10A为在P型硅{110}晶体平面上π11+π12压阻系数沿晶体方向的变化示意图。
图10B为在N型硅{110}晶体平面上π11+π12压阻系数沿晶体方向的变化示意图。
图11为压力计芯片中第一实施例的制造工艺的第一步、第二步示意图。
图12为压力计芯片中第一实施例的制造工艺的第三步、第四步示意图。
图13为压力计芯片中第一实施例的制造工艺的第五步、第六步示意图。
图14为压力计芯片中第一实施例的制造工艺的第七步示意图。
图15为压力计芯片中第二实施例的制造工艺的第一步、第二步示意图。
图16为压力计芯片中第二实施例的制造工艺的第三步、第四步示意图。
图17为压力计芯片中第二实施例的制造工艺的第五步、第六步示意图。
图18为压力计芯片中第二实施例的制造工艺的第七步示意图。
衬底1、器件层2、盖板3、氧化硅层4、凹陷部5、基板6、金属触点8、 A类浓掺杂区9、B类浓掺杂区10、槽11、压阻测量元件23、恒流电源24；
压力计芯片31、芯片粘接胶32、腔体33、焊线34、金属柱体35、绝缘体36、电绝缘液体37、金属膜片38、外界压力39。
具体实施方式
下面将结合实施例以及附图对本发明加以详细说明，需要指出的是，所描述的实施例仅旨在便于对本发明的理解，而对其不起任何限定作用。
参照图1、图2、以及图3，按照本发明提供一种压力计芯片中的第一实施例。所述压力计芯片基本由单晶硅制成，包括相互连接的基板6及盖板3，采用硅结构去除了因为各种不同材料的热胀冷缩系数不同而产生的误差。所述盖板3上形成有凹陷部5，并与所述基板6相键合后形成一个密封空腔。在图3的俯视图中，所述盖板与基板的连接面由虚线示处。所述基板包括压阻测量元件23，所述压阻测量元件23的主要部分位于所述密封空腔之内。此外，优选地，所述密封空腔为真空密封空腔，从而防止了外界异物以及温度波动对压阻测量元件23的影响。所述基板6与所述盖板3之间形成有氧化硅层4，所述氧化硅层4上设置有金属触点8，所述金属触点8与基板6中的压阻测量元件23相电连接，而外部电路以及其它电子元件也只与电子触点8相电连接，进一步地减少了对压阻测量元件23的干扰。
参照俯视图3，在本实施例中，所述基板6上设置有四个形状大小相同的压阻测量元件23，分别为R1至R4，其中R1、R3与R2、R4相互垂直。每个压阻测量元件采用了U型的弯折设计，优选地，所述压阻测量元件23包括多个相互连接的U型弯折结构。在第一实施例中，压阻测量元件23是通过在基板6上局部掺杂制造而成的扩散电阻，并利用反向偏置的PN结来相互隔离绝缘。所述掺杂是根据基板6的性质来确定是P型掺杂还是N型掺杂的。如果基板6为P型硅，则采用N型掺杂；如果基板6为N型硅，则采用P型掺杂。优选地，每个压阻测量元件23还形成有A类浓掺杂区9，目的是要局部提高压阻 测量元件23的掺杂浓度，因此，所述A类浓掺杂区9和压阻测量元件23原先所述非浓掺杂类型必须相同。由于非浓掺杂区的方块电阻大约为100Ω/方块，而浓掺杂区的方块电阻大约只为15Ω/方块，在每个压阻测量元件23设置A类浓掺杂区9局部降低了压阻测量元件23的电阻值，形成高导电区域，使得每个压阻测量元件23的总电阻值只略多于几根剩下的位于非浓掺杂区的部分电阻值之和。在检测压力计芯片所受的外界压力的过程中，这几根设置于所述密封空腔之内并沿同一个方向上布置的部分电阻的变化是最大的，通过设置A类浓掺杂区9来降低部分区域的电阻值，就可以增加所述压阻测量元件23电阻变化的百分比，从而提高了本压力计的检测精准度。再者，通过所述电子触点8与所述A类浓掺杂区的连接，亦可以保证电子触点8与压阻测量元件23有良好的电接触。此外，还设置B类浓掺杂区10以及与其相连的电子触点8，用作连接外部电路到基板6位于压阻测量元件23之外的其它部分，为各PN结提供所需的反向偏置。所述B类浓掺杂区10与基板6的掺杂类型必须是相同的，目的是要保证电子触点8与基板6有良好的电接触。
由于四个压阻测量元件R1至R4形状大小相同，理论上说，在压力计芯片没受外界压力的情况下，四个压阻测量元件R1至R4的电阻值应当是基本相同的。由于单晶硅的压阻效应呈各向异性，优选地，两对相互垂直的压阻测量元件R1、R3与R2、R4可沿不同的晶体方向布置，目的是当压力计芯片受被检测的外界压力均匀压缩并且能够自由的产生形变时，要令两对压阻测量元件R1、R3与R2、R4的压阻效应差别最大。如是，就会产生不一样的电阻变化。然而，影响压阻测量元件23的电阻值的因素不仅限于应力，其他因素，例如周围环境温度的变化也会导致压阻测量元件23电阻值的变化。为此，优选地，参照图8，压阻测量元件R1至R4是以惠斯登电桥的形式来进行电连接，并由一恒流电源24来供电。通过测量点V+和点V-两点之间的电压则可以计算出被检测的外界压力。当压力计芯片在没有外界压力的情况下，压阻测量元件R1至R4的电阻值基本相同，测量点V+和V-之间的电压基本为零。而当外界压 力使得R1、R3与R2、R4的电阻产生不一样的变化时，V+和V-之间也会产生一定的电压。惠斯登电桥的连接方式主要消除了共模误差。例如，当温度产生变化时，四个压阻测量元件R1至R4所产生的电阻变化是相同的，所以在没有外界压力的情况下，V+和V-两点之间的电压依旧为零。所述惠斯登电桥可以由恒压电源或者恒流电源来驱动，但优选地，由恒流电源所激励的惠斯登电桥还有如下优点：硅的压阻效应的负温度系数中的一部分会被电阻的正温度系数所抵消，从而整体降低了由温度造成的误差比例系数。而通过测量测量点Vb的电桥电压可以计算出相应的温度信息，可以进一步对环境温度导致的误差进行补偿。
相对于现有技术中通过单一方向设置压阻测量元件的方案来说，本发明在两个垂直方向上均设置了压阻测量元件，因此在检测压力时，压阻测量元件所采集到的压力信息更加周全。而且现有技术，例如，常规的硅MEMS薄膜式压力计芯片，是通过检测设置在单一方向上的两组(每组两个)压阻测量元件来产生检测信号，由于受到薄膜边缘的限制，两组压阻测量元件的形状设计往往无法保持一致，而两组压阻测量元件自身的形状或尺寸的不同也会导致压阻测量元件之间的电阻或温度系数不匹配，以致经惠斯登电桥处理后共模误差不能完全被消除。虽然之后仍可以作模拟或数字补偿，但依然会牺牲一定的检测精度。而本发明则是通过对两组形状大小完全相同的压阻测量元件的信号进行差分处理，以至于本发明的检测精确度更高。
参照图1及图3，优选地，本压力计芯片的尺寸大约为：1.6毫米长，1.6毫米宽，1毫米厚，而密封空腔的尺寸大约为：0.4毫米长，0.4毫米宽，0.2毫米高。在制造过程时，一块普通的8英寸硅晶圆片可以制造出数千至一万多个压力计芯片，使得本压力计芯片的制造成本非常的低。然而，以上的尺寸数据仅为本发明的一种示例，而非对本发明保护范围的限制。本领域的技术人员完全可以根据其具体需求来对该尺寸进行修改。
在第一实施例中，由于压阻测量元件23之间是依靠PN结隔离的，其截流 电流与温度之间的关系为指数关系，当温度提高至150摄氏度时，PN结隔离将会失效，所以本实施例只适宜于150摄氏度以下的温度中应用。
参照图4、图5、图6、以及图7，按照本发明提供一种压力计芯片中的第二实施例。本实施例的工作原理、大小尺寸、外置电路等均与第一实施例相同，唯在本实施例中的基板6是采用绝缘体上硅结构，包括相互连接的衬底1、器件层2、以及位于衬底1与器件层2之间的氧化硅层4。该氧化硅层4也被称为氧化硅埋层，其用于电隔离衬底1和器件层2。与第一实施例不同，本实施例的压阻测量元件23是设置在器件层2，并且每个压阻测量元件23的四周侧壁均形成有氧化硅层4。因此，每个压阻测量元件的上下四周均有氧化硅层4进行隔离，不但可以防止压阻测量元件23之间的电串扰，同时亦使得本压力计芯片可以在高达250摄氏度的高温中工作，不受第一实施例中的PN结隔离在高温时失效所限制。此外，位于压阻测量元件23两端及U形拐弯处的A类浓掺杂区9，目的是要局部提高压阻测量元件23的掺杂浓度，形成高导电区域，其作用与第一实施例所表述的相同。但由于在本实施例中，压阻测量元件23本身就是利用器件层2的单晶硅材料所形成的电阻，因此所述A类浓掺杂区9，其掺杂类型与器件层2的必须相同。在本实施例中，器件层2的厚度约为2微米而氧化硅层4的厚度约为1微米。然而，以上的尺寸数据仅为本发明的一种示例，而非对本发明保护范围的限制。本领域的技术人员完全可以根据其具体需求来对该尺寸进行修改。
图9展示了本压力计的示意图，适用于上述压力计芯片中的第一和第二实施例。其中，压力计芯片31被安装在压力计腔体33内。所述腔体由金属制成，内部填充有电绝缘液体37，所述压力计芯片31浸入在所述电绝缘液体37中。在一种实施例中，所述腔体33上还设置有金属膜片38，所述电绝缘液体37以及所述压力计芯片31密封于所述腔体33之内。所述金属膜片38与外界压力39相连，并将所述外界压力39传递到所述电绝缘液体37当中。优选地，所述金属膜片38设计为波纹金属膜片，其自身抗压性极小，令所述外界压力39几 乎全部通过所述电绝缘液体37传递到所述压力计芯片31上。优选地，所述压力计芯片31与所述腔体33的连接点相对较少，例如，所述压力计芯片31只通过一个边甚至一个点的芯片粘接胶32来与所述腔体33相连接，且芯片粘接胶32属柔性，从而在受到所述电绝缘液体37传递过来的所述外界压力39时，所述压力计芯片31被均匀压缩并且能够自由的产生形变。这种柔性安装同时亦避免了所述压力计芯片31可能受到所述腔体33因外力或温度引致的形变带来的影响。
此外，所述压力计芯片31内的基板6与盖板3之间形成的空腔处于真空状态，所以本压力计所测量的为绝对压力。在一种实施例中，所述压力计芯片31上的所述金属触点8通过焊线34连接到金属柱体35上，并被带出所述压力计腔体33之外，与外面电路相连接。所述金属柱体35与所述压力计腔体33之间被密封的绝缘体36电隔离。
接下来是对所述压力计芯片31以及所述压阻测量元件23所沿的晶体方向进行进一步的描述。首先，单晶硅的电阻率是与掺杂离子的类型和掺杂离子的浓度息息相关，其中，掺杂离子的类型包括P型或者N型。而由于单晶硅压阻效应呈各向异性，晶体方向的不同也会导致电阻率随应力变化幅度的不同。导致电阻率变化幅度的各项因素在Y.Kanda在IEEE电子器件期刊中(IEEE Transactions on Electron Devices，vol.ED-29，no.1，pp.64-70，1982.)所发表的《对硅的压阻系数的图解》一文中有详细的解释。其中，电阻率变化与应力及压阻系数的关系为
Δρ11/ρ＝π11σ11+π12σ22+π13σ33+π14σ23+π15σ13+π16σ12       (1)
当中，1、2、3分别为直角坐标的3个垂直方向；Δρ11/ρ为电场与电流均沿1方向时的电阻率变化；σ11、σ22、σ33分别为沿1、2、3方向的正应力；σ23、σ13、σ12分别为沿2-3、1-3、1-2方向的剪应力；而π11、π12、π13、π14、π15、π16分别为表述电阻率变化与各种应力之间的关系的压阻系数。假设所述压力计芯片31之所述基板6之顶面为垂直于3方向的1-2平面，而所述压阻测量元件23就是 位于该平面之上。参照图2及图5，首先，4个压阻测量元件23的主要(非浓掺杂)部分皆面向所述真空密封空腔，故其所在的1-2平面是一个自由面，因此所有与3方向有关的应力，亦即σ13、σ23、σ33，皆为零。再者，所述压力计芯片31被安装在所述压力计腔体33内受均匀压缩并且能够自由的产生形变。在此情况下，所述压力计芯片31的上下四周各表面的正应力与所述外界压力39相当，而各剪应力则几乎为零。及至所述压阻测量元件23所在的面对所述密封空腔的1-2平面时，σ12依旧约为零，而σ11及σ22彼此相当并与所述外界压力39的值，设为P，接近线性关系，唯σ11和σ22均小于P。优选地，所述基板6的厚度应比所述密封空腔的宽度大，不然的话，所述基板6会因所述外界压力39而向所述密封空腔凹陷，其结果为σ11及σ22将更小于P，压力计的灵敏度亦会因此而下降，但仍可用。综合以上各点，当公式(1)应用于所述压阻测量元件23的主要(非浓掺杂)部分时可约简化为
Δρ11/ρ≈(π11+π12)kP           (2)
k是一个通常小于1的常数。
由于电阻与电阻率成正比，从公式(2)得知，所述压阻测量元件23的电阻变化与所述外界压力39接近线性关系，而灵敏度大致上则与π11+π12压阻系数成正比。但由于单晶硅的压阻效应呈各向异性，π11+π12的大小会因为1-2平面及1方向的取向而改变。例如当1-2平面为硅{110}晶体平面时，参照图10，当1方向从0度旋转至360度时，π11+π12压阻系数就会发生如图10所示的变化。所以在硅{110}晶体平面上，不论是P型硅还是N型硅，π11+π12于<110>方向时达到最大值，而于与<110>方向垂直的<100>方向时达到最小值。
如前文有关压力计芯片31中的第一和第二实施例所述，优选地，所述两对压阻测量元件R1、R3与R2、R4可沿不同的晶体方向布置，目的是当所述压力计芯片31受被检测的所述外界压力39均匀压缩并且能够自由的产生形变时，要令所述两对压阻测量元件R1、R3与R2、R4的压阻效应，亦即π11+π12压阻系数差别最大。如是，就会产生不一样的电阻变化，经过惠斯登电桥处理后形 成电压输出。优选地，在第一实施例中的所述基板6以及在第二实施例中的所述衬底1和所述器件层2均是设置在{110}晶体平面上的单晶硅，而所述两对压阻测量元件所沿的方向分别为<100>和<110>这两个相互垂直的晶体方向。参照俯视图3及图7，两个压阻测量元件R1与R3的非浓掺杂区部分均沿<100>方向，故它们的电阻变化相同；同时，两个压阻测量元件R2与R4的非浓掺杂区部分均沿<110>方向，故它们的电阻变化也相同但与R1及R3的差异最大。此外，由于单晶硅受外力而产生形变时也呈各向异性，为了使所述压力计芯片31能够均匀压缩，优选地，所述盖板3也是设置在{110}晶体平面上的单晶硅，所述盖板3与所述基板6在键合面上盖板3与基板6相对应的每一条边所沿的晶体方向是一致的。或者盖板3与所述衬底1和所述器件层2相应的每一条边所沿的晶体方向一致。当然，技术人员也可以根据Y.Kanda的描述另行优选所述基板6或所述器件层2所在的晶体面以及所述压阻测量元件23的布置方向。
接下来，参照图11至图14对本压力计芯片的第一种制造工艺进行进一步的描述。本工艺适用于本压力计芯片中第一种实施例所展示的结构，所述基板6之原材料为单晶硅晶圆片，之后再作包括以下的加工步骤：
第一步，对单晶硅晶圆片进行高温氧化处理，在其顶面及底面形成一层氧化硅层4，或者利用化学气相淀积法(Chemical Vapor Deposition)淀积一层氧化硅层4。
第二步，在所述单晶硅晶圆片的顶面上涂覆光刻胶，之后按照特定图案对所述顶面进行曝光，并用显影剂将已曝光的光刻胶去除，及将未经曝光的光刻胶烘烤。这样被曝光的图案就会显现出来。再用离子注入技术，并通过能量控制，使离子有足够能量穿越未被光刻胶覆盖的顶面氧化硅层而注入所述单晶硅晶圆片里，同时，在被光刻胶覆盖的地方，离子却被挡于光刻胶层当中。这样就可以对所述单晶硅晶圆片的基板6进行局部掺杂，形成与所述基板6类型相反的所述压阻测量元件23。其中，如果基板6为P型，则使用N型掺杂离子，例如磷；如果基板6为N型，则使用P型掺杂离子，例如硼。最后将所有光刻 胶去除。除了上述离子注入技术之外，亦可以使用杂质高温扩散技术来进行局部掺杂。
第三步，通过光刻及离子注入，对所述单晶硅晶圆片的顶面进行局部浓掺杂，形成与所述压阻测量元件23类型相同的所述A类浓掺杂区9，从而降低该区域的电阻值，形成高导电区域。其中，如果基板6为P型，则使用N型掺杂离子，例如磷；如果基板6为N型，则使用P型掺杂离子，例如硼。
第四步，通过光刻及离子注入，对所述单晶硅晶圆片的顶面进行局部浓掺杂，形成与所述基板6类型相同的所述B类浓掺杂区10，从而降低该区域的电阻值，形成高导电区域。其中，如果基板6为P型，则使用P型掺杂离子，例如硼；如果基板6为N型，则使用N型掺杂离子，例如磷。最后，在所述单晶硅晶圆片的顶面及底面从新形成一层氧化硅层4，并将所述各种已引入的掺杂激活。
第五步，利用光刻技术，再用反应离子或等离子干法刻蚀、或氢氟酸腐蚀、对所述单晶硅晶圆片的顶面氧化硅层4进行局部刻蚀，从而在顶面形成多个深至所述基板6中A类浓掺杂区9和B类浓掺杂区10的孔，并在所述孔中及整个硅晶圆片顶面淀积金属，再利用光刻及金属腐蚀，引出所述金属触点8及电极图案。
第六步，将预先有凹陷加工的单晶硅盖板晶圆片与所述单晶硅晶圆片的顶面进行真空键合，形成密封的真空空腔。其中的键合技术可以为硅-硅直接键合、共熔键合、焊烧键合、或阳极键合。
第七步，通过划片，将所述已键合的硅晶圆片分割，形成完整的压力计芯片。
接下来，参照图15至图18对本压力计芯片的第二种制造工艺进行进一步的描述。本工艺适用于本压力计芯片中第二种实施例所展示的结构，所用之原材料为绝缘体上硅晶圆片，包括衬底1、器件层2以及设置在所述衬底与器件 层之间的氧化硅埋层4，之后再作包括以下的加工步骤：
第一步，对绝缘体上硅晶圆片进行高温氧化处理，在其顶面及底面形成一层氧化硅层4，或者利用化学气相淀积法(Chemical Vapor Deposition)淀积一层氧化硅层4。
第二步，在所述绝缘体上硅晶圆片的顶面上涂覆光刻胶，之后按照特定图案对所述顶面进行曝光，并用显影剂将已曝光的光刻胶去除，及将未经曝光的光刻胶烘烤。这样被曝光的图案就会显现出来。再用离子注入技术，并通过能量控制，使离子有足够能量穿越未被光刻胶覆盖的顶面氧化硅层而注入器件层里，同时，在被光刻胶覆盖的地方，离子却被挡于光刻胶层当中。这样就可以对所述绝缘体上硅晶圆片的器件层2进行局部浓掺杂，形成与所述器件层2类型相同的A类浓掺杂区9，从而降低该区域的电阻值，形成高导电区域；其中，如果器件层2为P型，则使用P型掺杂离子，例如硼。如果器件层2为N型，则使用N型掺杂离子，例如磷。最后将所有光刻胶去除。除了上述离子注入技术之外，亦可以使用杂质高温扩散技术来进行局部浓掺杂。
第三步，在所述绝缘体上硅晶圆片的顶面进行光刻，再用反应离子或等离子干法刻蚀、或氢氟酸腐蚀、对顶面氧化硅层4进行局部刻蚀，从而在顶面形成多个深至器件层2的槽11。之后，利用深度反应离子刻蚀或其它干法或湿法刻蚀，进一步将槽11中的器件层2刻蚀至氧化硅埋层4。从而形成多个压阻测量元件23。
第四步，利用高温氧化或化学气相淀积法在所述槽11中生长或淀积一层氧化硅隔离层4，并将所述已引入的浓掺杂激活。至此，压阻测量元件上下四周各方均被氧化硅绝缘层包裹。
第五步，利用光刻技术，再用反应离子或等离子干法刻蚀、或氢氟酸腐蚀、对所述高导电区域的顶面氧化硅层4进行局部刻蚀，从而在顶面形成多个深至所述器件层2中A类浓掺杂区9的孔，并在所述孔中及整个硅晶圆片顶面淀积 金属，再利用光刻及金属腐蚀，引出所述金属触点8及电极图案。
第六步，将预先有凹陷加工的单晶硅盖板晶圆片与所述绝缘体上硅晶圆片的顶面进行真空键合，形成密封的真空空腔。其中的键合技术可以为硅-硅直接键合、共熔键合、焊烧键合、或阳极键合。
第七步，通过划片，将所述已键合的硅晶圆片分割，形成完整的压力计芯片。
其中，所述刻蚀的方法为以下方法中的一种或多种方法：干法刻蚀或湿法刻蚀，所述干法刻蚀包括：硅的深度反应离子、反应离子、以及气态的二氟化氙刻蚀和氧化硅的反应离子、等离子、以及气态的氟化氢刻蚀。
所述用于湿法腐蚀硅层的腐蚀剂为以下腐蚀剂中的一种或多种的组合：氢氧化钾、四甲基氢氧化铵、或乙二胺邻苯二酚腐蚀液。
所述用于湿法腐蚀氧化硅层的腐蚀剂为氢氟酸或缓冲氢氟酸。
本发明的压力计芯片采用一种非薄膜式的新颖结构，将芯片均匀受压时内部所产生的应力，利用单晶硅的压阻效应将之转化为压阻测量元件23的电阻值变化，更利用单晶硅压阻效应的各向异性，优化两对压阻测量元件23所处的晶体面以及所沿的晶体方向，令两对之间的电阻值变化差异达到最大，从而检测高达200MPa的压力。另外，将压阻测量元件23的主要部分设置在真空的空腔中，大大减少了外界环境因素和异物对本压力计芯片的影响，也增强了本压力计的可靠性和检测精准度。在一个实施例中，将每一个压阻测量元件23完全包裹在一层氧化硅层4中，使得每个压阻测量元件23之间相互隔离，这种利用绝缘体的隔离方式也使得本压力计可以在高温环境中进行检测。再者，将压阻测量元件以惠斯登电桥的方式进行电连接能够减少由外界因素导致的共模误差，也降低了温度对压力计检测精准度的影响。而通过采用硅MEMS工艺来制作本压力计芯片，一方面为成熟技术，且成本低廉。而正如上文所提到的，一块普通的8英寸硅晶圆片可以制造数千至一万多个本压力计芯片，从此也可以看出本压力计的制造成本低的特点。
最后应当说明的是，以上实施例仅用以说明本发明的技术方案，而非对本发明保护范围的限制，尽管参照较佳实施例对本发明作了详细地说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或者等同替换，而不脱离本发明技术方案的实质和范围。

Claims (22)

  1. 一种压力计，包括腔体、以及设置在所述腔体内的压力计芯片，所述压力计芯片由单晶硅制成，包括相互连接的基板及盖板，其特征在于：所述盖板上形成有凹陷部，所述凹陷部与所述基板形成一密封空腔，所述基板与所述盖板之间形成有氧化硅层；所述基板上设置有至少两组压阻测量元件，所述压阻测量元件位于所述空腔之内，两组压阻测量元件之间相互垂直，每组所述压阻测量元件沿不同的晶体方向设置。
  2. 如权利要求1所述的压力计，其特征在于：所述密封空腔为真空密封空腔。
  3. 如权利要求1所述的压力计，其特征在于：所述压阻测量元件的末端形成有金属触点。
  4. 如权利要求1所述的压力计，其特征在于：所述压阻测量元件包括多个相互连接的U型弯折部。
  5. 如权利要求1所述的压力计，其特征在于：所述压阻测量元件相互之间以惠斯登电桥方式相电连接。
  6. 如权利要求1所述的压力计，其特征在于：所述基板是设置在{110}晶体平面上的P型硅，所述压阻测量元件是设置在所述基板上的N型掺杂区，一组所述压阻测量元件沿<100>晶体方向布置，另一组所述压阻测量元件沿<110>晶体方向布置。
  7. 如权利要求1所述的压力计，其特征在于：所述基板是设置在{110}晶体平面上的N型硅，所述压阻测量元件是设置在所述基板上的P型掺杂区，一组所述压阻测量元件沿<100>晶体方向布置，另一组所述压阻测量元件沿<110>晶体方向布置。
  8. 如权利要求6或7所述的压力计，其特征在于：所述盖板以及所述基板为长方体，所述盖板是设置在{110}晶体平面上的单晶硅；在所述盖板与所述基板的键合面上，所述盖板的每一条边与所述基板相对应的每一条边所沿的晶体 方向一致。
  9. 如权利要求1所述的压力计，其特征在于：所述压力计芯片基板为绝缘体上硅结构，包括衬底、器件层以及设置在所述衬底与器件层之间的氧化硅埋层；所述压阻测量元件设置于所述器件层上。
  10. 如权利要求9所述的压力计，其特征在于：所述压阻测量元件的顶端、底端及侧壁上分别形成有氧化硅隔离层。
  11. 如权利要求9所述的压力计，其特征在于：所述器件层是设置在{110}晶体平面上的P型硅，所述压阻测量元件是设置在所述器件层上的P型硅，一组所述压阻测量元件沿<100>晶体方向布置，另一组所述压阻测量元件沿<110>晶体方向布置。
  12. 如权利要求9所述的压力计，其特征在于：所述器件层是设置在{110}晶体平面上的N型硅，所述压阻测量元件是设置在所述器件层上的N型硅，一组所述压阻测量元件沿<100>晶体方向布置，另一组所述压阻测量元件沿<110>晶体方向布置。
  13. 如权利要求9所述的压力计，其特征在于：所述基板为长方体，所述衬底是设置在{110}晶体平面上的单晶硅，所述衬底与所述器件层相应的每一条边所沿的晶体方向一致。
  14. 如权利要求9所述的压力计，其特征在于：所述盖板为长方体，所述盖板是设置在{110}晶体平面上的单晶硅，所述盖板与所述器件层相应的每一条边所沿的晶体方向一致。
  15. 如权利要求1所述的压力计，其特征在于：所述腔体由金属制成，所述腔体内填充有电绝缘液体，所述压力计芯片浸入在所述电绝缘液体中。
  16. 如权利要求15所述的压力计，其特征在于：所述压力计上还设置有金属膜片，所述金属膜片将所述电绝缘液体以及所述压力计芯片密封在所述腔体中，外界压力通过所述金属膜片传递至所述压力计芯片上。
  17. 一种压力计芯片的制造工艺，其特征在于：所述制造工艺包括以下步 骤：
    第一步，在单晶硅晶圆片的顶面及底面生长或淀积一层氧化硅层；
    第二步，通过光刻及离子注入，对所述单晶硅晶圆片的顶面进行局部掺杂；形成多个与所述单晶硅晶圆片掺杂类型相反的压阻测量元件；
    第三步，通过光刻及离子注入，对所述单晶硅晶圆片的顶面进行局部浓掺杂；形成与所述单晶硅晶圆片掺杂类型相反的高导电区域；
    第四步，通过光刻及离子注入，对所述单晶硅晶圆片的顶面进行局部浓掺杂；形成与所述单晶硅晶圆片掺杂类型相同的高导电区域。之后再在所述单晶硅晶圆片的顶面及底面生长或淀积一层氧化硅层，并将所述各种已引入的掺杂激活；
    第五步，通过光刻和刻蚀，在所述高导电区域的顶面氧化硅层刻蚀出多个深至所述浓掺杂区的孔；并在所述孔内淀积金属并引出电极；
    第六步，将预先加工有凹陷部的单晶硅盖板晶圆片与所述单晶硅晶圆片的顶面进行键合；
    第七步，通过划片，将所述已键合的硅晶圆片分割，形成完整的压力计芯片。
  18. 一种压力计芯片的制造工艺，其特征在于：所述制造工艺包括以下步骤：
    第一步，在绝缘体上硅晶圆片的顶面及底面生长或淀积一层氧化硅层；
    第二步，通过光刻及离子注入，对所述绝缘体上硅晶圆片的器件层进行局部浓掺杂；形成与所述器件层掺杂类型相同的高导电区域；
    第三步，通过光刻以及刻蚀，在所述器件层上刻蚀出多个深至氧化硅埋层的槽；形成多个压阻测量元件；
    第四步，在所述槽内生长或淀积一层氧化硅层，并将所述已引入的浓掺杂激活；
    第五步，通过光刻和刻蚀，在所述高导电区域的顶面氧化硅层刻蚀出多 个深至所述器件层中浓掺杂区的孔；并在所述孔内淀积金属并引出电极；
    第六步，将预先加工有凹陷部的单晶硅盖板晶圆片与所述绝缘体上硅晶圆片的顶面进行键合；
    第七步，通过划片，将所述已键合的硅晶圆片分割，形成完整的压力计芯片。
  19. 根据权利要求17或18所述的压力计芯片的制造工艺，其特征在于：对所述盖板的凹陷部的加工步骤包括：通过光刻和刻蚀，在所述盖板上刻蚀出凹陷部。
  20. 根据权利要求17或18所述的压力计芯片的制造工艺，其特征在于：所述刻蚀的方法为以下方法中的一种或多种方法：干法刻蚀或湿法刻蚀，所述干法刻蚀包括：硅的深度反应离子、反应离子、以及气态的二氟化氙刻蚀和氧化硅的反应离子、等离子、以及气态的氟化氢刻蚀。
  21. 根据权利要求17或18所述的压力计芯片的制造工艺，其特征在于：所述用于湿法腐蚀硅层的腐蚀剂为以下腐蚀剂中的一种或多种的组合：氢氧化钾、四甲基氢氧化铵、或乙二胺邻苯二酚腐蚀液。
  22. 根据权利要求17或18所述的压力计芯片的制造工艺，其特征在于：所述用于湿法腐蚀氧化硅层的腐蚀剂为以下腐蚀剂中的一种或多种的组合：氢氟酸以及缓冲氢氟酸。
PCT/CN2017/000198 2016-03-04 2017-02-28 一种压力计芯片及其制造工艺 WO2017148215A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/073,732 US11255740B2 (en) 2016-03-04 2017-02-28 Pressure gauge chip and manufacturing process thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610124330.0 2016-03-04
CN201610124330.0A CN105784214B (zh) 2016-03-04 2016-03-04 一种压力计芯片

Publications (1)

Publication Number Publication Date
WO2017148215A1 true WO2017148215A1 (zh) 2017-09-08

Family

ID=56386912

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/000198 WO2017148215A1 (zh) 2016-03-04 2017-02-28 一种压力计芯片及其制造工艺

Country Status (3)

Country Link
US (1) US11255740B2 (zh)
CN (1) CN105784214B (zh)
WO (1) WO2017148215A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112834106A (zh) * 2021-01-15 2021-05-25 长芯科技(上海)有限公司 压阻式表压压力传感器的制造方法
CN114136510A (zh) * 2021-12-07 2022-03-04 华东光电集成器件研究所 一种基于soi敏感芯片的小型压力传感器
CN114136511A (zh) * 2021-12-07 2022-03-04 华东光电集成器件研究所 一种电缆线系soi压阻压力传感器

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105784214B (zh) 2016-03-04 2019-05-28 中国科学院地质与地球物理研究所 一种压力计芯片
CN106124117B (zh) * 2016-06-14 2019-04-23 中国科学院地质与地球物理研究所 一种双空腔压力计芯片及其制造工艺
CN106525295A (zh) * 2016-11-11 2017-03-22 中国电子科技集团公司第四十八研究所 一种硅压阻式芯体
IT201700019426A1 (it) * 2017-02-21 2018-08-21 St Microelectronics Srl Sensore di forza/pressione microelettromeccanico scalabile piezoresistivo di tipo bulk
WO2020124477A1 (zh) * 2018-12-20 2020-06-25 深圳纽迪瑞科技开发有限公司 压力感应装置、压力感应方法及电子终端
CN110567619A (zh) * 2019-09-20 2019-12-13 南京皮埃尔智能传感技术有限公司 一种高灵敏度压力传感器及其制作方法
CN111504526B (zh) * 2020-05-29 2021-05-28 西安交通大学 具有应力集中结构的压阻式压力传感器芯片及其制备方法
US11650110B2 (en) 2020-11-04 2023-05-16 Honeywell International Inc. Rosette piezo-resistive gauge circuit for thermally compensated measurement of full stress tensor
CN112903149A (zh) * 2021-01-22 2021-06-04 上海芯物科技有限公司 一种压力传感器及其制作方法
CN113447171B (zh) * 2021-06-02 2023-01-10 中国科学院地质与地球物理研究所 一种压力计芯片及其制造工艺
CN113465794B (zh) * 2021-06-02 2023-01-10 中国科学院地质与地球物理研究所 一种双空腔压力计芯片及其制造工艺

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101271028A (zh) * 2008-04-18 2008-09-24 中国科学院上海微系统与信息技术研究所 基于硅硅键合和绝缘层上硅的压力传感器芯片及方法
US8109149B2 (en) * 2004-11-17 2012-02-07 Lawrence Livermore National Security, Llc Contact stress sensor
CN102359836A (zh) * 2011-08-09 2012-02-22 浙江双友物流器械股份有限公司 一种mems压阻式拉压力芯片及传感器的制作方法
CN105203234A (zh) * 2015-09-18 2015-12-30 中国科学院电子学研究所 谐振式压力传感器
CN105241600A (zh) * 2015-08-17 2016-01-13 中国科学院地质与地球物理研究所 一种mems压力计芯片及其制造工艺
CN105784214A (zh) * 2016-03-04 2016-07-20 中国科学院地质与地球物理研究所 一种压力计芯片及其制造工艺

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3617780A (en) 1967-10-26 1971-11-02 Hewlett Packard Co Piezoelectric transducer and method for mounting same
FR2638524B1 (fr) 1988-10-27 1994-10-28 Schlumberger Prospection Capteur de pression utilisable dans les puits de petrole
JP2001044449A (ja) * 1999-07-27 2001-02-16 Nikon Corp 力検出センサ及び力検出センサの製造方法
JP3891037B2 (ja) * 2002-05-21 2007-03-07 株式会社デンソー 半導体圧力センサおよび半導体圧力センサ用の半導体ウェハ
US7430920B2 (en) * 2005-12-16 2008-10-07 Hitachi, Ltd. Apparatus for measuring a mechanical quantity
JP5687202B2 (ja) * 2009-11-04 2015-03-18 ローム株式会社 圧力センサおよび圧力センサの製造方法
US7998777B1 (en) * 2010-12-15 2011-08-16 General Electric Company Method for fabricating a sensor
CN102998037B (zh) * 2012-09-15 2014-11-12 华东光电集成器件研究所 介质隔离压阻式压力传感器及其制备方法
WO2015194105A1 (ja) * 2014-06-17 2015-12-23 株式会社鷺宮製作所 センサユニット、および、それを備える圧力検出装置
CN104266781A (zh) * 2014-10-09 2015-01-07 苏州敏芯微电子技术有限公司 压阻式压力传感器及其制造方法
US10288498B2 (en) * 2015-04-06 2019-05-14 Denso Corporation Force detection device
CN105151231A (zh) * 2015-10-29 2015-12-16 威海中复西港船艇有限公司 一种锚缆座

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8109149B2 (en) * 2004-11-17 2012-02-07 Lawrence Livermore National Security, Llc Contact stress sensor
CN101271028A (zh) * 2008-04-18 2008-09-24 中国科学院上海微系统与信息技术研究所 基于硅硅键合和绝缘层上硅的压力传感器芯片及方法
CN102359836A (zh) * 2011-08-09 2012-02-22 浙江双友物流器械股份有限公司 一种mems压阻式拉压力芯片及传感器的制作方法
CN105241600A (zh) * 2015-08-17 2016-01-13 中国科学院地质与地球物理研究所 一种mems压力计芯片及其制造工艺
CN105203234A (zh) * 2015-09-18 2015-12-30 中国科学院电子学研究所 谐振式压力传感器
CN105784214A (zh) * 2016-03-04 2016-07-20 中国科学院地质与地球物理研究所 一种压力计芯片及其制造工艺

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112834106A (zh) * 2021-01-15 2021-05-25 长芯科技(上海)有限公司 压阻式表压压力传感器的制造方法
CN114136510A (zh) * 2021-12-07 2022-03-04 华东光电集成器件研究所 一种基于soi敏感芯片的小型压力传感器
CN114136511A (zh) * 2021-12-07 2022-03-04 华东光电集成器件研究所 一种电缆线系soi压阻压力传感器
CN114136510B (zh) * 2021-12-07 2024-01-23 华东光电集成器件研究所 一种基于soi敏感芯片的小型压力传感器
CN114136511B (zh) * 2021-12-07 2024-03-01 华东光电集成器件研究所 一种电缆线系soi压阻压力传感器

Also Published As

Publication number Publication date
CN105784214B (zh) 2019-05-28
US11255740B2 (en) 2022-02-22
US20190113411A1 (en) 2019-04-18
CN105784214A (zh) 2016-07-20

Similar Documents

Publication Publication Date Title
US11226251B2 (en) Method of making a dual-cavity pressure sensor die
WO2017148215A1 (zh) 一种压力计芯片及其制造工艺
WO2017028465A1 (zh) 一种mems压力计芯片及其制造工艺
WO2017028466A1 (zh) 一种mems应变计芯片及其制造工艺
CN104040315B (zh) 流体压力传感器以及测量探针
CN103983395B (zh) 一种微压力传感器及其制备与检测方法
CN112284607B (zh) 一种十字岛耐高温耐腐蚀压力传感器芯片及制备方法
Zeng et al. MEMS pressure sensors for high-temperature high-pressure downhole applications
CN112284605B (zh) 一种十字岛梁膜高温微压传感器芯片及制备方法
CN113465794B (zh) 一种双空腔压力计芯片及其制造工艺
CN1182587C (zh) 耐高温固态压阻式平膜力敏芯片及其制作方法
Du et al. Poly-SiC capacitive pressure sensors made by wafer bonding
Li et al. Ultra-small high‐temperature pressure sensor chips fabricated in single‐layer (111) SOI wafers
CN111122904B (zh) 一种三明治加速度计微结构制作方法
CN113447171B (zh) 一种压力计芯片及其制造工艺
JP2004325361A (ja) 静電容量型圧力センサ及びその製造方法
CN112284606B (zh) 一种t型交叉梁十字岛膜压力传感器芯片及制备方法
Zhang et al. A Si-Glass based pressure sensor with a single piezoresistive element for harsh environment applications
CN113063529A (zh) 一种微机械谐振式压力传感器及制造方法
Lee et al. Fabrication of high-temperature silicon pressure sensor using SDB-SOI technology
Wang et al. Micro machining process of high temperature pressure sensor gauge chip based on SIMOX SOI wafer
Basov et al. Investigation of High Sensitivity Piezoresistive Pressure Sensors for-0.5…+ 0.5 kPa
Basov et al. Investigation of High Sensitivity Piezoresistive Pressure Sensors for-0.5…+ 0
CN116539211A (zh) 基于梁膜敏感和体压缩敏感的谐振式高压传感器
Prigodskiy Investigation of High Sensitivity Piezoresistive Pressure Sensors for-0.5…+ 0.5 kPa

Legal Events

Date Code Title Description
NENP Non-entry into the national phase

Ref country code: DE

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17759066

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 17759066

Country of ref document: EP

Kind code of ref document: A1