WO2017143857A1 - 数据传输的方法、扩展装置、外围设备及系统 - Google Patents

数据传输的方法、扩展装置、外围设备及系统 Download PDF

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Publication number
WO2017143857A1
WO2017143857A1 PCT/CN2016/113065 CN2016113065W WO2017143857A1 WO 2017143857 A1 WO2017143857 A1 WO 2017143857A1 CN 2016113065 W CN2016113065 W CN 2016113065W WO 2017143857 A1 WO2017143857 A1 WO 2017143857A1
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address
read
readout
intention information
information
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PCT/CN2016/113065
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English (en)
French (fr)
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许松清
邱忠英
潘峰
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广州视源电子科技股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)

Definitions

  • the present invention relates to the field of communications technologies, and in particular, to a data transmission method, an extension device, a peripheral device, and a system.
  • I2C Inter-Integrated Circuit
  • PHILIPS complementary metal-oxide-semiconductor
  • a bus standard is a special form of synchronous communication.
  • the I2C bus is divided into a master mode and a slave mode.
  • the master mode initializes the data transmission of the bus and generates a clock signal that allows transmission.
  • the slave mode follows the request initiated by the master mode. Data is written or read.
  • the main control device and the peripheral device need to communicate through the I2C bus, it is first necessary to determine whether the main control device has the main I2C function, whether the peripheral device has the slave I2C function, and when the master control device has the main I2C function, and the periphery
  • the master device and the peripheral device can communicate through the I2C bus; and when the master device has the main I2C function and the peripheral device does not have the slave I2C function, the extension device is usually set to be non- The bridging mode is connected with the peripheral device, and the peripheral device is extended from the I2C function.
  • the main control device caches the data to be transmitted by the expansion device, and after the main control device ends communication, the expansion device caches the device.
  • the data is processed and transmitted to the peripheral device, thereby realizing the purpose of communication between the master device and the peripheral device through the I2C bus.
  • FIG. 1 is a timing diagram of I2C write-only timing in the I2C communication protocol provided by the prior art
  • FIG. 2 is an I2C read-only in the I2C communication protocol provided by the prior art.
  • the timing diagram of the timing is based on the I2C write-only timing and the I2C read-only timing in the figure.
  • the I2C communication is one byte by one byte in chronological order.
  • the peripheral device with the I2C communication function can recognize the received register address, and then start the byte-by-byte write data or read out with the register address as a start address.
  • Data for a peripheral device that does not have the I2C function, the data in the I2C timing received from the master device cannot be recognized, that is, the register address cannot be recognized, and the transmitted byte data cannot be written or read.
  • the data processed by the device is used to implement I2C communication, but since the complete one-time communication is extended and buffered and processed and then completely transmitted to the peripheral device, it takes too long, and when the master device and the peripheral device When a large amount of data needs to be transferred between devices, the data transmission efficiency is degraded due to the limited resources of the expansion module.
  • the embodiment of the invention provides a data transmission method, an extension device, a peripheral device and a system, which can implement I2C communication and improve data transmission efficiency.
  • An embodiment of the present invention provides, in an aspect, a data transmission method, including:
  • the write address information includes a write identifier and a device address
  • the method for data transmission further includes a write operation, specifically:
  • the receiving intention information includes a received signal and a first interrupt signal
  • the receiving the intent information is sent to the peripheral device corresponding to the device address, so that the peripheral device prepares to receive the register address according to the receiving intention information, specifically:
  • the method for data transmission further includes a read operation, specifically:
  • the read address information includes a read identifier and the device address
  • the readout identifier Generating readout intention information according to the readout identifier, and transmitting the readout intention information to a peripheral device corresponding to the device address, so that the peripheral device returns from the readout address according to the readout intention information
  • Read data read in the memory the read address is the register address;
  • the method for data transmission further includes a read operation, specifically:
  • the read address information includes a read identifier and the device address
  • the readout identifier Generating readout intention information according to the readout identifier, and transmitting the readout intention information to a peripheral device corresponding to the device address, so that the peripheral device returns from the readout address according to the readout intention information
  • Read data read in the memory the read address is the register address plus the byte length of the write data
  • the readout intention information further includes a readout signal and a second interrupt signal
  • the method for data transmission further includes:
  • the readout intention information is generated again, and the readout intention information is transmitted to the peripheral device, so that the peripheral device according to the readout intention
  • the interrupt signal in the message responds to the interrupt, identifies the read signal in the read intention information, and returns the read data read in the memory corresponding to the next read address when the recognition is successful; wherein, the next The read address is the last read address plus one.
  • the method for data transmission further includes:
  • the stop intention information includes a stop signal and a third interrupt signal
  • an embodiment of the present invention provides a data transmission method, including:
  • reception intention information transmitted by the extension device wherein the reception intention information is generated by the extension device according to a write identifier of the write address information received from the master device through the I2C interface, and is Said expansion device is addressed and transmitted according to the device address of the write address information;
  • the register address is that the extension device passes the I2C interface from the Received from the master device.
  • the method for data transmission further includes:
  • the write data forwarded by the extension device is received byte by byte in a pipeline manner, and the write data is written byte by byte into the corresponding memory starting from the received register address as a start address.
  • the receiving intention information includes a received signal and a first interrupt signal
  • the method for data transmission further includes:
  • the readout intention information is read by the extension device according to readout address information received from the master device through the I2C interface Generating the identifier, and is addressed by the extension device according to the device address in the read address information;
  • the extension device Returning the read data read from the memory corresponding to the read address to the extension device according to the read intention information, so that the extension device forwards the read data to the The master device; the read address is the register address.
  • the method for data transmission further includes:
  • the extension device Returning the read data read from the memory corresponding to the read address to the extension device according to the read intention information, so that the extension device forwards the read data to the The master device; the read address is the register address plus the byte length of the write data.
  • the readout intention information further includes a readout signal and a second interrupt signal
  • the method for data transmission further includes:
  • the readout intention information received again is generated again by the extension device when receiving the returned readout data;
  • the method for data transmission further includes:
  • the stop intention information is generated by the extension device according to stop information received from the master device through the I2C interface, the stop intention information includes stopping Signal and third interrupt signal;
  • the stop signal in the stop intention information is identified according to the third interrupt signal response interrupt in the stop intention information, and the current operation is stopped when the recognition is successful.
  • the embodiment of the present invention provides an extension device for data transmission, including:
  • Writing to the address receiving module configured to receive, by using an I2C interface, write address information sent by the master control device; the write address information includes a write identifier and a device address;
  • Receiving an intent generating module configured to generate receiving intent information according to the write identifier, and send the receiving intent information to a peripheral device corresponding to the device address, so that the peripheral device is ready to receive according to the receiving intent information Register address
  • An address forwarding module configured to receive, by using the I2C interface, a register address sent by the master device, and forward the register address to the peripheral device, so that the peripheral device starts with the received register address
  • the start address is ready for a write operation or a read operation.
  • the expansion device of the data transmission further includes:
  • a data forwarding module configured to receive, by the I2C interface, a byte-by-byte manner by the host control device in a pipeline manner Writing data and forwarding the write data byte by byte to the peripheral device for the peripheral device to byte by byte from the received register address as a starting address Write to the corresponding memory.
  • the expansion device of the data transmission further includes:
  • a first read address receiving module configured to receive read address information sent by the master device by using the I2C interface; the read address information includes a read identifier and the device address;
  • a first readout intention generating module configured to generate readout intention information according to the readout identifier, and send the readout intention information to a peripheral device corresponding to the device address, so that the peripheral device according to the The read intention information returns read data read from the memory corresponding to the read address; the read address is the register address plus the byte length of the write data.
  • the first read data forwarding module is configured to receive the read data returned by the peripheral device, and forward the returned read data to the master control device through the I2C interface.
  • the embodiment of the present invention further provides a peripheral device for data transmission, including:
  • Receiving an intent module configured to receive receiving intent information sent by the extension device, wherein the receiving intent information is generated by the extension device according to a write identifier of the write address information received from the master device through the I2C interface And being addressed and transmitted by the extension device according to the device address of the write address information;
  • Preparing a receiving module configured to prepare to receive a register address according to the receiving intention information
  • a receiving address module configured to receive a register address forwarded by the extension device, and prepare a write operation or a read operation with the received register address as a start address; the register address is a pass by the expansion device
  • the I2C interface is received from the master device.
  • the data transmission peripheral device further includes:
  • a writing module configured to receive the write data forwarded by the extension device byte by byte in a pipeline manner, and write the write data byte by byte starting from a received register address as a start address Corresponding in memory.
  • the peripheral device for data transmission further includes:
  • a first readout intent module configured to receive readout intent information sent by the extension device, wherein the readout intent information is received by the extension device from the master device according to the I2C interface And the read identifier in the read address information is generated, and is sent by the extension device according to the device address in the read address information;
  • a first readout return module configured to return, according to the read intention information, read data read from a memory corresponding to the read address to the expansion device, so that the expansion device passes the I2C interface
  • the read data is forwarded to the master device; the read address is the register address plus the byte length of the write data.
  • the embodiment of the present invention further provides a system for data transmission, the system comprising a main control device, an expansion device and at least one peripheral device; wherein the expansion device is an extension device for data transmission; the periphery The device is a peripheral device for data transmission as described above;
  • the master device is connected to the extension device through an I2C interface; the extension device is connected to the peripheral device.
  • the method, the extension device, the peripheral device and the system for data transmission provided by the invention have the following beneficial effects:
  • the invention provides a data transmission method, an extension device, a peripheral device and a system, and the extension device can receive and recognize the write address information sent by the master control device through the I2C interface; the extension device writes according to the write address information.
  • the input identifier generates the reception intent information and sends it to the peripheral device corresponding to the device address, the peripheral device prepares to receive the register address by identifying the reception intention information; then, the extension device receives the identifier through the I2C interface
  • the data sent by the master device cannot be identified, and the extension device provided by the present invention not only needs to perform the data forwarding in the subsequent step by notifying the peripheral device of its specific register address.
  • the peripheral device can perform the write operation or the read operation according to the address, realize the I2C communication between the master device and the peripheral device that does not specifically expand the I2C function, and the expansion device does not need to receive a complete time series data.
  • it is packaged and transmitted to the peripheral device, it is not limited to the memory space of the expansion device, and the data transmission efficiency is improved.
  • FIG. 1 is a timing diagram of I2C write-only timing in an I2C communication protocol provided by the prior art
  • FIG. 2 is a timing diagram of I2C read-only timing in an I2C communication protocol provided by the prior art
  • FIG. 3 is a schematic flow chart of an embodiment of a method for data transmission provided by the present invention.
  • FIG. 4 is a schematic flow chart of another embodiment of a method for data transmission provided by the present invention.
  • FIG. 5 is a schematic structural diagram of an embodiment of an extension device for data transmission provided by the present invention.
  • FIG. 6 is a schematic structural diagram of an embodiment of a peripheral device for data transmission provided by the present invention.
  • FIG. 7 is a schematic structural diagram of an embodiment of a system for data transmission provided by the present invention.
  • FIG. 8 is a flow chart showing an embodiment of a communication process of a write-only operation of the data transmission method provided by the present invention.
  • FIG. 9 is a flow chart showing an embodiment of a communication process of a read-only operation of the data transmission method provided by the present invention.
  • FIG. 3 is a schematic flowchart diagram of an embodiment of a data transmission method provided by the present invention, which is performed by an extension device, and the expansion device may be an MCU installed outside the peripheral device for expanding the I2C function ( MicrocontrollerUnit, micro control unit, and connected to the master device through the I2C interface, the method includes the following steps:
  • S11 receiving, by using an I2C interface, write address information sent by the master control device;
  • the write address information includes a write identifier and a device address;
  • S13 Receive, by using the I2C interface, a register address sent by the master device, and forward the register address to the peripheral device, so that the peripheral device prepares with the received register address as a starting address. Write operation or read operation.
  • the device address devive address and the write flag W following the device address devive address as shown in FIG. 1 and FIG. 2 are the device address and write address of the address information in the embodiment of the present invention.
  • the identifier when the extension device MCU receives the write address information sent by the master device through the I2C interface, generates a reception intention information, such as setting the state of the I/O port, and the extension device MCU sends it through the I/O port.
  • the peripheral device is notified that the next received byte data is a register address, and the peripheral device receives the byte data as a register address for performing a write operation or a read operation, that is, the expansion device in the subsequent step Only need to forward the data in real time, the peripheral device can realize the write operation or the read operation according to the address, realize the I2C communication between the master device and the peripheral device that does not specifically expand the I2C function, and the extension device does not need to receive the When a complete time series data is packaged and transmitted to the peripheral device, it is not limited to the memory space of the expansion device, and the data transmission efficiency is improved.
  • the write operation performed in the subsequent step in the embodiment of the present invention is as follows:
  • the master control device transmits data
  • the extension device MCU forwards each received word data to the peripheral device
  • the write operation of the I2C communication performed between the three is one byte by one byte.
  • Write the write data into the memory the write operation of the pipeline mode is efficient in the write data transfer process, saves the transmission time, and can improve the efficiency of data writing.
  • the master control device and the extension device MCU in this embodiment
  • the connection is through the I2C interface
  • the transmission line is the I2C bus
  • the communication rate is 100 kbit/s. Accordingly, the transmission rate of the write data or the read data between the extension device MCU and the external conversion device should be greater than or equal to 100 kbit/s. To ensure that only one byte of data exists in the memory at the moment when the extension device MCU transmits data, the transmission efficiency is improved.
  • the receiving intention information includes a received signal and a first interrupt signal
  • the receiving the intent information is sent to the peripheral device corresponding to the device address, so that the peripheral device prepares to receive the register address according to the receiving intention information, specifically:
  • the peripheral device can quickly and in real time know the intention of the master device by identifying the intent information sent by the extension device, that is, the content and the object of the I2C communication are to be performed next, so that the peripheral device can perform the I2C communication.
  • the receiving intention information includes a receiving signal and a first interrupt signal.
  • the receiving signal is configured as SO
  • the first interrupt signal is generated by the expansion device MCU to trigger the interrupt to generate a first interrupt signal INT1, and the received signal SO passes through the expansion device.
  • the I/O interface of the MCU is sent to the I/O interface of the peripheral device, and the first interrupt signal INT1 is sent to the external interrupt interface of the peripheral device through the I/O interface of the expansion device, and the peripheral device receives the external interrupt signal, that is, the first When the interrupt signal INT1 is interrupted, the interrupt service routine is entered to identify the specific state of the I/O interface.
  • the peripheral device prepares to receive the register address, that is, notifies the peripheral device.
  • the next received byte data is the register address. In this embodiment, the register address length is 1 byte.
  • the read operation performed in the subsequent embodiment of the present invention is specifically:
  • the read address information includes a read identifier and the device address
  • the readout identifier Generating readout intention information according to the readout identifier, and transmitting the readout intention information to a peripheral device corresponding to the device address, so that the peripheral device returns from the readout address according to the readout intention information
  • Read data read in the memory the read address is the register address;
  • the embodiment of the present invention may also perform a read operation which is substantially the same as the previous read operation, except that the read address is read.
  • the implementation steps are specifically as follows:
  • the read address information includes a read identifier and the device address
  • the readout identifier Generating readout intention information according to the readout identifier, and transmitting the readout intention information to a peripheral device corresponding to the device address, so that the peripheral device returns from the readout address according to the readout intention information
  • Read data read in the memory the read address is the register address plus the byte length of the write data
  • the readout intention information further includes a readout signal and a second interrupt signal
  • the read signal and the second interrupt signal included in the read intention information are configured in the embodiment that the read signal is S1, and the second interrupt signal is generated by the extension device MCU to generate a second interrupt signal.
  • the receiving signal S1 is sent to the I/O interface of the peripheral device through the I/O interface of the expansion device MCU, and the second interrupt signal INT2 is sent to the external interrupt interface of the peripheral device through the I/O interface of the expansion device, and the peripheral device
  • the interrupt service routine is entered to identify the specific state of the I/O interface.
  • the peripheral device returns to read from the memory corresponding to the read address. Read data, that is, notify the peripheral device to perform the read operation.
  • the method for data transmission further includes:
  • the readout intention information is generated again, and the readout intention information is transmitted to the peripheral device, so that the peripheral device according to the readout intention
  • the interrupt signal in the message responds to the interrupt, identifies the read signal in the read intention information, and returns the read data read in the memory corresponding to the next read address when the recognition is successful; wherein, the next The read address is the last read address plus one.
  • the peripheral device only returns a byte correspondingly when receiving the read signal S1 in the read intention information.
  • the read data is read, and the extension device MCU receives the read data of one byte returned by the peripheral device, and generates the read intention information again and sends it to the peripheral device, so that the read data is transmitted byte by byte.
  • the master device is in compliance with the I2C communication protocol.
  • the method for data transmission further includes:
  • the stop intention information includes a stop signal and a third interrupt signal
  • the stop signal and the third interrupt signal included in the stop intention information are configured in the embodiment that the stop signal is S2, and the third interrupt signal is a third interrupt signal INT3 generated by the expansion device MCU trigger interrupt.
  • the stop signal S2 is sent to the I/O interface of the peripheral device through the I/O interface of the extension device MCU, and the third interrupt signal INT3 is sent to the external interrupt interface of the peripheral device through the I/O interface of the expansion device, and the peripheral device receives the external device.
  • the interrupt signal that is, the third interrupt signal INT3
  • enters the interrupt service routine and identifies the specific state of the I/O interface.
  • the peripheral device stops the current operation, that is, the extension device MCU notifies the peripheral device to stop the current operation, indicating Complete a complete I2C communication between the master device and the peripheral device.
  • the signals represented by the first interrupt signal INT1, the second interrupt signal INT2, and the third interrupt signal INT3 in the above embodiment are the same.
  • the present invention provides a data transmission method, which can receive and recognize the write address information sent by the master device through the I2C interface; the extension device generates the reception intention information according to the write identifier in the write address information, and sends the same.
  • a peripheral device corresponding to the device address the peripheral device preparing to receive a register address by identifying the receiving intention information; then, the extension device receives a register address sent by the master device through the I2C interface, and The register address is forwarded to the peripheral device, and the peripheral device prepares a write operation or a read operation by using the register address as a start address.
  • the data sent by the master device cannot be identified, and the extension device provided by the present invention not only needs to perform the data forwarding in the subsequent step by notifying the peripheral device of its specific register address.
  • the peripheral device can perform the write operation or the read operation according to the address, realize the I2C communication between the master device and the peripheral device that does not specifically expand the I2C function, and the expansion device does not need to receive a complete time series data.
  • it is packaged and transmitted to the peripheral device, it is not limited to the memory space of the expansion device, and the data transmission efficiency is improved.
  • FIG. 4 is a schematic flowchart diagram of another embodiment of a data transmission method provided by the present invention, which is performed by a device disposed in a peripheral device, and the technical effect achieved is the same as that of the previous embodiment. I will not go into details here.
  • the specific implementation steps are as follows:
  • S23 Receive a register address that is sent by the extension device, and prepare for starting with the received register address. a write operation or a read operation; the register address is received by the extension device from the master device via the I2C interface.
  • the write operation performed in the subsequent embodiment of the present invention is as follows:
  • the method for data transmission further includes:
  • the write data forwarded by the extension device is received byte by byte in a pipeline manner, and the write data is written byte by byte into the corresponding memory starting from the received register address as a start address.
  • the receiving intention information includes a received signal and a first interrupt signal
  • the read operation performed in the subsequent step in the embodiment of the present invention is as follows:
  • the readout intention information is read by the extension device according to readout address information received from the master device through the I2C interface Generating the identifier, and is addressed by the extension device according to the device address in the read address information;
  • the extension device Returning the read data read from the memory corresponding to the read address to the extension device according to the read intention information, so that the extension device forwards the read data to the The master device; the read address is the register address.
  • the embodiment of the present invention may also perform a read operation which is substantially the same as the previous read operation, except that the read address is read.
  • the implementation steps are specifically as follows:
  • the readout intention information is read by the extension device according to readout address information received from the master device through the I2C interface Generating the identifier, and is addressed by the extension device according to the device address in the read address information;
  • the extension device Returning the read data read from the memory corresponding to the read address to the extension device according to the read intention information, so that the extension device forwards the read data to the The master device; the read address is the register address plus the byte length of the write data.
  • the readout intention information further includes a readout signal and a second interrupt signal
  • the method for data transmission further includes:
  • the readout intention information received again is generated again by the extension device when receiving the returned readout data;
  • the method for data transmission further includes:
  • the stop intention information is generated by the extension device according to stop information received from the master device through the I2C interface, the stop intention information includes stopping Signal and third interrupt signal;
  • the stop signal in the stop intention information is identified according to the third interrupt signal response interrupt in the stop intention information, and the current operation is stopped when the recognition is successful.
  • extension device MCU can implement the entire process of the data transmission method proposed in the first embodiment, and achieve the technical effect. It is consistent with the technical effects of the first embodiment, and details are not described herein again. Only the specific structure of the extension device MCU is specifically described:
  • the address receiving module 101 is configured to receive, by using an I2C interface, write address information sent by the master control device; the write address information includes a write identifier and a device address;
  • the receiving intent generating module 102 is configured to generate receiving intention information according to the writing identifier, and send the receiving intent information to a peripheral device corresponding to the device address, so that the peripheral device prepares according to the receiving intent information Receive register address;
  • An address forwarding module 103 configured to receive, by using the I2C interface, a register address sent by the master device, and forward the register address to the peripheral device, so that the peripheral device uses the received register address as The start address is ready for a write operation or a read operation.
  • the extension device MCU of the data transmission further includes:
  • Writing to the data forwarding module 104 configured to receive the write data sent by the master device byte by byte through the I2C interface in a pipeline manner, and forward the write data to the periphery byte by byte And means for the peripheral device to write the write data byte by byte into the corresponding memory starting from the received register address as a start address.
  • the receiving intention information includes a received signal and a first interrupt signal
  • the receiving intent generating module 102 is further configured to send the receiving intent information to a peripheral device corresponding to the device address, so that the peripheral device responds to the interrupt according to the first interrupt signal in the receiving intent information,
  • the received signal in the reception intention information is identified, and is ready to receive a register address when the recognition is successful.
  • the extension device MCU of the data transmission further includes:
  • the first read address receiving module 105 is configured to receive read address information sent by the master device by using the I2C interface; the read address information includes a read identifier and the device address;
  • a first readout intention generating module 106 configured to generate readout intention information according to the readout identifier, and send the readout intention information to a peripheral device corresponding to the device address, so that the peripheral device according to the The read intention information returns read data read from a memory corresponding to the read address; the read address is the register address;
  • the first read data forwarding module 107 is configured to receive the read data returned by the peripheral device, and forward the returned read data to the master control device through the I2C interface.
  • the first readout intention generating module 106 included in the extension device MCU of the data transmission further And generating readout intention information according to the readout identifier, and transmitting the readout intention information to a peripheral device corresponding to the device address, so that the peripheral device returns from the readout intention information
  • the readout intention information further includes a readout signal and a second interrupt signal
  • the first readout intention generating module 106 is further configured to send the readout intention information to a peripheral device corresponding to the device address, so that the peripheral device is configured to perform a second interrupt according to the readout intention information.
  • the signal response is interrupted, the read signal in the read intention information is identified, and when the recognition is successful, the read data read from the memory corresponding to the read address is returned.
  • extension device MCU of the data transmission further includes:
  • a second readout intention generating module 108 configured to: when the readout data returned by the peripheral device is received, generate the readout intention information again, and send the readout intention information to the peripheral device to And causing the peripheral device to recognize the readout signal in the readout intention information according to the interrupt signal response interrupt in the readout intention information, and return to the memory corresponding to the next readout address when the recognition is successful
  • the read data is read; wherein the next read address is the previous read address plus one.
  • extension device MCU of the data transmission further includes:
  • the stop information receiving module 109 is configured to receive, by using the I2C interface, stop information sent by the master control device;
  • the stop intention generating module 110 is configured to generate stop intention information according to the stop information; the stop intention information includes a stop signal and a third interrupt signal;
  • the stop intention sending module 111 is configured to send the stop intention information to a peripheral device corresponding to the device address, so that the peripheral device responds to the interrupt according to the third interrupt signal in the stop intention information, and stops the stop The stop signal in the intent information is identified and the current operation is stopped when the recognition is successful.
  • FIG. 6 is a schematic structural diagram of another embodiment of an apparatus for extending data transmission according to the present invention.
  • the extension apparatus MCU can implement the entire process of the data transmission method proposed by the second embodiment, and the obtained technology. The effect is consistent with the technical effect of the second embodiment, and details are not described herein again. Only the specific structure of the extension device MCU is specifically described:
  • the receiving intent module 201 is configured to receive the receiving intent information sent by the extension device MCU, where the receiving intent information is written by the extension device MCU according to the write address information received from the master device through the I2C interface.
  • the identifier is generated, and is addressed by the extension device MCU according to the device address of the write address information;
  • the receiving module 202 is configured to prepare to receive a register address according to the receiving intention information
  • the receiving address module 203 is configured to receive a register address sent by the extension device MCU, and prepare a write operation or a read operation with the received register address as a start address; the register address is the expansion device
  • the MCU is received from the master device through the I2C interface.
  • the data transmission peripheral device further includes:
  • the writing module 204 is configured to receive, in a pipeline manner, the write data forwarded by the extension device MCU byte by byte, and start the write data byte by byte starting from the received register address as a start address Write to the corresponding memory.
  • the receiving intention information includes a received signal and a first interrupt signal
  • the preparation receiving module 202 is further configured to: according to the first interrupt signal in the receiving intention information, respond to the interrupt, identify the received signal in the receiving intention information, and prepare to receive the register address when the recognition is successful.
  • the peripheral device for data transmission further includes:
  • a first readout intention module 205 configured to receive readout intention information sent by the extension device MCU, wherein the readout intention information is used by the extension device MCU according to the I2C interface from the master control device
  • the read identifier in the read address information received in the received identifier is generated by the extension device MCU according to the device address in the read address information;
  • a first readout returning module 206 configured to return, according to the readout intention information, readout data read from a memory corresponding to the readout address to the extension device MCU, so that the extension device MCU passes the The I2C interface forwards the read data to the master device; the read address is the register address.
  • the first readout return module 206 of the data transmission peripheral device is configured to return the readout read from the memory corresponding to the read address according to the readout intention information.
  • Data to the extension device MCU such that the extension device MCU forwards the read data to the master device via the I2C interface; the read address is the register address plus the write The length in bytes of the data.
  • the readout intention information further includes a readout signal and a second interrupt signal
  • the first readout return module 206 is further configured to: according to the second interrupt signal in the readout intention information, respond to the interrupt, identify the readout signal in the readout intention information, and return when the recognition is successful.
  • the read data read from the memory corresponding to the read address.
  • peripheral device for data transmission further includes:
  • a second readout intention module 207 configured to receive the readout intention information by the extension device MCU again; the readout intention information received again is the readout data received by the extension device MCU Generated again;
  • the second readout returning module 208 is configured to identify the readout signal in the readout intention information according to the interruption signal response interrupt in the readout intention information received again, and when the recognition is successful Returning the read data read in the memory corresponding to the next read address to the extension device MCU, so that the extension device MCU forwards the read data to the master control device through the I2C interface; Among them, the next read address is the previous read address plus one.
  • peripheral device for data transmission further includes:
  • Stop intention module 209 configured to receive stop intention information sent by the extension device MCU; the stop intention information is generated by the extension device MCU according to stop information received from the master device through the I2C interface
  • the stop intention information includes a stop signal and a third interrupt signal;
  • the stop response module 210 is configured to identify the stop signal in the stop intention information according to the third interrupt signal response interrupt in the stop intention information, and stop the current operation when the recognition is successful.
  • FIG. 7 is a schematic structural diagram of an embodiment of a system for data transmission provided by the present invention, where the system includes a master device 10, an extension device MCU, and at least one peripheral device 20; wherein the extension device MCU is implemented as described above. Extension provided by the example The device MCU; the peripheral device 20 is the peripheral device 20 provided by the above embodiment;
  • the master device 10 is connected to the extension device MCU through an I2C interface; the extension device MCU is connected to the peripheral device 20.
  • the present invention provides a system for data transmission, which can implement all the processes of the data transmission method provided by the foregoing embodiments, and the technical effects achieved are consistent.
  • FIG. 8 is a schematic flowchart diagram of an embodiment of a communication process of a write-only operation of a data transmission method provided by the present invention; the following is a data transmission method, an extension device, a peripheral device 20, and a system provided by the present invention.
  • the write-only operation is described in detail:
  • Step S31 The master device 10 sends the write address information to the extension device MCU;
  • Step S321 the extension device MCU generates a signal SO and a first interrupt signal INT1,
  • Step S322 the extension device MCU sends a signal SO and a first interrupt signal INT1 to the peripheral device 20;
  • Step S33 The peripheral device 20 enters the interrupt service routine in response to the first interrupt signal INT1, and determines the signal received by the I/O interface, and identifies it as the signal SO, ready to receive the register address;
  • Step S341 The master device 10 sends the register address to the extension device MCU;
  • Step S342 the extension device MCU sends the received register address to the peripheral device 20;
  • Step S35 operating in a pipeline mode, the master device 10 sends the data to the extension device MCU according to the timing byte by byte, and the extension device MCU directly forwards each byte received to the peripheral device 20, and the peripheral device 20 registers.
  • the address is the start address and the write data of each byte received is written into the corresponding memory.
  • Step S36 The master device 10 sends a stop message to the extension device
  • Step S37 the extension device MCU generates a signal S2 and a third interrupt signal INT3, and sends it to the peripheral device 20;
  • Step S38 The peripheral device 20 performs an interrupt service routine in response to the third interrupt signal INT3, determines the signal received by the I/O interface, recognizes the signal S2, and stops the current operation.
  • FIG. 9 is a schematic flowchart of an embodiment of a communication process of a read-only operation of the data transmission method provided by the present invention; the following is a data transmission method, an extension device, a peripheral device 20, and a system provided by the present invention.
  • the read-only operation is described in detail:
  • Step S31 The master device 10 sends the write address information to the extension device MCU;
  • Step S321 the extension device MCU generates a signal SO and a first interrupt signal INT1,
  • Step S322 the extension device MCU sends a signal SO and a first interrupt signal INT1 to the peripheral device 20;
  • Step S33 The peripheral device 20 enters the interrupt service routine in response to the first interrupt signal INT1, and determines the signal received by the I/O interface, and identifies it as the signal SO, ready to receive the register address;
  • Step S341 The master device 10 sends the register address to the extension device MCU;
  • Step S342 the extension device MCU sends the received register address to the peripheral device 20;
  • Step S41 The master device 10 sends the readout address information to the extension device MCU;
  • Step S421 the extension device MCU generates a signal S2 and a second interrupt signal INT2;
  • Step S422 the extension device MCU transmission signal S2 and the second interrupt signal INT2 are sent to the peripheral device 20;
  • Step S43 The peripheral device 20 enters the interrupt service program in response to the second interrupt signal INT2, and judges the signal received by the I/O interface, and recognizes that it is the signal S2, and is ready to receive a byte returned from the memory corresponding to the read address.
  • Read data is the register address;
  • Step S44 The extension device MCU receives the read data of one byte returned by the peripheral device 20, generates the signal S2 and the second interrupt signal INT2 again, and sends it to the peripheral device 20 to perform step S43 again, but reads
  • the out address is the last read address plus one;
  • Step S45 the extension device MCU forwards each read data received to the master device 10;
  • Step S36 The master device 10 sends a stop message to the extension device
  • Step S37 the extension device MCU generates a signal S1 and a third interrupt signal INT3, and sends it to the peripheral device 20;
  • Step S38 The peripheral device 20 performs an interrupt service routine in response to the third interrupt signal INT3, determines the signal received by the I/O interface, recognizes the signal S1, and stops the current operation.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

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Abstract

一种数据传输的方法包括：通过I2C接口接收主控设备发送的写入地址信息（S11）；所述写入地址信息包括写入标识和器件地址；根据所述写入标识生成接收意图信息，并将所述接收意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述接收意图信息准备接收寄存器地址（S12）；通过所述I2C接口接收所述主控设备发送的寄存器地址，并将所述寄存器地址转发给所述外围设备，以使所述外围设备以所接收到的寄存器地址为起始地址准备进行写入操作或读出操作（S13）。相应地，还提出另一种数据传输方法，以及一种数据传输扩展装置、外围设备和系统。采用上述技术方案，能实现I2C通信，并提高数据传输效率。

Description

数据传输的方法、扩展装置、外围设备及系统 技术领域
本发明涉及通信技术领域，尤其涉及一种数据传输的方法、扩展装置、外围设备及系统。
背景技术
I2C(Inter-Integrated Circuit，两线式串行总线)是由PHILIPS公司开发的两线式串行总线，用于实现主控设备与外围设备之间的通信，是微电子通信控制领域广泛采用的一种总线标准，是同步通信的一种特殊形式，其中I2C总线分为主模式和从模式，主模式初始化总线的数据传输并产生允许传输的时钟信号，从模式则遵循主模式发起的请求进行数据写入或读出。
现有技术中，主控设备与外围设备需要通过I2C总线进行通信时，首先需要确定主控设备是否具有主I2C功能，外围设备是否具有从I2C功能，当主控设备具有主I2C功能，同时外围设备也具有从I2C功能时，则主控设备与外围设备可以通过I2C总线进行通信；而当主控设备具有主I2C功能，外围设备不具有从I2C功能时，则通常采用设置一扩展装置以非桥接方式与该外围设备连接，并对外围设备扩展从I2C功能，具体过程为：主控设备将所需传输的数据经扩展装置进行缓存，待主控设备一次通讯结束后，扩展装置对缓存的数据进行处理后传输给此外围设备，从而实现主控设备与外围设备通过I2C总线进行通信的目的。
对于完整一次I2C通讯可参见图1和图2，图1是现有技术提供的I2C通信协议中的I2C只写时序的时序图，图2是现有技术提供的I2C通信协议中的I2C只读时序的时序图，依据图中的I2C只写时序和I2C只读时序，对于能直接通I2C接口进行I2C通信息的主控设备和外围设备，I2C通信是按时间顺序一个字节一个字节地写入数据或读出数据，具备从I2C通信功能的外围设备是可以识别接收到的寄存器地址，然后以该寄存器地址为一个起始地址开始逐个字节地进行后序的写入数据或者读出数据；但是对不具备从I2C功能的外围设备，无法识别从主控设备接收到的I2C时序里的数据，即无法识别寄存器地址，导致无法将传送过来的每一字节数据写入或读出，因而，现有技术提供的主控设备与不具备从I2C通信功能的外围设备之间所进行非桥接式I2C通信方式，虽然能让该外围设备识别扩展装置处理后的数据来实现I2C通信，但由于完整的一次时序通讯，是要经过扩展进行缓存并处理后再完整的传送给外围设备，所花的时间过长，而且当主控设备与外围设备之间需要传输大量数据时，由于扩展模块的资源有限，从而导致数据传输效率降低。
发明内容
本发明实施例提出一种数据传输的方法、扩展装置、外围设备及系统，能实现I2C通信，并提高数据传输效率。
本发明实施例在一个方面提供一种数据传输的方法，包括：
通过I2C接口接收主控设备发送的写入地址信息；所述写入地址信息包括写入标识和器件地址；
根据所述写入标识生成接收意图信息，并将所述接收意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述接收意图信息准备接收寄存器地址；
通过所述I2C接口接收所述主控设备发送的寄存器地址，并将所述寄存器地址转发给所述外围设备，以使所述外围设备以所接收到的寄存器地址为起始地址准备进行写入操作或读出操作。
在一种实施方式中，所述数据传输的方法还包括写入操作，具体为：
以流水线方式，通过所述I2C接口逐个字节地接收所述主控设备发送的写入数据，并逐个字节地将所述写入数据转发给所述外围设备，以供所述外围设备从以所接收到的寄存器地址为起始地址开始将所述写入数据逐个字节地写入相应的内存中。
进一步地，所述接收意图信息包括接收信号和第一中断信号；
则，所述将所述接收意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述接收意图信息准备接收寄存器地址，具体为：
将所述接收意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述接收意图信息中的第一中断信号响应中断，对所述接收意图信息中的接收信号进行识别，并在识别成功时准备接收寄存器地址。
在另一种实施方式中，所述数据传输的方法还包括读出操作，具体为：
通过所述I2C接口接收所述主控设备发送的读出地址信息；所述读出地址信息包括读出标识和所述器件地址；
根据所述读出标识生成读出意图信息，并将所述读出意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述读出意图信息返回从读出地址对应的内存中所读取的读出数据；所述读出地址为所述寄存器地址；
接收所述外围设备返回的读出数据，并通过所述I2C接口将返回的读出数据转发给所述主控设备。
在又一种实施方式中，所述数据传输的方法还包括读出操作，具体为：
通过所述I2C接口接收所述主控设备发送的读出地址信息；所述读出地址信息包括读出标识和所述器件地址；
根据所述读出标识生成读出意图信息，并将所述读出意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述读出意图信息返回从读出地址对应的内存中所读取的读出数据；所述读出地址为所述寄存器地址加上所述写入数据的字节长度；
接收所述外围设备返回的读出数据，并通过所述I2C接口将返回的读出数据转发给所述主控设备。
进一步地，所述读出意图信息还包括读出信号和第二中断信号；
则所述将所述读出意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述读出意图信息返回从读出地址对应的内存中所读取的读出数据，具体为：
将所述读出意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述读出意图信息中的第二中断信号响应中断，对所述读出意图信息中的读出信号进行识别，并在识别成功时返回从读出地址对应的内存中所读取的读出数据。
进一步地，所述数据传输的方法还包括：
当接收到所述外围设备返回的读出数据时，再次生成所述读出意图信息，并将所述读出意图信息发送给所述外围设备，以使所述外围设备根据所述读出意图信息中的中断信号响应中断，对所述读出意图信息中的读出信号进行识别，并在识别成功时返回下一个读出地址对应的内存中所读取的读出数据；其中，下一个读出地址为上一个读出地址加一。
再进一步地，所述数据传输的方法还包括：
通过所述I2C接口接收所述主控设备发送的停止信息；
根据所述停止信息生成停止意图信息；所述停止意图信息包括停止信号和第三中断信号；
将所述停止意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述停止意图信息中的第三中断信号响应中断，对所述停止意图信息中的停止信号进行识别，并在识别成功时停止当前操作。
本发明实施例在另一个方面提出一种数据传输的方法，包括：
接收扩展装置发送的接收意图信息；其中，所述接收意图信息是由所述扩展装置根据通过I2C接口从主控设备中所接收到的写入地址信息的写入标识生成的，且是由所述扩展装置根据所述写入地址信息的器件地址进行寻址发送的；
根据所述接收意图信息准备接收寄存器地址；
接收所述扩展装置转发送的寄存器地址，并以所接收到的寄存器地址为起始地址准备进行写入操作或读出操作；所述寄存器地址是所述扩展装置通过所述I2C接口从所述主控设备中接收到的。
在一种实施方式中，所述数据传输的方法还包括：
以流水线方式，逐个字节地接收所述扩展装置转发的写入数据，并从以所接收到的寄存器地址为起始地址开始将所述写入数据逐个字节写入相应的内存中。
进一步地，所述接收意图信息包括接收信号和第一中断信号；
则，根据所述接收意图信息准备接收寄存器地址，具体为：
根据所述接收意图信息中的第一中断信号响应中断，对所述接收意图信息中的接收信号进行识别，并在识别成功时准备接收寄存器地址。
在另一种实施方式中，所述数据传输的方法还包括：
接收所述扩展装置发送的读出意图信息；其中，所述读出意图信息是由所述扩展装置根据通过所述I2C接口从所述主控设备中所接收到的读出地址信息中的读出标识生成的，且是由所述扩展装置根据所述读出地址信息中的所述器件地址进行寻址发送的；
根据所述读出意图信息返回从读出地址对应的内存中所读取的读出数据给所述扩展装置，以使所述扩展装置通过所述I2C接口将所述读出数据转发给所述主控设备；所述读出地址为所述寄存器地址。
在又一种实施方式中，所述数据传输的方法还包括：
接收所述扩展装置发送的读出意图信息；其中，所述读出意图信息是由所述扩展装置根据通过所 述I2C接口从所述主控设备中所接收到的读出地址信息中的读出标识生成的，且是由所述扩展装置根据所述读出地址信息中的所述器件地址进行寻址发送的；
根据所述读出意图信息返回从读出地址对应的内存中所读取的读出数据给所述扩展装置，以使所述扩展装置通过所述I2C接口将所述读出数据转发给所述主控设备；所述读出地址为所述寄存器地址加上所述写入数据的字节长度。
进一步地，所述读出意图信息还包括读出信号和第二中断信号；
则所述根据所述读出意图信息返回从读出地址对应的内存中所读取的读出数据给所述扩展装置，具体为：
根据所述读出意图信息中的第二中断信号响应中断，对所述读出意图信息中的读出信号进行识别，并在识别成功时返回从读出地址对应的内存中所读取的读出数据。
进一步地，所述数据传输的方法还包括：
再次接收所述扩展装置发送所述读出意图信息；再次接到的所述读出意图信息是由所述扩展装置在接收到返回的读出数据时再次生成的；
根据所述再次接收到的所述读出意图信息中的中断信号响应中断，对所述读出意图信息中的读出信号进行识别，并在识别成功时返回下一个读出地址对应的内存中所读取的读出数据给所述扩展装置，以使所述扩展装置通过所述I2C接口将所述读出数据转发给所述主控设备；其中，下一个读出地址为上一个读出地址加一。
再进一步地，所述数据传输的方法还包括：
接收所述扩展装置发送的停止意图信息；所述停止意图信息是由所述扩展装置根据通过所述I2C接口从所述主控设备中接收到的停止信息生成的，所述停止意图信息包括停止信号和第三中断信号；
根据所述停止意图信息中的第三中断信号响应中断，对所述停止意图信息中的停止信号进行识别，并在识别成功时停止当前操作。
对应于上述第一个方面所提出的数据传输的方法，本发明实施例提出一种数据传输的扩展装置，包括：
写入地址接收模块，用于通过I2C接口接收主控设备发送的写入地址信息；所述写入地址信息包括写入标识和器件地址；
接收意图生成模块，用于根据所述写入标识生成接收意图信息，并将所述接收意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述接收意图信息准备接收寄存器地址；
地址转发模块，用于通过所述I2C接口接收所述主控设备发送的寄存器地址，并将所述寄存器地址转发给所述外围设备，以使所述外围设备以所接收到的寄存器地址为起始地址准备进行写入操作或读出操作。
在一种实施方式中，所述数据传输的扩展装置还包括：
写入数据转发模块，用于以流水线方式，通过所述I2C接口逐个字节地接收所述主控设备发送的 写入数据，并逐个字节地将所述写入数据转发给所述外围设备，以供所述外围设备从以所接收到的寄存器地址为起始地址开始将所述写入数据逐个字节地写入相应的内存中。
在另一种实施方式中，所述数据传输的扩展装置还包括：
第一读出地址接收模块，用于通过所述I2C接口接收所述主控设备发送的读出地址信息；所述读出地址信息包括读出标识和所述器件地址；
第一读出意图生成模块，用于根据所述读出标识生成读出意图信息，并将所述读出意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述读出意图信息返回从读出地址对应的内存中所读取的读出数据；所述读出地址为所述寄存器地址加上所述写入数据的字节长度。
第一读出数据转发模块，用于接收所述外围设备返回的读出数据，并通过所述I2C接口将返回的读出数据转发给所述主控设备。
对应于第二方面所提出的数据传输的方法，本发明实施例还提供一种数据传输的外围设备，包括：
接收意图模块，用于接收扩展装置发送的接收意图信息；其中，所述接收意图信息是由所述扩展装置根据通过I2C接口从主控设备中所接收到的写入地址信息的写入标识生成的，且是由所述扩展装置根据所述写入地址信息的器件地址进行寻址发送的；
准备接收模块，用于根据所述接收意图信息准备接收寄存器地址；
接收地址模块，用于接收所述扩展装置转发送的寄存器地址，并以所接收到的寄存器地址为起始地址准备进行写入操作或读出操作；所述寄存器地址是所述扩展装置通过所述I2C接口从所述主控设备中接收到的。
在一种实施方式中，所述数据传输的外围设备还包括：
写入模块，用于以流水线方式，逐个字节地接收所述扩展装置转发的写入数据，并从以所接收到的寄存器地址为起始地址开始将所述写入数据逐个字节写入相应的内存中。
在另一种实施方式中，所述数据传输的外围设备还包括：
第一读出意图模块，用于接收所述扩展装置发送的读出意图信息；其中，所述读出意图信息是由所述扩展装置根据通过所述I2C接口从所述主控设备中所接收到的读出地址信息中的读出标识生成的，且是由所述扩展装置根据所述读出地址信息中的所述器件地址进行寻址发送的；
第一读出返回模块，用于根据所述读出意图信息返回从读出地址对应的内存中所读取的读出数据给所述扩展装置，以使所述扩展装置通过所述I2C接口将所述读出数据转发给所述主控设备；所述读出地址为所述寄存器地址加上所述写入数据的字节长度。
相应地，本发明实施例还提供一种数据传输的系统，所述系统包括主控设备、扩展装置和至少一个外围设备；其中，所述扩展装置为上述的数据传输的扩展装置；所述外围设备为上述的数据传输的外围设备；
所述主控设备通过I2C接口与所述扩展装置连接；所述扩展装置与所述外围设备连接。
本发明提供的一种数据传输的方法、扩展装置、外围设备和系统具有以下有益效果：
本发明提供了一种数据传输的方法、扩展装置、外围设备和系统，扩展装置能通过I2C接口接收并识主控设备发送的写入地址信息；扩展装置根据所述写入地址信息中的写入标识生成接收意图信息，并其发送给所述器件地址对应的外围设备，所述外围设备通过识别所述接收意图信息准备接收寄存器地址；接着，所述扩展装置通过所述I2C接口接收所述主控设备发送的寄存器地址，并将所述寄存器地址转发给所述外围设备，所述外围设备将该寄存器地址作为起始地址准备进行写入操作或读出操作。对于不具备扩展I2C功能的外围设备，无法识别主控设备发送的数据，则本发明提供的扩展装置通过通知外围设备其具体的寄存器地址后，后序步骤中该扩展装置只需要进行即时转发数据，即可让外围设备实现根据该地址就进行写入操作或读出操作，实现主控设备与不具体扩展I2C功能的外围设备的I2C通信，而且扩展装置不需要在接收到一次完整的时序数据时再打包传输给外围设备，不受限于扩展装置的内存空间，提高数据传输效率。
附图说明
图1是现有技术提供的I2C通信协议中的I2C只写时序的时序图；
图2是现有技术提供的I2C通信协议中的I2C只读时序的时序图；
图3是本发明提供的数据传输的方法的一个实施例的流程示意图；
图4是本发明提供的数据传输的方法的另一个实施例的流程示意图；
图5是本发明提供的数据传输的扩展装置的一个实施例的结构示意图；
图6是本发明提供的数据传输的外围设备的一个实施例的结构示意图；
图7是本发明提供的数据传输的系统的一个实施例的结构示意图；
图8是本发明提供的数据传输的方法的只写操作的通信过程的一个实施例的流程示意图；
图9是本发明提供的数据传输的方法的只读操作的通信过程的一个实施例的流程示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
参见图3，是本发明提供的数据传输的方法的一个实施例的流程示意图，该方法由扩展装置执行，而该扩展装置可以是一个安装在外围设备外部的用于扩展从I2C功能的MCU(MicrocontrollerUnit，微控制单元)，并通过I2C接口与主控设备连接，该方法包括以下步骤：
S11，通过I2C接口接收主控设备发送的写入地址信息；所述写入地址信息包括写入标识和器件地址；
S12，根据所述写入标识生成接收意图信息，并将所述接收意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述接收意图信息准备接收寄存器地址；
S13，通过所述I2C接口接收所述主控设备发送的寄存器地址，并将所述寄存器地址转发给所述外围设备，以使所述外围设备以所接收到的寄存器地址为起始地址准备进行写入操作或读出操作。
需要说明的是，如图1和图2所述的器件地址devive address和跟随在器件地址devive address后的写标志位W，即为本发明实施例中的写入地址信息的器件地址和写入标识，在扩展装置MCU通过I2C接口接收到主控设备发送的写入地址信息时，会生成一个接收意图信息，如设置I/O口的状态，并且扩展装置MCU将其通过I/O口发送给外围设备，通知下一个接收到的字节数据为寄存器地址，外围设备接收该字节数据，将其作为接下来进行写入操作或读出操作的寄存器地址，即后序步骤中该扩展装置只需要进行即时转发数据，就可让外围设备实现根据该地址进行写入操作或读出操作，实现主控设备与不具体扩展I2C功能的外围设备的I2C通信，而且扩展装置不需要在接收到一次完整的时序数据时再打包传输给外围设备，不受限于扩展装置的内存空间，提高数据传输效率。
在将寄存器地址转发给外围设备后，本发明实施例中后序进行的写入操作，具体实施步骤如下：
以流水线方式，通过所述I2C接口逐个字节地接收所述主控设备发送的写入数据，并逐个字节地将所述写入数据转发给所述外围设备，以供所述外围设备从以所接收到的寄存器地址为起始地址开始将所述写入数据逐个字节地写入相应的内存中。
在本实施方式中，上述主控设备发送数据，扩展装置MCU将接收到的每一字数据转发给外围设备，这三者之间进行的I2C通信的写入操作是按一个字节一个字节地将写入数据写入内存中，该流水线方式的写入操作在写入数据传输过程效率，节省传输时间，可以提高数据写入的效率，由于本实施例中主控设备与扩展装置MCU之间是通过I2C接口连接，传输线为I2C总线，其通讯速率为100kbit/S，则相应地扩展装置MCU与外转设备之间进行写入数据或读出数据的传送速率应该大于或等于100kbit/S，确保扩展装置MCU进行传输数据时的每一瞬间只存在1个字节的数据存在内存中，提高传输效率。
进一步地，所述接收意图信息包括接收信号和第一中断信号；
则，所述将所述接收意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述接收意图信息准备接收寄存器地址，具体为：
将所述接收意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述接收意图信息中的第一中断信号响应中断，对所述接收意图信息中的接收信号进行识别，并在识别成功时准备接收寄存器地址。
在本实施例中，通过设置中断机制，能使外围设备快速并实时通过识别扩展设备发送的意图信息获知主控设备的意图，即接下来要进行I2C通讯的内容和对象，从而能快速地进行写入操作或读出操作。上述接收意图信息所包括接收信号和第一中断信号在本实施例中配置为：接收信号为SO，第一中断信号为扩展装置MCU触发中断生成第一中断信号INT1，该接收信号SO通过扩展装置MCU的I/O接口发送到外围设备的I/O接口，该第一中断信号INT1通过扩展装置的I/O接口发送至外围设备的外部中断接口，外围设备接收到外部中断信号，即第一中断信号INT1时，进入中断服务程序，识别I/O接口的具体状态，当识别到信号SO时，外围设备进行准备接收寄存器地址，即通知外围设备 下一个接收到的字节数据为寄存器地址。在本实施例中，寄存器地址长度为1个字节。
在将寄存器地址转发给外围设备后，本发明实施例中后序进行的读出操作，具体为：
通过所述I2C接口接收所述主控设备发送的读出地址信息；所述读出地址信息包括读出标识和所述器件地址；
根据所述读出标识生成读出意图信息，并将所述读出意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述读出意图信息返回从读出地址对应的内存中所读取的读出数据；所述读出地址为所述寄存器地址；
接收所述外围设备返回的读出数据，并通过所述I2C接口将返回的读出数据转发给所述主控设备。
在上述实施例中的写入操作之后，本发明实施例还会有可能进行读出操作，该读出操作与上一个读出操作的实施步骤基本相同，区别在于读取地址，该读出操作的实施步骤具体为：
通过所述I2C接口接收所述主控设备发送的读出地址信息；所述读出地址信息包括读出标识和所述器件地址；
根据所述读出标识生成读出意图信息，并将所述读出意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述读出意图信息返回从读出地址对应的内存中所读取的读出数据；所述读出地址为所述寄存器地址加上所述写入数据的字节长度；
接收所述外围设备返回的读出数据，并通过所述I2C接口将返回的读出数据转发给所述主控设备。
进一步地，所述读出意图信息还包括读出信号和第二中断信号；
则所述将所述读出意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述读出意图信息返回从读出地址对应的内存中所读取的读出数据，具体为：
将所述读出意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述读出意图信息中的第二中断信号响应中断，对所述读出意图信息中的读出信号进行识别，并在识别成功时返回从读出地址对应的内存中所读取的读出数据。
需要说明的是，上述读出意图信息所包括的读出信号和第二中断信号在本实施例中配置为：读出信号为S1，第二中断信号为扩展装置MCU触发中断生成第二中断信号INT2，该接收信号S1通过扩展装置MCU的I/O接口发送到外围设备的I/O接口，该第二中断信号INT2通过扩展装置的I/O接口发送至外围设备的外部中断接口，外围设备接收到外部中断信号，即第二中断信号INT2时，进入中断服务程序，识别I/O接口的具体状态，当识别到信号S1时，外围设备进行返回从读出地址对应的内存中所读取的读出数据，即通知外围设备进行读出操作。
进一步地，所述数据传输的方法还包括：
当接收到所述外围设备返回的读出数据时，再次生成所述读出意图信息，并将所述读出意图信息发送给所述外围设备，以使所述外围设备根据所述读出意图信息中的中断信号响应中断，对所述读出意图信息中的读出信号进行识别，并在识别成功时返回下一个读出地址对应的内存中所读取的读出数据；其中，下一个读出地址为上一个读出地址加一。
需要说明的是，外围设备只有在接收到读出意图信息中的读出信号S1，会相应地返回一个字节 的读出数据，而扩展装置MCU只要接收到外围设备返回的一个字节的读出数据，就会再次生成读出意图信息发送给外围设备，如此循环，逐个字节地将读出数据传输给主控设备，以符合I2C通信协议。
再进一步地，所述数据传输的方法还包括：
通过所述I2C接口接收所述主控设备发送的停止信息；
根据所述停止信息生成停止意图信息；所述停止意图信息包括停止信号和第三中断信号；
将所述停止意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述停止意图信息中的第三中断信号响应中断，对所述停止意图信息中的停止信号进行识别，并在识别成功时停止当前操作。
需要说明的是，上述停止意图信息所包括的停止信号和第三中断信号在本实施例中配置为：停止信号为S2，第三中断信号为扩展装置MCU触发中断生成第三中断信号INT3，该停止信号S2通过扩展装置MCU的I/O接口发送到外围设备的I/O接口，该第三中断信号INT3通过扩展装置的I/O接口发送至外围设备的外部中断接口，外围设备接收到外部中断信号，即第三中断信号INT3时，进入中断服务程序，识别I/O接口的具体状态，当识别到信号S3时，外围设备停止当前操作，即扩展装置MCU通知外围设备停止当前操作，表示完成主控设备与外围设备的一次完整的I2C通讯。
上述实施例中的第一中断信号INT1、第二中断信号INT2和第三中断信号INT3所代表的信号是相同的。
本发明提供了一种数据传输的方法，能通过I2C接口接收并识主控设备发送的写入地址信息；扩展装置根据所述写入地址信息中的写入标识生成接收意图信息，并其发送给所述器件地址对应的外围设备，所述外围设备通过识别所述接收意图信息准备接收寄存器地址；接着，所述扩展装置通过所述I2C接口接收所述主控设备发送的寄存器地址，并将所述寄存器地址转发给所述外围设备，所述外围设备将该寄存器地址作为起始地址准备进行写入操作或读出操作。对于不具备扩展I2C功能的外围设备，无法识别主控设备发送的数据，则本发明提供的扩展装置通过通知外围设备其具体的寄存器地址后，后序步骤中该扩展装置只需要进行即时转发数据，即可让外围设备实现根据该地址就进行写入操作或读出操作，实现主控设备与不具体扩展I2C功能的外围设备的I2C通信，而且扩展装置不需要在接收到一次完整的时序数据时再打包传输给外围设备，不受限于扩展装置的内存空间，提高数据传输效率。
参见图4，是本发明提供的数据传输的方法的另一个实施例的流程示意图，该方法由设置在外围设备中的一个装置执行，所达到的技术效果与上一实施例的相同，在此不再赘述，具体实施步骤如下：
S21，接收扩展装置发送的接收意图信息；其中，所述接收意图信息是由所述扩展装置根据通过I2C接口从主控设备中所接收到的写入地址信息的写入标识生成的，且是由所述扩展装置根据所述写入地址信息的器件地址进行寻址发送的；
S22，根据所述接收意图信息准备接收寄存器地址；
S23，接收所述扩展装置转发送的寄存器地址，并以所接收到的寄存器地址为起始地址准备进行 写入操作或读出操作；所述寄存器地址是所述扩展装置通过所述I2C接口从所述主控设备中接收到的。
在接收到寄存器地址后，本发明实施例中后序进行的写入操作，具体实施步骤如下：
在一种实施方式中，所述数据传输的方法还包括：
以流水线方式，逐个字节地接收所述扩展装置转发的写入数据，并从以所接收到的寄存器地址为起始地址开始将所述写入数据逐个字节写入相应的内存中。
进一步地，所述接收意图信息包括接收信号和第一中断信号；
则，根据所述接收意图信息准备接收寄存器地址，具体为：
根据所述接收意图信息中的第一中断信号响应中断，对所述接收意图信息中的接收信号进行识别，并在识别成功时准备接收寄存器地址。
在接收到寄存器地址后，本发明实施例中后序进行的读出操作，具体实施步骤如下：
接收所述扩展装置发送的读出意图信息；其中，所述读出意图信息是由所述扩展装置根据通过所述I2C接口从所述主控设备中所接收到的读出地址信息中的读出标识生成的，且是由所述扩展装置根据所述读出地址信息中的所述器件地址进行寻址发送的；
根据所述读出意图信息返回从读出地址对应的内存中所读取的读出数据给所述扩展装置，以使所述扩展装置通过所述I2C接口将所述读出数据转发给所述主控设备；所述读出地址为所述寄存器地址。
在上述实施例中的写入操作之后，本发明实施例还会有可能进行读出操作，该读出操作与上一个读出操作的实施步骤基本相同，区别在于读取地址，该读出操作的实施步骤具体为：
接收所述扩展装置发送的读出意图信息；其中，所述读出意图信息是由所述扩展装置根据通过所述I2C接口从所述主控设备中所接收到的读出地址信息中的读出标识生成的，且是由所述扩展装置根据所述读出地址信息中的所述器件地址进行寻址发送的；
根据所述读出意图信息返回从读出地址对应的内存中所读取的读出数据给所述扩展装置，以使所述扩展装置通过所述I2C接口将所述读出数据转发给所述主控设备；所述读出地址为所述寄存器地址加上所述写入数据的字节长度。
进一步地，所述读出意图信息还包括读出信号和第二中断信号；
则所述根据所述读出意图信息返回从读出地址对应的内存中所读取的读出数据给所述扩展装置，具体为：
根据所述读出意图信息中的第二中断信号响应中断，对所述读出意图信息中的读出信号进行识别，并在识别成功时返回从读出地址对应的内存中所读取的读出数据。
进一步地，所述数据传输的方法还包括：
再次接收所述扩展装置发送所述读出意图信息；再次接到的所述读出意图信息是由所述扩展装置在接收到返回的读出数据时再次生成的；
根据所述再次接收到的所述读出意图信息中的中断信号响应中断，对所述读出意图信息中的读出信号进行识别，并在识别成功时返回下一个读出地址对应的内存中所读取的读出数据给所述扩展装置，以使所述扩展装置通过所述I2C接口将所述读出数据转发给所述主控设备；其中，下一个读出地 址为上一个读出地址加一。
再进一步地，所述数据传输的方法还包括：
接收所述扩展装置发送的停止意图信息；所述停止意图信息是由所述扩展装置根据通过所述I2C接口从所述主控设备中接收到的停止信息生成的，所述停止意图信息包括停止信号和第三中断信号；
根据所述停止意图信息中的第三中断信号响应中断，对所述停止意图信息中的停止信号进行识别，并在识别成功时停止当前操作。
参见图5，是本发明提供的数据传输的扩展装置的一个实施例的结构示意图，该扩展装置MCU能实施上述第一个实施例所提出的数据传输的方法的全部流程，所达到的技术效果与第一个实施例的技术效果一致，在此不再赘述，仅具体描这该扩展装置MCU的具体结构：
写入地址接收模块101，用于通过I2C接口接收主控设备发送的写入地址信息；所述写入地址信息包括写入标识和器件地址；
接收意图生成模块102，用于根据所述写入标识生成接收意图信息，并将所述接收意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述接收意图信息准备接收寄存器地址；
地址转发模块103，用于通过所述I2C接口接收所述主控设备发送的寄存器地址，并将所述寄存器地址转发给所述外围设备，以使所述外围设备以所接收到的寄存器地址为起始地址准备进行写入操作或读出操作。
在一种实施方式中，所述数据传输的扩展装置MCU还包括：
写入数据转发模块104，用于以流水线方式，通过所述I2C接口逐个字节地接收所述主控设备发送的写入数据，并逐个字节地将所述写入数据转发给所述外围设备，以供所述外围设备从以所接收到的寄存器地址为起始地址开始将所述写入数据逐个字节地写入相应的内存中。
进一步地，所述接收意图信息包括接收信号和第一中断信号；
所述接收意图生成模块102，还用于将所述接收意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述接收意图信息中的第一中断信号响应中断，对所述接收意图信息中的接收信号进行识别，并在识别成功时准备接收寄存器地址。
在另一种实施方式中，所述数据传输的扩展装置MCU还包括：
第一读出地址接收模块105，用于通过所述I2C接口接收所述主控设备发送的读出地址信息；所述读出地址信息包括读出标识和所述器件地址；
第一读出意图生成模块106，用于根据所述读出标识生成读出意图信息，并将所述读出意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述读出意图信息返回从读出地址对应的内存中所读取的读出数据；所述读出地址为所述寄存器地址；
第一读出数据转发模块107，用于接收所述外围设备返回的读出数据，并通过所述I2C接口将返回的读出数据转发给所述主控设备。
在又一种实施方式中，所述数据传输的扩展装置MCU所包括的第一读出意图生成模块106，还 用于根据所述读出标识生成读出意图信息，并将所述读出意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述读出意图信息返回从读出地址对应的内存中所读取的读出数据；所述读出地址为所述寄存器地址加上所述写入数据的字节长度。
进一步地，所述读出意图信息还包括读出信号和第二中断信号；
所述第一读出意图生成模块106，还用于将所述读出意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述读出意图信息中的第二中断信号响应中断，对所述读出意图信息中的读出信号进行识别，并在识别成功时返回从读出地址对应的内存中所读取的读出数据。
进一步地，所述数据传输的扩展装置MCU还包括：
第二读出意图生成模块108，用于当接收到所述外围设备返回的读出数据时，再次生成所述读出意图信息，并将所述读出意图信息发送给所述外围设备，以使所述外围设备根据所述读出意图信息中的中断信号响应中断，对所述读出意图信息中的读出信号进行识别，并在识别成功时返回下一个读出地址对应的内存中所读取的读出数据；其中，下一个读出地址为上一个读出地址加一。
再进一步地，所述数据传输的扩展装置MCU还包括：
停止信息接收模块109，用于通过所述I2C接口接收所述主控设备发送的停止信息；
停止意图生成模块110，用于根据所述停止信息生成停止意图信息；所述停止意图信息包括停止信号和第三中断信号；
停止意图发送模块111，用于将所述停止意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述停止意图信息中的第三中断信号响应中断，对所述停止意图信息中的停止信号进行识别，并在识别成功时停止当前操作。
参见图6，是本发明提供的数据传输的扩展装置的另一个实施例的结构示意图，该扩展装置MCU能实施上述第二个实施例所提出的数据传输的方法的全部流程，所达到的技术效果与第二个实施例的技术效果一致，在此不再赘述，仅具体描这该扩展装置MCU的具体结构：
接收意图模块201，用于接收扩展装置MCU发送的接收意图信息；其中，所述接收意图信息是由所述扩展装置MCU根据通过I2C接口从主控设备中所接收到的写入地址信息的写入标识生成的，且是由所述扩展装置MCU根据所述写入地址信息的器件地址进行寻址发送的；
准备接收模块202，用于根据所述接收意图信息准备接收寄存器地址；
接收地址模块203，用于接收所述扩展装置MCU转发送的寄存器地址，并以所接收到的寄存器地址为起始地址准备进行写入操作或读出操作；所述寄存器地址是所述扩展装置MCU通过所述I2C接口从所述主控设备中接收到的。
在一种实施方式中，，所述数据传输的外围设备还包括：
写入模块204，用于以流水线方式，逐个字节地接收所述扩展装置MCU转发的写入数据，并从以所接收到的寄存器地址为起始地址开始将所述写入数据逐个字节写入相应的内存中。
进一步地，所述接收意图信息包括接收信号和第一中断信号；
所述准备接收模块202，还用于根据所述接收意图信息中的第一中断信号响应中断，对所述接收意图信息中的接收信号进行识别，并在识别成功时准备接收寄存器地址
在另一种实施方式中，所述数据传输的外围设备还包括：
第一读出意图模块205，用于接收所述扩展装置MCU发送的读出意图信息；其中，所述读出意图信息是由所述扩展装置MCU根据通过所述I2C接口从所述主控设备中所接收到的读出地址信息中的读出标识生成的，且是由所述扩展装置MCU根据所述读出地址信息中的所述器件地址进行寻址发送的；
第一读出返回模块206，用于根据所述读出意图信息返回从读出地址对应的内存中所读取的读出数据给所述扩展装置MCU，以使所述扩展装置MCU通过所述I2C接口将所述读出数据转发给所述主控设备；所述读出地址为所述寄存器地址。
在又一种实施方式中，所述数据传输的外围设备的所述第一读出返回模块206，用于根据所述读出意图信息返回从读出地址对应的内存中所读取的读出数据给所述扩展装置MCU，以使所述扩展装置MCU通过所述I2C接口将所述读出数据转发给所述主控设备；所述读出地址为所述寄存器地址加上所述写入数据的字节长度。
进一步地，所述读出意图信息还包括读出信号和第二中断信号；
所述第一读出返回模块206，还用于根据所述读出意图信息中的第二中断信号响应中断，对所述读出意图信息中的读出信号进行识别，并在识别成功时返回从读出地址对应的内存中所读取的读出数据。
进一步地，所述数据传输的外围设备还包括：
第二读出意图模块207，用于再次接收所述扩展装置MCU发送所述读出意图信息；再次接到的所述读出意图信息是由所述扩展装置MCU在接收到返回的读出数据时再次生成的；
第二读出返回模块208，用于根据所述再次接收到的所述读出意图信息中的中断信号响应中断，对所述读出意图信息中的读出信号进行识别，并在识别成功时返回下一个读出地址对应的内存中所读取的读出数据给所述扩展装置MCU，以使所述扩展装置MCU通过所述I2C接口将所述读出数据转发给所述主控设备；其中，下一个读出地址为上一个读出地址加一。
再进一步地，所述数据传输的外围设备还包括：
停止意图模块209，用于接收所述扩展装置MCU发送的停止意图信息；所述停止意图信息是由所述扩展装置MCU根据通过所述I2C接口从所述主控设备中接收到的停止信息生成的，所述停止意图信息包括停止信号和第三中断信号；
停止响应模块210，用于根据所述停止意图信息中的第三中断信号响应中断，对所述停止意图信息中的停止信号进行识别，并在识别成功时停止当前操作。
参见图7，是本发明提供的数据传输的系统的一个实施例的结构示意图，所述系统包括主控设备10、扩展装置MCU和至少一个外围设备20；其中，所述扩展装置MCU为上述实施例所提供的扩展 装置MCU；所述外围设备20为上述实施例所提供的外围设备20；
所述主控设备10通过I2C接口与所述扩展装置MCU连接；所述扩展装置MCU与所述外围设备20连接。
本发明提供了一种数据传输的系统，能实施上述实施例所提供的数据传输方法的全部流程，所达到的技术效果一致。
参见图8，是本发明提供的数据传输的方法的只写操作的通信过程的一个实施例的流程示意图；下面以本发明提供的数据传的方法、扩展装置、外围设备20和系统，所进行的只写操作进行详细的描述：
步骤S31：主控设备10发送写入地址信息给扩展装置MCU；
步骤S321：扩展装置MCU生成信号SO和第一中断信号INT1，
步骤S322：扩展装置MCU发送信号SO和第一中断信号INT1给外围设备20；
步骤S33：外围设备20响应第一中断信号INT1，进入中断服务程序，对I/O接口所接收到的信号进行判断，识别为信号SO，准备接收寄存器地址；
步骤S341：主控设备10发送寄存器地址给扩展装置MCU；
步骤S342：扩展装置MCU将接收到的寄存器地址发送给外围设备20；
步骤S35：以流水线方式操作，主控设备10按时序逐个字节的写入数据发送给扩展装置MCU，扩展装置MCU直接将接收到的每一个字节转发给外围设备20，外围设备20以寄存器地址为起始地址将接收到的每一个字节的写入数据写入相应的内存中。
步骤S36：主控设备10发送停止信息给扩展装置；
步骤S37：扩展装置MCU生成信号S2和第三中断信号INT3，并发送给外围设备20；
步骤S38：外围设备20响应第三中断信号INT3，进行中断服务程序，对I/O接口所接收到的信号进行判断，识别为信号S2，停止当前操作。
参见图9，是本发明提供的数据传输的方法的只读操作的通信过程的一个实施例的流程示意图；下面以本发明提供的数据传的方法、扩展装置、外围设备20和系统，所进行的只读操作进行详细的描述：
步骤S31：主控设备10发送写入地址信息给扩展装置MCU；
步骤S321：扩展装置MCU生成信号SO和第一中断信号INT1，
步骤S322：扩展装置MCU发送信号SO和第一中断信号INT1给外围设备20；
步骤S33：外围设备20响应第一中断信号INT1，进入中断服务程序，对I/O接口所接收到的信号进行判断，识别为信号SO，准备接收寄存器地址；
步骤S341：主控设备10发送寄存器地址给扩展装置MCU；
步骤S342：扩展装置MCU将接收到的寄存器地址发送给外围设备20；
步骤S41：主控设备10发送读出地址信息给扩展装置MCU；
步骤S421：扩展装置MCU生成信号S2和第二中断信号INT2；
步骤S422：扩展装置MCU发送信号S2和第二中断信号INT2发送给外围设备20；
步骤S43：外围设备20响应第二中断信号INT2，进入中断服务程序，对I/O接口所接收到的信号进行判断，识别为信号S2，准备接收从读出地址对应的内存中返回一个字节的读出数据；所述读出地址为所述寄存器地址；
步骤S44：扩展装置MCU每接收到外围设备20返回的一个字节的读出数据，再次生生成信号S2和第二中断信号INT2，并发送给外围设备20，使其再执行步骤S43，但读出地址为上一个读出地址加一；
步骤S45：扩展装置MCU将接收到的每一个读出数据转发给主控设备10；
步骤S36：主控设备10发送停止信息给扩展装置；
步骤S37：扩展装置MCU生成信号S1和第三中断信号INT3，并发送给外围设备20；
步骤S38：外围设备20响应第三中断信号INT3，进行中断服务程序，对I/O接口所接收到的信号进行判断，识别为信号S1，停止当前操作。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，所述的存储介质可为磁碟、光盘、只读存储记忆体(Read-Only Memory，ROM)或随机存储记忆体(Random Access Memory，RAM)等。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围。

Claims (23)

  1. 一种数据传输的方法，其特征在于，包括：
    通过I2C接口接收主控设备发送的写入地址信息；所述写入地址信息包括写入标识和器件地址；
    根据所述写入标识生成接收意图信息，并将所述接收意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述接收意图信息准备接收寄存器地址；
    通过所述I2C接口接收所述主控设备发送的寄存器地址，并将所述寄存器地址转发给所述外围设备，以使所述外围设备以所接收到的寄存器地址为起始地址准备进行写入操作或读出操作。
  2. 如权利要求1所述的数据传输的方法，其特征在于，所述数据传输的方法还包括：
    以流水线方式，通过所述I2C接口逐个字节地接收所述主控设备发送的写入数据，并逐个字节地将所述写入数据转发给所述外围设备，以供所述外围设备从以所接收到的寄存器地址为起始地址开始将所述写入数据逐个字节地写入相应的内存中。
  3. 如权利要求1或2所述的数据传输的方法，其特征在于，所述接收意图信息包括接收信号和第一中断信号；
    则，所述将所述接收意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述接收意图信息准备接收寄存器地址，具体为：
    将所述接收意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述接收意图信息中的第一中断信号响应中断，对所述接收意图信息中的接收信号进行识别，并在识别成功时准备接收寄存器地址。
  4. 如权利要求1所述的数据传输的方法，其特征在于，所述数据传输的方法还包括：
    通过所述I2C接口接收所述主控设备发送的读出地址信息；所述读出地址信息包括读出标识和所述器件地址；
    根据所述读出标识生成读出意图信息，并将所述读出意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述读出意图信息返回从读出地址对应的内存中所读取的读出数据；所述读出地址为所述寄存器地址；
    接收所述外围设备返回的读出数据，并通过所述I2C接口将返回的读出数据转发给所述主控设备。
  5. 如权利要求2所述的数据传输的方法，其特征在于，所述数据传输的方法还包括：
    通过所述I2C接口接收所述主控设备发送的读出地址信息；所述读出地址信息包括读出标识和所述器件地址；
    根据所述读出标识生成读出意图信息，并将所述读出意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述读出意图信息返回从读出地址对应的内存中所读取的读出数据；所述读出地址为所述寄存器地址加上所述写入数据的字节长度；
    接收所述外围设备返回的读出数据，并通过所述I2C接口将返回的读出数据转发给所述主控设备。
  6. 如权利要求4或5所述的数据传输的方法，其特征在于，所述读出意图信息还包括读出信号和第二中断信号；
    则所述将所述读出意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述读出意图信息返回从读出地址对应的内存中所读取的读出数据，具体为：
    将所述读出意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述读出意图信息中的第二中断信号响应中断，对所述读出意图信息中的读出信号进行识别，并在识别成功时返回从读出地址对应的内存中所读取的读出数据。
  7. 如权利要求6所述的数据传输的方法，其特征在于，所述数据传输的方法还包括：
    当接收到所述外围设备返回的读出数据时，再次生成所述读出意图信息，并将所述读出意图信息发送给所述外围设备，以使所述外围设备根据所述读出意图信息中的中断信号响应中断，对所述读出意图信息中的读出信号进行识别，并在识别成功时返回下一个读出地址对应的内存中所读取的读出数据；其中，下一个读出地址为上一个读出地址加一。
  8. 如权利要求1所述的数据传输的方法，其特征在于，所述数据传输的方法还包括：
    通过所述I2C接口接收所述主控设备发送的停止信息；
    根据所述停止信息生成停止意图信息；所述停止意图信息包括停止信号和第三中断信号；
    将所述停止意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述停止意图信息中的第三中断信号响应中断，对所述停止意图信息中的停止信号进行识别，并在识别成功时停止当前操作。
  9. 一种数据传输的方法，其特征在于，包括：
    接收扩展装置发送的接收意图信息；其中，所述接收意图信息是由所述扩展装置根据通过I2C接口从主控设备中所接收到的写入地址信息的写入标识生成的，且是由所述扩展装置根据所述写入地址信息的器件地址进行寻址发送的；
    根据所述接收意图信息准备接收寄存器地址；
    接收所述扩展装置转发送的寄存器地址，并以所接收到的寄存器地址为起始地址准备进行写入操作或读出操作；所述寄存器地址是所述扩展装置通过所述I2C接口从所述主控设备中接收到的。
  10. 如权利要求9所述的数据传输的方法，其特征在于，所述数据传输的方法还包括：
    以流水线方式，逐个字节地接收所述扩展装置转发的写入数据，并从以所接收到的寄存器地址为起始地址开始将所述写入数据逐个字节写入相应的内存中。
  11. 如权利要求9或10所述的数据传输的方法，其特征在于，所述接收意图信息包括接收信号和第一中断信号；
    则，根据所述接收意图信息准备接收寄存器地址，具体为：
    根据所述接收意图信息中的第一中断信号响应中断，对所述接收意图信息中的接收信号进行识别，并在识别成功时准备接收寄存器地址。
  12. 如权利要求9所述的数据传输的方法，其特征在于，所述数据传输的方法还包括：
    接收所述扩展装置发送的读出意图信息；其中，所述读出意图信息是由所述扩展装置根据通过所述I2C接口从所述主控设备中所接收到的读出地址信息中的读出标识生成的，且是由所述扩展装置根据所述读出地址信息中的所述器件地址进行寻址发送的；
    根据所述读出意图信息返回从读出地址对应的内存中所读取的读出数据给所述扩展装置，以使所述扩展装置通过所述I2C接口将所述读出数据转发给所述主控设备；所述读出地址为所述寄存器地址。
  13. 如权利要求10所述的数据传输的方法，其特征在于，所述数据传输的方法还包括：
    接收所述扩展装置发送的读出意图信息；其中，所述读出意图信息是由所述扩展装置根据通过所述I2C接口从所述主控设备中所接收到的读出地址信息中的读出标识生成的，且是由所述扩展装置根据所述读出地址信息中的所述器件地址进行寻址发送的；
    根据所述读出意图信息返回从读出地址对应的内存中所读取的读出数据给所述扩展装置，以使所述扩展装置通过所述I2C接口将所述读出数据转发给所述主控设备；所述读出地址为所述寄存器地址加上所述写入数据的字节长度。
  14. 如权利要求12或13所述的数据传输的方法，其特征在于，所述读出意图信息还包括读出信号和第二中断信号；
    则所述根据所述读出意图信息返回从读出地址对应的内存中所读取的读出数据给所述扩展装置，具体为：
    根据所述读出意图信息中的第二中断信号响应中断，对所述读出意图信息中的读出信号进行识别，并在识别成功时返回从读出地址对应的内存中所读取的读出数据。
  15. 如权利要求14所述的数据传输的方法，其特征在于，所述数据传输的方法还包括：
    再次接收所述扩展装置发送所述读出意图信息；再次接到的所述读出意图信息是由所述扩展装置在接收到返回的读出数据时再次生成的；
    根据所述再次接收到的所述读出意图信息中的中断信号响应中断，对所述读出意图信息中的读出信号进行识别，并在识别成功时返回下一个读出地址对应的内存中所读取的读出数据给所述扩展装 置，以使所述扩展装置通过所述I2C接口将所述读出数据转发给所述主控设备；其中，下一个读出地址为上一个读出地址加一。
  16. 如权利要求9所述的数据传输的方法，其特征在于，所述数据传输的方法还包括：
    接收所述扩展装置发送的停止意图信息；所述停止意图信息是由所述扩展装置根据通过所述I2C接口从所述主控设备中接收到的停止信息生成的，所述停止意图信息包括停止信号和第三中断信号；
    根据所述停止意图信息中的第三中断信号响应中断，对所述停止意图信息中的停止信号进行识别，并在识别成功时停止当前操作。
  17. 一种数据传输的扩展装置，其特征在于，包括：
    写入地址接收模块，用于通过I2C接口接收主控设备发送的写入地址信息；所述写入地址信息包括写入标识和器件地址；
    接收意图生成模块，用于根据所述写入标识生成接收意图信息，并将所述接收意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述接收意图信息准备接收寄存器地址；
    地址转发模块，用于通过所述I2C接口接收所述主控设备发送的寄存器地址，并将所述寄存器地址转发给所述外围设备，以使所述外围设备以所接收到的寄存器地址为起始地址准备进行写入操作或读出操作。
  18. 如权利要求17所述的数据传输的扩展装置，其特征在于，所述数据传输的扩展装置还包括：
    写入数据转发模块，用于以流水线方式，通过所述I2C接口逐个字节地接收所述主控设备发送的写入数据，并逐个字节地将所述写入数据转发给所述外围设备，以供所述外围设备从以所接收到的寄存器地址为起始地址开始将所述写入数据逐个字节地写入相应的内存中。
  19. 如权利要求18所述的数据传输的扩展装置，其特征在于，所述数据传输的扩展装置还包括：
    第一读出地址接收模块，用于通过所述I2C接口接收所述主控设备发送的读出地址信息；所述读出地址信息包括读出标识和所述器件地址；
    第一读出意图生成模块，用于根据所述读出标识生成读出意图信息，并将所述读出意图信息发送给所述器件地址对应的外围设备，以使所述外围设备根据所述读出意图信息返回从读出地址对应的内存中所读取的读出数据；所述读出地址为所述寄存器地址加上所述写入数据的字节长度；
    第一读出数据转发模块，用于接收所述外围设备返回的读出数据，并通过所述I2C接口将返回的读出数据转发给所述主控设备。
  20. 一种数据传输的外围设备，其特征在于，包括：
    接收意图模块，用于接收扩展装置发送的接收意图信息；其中，所述接收意图信息是由所述扩展 装置根据通过I2C接口从主控设备中所接收到的写入地址信息的写入标识生成的，且是由所述扩展装置根据所述写入地址信息的器件地址进行寻址发送的；
    准备接收模块，用于根据所述接收意图信息准备接收寄存器地址；
    接收地址模块，用于接收所述扩展装置转发送的寄存器地址，并以所接收到的寄存器地址为起始地址准备进行写入操作或读出操作；所述寄存器地址是所述扩展装置通过所述I2C接口从所述主控设备中接收到的。
  21. 如权利要求20所述的数据传输的外围设备，其特征在于，所述数据传输的外围设备还包括：
    写入模块，用于以流水线方式，逐个字节地接收所述扩展装置转发的写入数据，并从以所接收到的寄存器地址为起始地址开始将所述写入数据逐个字节写入相应的内存中。
  22. 如权利要求21所述的数据传输的外围设备，其特征在于，所述数据传输的外围设备还包括：
    第一读出意图模块，用于接收所述扩展装置发送的读出意图信息；其中，所述读出意图信息是由所述扩展装置根据通过所述I2C接口从所述主控设备中所接收到的读出地址信息中的读出标识生成的，且是由所述扩展装置根据所述读出地址信息中的所述器件地址进行寻址发送的；
    第一读出返回模块，用于根据所述读出意图信息返回从读出地址对应的内存中所读取的读出数据给所述扩展装置，以使所述扩展装置通过所述I2C接口将所述读出数据转发给所述主控设备；所述读出地址为所述寄存器地址加上所述写入数据的字节长度。
  23. 一种数据传输的系统，其特征在于，所述系统包括主控设备、扩展装置和至少一个外围设备；其中，所述扩展装置为如权利要求17至24任一项所述的扩展装置；所述外围设备为如权利要求25至32任一项所述的外围设备；
    所述主控设备通过I2C接口与所述扩展装置连接；所述扩展装置与所述外围设备连接。
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