WO2017139973A1 - 一种闪存设备的访问方法和装置 - Google Patents

一种闪存设备的访问方法和装置 Download PDF

Info

Publication number
WO2017139973A1
WO2017139973A1 PCT/CN2016/074140 CN2016074140W WO2017139973A1 WO 2017139973 A1 WO2017139973 A1 WO 2017139973A1 CN 2016074140 W CN2016074140 W CN 2016074140W WO 2017139973 A1 WO2017139973 A1 WO 2017139973A1
Authority
WO
WIPO (PCT)
Prior art keywords
write
storage area
accessed
read
access
Prior art date
Application number
PCT/CN2016/074140
Other languages
English (en)
French (fr)
Inventor
石亮
薛春
李乔
单东方
徐君
王元钢
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2016/074140 priority Critical patent/WO2017139973A1/zh
Priority to SG11201806099WA priority patent/SG11201806099WA/en
Priority to CN201680000818.0A priority patent/CN107710169B/zh
Priority to KR1020187023110A priority patent/KR102114256B1/ko
Priority to CA3012236A priority patent/CA3012236C/en
Priority to EP16890206.2A priority patent/EP3399421B1/en
Priority to AU2016393275A priority patent/AU2016393275B2/en
Priority to JP2018543654A priority patent/JP6817318B2/ja
Publication of WO2017139973A1 publication Critical patent/WO2017139973A1/zh
Priority to US16/105,723 priority patent/US10732898B2/en

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20—Employing a main memory using a specific memory technology
    • G06F2212/202—Non-volatile memory
    • G06F2212/2022—Flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/21—Employing a record carrier using a specific recording technology
    • G06F2212/214—Solid state disk
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7201—Logical to physical mapping or translation of blocks or pages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7202—Allocation control and policies

Definitions

  • the embodiments of the present invention relate to the field of computers, and in particular, to a method and an apparatus for accessing a flash memory device.
  • flash-based solid state drives Due to the advantages of good random access performance, low density, low power consumption, flash-based solid state drives (SSDs) have gradually replaced traditional disks and become important storage media.
  • flash memory technology has developed rapidly, and the storage density has grown from single-bit memory cells to the most recent multi-bit memory cells, such as 6-bit, and the manufacturing process has been extended from 65 nanometers to the nearest 10 nanometers.
  • LDPC decoding is implemented by a belief propagation algorithm, which is divided into hard decision decoding and soft decision decoding.
  • the hard decision decoding has high efficiency, and the required reading and decoding time is short, but only the data with low error rate can be decoded.
  • Soft decisions enable correct decoding of data with higher error rates, but require longer read and decode delays.
  • LDPC is used as the check code, the read request time is associated with the error rate, and the data read request for the high error rate takes longer.
  • the flash memory writes data by means of Incremental Step Pulse Programming (ISPP).
  • ISPP Incremental Step Pulse Programming
  • the programming step voltage is written by gradually increasing the programming voltage.
  • the unit of magnitude of the voltage determines the error rate of the data to a large extent.
  • the larger the programming step voltage the lesser the number of iterations to reach the predetermined voltage value.
  • the larger the programming step voltage the worse the programming accuracy and the higher the error rate. From this, it can be concluded that the faster the programming speed, the higher the error rate; the slower the programming speed, the lower the error rate.
  • the storage of the flash memory represents the data by charging a certain amount of charge to the flash memory element, and as the storage time increases, the charge of the memory element will flow out, that is, leakage. The longer the storage time, the more leakage, the higher the error rate.
  • the writing operation of the data can be modulated according to the storage time of the data in the flash memory. If the storage time is long, the writing operation is performed in the form of slow writing. The data slow write error rate is low to ensure correct readout; if the time required for saving is short, and the data has a relatively low error rate due to the save time leakage, the write operation can be performed in the form of fast write.
  • a hard decision is first used, and if the hard decision decoding fails, a soft decision is made.
  • the present invention discloses a method and apparatus for accessing a flash memory device. According to the access characteristics of the data, the read and write operations of the flash device are modulated to improve the overall performance of the flash device access.
  • the present application provides a method for accessing a flash memory device, wherein an access type of access to the flash memory device includes a write operation and a read operation, the method comprising: the storage controller receiving an access request, the access request indicating to be accessed a storage area, for example, carrying address information of the storage area to be accessed in the access request; the storage controller acquires historical access information of the storage area to be accessed, wherein the historical access information includes a historical access type of the storage area to be accessed; the storage controller is configured according to The historical access information and the access type of the access request, and access operations to the access storage area.
  • the read and write speeds of data in the flash memory can be established based on the error rate.
  • the read speed of the data is slow; on the contrary, when the data is written at a slow programming speed and the error rate is low, the data is read faster.
  • Modulation of the flash device can be accomplished based on the intrinsic link between the read operation and the write operation.
  • the storage controller performs an access operation on the access storage area, The storage controller performs a write operation on the access storage area in a fast write manner, wherein the write operation includes a fast write and a slow write, and the fast write write speed is greater than the slow write write speed.
  • the data stored in the storage area to be accessed has a "write only" characteristic, and the write operation frequency of the to-be-accessed storage area is far greater than the read operation. The frequency, so the storage area to be accessed can be written in a fast write manner, thereby improving the access speed to the flash device as a whole.
  • the storage controller treats the access The storage area performs the access operation, including: the storage controller uses the fast read form to read the access storage area, and if the fast read decoding fails, the access storage area is read again in the form of slow read, and the slow operation is adopted.
  • the form of the write-write rewrites the data held in the storage area to be accessed to the storage area to be accessed, wherein the read operation of the storage controller includes fast reading and slow reading, and the reading speed of the fast reading is greater than that of the slow reading. Read speed.
  • the data stored in the storage area to be accessed has a "read-only" attribute, and the frequency of the read operation of the to-be-accessed storage area is much greater than the write operation.
  • the frequency so if the access to the storage area fails to decode in the form of fast read, it means that the data stored in the storage area is not accurate enough, then the data saved in the storage area to be accessed is rewritten into the to-be-accessed form in slow write mode.
  • the storage area ensures the accuracy of the data to speed up subsequent read operations on the storage area to be accessed, thereby improving the access speed of the flash memory device as a whole.
  • the slow write is used.
  • the form rewrites the data saved in the storage area to be accessed to the storage area to be accessed.
  • the historical access information further includes a write speed flag, where the write speed flag is used to indicate a form of a write operation of data in the storage area to be accessed;
  • the access type of the access and the current access request are both read operations, and the write speed flag is not slow write.
  • the method further includes: the storage controller rewrites the data saved in the storage area to be accessed in a slow write manner. The storage area to be accessed.
  • the write speed flag is mainly used to indicate whether the data saved in the storage area to be accessed is written in a slow write manner. If the data saved in the storage area to be accessed is not written in slow write mode, it is very large. To a certain extent, the accuracy of the data stored in the storage area to be accessed is insufficient. If the data has a "read-only" feature, the data saved in the storage area to be accessed is rewritten into the to-be-accessed storage area in a slow write format. In order to ensure the accuracy of the data, the subsequent read operation of the storage area to be accessed is accelerated, thereby improving the access speed of the flash memory device as a whole.
  • the storage controller rewrites the data saved in the storage area to be accessed in a slow write manner. Before the access to the storage area, the method further includes: the storage controller saves the address information in the rewrite queue; and the storage controller reads the to-be-accessed storage area from the to-be-accessed storage area according to the address information saved in the rewrite queue. The data.
  • the address information of the to-be-accessed storage area that needs to be rewritten is written into a rewrite queue, and the rewriting operation is performed when the flash device is idle or the load is small, thereby avoiding the blocking of normal read and write access by the rewriting operation.
  • the read data is directly rewritten to the storage area to be accessed, thereby avoiding the consumption caused by subsequent re-reading.
  • the form of the write operation further includes a normal speed write, wherein the write speed of the normal speed write is greater than the slow speed The write speed of the write is less than the write speed of the fast write; if the historical access type is not a write operation, and the access type of the access request is a write operation, the storage controller performs an access operation on the access storage area, including: storing The controller writes to the access storage area in the form of a constant-speed write.
  • the data stored in the storage area to be accessed has a "cross-access" feature, indicating the frequency of read operations and write operations to the access storage area.
  • the access memory area can be written in the form of a normal-speed write, thereby balancing the speed of the read operation and the write operation, and improving the access speed to the flash memory device as a whole.
  • the historical access information further includes a write speed flag; if the access type of the current access request is In the read operation, the storage controller performs an access operation on the access storage area according to the historical access information and the access type of the access request, including: the storage controller performs a read operation on the storage area to be accessed according to the write speed mark, wherein the fast write corresponds to Slow read, slow write corresponds to fast read.
  • the corresponding read operation can reduce the time of the read operation to a certain extent, and the access speed to the flash memory device is improved as a whole.
  • the method further includes: The storage controller updates the historical access type according to the access type of this access request.
  • the history access information includes a write speed flag
  • the access type of the current access request is a write operation
  • the form of the write operation is different from the form indicated by the write speed flag in the historical access information, Need to update the write speed tag.
  • the storage controller acquires historical access information of the storage area to be accessed, including: storing controller search history Access historical access information of the storage area to be accessed recorded in the record.
  • the historical access information entry corresponding to the storage area to be accessed may be searched according to the address information of the storage area to be accessed, and the historical access information entry includes historical access information of the storage area to be accessed.
  • the method before the storage controller receives the access request, the method further includes: the storage controller receiving the second Write access request, the second write access request is a first write access request to the access storage area; the storage controller writes the to-be-written data of the second write access request into the to-be-access storage area, and records the to-be-accessed in the historical access record Historical access information for the storage area.
  • the second write access requests address information of the storage area to be accessed, and the storage controller creates a historical access information entry corresponding to the address information in the historical access record according to the address information.
  • the second write access request is the first write of the access data area from the "data invalid" state to the "data valid" state.
  • the historical access information of the storage area to be accessed is recorded, for example, created and to be accessed.
  • the historical access information entry corresponding to the storage area and records its historical access type as a write operation.
  • the storage controller writes the to-be-written data of the second write access request into the to-be-access storage area.
  • the method includes: the storage controller writes the data to be written of the second write access request into the storage area to be accessed in a form of slow writing.
  • the second write access request is the first write from the "data invalid" state to the "data valid" state of the access storage area, because it is impossible to determine whether the access type of the written data is a "read only” feature, so the first write is adopted.
  • the method further includes: when the storage controller determines that the data in the storage area to be accessed is invalid, The historical access information of the recorded storage area to be accessed is deleted. For example, the storage controller receives the deletion notification message, and the deletion notification message carries the address information; the storage controller deletes the historical access information of the to-be-accessed storage area according to the deletion notification message.
  • the deletion notification message may be a Trim instruction, which is used to indicate that the user will access the storage area.
  • the data of the domain is deleted, so that the storage controller invalidates the address information of the storage area to be accessed to facilitate subsequent garbage collection.
  • the present application provides a method for accessing a flash memory device, wherein access types to the flash memory device include write operations and read operations, and write operations to the flash memory device include fast write and slow write, and fast write The write speed is greater than the write speed of the slow write.
  • the method includes: receiving a first write access request to access the storage area, where the first access request carries the address information of the storage area to be accessed; and obtaining the to-be-accessed according to the address information
  • the historical access type of the storage area is the access type to be accessed by the storage area to be accessed before the first write access request. In the case where the historical access type of the storage area to be accessed is a write operation, the fast write form is adopted.
  • the data to be written of the first write access request is written to the storage area to be accessed.
  • the data stored in the to-be-accessed storage area has a write-only feature, and the write operation of the to-be-accessed storage area is The frequency is much larger than the frequency of the read operation, so the write access to the memory area to be accessed is performed in a fast write manner, thereby improving the access speed to the flash memory device as a whole.
  • obtaining a historical access type of the storage area to be accessed includes: searching for a historical access type of the to-be-accessed storage area recorded in the historical access record.
  • a historical access information table may be maintained, and a historical access information entry corresponding to each valid data address information is recorded in the historical access information table, and a historical access type of the storage area to be accessed is recorded in the historical access information entry.
  • the method before receiving the first write access request for accessing the storage area, the method further includes: receiving the Accessing a second write access request of the storage area, the second write access request is a first write access request to the access storage area; writing the to-be-written data of the second write access request to the to-be-access storage area, and in the historical access record Record the historical access type of the storage area to be accessed.
  • the second write access request is the first write of the access data area from the "data invalid" state to the "data valid” state.
  • a historical access information entry corresponding to the to-be-accessed storage area is created and The history access type is recorded as a write operation.
  • the data to be written of the second write access request is written into the to-be-access storage area
  • the method includes: writing the data to be written of the second write access request into the storage area to be accessed in a form of slow writing.
  • the second write access request is the first write from the "data invalid" state to the "data valid" state of the access storage area, because it is impossible to determine whether the access type of the written data is a "read only” feature, so the first write is adopted.
  • the actual write operation can also be used for the first write.
  • the method further includes: when determining that the data in the storage area to be accessed is invalid, the recorded The historical access type of the storage area to be accessed is deleted.
  • the Trim command of the operating system when the Trim command of the operating system is received, the historical access information entry corresponding to the storage area to be accessed is deleted, and the Trim command indicates that the data of the current storage area to be accessed has been deleted by the operating system.
  • the method further includes: if the historical access type of the storage area to be accessed is not a write operation Write the data to be written of the first write access request into the storage area to be accessed in a slow write format, and update the historical access type of the storage area to be accessed.
  • the historical access type is considered to be a write operation, and only when all the historical access types of the record are write operations are considered.
  • the historical access type is a write operation.
  • the write operation further includes a normal speed write, wherein the write speed of the normal speed write is greater than the slow speed The write speed of the write is less than the write speed of the fast write; the method further includes: in the case that the historical access type of the storage area to be accessed is not a write operation, the first write access request is to be written in the form of a normal write The incoming data is written to the storage area to be accessed, and the historical access type of the storage area to be accessed is updated.
  • the data stored in the storage area to be accessed has a "cross-access" feature, indicating the frequency of read operations and write operations to the access storage area.
  • the access memory area can be written in the form of a normal-speed write, thereby balancing the speed of the read operation and the write operation, and improving the access speed to the flash memory device as a whole.
  • the present application provides a method for accessing a flash memory device, wherein the flash memory device
  • the access types include write operations and read operations.
  • the write operations to the flash device include fast write and slow write.
  • the write speed of fast write is faster than the write speed of slow write.
  • the read operation of the flash device includes Fast read and slow read, fast read read speed read is faster than slow read read speed read, the method includes: receiving a read access request to access the storage area; using a fast read form to access the storage area for reading Get the historical access type of the storage area to be accessed.
  • the historical access type is the access type to be accessed by the storage area to be accessed before the read access request.
  • the fast read decoding fails and the historical access type is read
  • the slow mode is adopted.
  • the written form rewrites the data saved in the storage area to be accessed to the storage area to be accessed.
  • the data stored in the storage area to be accessed has a "read-only" attribute, and the frequency of the read operation of the to-be-accessed storage area is much greater than the write operation.
  • the frequency so if the access to the storage area fails to decode in the form of fast read, it means that the data stored in the storage area is not accurate enough, then the data saved in the storage area to be accessed is rewritten into the to-be-accessed form in slow write mode.
  • the storage area ensures the accuracy of the data to speed up subsequent read operations on the storage area to be accessed, thereby improving the access speed of the flash memory device as a whole.
  • the slow write is used.
  • the form rewrites the data saved in the storage area to be accessed to the storage area to be accessed.
  • the obtaining a historical access type of the storage area to be accessed includes: searching for a historical access type of the to-be-accessed storage area recorded in the historical access record.
  • a historical access information table may be maintained, and a historical access information entry corresponding to each valid data address information is recorded in the historical access information table, and a historical access type of the storage area to be accessed is recorded in the historical access information entry.
  • the method before receiving the read access request to access the storage area, the method further includes: receiving the storage to be accessed a second write access request of the area, the second write access request is a first write access request to the access storage area; the to-be-written data of the second write access request is written into the to-be-access storage area, and is recorded in the historical access record Access the historical access type of the storage area.
  • the second write access request is the first write of the access data area from the "data invalid" state to the "data valid" state.
  • a historical visit corresponding to the to-be-stored storage area is created.
  • the data to be written of the second write access request is written into the to-be-access storage area, including: The data to be written of the second write access request is written into the to-be-accessed storage area in the form of slow write.
  • the second write access request is the first write from the "data invalid" state to the "data valid" state of the access storage area, because it is impossible to determine whether the access type of the written data is a "read only” feature, so the first write is adopted.
  • the actual write operation can also be used for the first write.
  • the method further includes: when determining that the data in the storage area to be accessed is invalid, the recorded The historical access type of the storage area to be accessed is deleted.
  • the Trim command of the operating system when the Trim command of the operating system is received, the historical access information entry corresponding to the storage area to be accessed is deleted, and the Trim command indicates that the data of the current storage area to be accessed has been deleted by the operating system.
  • the method further includes: in the case of fast read decoding failure, using slow reading Reads the form of the storage area to be accessed.
  • the form of the read operation further includes a constant speed reading, wherein the reading speed reading of the constant speed reading The read speed reading is greater than the slow read, and is smaller than the fast read read speed read; the method further includes: in the case of the fast read decoding failure, the read operation is performed in the form of the normal speed read.
  • the access memory area is read more accurately by increasing the number of threshold voltages between different states, thereby increasing the success rate of decoding.
  • the method further includes: updating the historical access type if the historical access type is not a read operation .
  • the historical access type is considered to be a read operation, and only when all historical access types of the record are read operations are considered.
  • the historical access type is read.
  • the method before the data saved in the storage area to be accessed is rewritten into the to-be-accessed storage area, the method further includes: saving the address information of the storage area to be accessed in the rewrite queue; The data saved in the storage area to be accessed is read from the storage area to be accessed according to the address information saved in the rewrite queue.
  • the address information of the to-be-accessed storage area that needs to be rewritten is written into a rewrite queue, and the rewriting operation is performed when the flash device is idle or the load is small, thereby avoiding the blocking of normal read and write access by the rewriting operation.
  • the read data is directly rewritten to the storage area to be accessed, thereby avoiding the consumption caused by subsequent re-reading.
  • the present application provides a method for accessing a flash memory device, wherein access types to the flash memory device include write operations and read operations, and write operations to the flash memory device include fast write and slow write, and fast write The write speed is greater than the write speed of the slow write.
  • the method includes: receiving a read access request to access the storage area; obtaining historical access information of the storage area to be accessed, where the historical access information includes a historical access type of the storage area to be accessed and Write speed flag, the write speed flag is used to indicate the form of the write operation of the data to be saved in the storage area to be accessed, the history access type is the access type to be accessed by the storage area to be accessed before the read access request; the historical access type is read In the case where the operation and the write speed flag are not slow write, the data saved in the storage area to be accessed is rewritten into the storage area to be accessed in the form of slow write.
  • the write speed flag is mainly used to indicate whether the data saved in the storage area to be accessed is written in a slow write manner. If the data saved in the storage area to be accessed is not written in slow write mode, it is very large. To a certain extent, the accuracy of the data stored in the storage area to be accessed is insufficient. If the data has a "read-only" feature, the data saved in the storage area to be accessed is rewritten into the to-be-accessed storage area in a slow write format. In order to ensure the accuracy of the data, the subsequent read operation of the storage area to be accessed is accelerated, thereby improving the access speed of the flash memory device as a whole.
  • the obtaining the historical access information of the to-be-accessed storage area includes: searching historical access information of the to-be-accessed storage area recorded in the historical access record.
  • a historical access information table may be maintained, and a historical access information entry corresponding to each valid data address information is recorded in the historical access information table, and historical access information of the storage area to be accessed is recorded in the historical access information entry.
  • the method before receiving the read access request to access the storage area, the method further includes: receiving a second write access request to access the storage area, where the second write access request is a first write access request to the access storage area Writing the data to be written of the second write access request to the storage area to be accessed, and recording the historical access information of the storage area to be accessed in the historical access record.
  • the second write access request is the first write of the access data area from the "data invalid" state to the "data valid” state.
  • a historical access information entry corresponding to the to-be-accessed storage area is created and The history access type is recorded as a write operation.
  • the data to be written of the second write access request is written into the to-be-access storage area, including: The data to be written of the second write access request is written into the to-be-accessed storage area in the form of slow write.
  • the second write access request is the first write from the "data invalid" state to the "data valid" state of the access storage area, because it is impossible to determine whether the access type of the written data is a "read only” feature, so the first write is adopted.
  • the actual write operation can also be used for the first write.
  • the method further includes: when determining that the data in the storage area to be accessed is invalid, the recorded The historical access information of the storage area to be accessed is deleted.
  • the Trim command of the operating system when the Trim command of the operating system is received, the historical access information entry corresponding to the storage area to be accessed is deleted, and the Trim command indicates that the data of the current storage area to be accessed has been deleted by the operating system.
  • the data saved in the storage area to be accessed is rewritten to be accessed in a slow write manner. After storing the area, the method further includes updating the write speed flag to slow write.
  • the method further includes: according to the writing speed The memory area to be accessed is marked for reading, wherein fast write corresponds to slow read and slow write corresponds to fast read.
  • the corresponding read operation can reduce the time of the read operation to a certain extent, and the access speed to the flash memory device is improved as a whole.
  • the data saved in the storage area to be accessed is rewritten to be accessed in a slow write manner.
  • the method further includes: storing the address information of the storage area to be accessed in the rewrite queue; and reading the data saved in the storage area to be accessed from the storage area to be accessed according to the address information saved in the rewrite queue.
  • the address information of the to-be-accessed storage area that needs to be rewritten is written into a rewrite queue, and the rewriting operation is performed when the flash device is idle or the load is small, thereby avoiding the blocking of normal read and write access by the rewriting operation.
  • the read data is directly rewritten to the storage area to be accessed, thereby avoiding the consumption caused by subsequent re-reading.
  • the present application provides a readable medium, including executing instructions, when the processor of the memory controller executes an execution instruction, the memory controller performs any of the above aspects or any of the above aspects.
  • the method in the implementation includes executing instructions, when the processor of the memory controller executes an execution instruction, the memory controller performs any of the above aspects or any of the above aspects.
  • the present application provides a memory controller including: a processor, a memory, and a bus; a memory for storing execution instructions, a processor and a memory connected by a bus, and a processor performing memory storage when the memory controller is running Executing instructions to cause the memory controller to perform the method of any of the above or any of the possible implementations of any of the above aspects.
  • the present application provides an access device for a flash memory device, wherein access types to the flash memory device include write operations and read operations, and write operations to the flash memory device include fast write and slow write, fast write The writing speed is greater than the writing speed of the slow writing.
  • the device includes: a receiving unit, configured to receive a first write access request to be accessed, and an obtaining unit, configured to obtain a historical access type of the storage area to be accessed, and historical access
  • the type is an access type to be accessed by the storage area to be accessed before the first write access request;
  • the write unit is configured to write the first write in a fast write form if the historical access type of the to-be-accessed storage area is a write operation
  • the data to be written of the access request is written to the storage area to be accessed.
  • the acquiring unit is configured to obtain a historical access type of the storage area to be accessed, where the acquiring unit is configured to search for the to-be-accessed storage area recorded in the historical access record. Historical access type.
  • the second write access request is The first write access request of the storage area to be accessed; the write unit is further configured to write the data to be written of the second write access request into the storage area to be accessed, and record the historical access type of the storage area to be accessed in the historical access record.
  • the writing unit is configured to write the to-be-written data of the second write access request to be accessed
  • the storage area includes: a writing unit configured to write the data to be written of the second write access request into the to-be-accessed storage area in a form of slow writing.
  • the device further includes a deleting unit; when determining that data in the storage area to be accessed is invalid, deleting The unit is used to delete the historical access type of the recorded storage area to be accessed.
  • the writing unit is further configured to: when the historical access type of the storage area to be accessed is not a write operation Next, the data to be written of the first write access request is written into the storage area to be accessed in a slow write manner, and the historical access type of the storage area to be accessed is updated.
  • the form of the write operation further includes a normal speed write, wherein the write speed of the normal speed write is greater than the slow speed The write speed of the write is less than the write speed of the fast write; the write unit is further configured to use the form of the normal write to treat the first write access request in the case that the historical access type of the storage area to be accessed is not a write operation Write data is written to the storage area to be accessed, and the historical access type of the storage area to be accessed is updated.
  • the seventh aspect is the device implementation manner corresponding to the method of the second aspect, so the description in any of the possible implementation manners of the second aspect or the second aspect is applicable to any possible implementation manner of the seventh aspect or the seventh aspect, I will not repeat them here.
  • the present application provides an access device for a flash memory device, wherein access types to the flash memory device include write operations and read operations, and write operations to the flash memory device include fast write and slow write, and fast write
  • the write speed is greater than the write speed of the slow write.
  • the read operation of the flash device includes a fast read and a slow read, and the read fast read of the fast read is greater than the read read of the slow read.
  • the device includes: receiving a unit for receiving a read access request to access the storage area; a reading unit for reading the access storage area in a fast read manner; and an obtaining unit for obtaining a historical access type of the to-be-accessed storage area, historical access
  • the type is the access type to be accessed by the storage area to be accessed before the read access request; the write unit is used for the fast read decoding failure, and the history
  • the access type is a read operation, the data saved in the storage area to be accessed is rewritten into the storage area to be accessed in a slow write manner.
  • the acquiring unit is configured to obtain a historical access type of the to-be-accessed storage area, where the acquiring unit is configured to search for the to-be-accessed storage area recorded in the historical access record. Historical access type.
  • the second write access request before the receiving unit receives the read access request to access the storage area, a second write access request of the area, the second write access request is a first write access request to the access storage area; the write unit is further configured to write the data to be written of the second write access request into the storage area to be accessed, and The historical access record records the historical access type of the storage area to be accessed.
  • the writing unit is configured to write the to-be-written data of the second write access request to be accessed
  • the storage area includes: a writing unit configured to write the data to be written of the second write access request into the to-be-accessed storage area in a form of slow writing.
  • the device further includes: deleting the unit: deleting the data in the storage area to be accessed The unit is used to delete the historical access type of the recorded storage area to be accessed.
  • the reading unit is further configured to use the slow reading in the case that the fast read decoding fails
  • the form is read from the storage area to be accessed.
  • the form of the read operation further includes a constant speed reading, wherein the reading speed reading of the constant speed reading The read speed reading is greater than the slow read, and is smaller than the fast read read speed read; the read unit is further configured to perform the read operation on the storage area to be accessed in the form of the normal speed read in the case of the fast read decoding failure.
  • the writing unit is further configured to update the historical access if the historical access type is not a read operation Types of.
  • the writing unit rewrites the data saved in the storage area to be accessed by using slow writing Before entering the storage area, it is also used to store the address information of the storage area to be accessed.
  • the data is saved in the rewrite queue.
  • the reading unit is further configured to read data saved in the storage area to be accessed from the storage area to be accessed according to the address information saved in the rewrite queue.
  • the eighth aspect is the apparatus implementation manner corresponding to the method of the third aspect, so the description in any of the possible implementation manners of the third aspect or the third aspect is applicable to any possible implementation manner of the eighth aspect or the eighth aspect, I will not repeat them here.
  • the present application provides an access device for a flash memory device, wherein access types to the flash memory device include write operations and read operations, and write operations to the flash memory device include fast write and slow write, and fast write The writing speed is greater than the writing speed of the slow writing.
  • the device includes: a receiving unit, configured to receive a read access request to access the storage area; and an obtaining unit, configured to acquire historical access information of the storage area to be accessed, in the historical access information Containing a historical access type and a write speed flag of the storage area to be accessed, the write speed flag is used to indicate the form of the write operation of the data held in the storage area to be accessed, and the historical access type is to be accessed before the read access request is accessed.
  • the access type; the write unit is used to re-save the data saved in the storage area to be accessed in a slow write manner when the history access type is a read operation and the write speed flag is not slow write. Write to the storage area to be accessed.
  • the acquiring unit is configured to obtain the historical access information of the to-be-accessed storage area, where the acquiring unit is configured to search for the to-be-accessed storage area recorded in the historical access record. Historical access information.
  • the second write access request before the receiving unit receives the read access request to access the storage area, a second write access request of the area, the second write access request is a first write access request to the access storage area; the write unit is further configured to write the data to be written of the second write access request into the storage area to be accessed, and The historical access record records the historical access information of the storage area to be accessed.
  • the writing unit is configured to write the to-be-written data of the second write access request to be accessed
  • the storage area includes: a writing unit configured to write the data to be written of the second write access request into the to-be-accessed storage area in a form of slow writing.
  • the device further includes: deleting the unit: deleting the data in the storage area to be accessed
  • the unit is configured to delete historical access information of the recorded storage area to be accessed.
  • the writing unit rewrites the data saved in the storage area to be accessed by using slow writing After entering the storage area, it is also used to update the write speed flag to slow write.
  • the device further includes a reading unit; after the obtaining unit acquires historical access information of the storage area to be accessed The reading unit is configured to perform a read operation on the storage area to be accessed according to the write speed flag, wherein the fast write corresponds to the slow read and the slow write corresponds to the fast read.
  • the device further includes a reading unit; the writing unit is to be accessed in a slow writing manner Before the data saved in the storage area is rewritten into the storage area to be accessed, the address information of the storage area to be accessed is also saved in the rewrite queue; the reading unit is configured to access the information according to the address information stored in the rewrite queue. The data saved in the storage area to be accessed is read in the storage area.
  • the ninth aspect is the device implementation manner corresponding to the method of the fourth aspect, so the description in any of the possible implementation manners of the fourth aspect or the fourth aspect is applicable to any possible implementation manner of the ninth aspect or the ninth aspect, I will not repeat them here.
  • the present application provides a flash memory device, wherein access types of the flash memory device include a write operation and a read operation, and the write operation to the flash memory device includes a fast write and a slow write, and a fast write write.
  • the speed is greater than the write speed of the slow write
  • the flash device includes a storage controller and a flash array: the flash array is used to store data; the storage controller is configured to receive a first write access request to the storage area of the flash array to be accessed, and obtain The historical access type of the storage area to be accessed.
  • the historical access type is the access type of the storage area to be accessed before the first write access request.
  • fast write is used.
  • the form writes the data to be written of the first write access request to the storage area to be accessed.
  • the storage controller is further configured to: when the historical access type of the storage area to be accessed is not a write operation, adopt the form of slow writing The data to be written of the write access request is written to the storage area to be accessed, and the historical access type of the storage area to be accessed is updated.
  • the form of the write operation further includes a normal speed write, wherein the write speed of the normal write is greater than the write speed of the slow write, and is less than the write of the fast write.
  • the storage controller is further configured to: write the data to be written of the first write access request into the form of the normal write in the case that the historical access type of the storage area to be accessed is not a write operation Access the storage area and update the historical access type of the storage area to be accessed.
  • the tenth aspect is the apparatus implementation manner corresponding to the method of the second aspect, so the description in any one of the possible implementation manners of the second aspect or the second aspect corresponds to any one of the possible implementation manners of the tenth aspect or the tenth aspect, I will not repeat them here.
  • the present application provides a flash memory device, wherein access types to flash memory devices include write operations and read operations, and write operations to flash memory devices include fast write and slow write, fast write writes.
  • the speed is greater than the write speed of the slow write
  • the read operation of the flash device includes a fast read and a slow read
  • the read fast read of the fast read is greater than the read read of the slow read
  • the flash device includes a memory controller
  • a flash array the flash array is used to store data; the storage controller is configured to receive a read access request to the storage area of the storage array, to read the access storage area in a fast read manner, and obtain a history of the storage area to be accessed.
  • the access type, the history access type is the access type to be accessed by the storage area to be accessed before the read access request.
  • the storage area to be accessed is to be accessed in a slow write manner. The saved data is rewritten into the storage area to be accessed.
  • the storage controller is further configured to perform a read operation on the storage area to be accessed in the form of a slow read in the case that the fast read decoding fails.
  • the form of the read operation further includes a normal speed read, wherein the read speed read of the normal speed read is greater than the read speed read of the slow read, And the read speed reading is smaller than the fast read; the storage controller is further configured to perform a read operation on the storage area to be accessed in the form of a normal speed read in the case that the fast read decoding fails.
  • the eleventh aspect is the apparatus implementation manner corresponding to the method of the third aspect, so the description in any one of the possible implementation manners of the third aspect or the third aspect is applicable to any one of the eleventh aspect or the eleventh aspect.
  • the implementation method will not be described here.
  • the present application provides a flash memory device, wherein access types to flash memory devices include write operations and read operations, and write operations to flash memory devices include fast write and slow write, fast write writes.
  • the speed is greater than the write speed of the slow write
  • the flash device includes a storage controller and a flash array: the flash array is used to store data; the storage controller is configured to receive a read access request to access the storage area, and obtain historical access of the storage area to be accessed.
  • the information, the historical access information includes a historical access type and a write speed flag of the storage area to be accessed, the write speed flag is used to indicate the form of the write operation of the data held in the storage area to be accessed, and the historical access type is the read access request.
  • the access type to be accessed in the storage area to be accessed is rewritten in the form of slow write in the case where the history access type is a read operation and the write speed flag is not slow write.
  • the storage controller rewrites the data saved in the storage area to be accessed into the to-be-accessed storage area in a slow write manner, and is further used for Update the write speed flag to slow write.
  • the second possible implementation manner of the twelfth aspect after the storage controller acquires historical access information of the storage area to be accessed, Read operations are performed on the memory area to be accessed according to the write speed flag, wherein the read operation of the flash memory device includes fast read and slow read, fast read read speed read is faster than slow read read speed read, fast Write corresponds to slow read, slow write corresponds to fast read.
  • the twelfth aspect is the apparatus implementation corresponding to the method of the fourth aspect, so the description in any one of the possible implementations of the fourth aspect or the fourth aspect corresponds to any one of the twelfth aspect or the twelfth aspect.
  • the implementation method will not be described here.
  • the data is divided into three categories: read-only, write-only, and cross-access, and the three types of data are distinguished by using the historical access type, thereby modulating the read-only feature data.
  • Speed slow write for fast read, thus greatly improving read performance with little impact on write performance; modulation writes only the speed of feature data, fast writes, greatly improving write performance with little impact on read performance; further It is also possible to modulate the speed of the cross-access characteristic data and perform constant-speed writing to balance the read/write speed.
  • FIG. 1 is a schematic diagram of a logical structure of a data access system
  • FIG. 2 is a schematic structural diagram of a hardware of a memory controller according to an embodiment of the invention.
  • FIG. 3 is a schematic flow chart of an ISPP programming process according to an embodiment of the invention.
  • FIG. 5 is a soft decision threshold voltage distribution diagram according to an embodiment of the invention.
  • FIG. 6 is an exemplary flowchart of a method for accessing a flash memory device according to an embodiment of the invention.
  • FIG. 7 is a schematic diagram of a history access information entry according to an embodiment of the invention.
  • FIG. 8 is an exemplary flowchart of a method for accessing a flash memory device according to an embodiment of the invention.
  • FIG. 9 is a schematic diagram of a history access information entry according to an embodiment of the invention.
  • FIG. 10 is a schematic diagram showing the logical structure of an access device of a flash memory device according to an embodiment of the invention.
  • FIG. 11 is a schematic diagram showing the logical structure of an access device of a flash memory device according to an embodiment of the invention.
  • FIG. 12 is a schematic diagram showing the logical structure of an access device of a flash memory device according to an embodiment of the invention.
  • FIG. 1 is a schematic diagram 100 of a logical structure of a flash memory device access system according to an embodiment of the present invention. As shown in FIG. 1, the system 100 includes an operating system 102 and a flash memory device 108.
  • Operating system 102 includes various software components and/or drivers for controlling and managing conventional system tasks (eg, memory management, storage device control, power management, etc.) as well as facilitating communication between various hardware and software components.
  • the operating system 102 may be a Darwin, an RTXC, a LINUX, a UNIX, an OS X, a MAC OS, a WINDOWS, or an embedded operating system such as Vxworks, which is not limited by the embodiment of the present invention.
  • the operating system 102 includes a file system 104 and a driver 106.
  • file system 104 is a method and data structure used by operating system 102 to clarify files on flash device 108, ie, a method of organizing files on flash device 108.
  • File system 104 can be of any type such as FAT, NTFS, exFAT, RAW, Ext2, Ext3, Ext4, Btrfs, ZFS, HFS, HFS+, ReiserFS, JFS, VMFS, XFSUFS, or VXFS.
  • the application 102 runs on the operating system 102, and the application implements human-computer interaction in the form of accessing the underlying hardware.
  • the driver 106 is a bridge between the application and the hardware. On the one hand, the application sends corresponding commands to the driver 106. To achieve hardware control, on the other hand, the driver 106 transfers the state of hardware read and write, and the data obtained from the hardware to the application, thereby realizing the interaction between the application and the underlying hardware.
  • the operating system 102 is coupled to the flash device 108 via an Advanced Technology Attachment (ATA).
  • ATA Advanced Technology Attachment
  • the flash device 108 is a flash-based storage device, such as an SSD, and the flash device 108 includes a cache 110, a memory controller 112, and a flash array 130.
  • the storage controller 112 includes a host interface 114, a Flash Translation Layer (FTL) 116, and a flash interface 128.
  • FTL Flash Translation Layer
  • the host interface 114 is used to connect to the host to control data transfer with the operating system 102.
  • the flash interface 128 is used to interface with the flash array 130 to control data transfer with the flash array 130.
  • the flash translation layer 116 includes a Bad Block Management (BBM) module 118, a Wear Leveling (WL) module 120, an address translation module 122, an Error Checking and Correction (ECC) module 124, and garbage.
  • BBM Bad Block Management
  • WL Wear Leveling
  • ECC Error Checking and Correction
  • GC Garbage Collection
  • the flash array 130 can be divided into a plurality of blocks, each of which can be divided into a plurality of pages. Data can be written directly in pages, but to erase data, it needs to be in blocks and cannot be written without erasing.
  • the operating system 102 reads and writes data generally according to the sector size of a hard disk drive (HDD). This causes the file system 104 currently used by the operating system 102 to fail to manage the SSD, and needs to replace a more advanced and complicated file system. This problem is solved, but this will increase the burden on the operating system 102.
  • the flash device 108 virtualizes the operation of the flash array 130 into separate sector operations of the disk in a software manner, which is the function of the flash translation layer 116.
  • the flash translation layer 116 exists between the file system 104 and the physical medium (flash array 130), and the operating system 102 only needs to operate the logical block address (LBA) as it is, and the logical address to the physical block address ( All conversion work of the Physics Block Address (PBA) is handled by the flash translation layer 116.
  • LBA logical block address
  • PBA Physics Block Address
  • the bad block management module 118 is used to manage the bad blocks of the flash array 130.
  • the unstable blocks in the flash array 130 that cannot guarantee the accuracy of the read/write/erase data are called bad blocks, and the bad block management module 118 uses bad.
  • Block table to manage bad blocks.
  • the bad block management module 118 stores the bad block table in a good block, and after each restart, loads the bad block table into the cache 110 from the block.
  • the write of the flash array 130 is operated in units of pages, and the operation may affect the data of other pages in the entire block, so when it is found that an error occurs in the write, the bad block management module 118 replaces the bad block with a good block. Rewrite this data in the new good block, and copy all the remaining valid page data in the detected bad block to the new block, mark the old block as a bad block, and update the address in the bad block table. Remap the address of the original bad block to the new good block.
  • the lifetime of the flash array 130 is calculated by the number of program/erase times, while the wear leveling module 120 It is a mechanism to ensure that the number of times each block in the flash array 130 is written is equal. Without this mechanism, flash granules within flash array 130 cannot reach the lifecycle at the same time. Because users update data in the logical address space at different speeds, some of them often need to be updated, while others do not need to be changed for a long time. Therefore, if there is no WL mechanism, the flash chip life of the data that is frequently updated will be first After the consumption is completed, the flash memory loss of the data with less change is much smaller. In order to avoid this situation, the WL mechanism is required to maintain the wear level of each flash ray in the flash array 130 in a relatively consistent state.
  • the wear balancing module 120 functions in conjunction with the address translation module 122. Each time the application program overwrites or updates the same logical address on the operating system 102, the address translation module 122 dynamically maps the logical address to another different one. The physical address and store this mapping in a specific "address mapping table". Expired physical addresses are marked as "invalid" and awaiting subsequent erase operations. The wear leveling module 120 controls the programming/erasing frequency of each of the stored particles during this mapping process so that all of the physical blocks can be controlled to an equal wear range and simultaneously "aged”.
  • the check error correction module 124 is used for error detection and correction at the time of data reading.
  • the verification error correction module 124 inside the memory controller 112 When data is written, the verification error correction module 124 inside the memory controller 112 generates an ECC signature based on the data.
  • the ECC signature is generally stored in the spare area (Spare Area, SA) at the back of the flash page.
  • the error correction module 124 reads the ECC signature and judges based on the read data and the ECC signature. Whether there is a data error. If it is detected that the read data contains error bits, then the ECC algorithm is needed to correct the detected errors.
  • the ECC algorithm may be a BCH code, an LDPC code, or the like. The embodiment of the present invention describes the solution by using the LDPC code, but it should be understood that the embodiment of the present invention does not limit the coding algorithm used by the ECC.
  • the garbage collection module 126 is specifically configured to copy "valid" page data in one flash block to another data block, and then completely erase the previous data block. Unlike the conventional HDD, the flash array 130 does not directly cover the original data, and the flash device 108 must erase the old data before writing the new data. For flash array 130, garbage collection is the process of re-transferring existing data to other flash locations and completely erasing some useless data.
  • the flash array 130 data can be written directly in units of pages, but it is necessary to block the data in order to erase the data. Therefore, to erase useless data, the flash array 130 first needs to copy the useful data contained in one block to the page in another block, so that the useless data contained in the original block can be erased in units of blocks. After erasing, new data can be written.
  • the flash device 108 also supports a Trim function, Trim is an ATA command, and the operating system 102 sends this command to the memory controller 112 to inform it which addresses occupying the address is "invalid".
  • Trim is an ATA command
  • the operating system 102 sends this command to the memory controller 112 to inform it which addresses occupying the address is "invalid”.
  • the operating system 102 does not actually delete the data of the file. It simply marks the address occupied by the data as "invalid”, that is, it can be overwritten. But this is only an operation at the file system 104 level, and the flash device 108 itself does not know which addresses of the data have been "invalid" until the operating system 102 notifies it that it is writing new data at these addresses.
  • the flash array 130 does not allow for overwriting, and can only be erased and rewritten first.
  • the memory controller 112 cannot know in advance which ones are “deleted” without the Trim mechanism.
  • the data page is already “invalid” and must be known to the operating system 102 when it is required to write data at the same location. This will not allow the best optimization at the most appropriate time, affecting the GC.
  • the efficiency affects the life of the flash array 130.
  • the cache 110 is used to store data such as a bad block table or a logical address to an "address mapping table" of a physical address at the time of startup, and the storage controller 112 stores the bad block table and the "address mapping table” and the like in the flash array 130 each time. After the restart, data such as a bad block table and an "address map" is loaded from the flash array 130 into the cache 110.
  • the flash array 130 can be divided into a plurality of blocks, and each block can be divided into a plurality of pages.
  • the data can be directly written in units of pages, erased and written in units of blocks. Need to erase before.
  • the flash array 130 may use a single-level cell (SLC) or a multi-level cell (MLC), wherein each SLC cell stores 1-bit information, and each MLC cell may store More than 1 bit of data. This embodiment of the present invention does not limit this.
  • FIG. 1 is merely exemplary participants of the system 100 and their interrelationships. Therefore, the depicted system 100 is greatly simplified, and the embodiments of the present invention are merely described in general terms.
  • the system 100 may include more or fewer components in actual use, and embodiments of the present invention are not implemented. Make any restrictions.
  • FIG. 2 is a schematic diagram showing the hardware structure of a memory controller 200 according to an embodiment of the invention.
  • the memory controller 200 includes a processor 202, a memory 204, an input/output interface 206, a communication interface 208, and a bus 210.
  • the processor 202, the memory 204, the input/output interface 206, and the communication interface 208 implement a communication connection with each other through the bus 210.
  • the processor 202 is a control center of the storage controller 200 for executing related programs to implement the technical solutions provided by the embodiments of the present invention.
  • the processor 202 can employ a general purpose central processor (Central Processing Unit, CPU), a microprocessor, an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits for executing related programs to implement the technical solution provided by the embodiments of the present invention.
  • a component for performing a specific function for example, the processor 202 or the memory 204, may be implemented by configuring a general-purpose component to perform a corresponding function, or may perform a specific function through a specific function.
  • the specific components are implemented, and this application does not limit this.
  • the memory 204 can be a read only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM).
  • the memory 204 can store an operating system and other applications.
  • the program code for implementing the technical solution provided by the embodiment of the present invention is stored in the memory 204 and executed by the processor 202.
  • the memory 204 can be integrated with or integrated with the processor 202, or it can be one or more memory units independent of the processor 202.
  • Program code for execution by processor 202 may be stored in flash memory or memory 204 coupled thereto.
  • the memory 204 is a RAM, and program code (eg, a communication module or an access control module, etc.) stored inside the flash memory is copied into the memory 204 for execution by the processor 202.
  • the memory 204 is further configured to store a bad block table, an address mapping table, or other mapping table according to an embodiment of the present invention. More specifically, when the system is started, the storage controller 200 stores a bad block table, an address mapping table, or the like stored in the flash memory. The mapping table is loaded into memory 204 for use by processor 202.
  • the memory 204 of the memory controller 200 includes an access control module, and the processor 202 executes the access control module program code to implement access to the flash memory device.
  • the memory 204 further includes one or more of the bad block management module 118, the wear balancing module 120, the address conversion module 122, the verification error correction module 124, and the garbage collection module 126 in the storage controller 112 of FIG. .
  • the input/output interface 206 is for receiving input data and information, and outputting data such as operation results.
  • Communication interface 208 implements communication between storage controller 200 and other devices or communication networks using transceivers such as, but not limited to, transceivers.
  • Bus 210 may include a path for communicating information between various components of memory controller 200, such as processor 202, memory 204, input/output interface 206, and communication interface 208.
  • the memory controller 200 shown in FIG. 2 only shows the processor 202, the memory 204, the input/output interface 206, the communication interface 208, and the bus 210, in a specific implementation process, Those skilled in the art will appreciate that the memory controller 200 also includes other devices necessary to achieve proper operation. In the meantime, those skilled in the art will appreciate that the memory controller 200 may also include hardware devices that implement other additional functions, depending on the particular needs. Moreover, those skilled in the art will appreciate that the memory controller 200 may also only include the components necessary to implement the embodiments of the present invention, and does not necessarily include all of the devices shown in FIG.
  • FIG. 2 and the foregoing description are applicable to the access device and system of various flash memory devices provided by the embodiments of the present invention, which are suitable for performing the access methods of various flash memory devices provided by the embodiments of the present invention.
  • the flash writes data in units of pages.
  • the time of a write operation mainly includes two parts: the data transfer time and the data write time (ie, the program operation).
  • the transmission time of one page of data on the bus is constant, and the time of the write operation depends mainly on the time of the programming operation.
  • the flash memory generally writes data by means of ISPP programming. To make the memory element reach a predetermined voltage, the programming voltage of each round is changed by gradually increasing the step voltage, and the memory element is charged until the memory element reaches a predetermined voltage value.
  • the stride voltage is fixed.
  • each iteration of the ISPP programming operation consists of two parts: programming and verification.
  • programming applies a programming voltage to the memory cell to increase the amount of charge in the memory cell, and each programming voltage is continued for a period of time in the memory cell.
  • Verification adds a smaller voltage to determine if the storage element has reached a predetermined value. If it is reached, the charging is completed and the programming is stopped; otherwise, the programming voltage is increased by one step voltage to continue charging the memory cell until the data is written.
  • Such an iterative process is proportional to the stride voltage.
  • the larger the stride voltage the smaller the number of iterations is required to reach the predetermined voltage value, so the programming time is inversely proportional to the stride voltage.
  • the programming time is inversely proportional to the stride voltage.
  • there is another relationship between the programmed step voltage and the error rate The larger the stride voltage, the worse the programming accuracy and the higher the subsequent error rate; the smaller the stride voltage, the better the programming accuracy and the lower the subsequent error rate. Therefore, the step voltage of the ISPP programming during the write operation affects the data error rate during subsequent read operations.
  • the format of the write operation of the flash memory device is divided according to the step voltage of the ISPP programming, and the write operation includes fast write and slow write, wherein the fast write write speed is greater than the slow write
  • the write speed that is, the step voltage of the ISPP programming of the fast write is greater than the step voltage of the ISPP programming of the slow write.
  • the write operation to the flash memory may further include a normal speed write, wherein the write speed of the normal write is greater than the write speed of the slow write, and is less than the write speed of the fast write, that is, the ISPP of the constant speed write.
  • the programmed step voltage is greater than the step voltage of the ISPP programming programmed for slow writing and less than the step voltage of the ISPP programming for fast writing.
  • fast write herein may refer to a fast write operation supported by a flash device
  • slow write may refer to a slow write operation supported by a flash device
  • normal write is a speed between “slow write”
  • the flash memory device supports the speed of at least two write operations, and the speed of the write operation is generally determined by the programming step voltage, and the corresponding step voltage is relatively fast.
  • the write operation, the programming step voltage is small corresponding to the slow write operation.
  • the fast write in this embodiment corresponds to the fastest or faster speed of the write operation speed of the flash device, the slow speed in this embodiment Write the slowest or slower speed of the write operation corresponding to the flash device.
  • fast write refers to a fast write operation
  • slow write refers to a slow speed.
  • write operation for flash devices that support more than two write speeds, fast write refers to the fastest or second fastest or relatively fast write operation, slow write refers to the slowest or slowest or relative Slow writes.
  • the time of a read operation mainly includes two parts: the read time from the data and the transfer time of the data. Among them, the reading time is positively correlated with the number of threshold voltages, and the transmission time is positively correlated with the amount of data transmitted. Assuming that there are N threshold voltages, the voltage value in the flash memory cell is divided into N+1 regions, then ceil (Log 2 (N+1)) bits are needed to represent N+1 voltage regions, wherein, read The time is positively correlated with N, the transmission time is positively correlated with ceil(Log 2 (N+1)), and ceil() is rounded up.
  • the LDPC code is used as the check code, and the unit memory element stores the 2 bit data for illustration.
  • the read operation scheme generally adopts the LDPC hard decision decoding first, and FIG. 4 is the threshold voltage distribution of the LDPC hard decision, and the adjacent two states There is only one threshold voltage between them, and there are a total of three threshold voltages between the four states.
  • the voltage of each memory cell of the read data page is compared with three threshold voltages to determine the memory cell.
  • the threshold voltage distribution of the soft decision is not limited to the example in FIG. 5, and the number of threshold voltages between adjacent two states is variable, which determines the error rate of data that can be tolerated by LDPC decoding, and the number of threshold voltages. The more you can correctly decode, the higher the error rate that can be tolerated.
  • the stride voltage of the slow write is small, and the data writing accuracy is high.
  • the correctness of reading data from the flash memory is higher, and it is easier to decode successfully, but write The input speed is slow; the fast write step voltage is large, the writing speed is fast, but the data writing accuracy is low.
  • the reading operation is performed, the correctness of reading data from the flash memory is relatively low, and the Multiple rounds of reading or iteration to accurately read the data in the flash.
  • the read operation form of the flash memory includes a fast read and a slow read, wherein the fast read read speed read is greater than the slow read read speed.
  • the number of read, ie fast read, threshold voltages is less than the number of slow read threshold voltages.
  • the read operation of the flash memory may further include a normal speed read, wherein the read speed read of the normal speed read is greater than the read speed read of the slow read, and is less than the fast read read speed read, that is, The number of threshold voltages for fast read is less than the number of threshold voltages for slow read and greater than the number of threshold voltages for fast read.
  • the flash memory device supports the speed of at least two read operations, and the speed of the read operation is generally determined by a number of threshold voltages between adjacent states, and a corresponding fast read operation with a small number of threshold voltages between adjacent states.
  • the number of threshold voltages between adjacent states corresponds to a slow read operation.
  • the fast read in this embodiment corresponds to the fastest or faster speed of the read operation speed of the flash memory device, and the slow read in this embodiment corresponds to the slowest or slower of the read operation speed of the flash memory device.
  • fast read refers to a fast read operation
  • slow read refers to a slow read operation
  • flash device that supports two or more read operations speeds
  • Read is the fastest or second fastest or relatively fast read operation
  • Slow read refers to the slowest or slowest or relatively slow read operation.
  • the access of the flash memory has certain characteristics. Mainly divided into the following three characteristics:
  • Read-only features Almost all visits that occurred on a single page of data for a period of time For read access, these read accesses have read-only features. For example, after a media file is written, the write access will not occur again, and it will only be read multiple times.
  • the embodiment of the invention realizes the adjustment of the write speed of the flash page according to the access feature of the flash page, so as to improve the reading of the flash memory.
  • the purpose of writing performance The specific method is described in the following examples.
  • FIG. 6 is a flow chart of a method 600 for accessing a flash memory device in accordance with an embodiment of the present invention.
  • access types to flash devices include write operations and read operations.
  • the write operations to flash devices include fast write and slow write, fast write write speeds are faster than slow write write speeds, and flash memory devices.
  • Read operations include fast read and slow read, fast read read speed read is faster than slow read read speed read.
  • method 600 includes:
  • S602 The storage controller receives an access request from an operating system.
  • the access request indicates the storage area to be accessed. Specifically, the access request carries the address information of the storage area to be accessed.
  • the address information is a logical address of a storage area to be accessed.
  • the storage area to be accessed in the embodiment of the present invention refers to a storage area indicated by a logical address. Because the flash memory of the flash memory cannot directly cover the original data, the old data must be erased before the new data can be written. Therefore, the address information of the embodiment of the present invention is the logical address of the to-be-accessed area, and is to be accessed for storage.
  • the area is associated with a logical address because the flash cannot be overwritten and the actual physical address corresponding to the same logical address can be changed.
  • the storage controller determines the access type of the access request. Among them, the access type of the flash device includes a write operation and a read operation. If the access type of the access request is a write operation, step S606 is performed, and if the access type of the access request is a read operation, step S616 is performed.
  • S606 The storage controller determines whether there is historical access information of the storage area to be accessed. If not, execute S608, if yes, execute step S610.
  • the storage controller searches for historical access information of the storage area to be accessed in the historical access record, where the historical access information includes the historical access type of the storage area to be accessed, and the historical access type is the to-be-accessed storage area is accessed before the current access request. Type of access.
  • the historical access information may record the previous historical access type of the to-be-accessed storage area. For example, one bit may be used for distinguishing, “0” indicates that the last historical access type is a write operation, and “1” indicates the last time.
  • the type of historical access operation is a read operation.
  • the historical access information may record the historical access type N times before the access to the storage area, where N is a positive integer greater than one.
  • N 2 bit bits
  • “00” indicates that the first two historical access types are write operations
  • "01” indicates that the first two historical access types are write and read operations in sequence
  • "10” indicates that the first two historical access types are read and write in sequence
  • "11” indicates that the first two historical access types are read operations.
  • N is another positive integer, and so on.
  • the "0" is used to indicate the write operation
  • the "1" is used to indicate the read operation.
  • the history access type may be recorded by using other representation methods. This is not limited.
  • the historical access information records the correspondence between the address information of the storage area and the historical access type, and the historical access information can be recorded in the address mapping table of the logical address to the physical address, so that redundant information can be saved. Record the space consumption of the address information of the storage area to be accessed.
  • the historical access information may be recorded separately.
  • the embodiment of the present invention does not limit the form of the historical access information.
  • the storage controller maintains a historical access information table, where the historical access information table includes historical access information entries corresponding to the plurality of effective address information, and the historical access information entry stores the correspondence between the address information of the storage area and the historical access type. .
  • the historical access information may be recorded by using the flash page as the granularity, or the historical access information may be recorded at a higher granularity by using other algorithms, which is not limited by the embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a historical access information entry according to an embodiment of the present invention.
  • the historical access information entry records the address information and the historical access type of the storage area to be accessed.
  • the storage controller records historical access information of the storage area to be accessed.
  • the storage controller does not find the historical access information of the storage area to be accessed in the historical access record, more specifically, if the storage controller does not find the historical access information entry corresponding to the address information in the historical access information table, The storage controller writes the data to be accessed to the storage area to be accessed, and records the historical access information of the storage area to be accessed in the historical access record, more specifically, Storage controller in historical visit A history access information entry is created in the question information table, and the history access type of the storage area to be accessed is set to a write operation.
  • the first write here refers to the first write access request to access the storage area, and refers to the first write of the access storage area from the "data invalid" state to the "data valid” state, when writing for the first time, Create a historical access information entry corresponding to the storage area to be accessed, and record its historical access type as a write operation.
  • the storage controller when the first write is performed, writes the data to be written into the to-be-accessed storage area in a form of slow write, wherein the form of the write operation includes slow write and fast write.
  • the subsequent access characteristics of the data are not known when writing, that is, whether the data is read-only, write-only, or cross-access. Therefore, when writing for the first time, it is possible to uniformly write the write data in a slow write format.
  • the form of the write operation may also include a normal speed write, and the initial write may also take the form of a normal write or a fast write, but the data may have a read-only characteristic, which is not conducive to the data read operation.
  • the embodiment of the present invention does not limit the form in which data is first written.
  • step S610 The storage controller determines whether the historical access type of the storage area to be accessed is a write operation. If yes, step S612 is performed; otherwise, step S614 is performed.
  • the storage controller determines whether the historical access type recorded in the historical access information entry corresponding to the storage area to be accessed is a write operation.
  • the historical access type is a write operation.
  • the history access type is a write operation. If the historical access type of the storage area to be accessed is a write operation, the access type of the access request is also a write operation, indicating that the access type is in the storage area to be accessed.
  • the data has a write-only feature. If the history access type is not all write operations, the historical access type is not a write operation.
  • the access type of the access request is a write operation, indicating that the data in the storage area to be accessed has cross-access characteristics.
  • the storage controller writes the data to be written into the storage area to be accessed in a fast write manner.
  • the historical access type of the storage area to be accessed is a write operation
  • the type of the access request is a write operation
  • the data to be written is written in a fast write form.
  • the historical access type is a write operation, and the access type of the access request is also a write operation
  • the current access request does not change the historical access type, and the historical access information may not be updated.
  • the historical access type in the historical access information entry remains unchanged.
  • the storage controller first modifies the address mapping table of the logical address to the physical address, and redirects the logical address to a The new physical address, and then write the data to be written to the new physical address.
  • the data in the original physical address is placed in the "invalid" state by the storage controller, and can be re-read after waiting for the subsequent garbage collection mechanism to erase. Write.
  • S614 The storage controller performs a write operation on the access storage area in a form of normal-speed writing, and updates historical access information of the storage area to be accessed.
  • the access storage area is written in a normal-speed write manner, thereby balancing the cost of reading and writing.
  • the storage controller may also perform a write operation on the access storage area in the form of slow write or fast write, but a slow write requires a large write cost, and a fast write requires a larger write. The cost of reading.
  • the history access type Since the history access type is not a write operation, and the access type of this access request is a write operation, the history access type needs to be updated. If only one bit is used to record the last historical access type, you only need to update the historical access type to a write operation. If the first N historical access types are recorded, you can use the "shift” method according to the actual situation. Update the history access type. For example, when N is 2, the history access type is marked as "11", indicating that the first two historical access types are read operations (write operation with "0", read operation with "1”), because this time is “0”, just change “11” to “10”.
  • S616 The storage controller performs a read operation on the access storage area.
  • the access memory area is read in a fast read manner.
  • a hard decision can be used, or a soft decision with a small number of threshold voltages between adjacent states can be used. If the decoding is successful, the read operation ends; if decoding is performed; If it is unsuccessful, the speed of the read operation is slowed down, the precision of the read operation is increased, re-reading is performed, and decoding is performed.
  • the hard decision can be turned into a soft decision, or the number of threshold voltages between adjacent states of the soft decision can be increased.
  • the storage controller may adopt LDPC as the check code, and the read operation may first adopt LDPC hard decision decoding. If the check succeeds, the read operation succeeds; if the check is unsuccessful, the decoding fails, and then the soft decision is used. Decoding is performed, if still unsuccessful, by sequentially increasing the number of threshold voltages between adjacent states of the soft decision until the information is correctly decoded.
  • step S618 The storage controller determines whether the historical access type of the storage area to be accessed is a read operation. If it is a read operation, step S622 is performed; otherwise, step S620 is performed.
  • the storage controller determines whether the historical access type recorded in the historical access information entry corresponding to the storage area to be accessed is a read operation.
  • the history access type is a read operation, which means that the history access type is all read operations. If the history access type is a read operation, because the type of the access request is also a read operation, the storage area to be accessed indicated by the address information has read-only access. If the historical access type is not all read operations, the historical access type is not a read operation, indicating that the to-be-accessed storage area indicated by the address information has cross-access characteristics.
  • S620 The storage controller updates historical access information.
  • the historical access type is not a read operation, and the access type of this access request is a read operation, the historical access type needs to be updated. If only one bit is used to record the last historical access type, you only need to update the historical access type to read. If the first N historical access types are recorded, you can use the "shift” method according to the actual situation. Update the history access type. For example, when N is 2, the history access type is marked with "00", indicating that the first two historical access types are write operations (write operation with "0", read operation with "1”), because this time is "1", just change "00" to "01".
  • step S622 The storage controller determines whether the fast read fails during the read operation, and if it fails, executes step S624, and if there is no failure, ends the process.
  • the historical access type of the storage area to be accessed is a read operation, and the type of the access request is a read operation, it indicates that the to-be-accessed storage area indicated by the address information has a read-only access feature, and most of the access to the to-be-accessed storage area is accessed. For read operations.
  • the storage controller fails to read in the form of fast read, indicating that the data stored in the storage area to be accessed is not accurate.
  • S624 The storage controller performs a rewriting operation on the access storage area in a form of slow writing.
  • the storage controller rewrites the to-be-accessed storage area in a slow write manner. To increase the speed of subsequent read operations on the memory area to be accessed. That is, in the case that the fast read decoding fails and the history access type is a read operation, the data saved in the storage area to be accessed is rewritten into the to-be-accessed storage area in the form of slow write.
  • the rewrite operation here refers to the rewriting of the logical address
  • the storage controller modifies the address mapping relationship of the logical address to the physical address, makes the logical address point to the new available physical address, and rewrites the data at the new physical address.
  • the original physical address is marked as "invalid" and will not be reused until it is subsequently erased.
  • the slow write form rewrites the data saved in the storage area to be accessed to the storage area to be accessed.
  • the storage controller may save the address information of the storage area to be accessed in the rewrite queue, and when idle, read from the storage area to be accessed according to the address information contained in the rewrite queue.
  • the data is fetched and the read data is rewritten into the to-be-accessed storage area in a slow write format.
  • the address information that needs to be rewritten may be organized into an LRU (Least Recently Used) linked list, and the LRU linked list is stored in the cache, and when the storage controller detects that the system is idle, the LRU linked list is read from the cache, and Obtaining the address information from the LRU linked list, reading the data to be rewritten corresponding to the address information, adjusting the stride voltage of the write operation, and rewriting the rewritten data to the flash memory in a slow write manner, and The logical address is removed from the rewrite queue.
  • LRU Least Recently Used
  • the storage controller may directly rewrite the storage area according to the successfully read data, thereby avoiding multiple readings of the data, but may block the flash memory. Normal access operation.
  • the storage controller When the storage controller determines that the data in the storage area to be accessed is invalid, the storage controller deletes the historical access information corresponding to the storage area to be accessed. For example, the storage controller may receive a deletion notification message from the operating system, where the deletion notification message is used to indicate that the data in the storage area to be accessed is invalid, and the storage controller deletes the historical access information item of the storage area to be accessed, and the storage area to be accessed From active to inactive.
  • the storage controller may also receive a Trim command, where the Trim command carries address information, which is used to indicate that the data on the address information is deleted by the operating system, and the storage controller may be in the history information table.
  • the historical access information bar corresponding to the address information The object is deleted, and the data on the physical block address corresponding to the address information is marked as "invalid", and the subsequent erasing operation is awaited.
  • the historical access information further includes a write speed flag for recording the speed of the write operation in detail
  • the storage controller may also establish a correspondence between the speed of the write operation and the speed of the read operation, and then the cross-access scene.
  • the memory area to be accessed is read according to the write speed flag, wherein the fast write corresponds to the slow read, and the slow write corresponds to the fast read.
  • the method 600 is only an exemplary description of the method of the flash memory device, wherein the specific steps may be performed in any order or may be combined.
  • the step numbers of the present invention are only for more clearly describing the flow of the solution, and are not limited. The order in which the steps are performed.
  • the data is divided into three categories: read-only, write-only, and cross-access, and the three types of data are distinguished by using the historical access type, thereby modulating the read-only feature data.
  • Speed slow write for fast read, thus greatly improving read performance with little impact on write performance; modulation writes only the speed of feature data, fast writes, greatly improving write performance with little impact on read performance; further It is also possible to modulate the speed of the cross-access characteristic data and perform constant-speed writing to balance the read/write speed.
  • FIG. 8 is a flow diagram of a method 800 of accessing a flash memory device in accordance with an embodiment of the present invention.
  • the historical access information further includes a write speed flag, and the write speed flag is used to record a form of the write operation, and is used to indicate whether the data saved in the storage area to be accessed is written in a slow write manner.
  • the storage controller can record whether the data is written in a slow write manner by using a bit write speed flag. For example, “0” indicates that the data is written in a slow write manner, “1”. Indicates that the data was not written in slow write.
  • FIG. 9 is a schematic diagram of a historical access information entry according to an embodiment of the present invention.
  • the historical access information entry records historical access information corresponding to the storage area to be accessed.
  • method 800 includes:
  • S802-S814 refers to steps S602-S614. Further, when the memory controller performs a write operation, it further records whether the form of the write operation is a slow write, or a detailed record write operation. For the speed grade, the rest is referred to S602-S614, and will not be described here.
  • step S816 The storage controller determines whether the historical access type of the storage area to be accessed is a read operation. If yes, step S820 is performed; otherwise, step S818 is performed.
  • step S618 For details, refer to step S618, and details are not described herein again.
  • step S620 For details, refer to step S620, and details are not described herein again.
  • step S820 The storage controller determines whether the form of the write operation is slow write, if yes, step S824 is performed, otherwise step S822 is performed.
  • the storage controller Determining whether the speed flag in the historical access information entry corresponding to the address information is a slow write, if it is a slow write, directly performing a read operation, and if it is not a slow write, indicating that the data cannot be quickly read, it is required Perform a slow rewrite operation on the to-be-accessed storage area.
  • S822 The storage controller performs a rewriting operation on the access storage area in a form of slow writing.
  • the controller needs to rewrite the to-be-accessed storage area in a slow write manner to improve the speed of subsequent read operations on the to-be-accessed storage area. That is, in the case that the historical access type of the storage area to be accessed is a read operation, and the write speed flag is not slow write, the data saved in the storage area to be accessed is rewritten into the storage area to be accessed in a slow write manner. .
  • step S624 For details, refer to step S624, and details are not described herein again.
  • the storage controller After the data saved in the storage area to be accessed is rewritten into the to-be-accessed storage area in the form of slow write, the storage controller updates the write speed flag to slow write.
  • S824 The storage controller performs a read operation on the to-be-accessed storage area indicated by the address information.
  • step S824 refers to step S616, and is described in this step.
  • the storage controller uses the write speed flag to record the speed of the write operation in detail, it is also possible to establish a correspondence between the speed of the write operation and the speed of the read operation, and perform a read operation on the storage area to be accessed according to the write speed flag, wherein, Write corresponds to slow read, slow write corresponds to fast read.
  • the write operation can be divided into three levels: slow write, constant speed write and fast write.
  • the read operation can be divided into three levels: fast read, normal speed read and slow read. Speed reading, constant speed writing corresponds to normal speed reading, fast writing corresponds to slow reading.
  • the storage controller may directly select the corresponding read operation to read according to the form of the write operation recorded in the historical access information.
  • the storage controller determines that the data in the storage area to be accessed is invalid, the storage controller deletes the historical access information corresponding to the storage area to be accessed.
  • the method 800 is only an exemplary description of the method of the flash memory device, wherein the specific steps may be performed in any order or may be combined.
  • the step numbers of the present invention are only for more clearly describing the flow of the solution, and are not limited. The order in which the steps are performed.
  • the data is divided into three categories: read-only, write-only, and cross-access, and the three types of data are distinguished by using the historical access type, thereby modulating the read-only feature data.
  • Speed slow write for fast read, thus greatly improving read performance with little impact on write performance; modulation writes only the speed of feature data, fast writes, greatly improving write performance with little impact on read performance; further It is also possible to modulate the speed of the cross-access characteristic data and perform constant-speed writing to balance the read/write speed.
  • FIG. 10 is a schematic diagram showing the logical structure of a flash memory device access device 1000 according to an embodiment of the present invention. As shown in FIG. 10, the device 1000 includes a receiving unit 1002, an obtaining unit 1004, and a writing unit 1006.
  • the receiving unit 1002 is configured to receive a first write access request to access the storage area.
  • the receiving unit 1002 can be implemented by the processor 202, the memory 204, and the communication interface 208 shown in FIG. More specifically, the communication module in processor 204 can be executed by processor 202 to cause communication interface 208 to receive a first write access request from an operating system.
  • the obtaining unit 1004 is configured to obtain a historical access type of the storage area to be accessed, where the historical access type is an access type to be accessed by the storage area to be accessed before the first write access request, where the access type to the flash device includes a write operation and a read operating.
  • the obtaining unit 1004 can be implemented by the processor 202 and the memory 204 shown in FIG. 2. More specifically, the access control module in the memory 204 can be executed by the processor 202 to obtain the historical access type of the storage area to be accessed according to the address information of the storage area to be accessed.
  • the writing unit 1006 is configured to write the data to be written of the first write access request into the storage area to be accessed in a fast write manner in a case where the historical access type of the storage area to be accessed is a write operation, wherein the flash memory is The format of the device's write operations includes fast write and slow write, fast write write speed Greater than the write speed of slow writes.
  • the writing unit 1006 can be implemented by the processor 202 and the memory 204 shown in FIG. 2. More specifically, the access control module in the memory 204 can be executed by the processor 202 to write the data to be written of the first write access request into the storage area to be accessed in a fast write form.
  • the obtaining unit 1004 is configured to obtain a historical access type of the to-be-accessed storage area, and the acquiring unit 1004 is configured to search for a historical access type of the to-be-accessed storage area recorded in the historical access record.
  • the receiving unit 1002 Before receiving the first write access request to access the storage area, the receiving unit 1002 is further configured to receive a second write access request to be accessed to the storage area, where the second write access request is a first write access request to the access storage area;
  • the 1006 is further configured to write the to-be-written data of the second write access request into the to-be-accessed storage area, and record the historical access type of the to-be-accessed storage area in the historical access record.
  • the writing unit 1006 is configured to write the data to be written of the second write access request into the storage area to be accessed, and the method includes: the writing unit 1006 is configured to write the data to be written of the second write access request in a form of slow writing. Access to the storage area.
  • the device 1000 further includes a deleting unit 1008.
  • the deleting unit 1008 is configured to delete the recorded historical access type of the to-be-accessed storage area.
  • the deleting unit 1008 can be implemented by the processor 202 and the memory 204 shown in FIG. 2. More specifically, the access control module in the memory 204 may be executed by the processor 202 to delete the recorded historical access type of the to-be-accessed storage area according to the deletion notification message received by the receiving unit 1002 from the operating system.
  • the writing unit 1006 is further configured to write the data to be written of the first write access request into the to-be-accessed storage area in a slow write manner in a case that the historical access type of the storage area to be accessed is not a write operation. And update the historical access type of the storage area to be accessed.
  • the form of the write operation further includes a normal speed write, wherein the write speed of the normal write is greater than the write speed of the slow write, and is less than the write speed of the fast write; the writing unit 1006 is further configured to be used in the storage to be accessed. If the historical access type of the area is not a write operation, the data to be written of the first write access request is written into the storage area to be accessed in the form of a normal write, and the historical access type of the storage area to be accessed is updated.
  • the functions of the obtaining unit 1004, the writing unit 1006, and the deleting unit 1008 of the embodiments of the present invention may be collected in the access controller module shown in FIG. 2, and the processor 202 performs different access control modules. Part, to achieve different functions, but in the specific implementation, you can The access controller module is further refined, which is not limited by the embodiment of the present invention.
  • the embodiment of the present invention is an apparatus embodiment of the storage controller 112, and the feature description of the embodiment of FIG. 6 and FIG. 8 is applicable to the embodiment of the present invention, and details are not described herein again.
  • FIG. 11 is a schematic diagram showing the logical structure of a flash memory device accessing device 1100 according to an embodiment of the present invention. As shown in FIG. 11, the device 1100 includes a receiving unit 1102, a reading unit 1104, an obtaining unit 1106, and a writing unit 1108, where
  • the receiving unit 1102 is configured to receive a read access request to access the storage area.
  • the receiving unit 1102 can be implemented by the processor 202, the memory 204, and the communication interface 208 shown in FIG. More specifically, the communication module in processor 204 can be executed by processor 202 to cause communication interface 208 to receive a read access request from an operating system.
  • the reading unit 1104 is configured to perform a read operation on the access storage area in a fast read form, wherein the read operation of the flash memory device includes a fast read and a slow read, and the read fast read of the fast read is greater than the slow read Read speed reading.
  • the reading unit 1104 can be implemented by the processor 202 and the memory 204 shown in FIG. 2. More specifically, the access control module in memory 204 can be executed by processor 202 to perform a read operation on the access memory area.
  • the obtaining unit 1106 is configured to obtain a historical access type of the storage area to be accessed, where the historical access type is an access type to be accessed by the storage area to be accessed before the read access request, wherein the access type to the flash device includes a write operation and a read operation.
  • the obtaining unit 1106 can be implemented by the processor 202 and the memory 204 shown in FIG. 2. More specifically, the access control module in the memory 204 can be executed by the processor 202 to obtain the historical access type of the storage area to be accessed according to the address information of the storage area to be accessed.
  • the writing unit 1108 is configured to rewrite the data saved in the storage area to be accessed into the to-be-accessed storage area by using a slow write format in the case that the fast read decoding fails and the historical access type is a read operation, where
  • the form of write operations to flash devices includes fast writes and slow writes, and write speeds for fast writes are greater than write speeds for slow writes.
  • the write unit 1108 can be implemented by the processor 202 and the memory 204 shown in FIG. 2. More specifically, the access control module in the memory 204 can be executed by the processor 202 to rewrite the data held in the storage area to be accessed into the to-be-accessed storage area in a slow write manner.
  • the obtaining unit 1106 is configured to obtain a historical access type of the storage area to be accessed, including: obtaining a single The element 1106 is used to find the historical access type of the to-be-accessed storage area recorded in the historical access record.
  • the receiving unit 1102 is further configured to receive a second write access request to access the storage area, where the second write access request is a first write access request to the access storage area; the writing unit 1108 further The data to be written of the second write access request is written into the storage area to be accessed, and the historical access type of the storage area to be accessed is recorded in the historical access record.
  • the writing unit 1108 is configured to write the data to be written of the second write access request into the storage area to be accessed, including: the writing unit 1108 is configured to write the data to be written of the second write access request in a form of slow writing. Access to the storage area.
  • the device 1100 further includes a deleting unit 1110: when determining that the data in the storage area to be accessed is invalid, the deleting unit 1110 is configured to delete the recorded historical access type of the to-be-accessed storage area.
  • the deleting unit 1110 can be implemented by the processor 202 and the memory 204 shown in FIG. 2. More specifically, the access control module in the memory 204 can be executed by the processor 202 to delete the recorded historical access type of the to-be-accessed storage area according to the deletion notification message received by the receiving unit 1102 from the operating system.
  • the reading unit 1104 is further configured to perform a read operation on the storage area to be accessed in the form of a slow read in the case that the fast read decoding fails.
  • the form of the read operation further includes a normal speed read, wherein the read speed read of the normal speed read is greater than the read speed read of the slow read, and is smaller than the read fast read of the fast read; the reading unit 1104 further uses In the case that the fast read decoding fails, the memory area to be accessed is read in the form of a normal speed read.
  • the write unit 1108 is also used to update the historical access type if the historical access type is not a read operation.
  • the writing unit 1108 rewrites the data saved in the storage area to be accessed into the to-be-accessed storage area in a slow write manner, and is further configured to save the address information of the to-be-accessed storage area in the rewrite queue;
  • the fetching unit 1104 is further configured to read data saved in the to-be-accessed storage area from the to-be-accessed storage area according to the address information saved in the rewrite queue.
  • the functions of the reading unit 1104, the obtaining unit 1106, the writing unit 1108, and the deleting unit 1110 of the embodiments of the present invention may be collected in the access controller module shown in FIG. 2, and executed by the processor 202. Accessing different parts of the control module to implement different functions, but in a specific implementation, the access controller module may be further refined, which is not limited by the embodiment of the present invention.
  • the embodiment of the present invention is an apparatus embodiment of the storage controller 112, and the special parts of the embodiment of FIG. 6 and FIG. The description is applicable to the embodiment of the present invention, and details are not described herein again.
  • FIG. 12 is a schematic diagram showing the logical structure of a flash memory device accessing apparatus 1200 according to an embodiment of the present invention. As shown in FIG. 12, the apparatus 1200 includes a receiving unit 1202, an obtaining unit 1204, and a writing unit 1206, where
  • the receiving unit 1202 is configured to receive a read access request to access the storage area.
  • the receiving unit 1202 can be implemented by the processor 202, the memory 204, and the communication interface 208 shown in FIG. More specifically, the communication module in processor 204 can be executed by processor 202 to cause communication interface 208 to receive a read access request from an operating system.
  • the obtaining unit 1204 is configured to obtain historical access information of the storage area to be accessed, where the historical access information includes a historical access type and a write speed flag of the storage area to be accessed, and the write speed flag is used to indicate the data saved in the storage area to be accessed.
  • the history access type is an access type to be accessed by the storage area to be accessed before the read access request, wherein the access type to the flash device includes a write operation and a read operation, and the form of the write operation to the flash memory device includes fast write With slow write, the write speed of fast write is greater than the write speed of slow write.
  • the obtaining unit 1204 can be implemented by the processor 202 and the memory 204 shown in FIG. 2. More specifically, the access control module in the memory 204 can be executed by the processor 202 to obtain historical access information of the storage area to be accessed according to the address information of the storage area to be accessed.
  • the write unit 1206 is configured to rewrite the data saved in the storage area to be accessed in a slow write manner when the history access type is a read operation and the write speed flag is not a slow write.
  • the storage area to be accessed is configured to rewrite the data saved in the storage area to be accessed.
  • the write unit 1206 can be implemented by the processor 202 and the memory 204 shown in FIG. 2. More specifically, the access control module in the memory 204 can be executed by the processor 202 to rewrite the data held in the storage area to be accessed into the to-be-accessed storage area in a slow write manner.
  • the obtaining unit 1204 is configured to obtain historical access information of the to-be-accessed storage area, and the acquiring unit 1204 is configured to search historical access information of the to-be-accessed storage area recorded in the historical access record.
  • the receiving unit 1202 is further configured to receive a second write access request to access the storage area, where the second write access request is a first write access request to the access storage area; the writing unit 1206 further The data to be written of the second write access request is written into the storage area to be accessed, and the historical access information of the storage area to be accessed is recorded in the historical access record.
  • the writing unit 1206 is configured to write the to-be-written data of the second write access request into the to-be-accessed storage area.
  • the field includes: the writing unit 1206 is configured to write the data to be written of the second write access request into the to-be-accessed storage area in a form of slow writing.
  • the device 1200 further includes a deleting unit 1208: when determining that the data in the storage area to be accessed is invalid, the deleting unit 1208 is configured to delete the historical access information of the recorded storage area to be accessed.
  • the deletion unit 1208 can be implemented by the processor 202 and the memory 204 shown in FIG. 2. More specifically, the access control module in the memory 204 can be executed by the processor 202 to delete the recorded historical access information of the to-be-accessed storage area according to the deletion notification message received by the receiving unit 1202 from the operating system.
  • the writing unit 1206 rewrites the data held in the storage area to be accessed to the storage area to be accessed in the form of slow writing, and is also used to update the writing speed flag to slow writing.
  • the device 1200 further includes a reading unit 1210; the reading operation includes a fast reading and a slow reading, and after the obtaining unit 1204 acquires the historical access information of the storage area to be accessed, the reading unit 1210 is configured to perform the storage area to be accessed according to the writing speed flag.
  • the reading unit 1210 can be implemented by the processor 202 and the memory 204 shown in FIG. 2. More specifically, the access control module in memory 204 can be executed by processor 202 to perform a read operation on the memory area to be accessed in accordance with the write speed.
  • the writing unit 1206 rewrites the data saved in the storage area to be accessed into the to-be-accessed storage area in a slow write manner, and is further configured to save the address information of the to-be-accessed storage area in the rewrite queue;
  • the fetching unit 1210 is configured to read data saved in the to-be-accessed storage area from the to-be-accessed storage area according to the address information saved in the rewrite queue.
  • the functions of the obtaining unit 1204, the writing unit 1206, the deleting unit 1208, and the reading unit 1210 of the embodiments of the present invention may be collected in the access controller module shown in FIG. 2 and executed by the processor 202. Accessing different parts of the control module to implement different functions, but in a specific implementation, the access controller module may be further refined, which is not limited by the embodiment of the present invention.
  • the embodiment of the present invention is an apparatus embodiment of the storage controller 112, and the feature description of the embodiment of FIG. 6 and FIG. 8 is applicable to the embodiment of the present invention, and details are not described herein again.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the modules is only a logical function division, and may be implemented when implemented. Additional partitioning, such as multiple modules or components, may be combined or integrated into another system, or some features may be omitted or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or module, and may be electrical, mechanical or otherwise.
  • the modules described as separate components may or may not be physically separated.
  • the components displayed as modules may or may not be physical modules, that is, may be located in one place, or may be distributed to multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.
  • the above integrated modules can be implemented in the form of hardware or in the form of hardware plus software function modules.
  • the above-described integrated modules implemented in the form of software function modules can be stored in a computer readable storage medium.
  • the software functional modules described above are stored in a storage medium and include instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform some of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a removable hard disk, a read only memory, a random access memory, a magnetic disk, or an optical disk, and the like, which can store program codes.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Memory System (AREA)

Abstract

本发明实施例提供了一种闪存设备的访问方法和装置，实现对闪存设备的访问效率的优化。该方法包括：存储控制器接收访问请求；存储控制器获取待访问存储区域的历史访问信息，其中，历史访问信息中包含对待访问存储区域的历史访问类型，对闪存设备访问的访问类型包括写操作和读操作；存储控制器根据历史访问信息和该访问请求的访问类型，对待访问存储区域进行访问操作。将数据分为只读、只写和交叉访问三类，并利用历史访问信息和本次访问请求的访问类型，对三类数据进行区分，从而加快只读数据的读取速读，加快只写数据的写入速度，从而在提升对闪存设备的整体访问效率。

Description

一种闪存设备的访问方法和装置 技术领域
本发明实施例涉及计算机领域，尤其涉及一种闪存设备的访问方法和装置。
背景技术
由于良好的随机访问性能、低密度、低功耗等优点，基于闪存的固态硬盘(Solid State Drive，SSD)已经逐步取代传统磁盘，成为重要的存储介质。近年来，闪存技术迅速发展，存储密度由单比特存储元发展到最近的多比特存储元，如6比特，制造工艺由65纳米展到最近的10纳米。这些发展使得闪存的存储密度快速增加，同时也使得闪存的可靠性大大降低，因此需要纠错能力更强的纠错码来正确编码和译码数据。
为了解决闪存的可靠性问题，当前普遍采用的解决方案是使用低密度奇偶校验码(Low Density Parity Check Code，LDPC)纠错机制。LDPC译码通过置信传播算法实现，分为硬判决译码和软判决译码。硬判决译码效率高，所需读取和译码时间短，但只能对错误率低的数据译码。软判决能对错误率更高的数据实现正确的译码，但需要更长的读取和译码时延。使用LDPC作为校验码时，读请求时间和错误率存在关联，对高错误率的数据读请求所需时间更长。
闪存采用增量阶跃脉冲编程(Incremental Step Pulse Programming，ISPP)的方式写入数据，要使得存储元达到预定的电压，通过逐步增加编程电压的方式，写数据时的编程步幅电压，即编程电压的单位变化幅度，很大程度上决定数据的错误率。编程步幅电压越大，需要迭代较少的次数就能达到预定电压值。但编程步幅电压越大，编程精确性越差，错误率越高。由此可以得出写入时，编程速度越快，错误率越高；编程速度越慢，错误率越低。
闪存的存储是通过向闪存存储元充一定量的电荷来表示数据，而随着保存时间的增加，存储元的电荷会流出，即漏电。保存时间越长，漏电越多，则错误率越高。现有技术中，可以根据闪存中数据的保存时间，来对数据的写操作进行调制，如果需要保存的时间长，则采用慢速写的形式进行写操作， 数据慢速写入错误率低，以保证能正确读出；如果需要保存的时间短，数据因保存时间漏电带来的错误率相对较低，则可以采用快速写的形式进行写操作。现有技术在进行读操作的时候，先采用硬判决，如果硬判决译码失败，则转为软判决。
现有技术中，无法对闪存的读写操作进行灵活有效的调节，需要开发新的技术来解决这一问题。
发明内容
有鉴于此，本发明公开了一种闪存设备的访问方法和装置。根据数据的访问特征，对闪存设备的读写操作进行调制，提高闪存设备访问的整体性能。
第一方面，本申请提供了一种闪存设备的访问方法，其中，对闪存设备的访问的访问类型包括写操作和读操作，该方法包括：存储控制器接收访问请求，该访问请求指示待访问存储区域，例如在访问请求中携带待访问存储区域的地址信息；存储控制器获取待访问存储区域的历史访问信息，其中，历史访问信息中包含对待访问存储区域的历史访问类型；存储控制器根据历史访问信息和本次访问请求的访问类型，对待访问存储区域进行访问操作。
闪存中数据的读写速度之间可以根据错误率建立起关系。闪存存储系统中，数据在写入时编程速度快，错误率高，则对该数据的读速度慢；反之，数据在写入时编程速度慢，错误率低，则对该数据的读速度快。可以根据读操作和写操作之间的内在联系，实现对闪存设备的调制。
结合第一方面，在第一方面第一种可能的实现方式中，如果历史访问类型为写操作，且本次访问请求的访问类型为写操作，则存储控制器对待访问存储区域进行访问操作，包括：存储控制器采用快速写的形式对待访问存储区域进行写操作，其中，写操作的形式包括快速写和慢速写，快速写的写入速度大于慢速写的写入速度。
如果历史访问类型和本次访问请求的访问类型均为写操作，则说明待访问存储区域中保存的数据具有“只写”特性，对该待访问存储区域的写操作的频率远远大于读操作的频率，所以可以采用快速写的形式对该待访问存储区域进行写操作，从而在整体上提升了对闪存设备的访问速度。
结合第一方面，在第一方面第二种可能的实现方式中，如果历史访问类型为读操作，且本次访问请求的访问类型为读操作，则存储控制器对待访问 存储区域进行访问操作，包括：存储控制器采用快速读的形式对待访问存储区域进行读操作，如果快速读译码失败，则采用慢速读的形式对待访问存储区域重新进行读取，并采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域，其中，存储控制器的读操作的形式包括快速读和慢速读，快速读的读取速度大于慢速读的读取速度。
如果历史访问类型和本次访问请求的访问类型均为读操作，则说明待访问存储区域中保存的数据具有“只读”特性，对该待访问存储区域的读操作的频率远远大于写操作的频率，所以如果对待访问存储区域采用快速读的形式译码失败，则说明其中保存的数据精确度不够，则采用慢速写的形式将待访问存储区域中保存的数据重新写入该待访问存储区域，从而保证数据的精确性，以加快后续对该待访问存储区域的读操作，从而在整体上提升了对闪存设备的访问速度。
可选的，在另外一种可能的实现方式中，如果待访问存储区域中的数据具有只读特性，在读操作时译码的误码率超过预设的阈值的情况下，采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域。
结合第一方面，在第一方面第三种可能的实现方式中，历史访问信息中还包含写入速度标记，写入速度标记用于指示待访问存储区域中数据的写操作的形式；如果历史访问和本次访问请求的访问类型均为读操作，且写入速度标记不是慢速写，该方法还包括：存储控制器采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域。
写入速度标记主要用于指示待访问存储区域中保存的数据是否是以慢速写的形式写入，如果待访问存储区域中保存的数据不是采用慢速写的形式写入，则在很大程度上说明待访问存储区域中保存的数据的精确度不够，如果该数据具有“只读”特性，则采用慢速写的形式将待访问存储区域中保存的数据重新写入该待访问存储区域，从而保证数据的精确性，以加快后续对该待访问存储区域的读操作，从而在整体上提升了对闪存设备的访问速度。
结合第一方面或第一方面以上任一种可能的实现方式，在第一方面第四种可能的实现方式中，存储控制器采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域之前，该方法还包括：存储控制器将地址信息保存于重写队列；存储控制器根据重写队列中保存的地址信息，从待访问存储区域中读取待访问存储区域保存的数据。
将需要重写的待访问存储区域的地址信息写入一个重写队列，当闪存设备空闲或负载较小时再进行重写操作，从而避免了重写操作对正常的读写访问的阻塞。
可选的，也可以在本次读操作结束后，直接将读出的数据重写到待访问的存储区域，从而避免了后续重新读取带来的消耗。
结合第一方面或第一方面以上任一种可能的实现方式，在第一方面第五种可能的实现方式中，写操作的形式还包括常速写，其中，常速写的写入速度大于慢速写的写入速度，且小于快速写的写入速度；如果历史访问类型不是写操作，且本次访问请求的访问类型为写操作，则存储控制器对待访问存储区域进行访问操作，包括：存储控制器采用常速写的形式对待访问存储区域进行写操作。
如果历史访问类型不是写操作，且本次访问请求的访问类型为写操作，则说明待访问存储区域中保存的数据具有“交叉访问”特性，说明对待访问存储区域的读操作和写操作的频率相当，则可以采用常速写的形式对待访问存储区域进行写操作，从而平衡了读操作和写操作的速度，在整体上提升了对闪存设备的访问速度。
结合第一方面或第一方面以上任一种可能的实现方式，在第一方面第六种可能的实现方式中，历史访问信息中还包含写入速度标记；如果本次访问请求的访问类型为读操作，则存储控制器根据历史访问信息和访问请求的访问类型，对待访问存储区域进行访问操作，包括：存储控制器根据写入速度标记对待访问的存储区域进行读操作，其中，快速写对应慢速读，慢速写对应快速读。
根据待访问存储区域中数据写操作的形式，采用相应的读操作的形式，可以在一定程度上减少读操作的时间，在整体上提升了对闪存设备的访问速度。
结合第一方面或第一方面以上任一种可能的实现方式，在第一方面第七种可能的实现方式中，如果历史访问类型与本次访问请求的访问类型不相同，该方法还包括：存储控制器根据本次访问请求的访问类型更新历史访问类型。
进一步的，如果历史访问信息中包含写入速度标记，且本次访问请求的访问类型为写操作，若本次写操作的形式与历史访问信息中的写入速度标记指示的形式不同，则还需要更新写入速度标记。
结合第一方面或第一方面以上任一种可能的实现方式，在第一方面第八种可能的实现方式中，存储控制器获取待访问存储区域的历史访问信息，包括：存储控制器查找历史访问记录中记录的待访问存储区域的历史访问信息。例如，可以根据待访问存储区域的地址信息查找与待访问存储区域对应的历史访问信息条目，历史访问信息条目中包含对待访问存储区域的历史访问信息。
结合第一方面或第一方面以上任一种可能的实现方式，在第一方面第九种可能的实现方式中，存储控制器接收该访问请求之前，该方法还包括：存储控制器接收第二写访问请求，第二写访问请求为对待访问存储区域的首次写访问请求；存储控制器将第二写访问请求的待写入数据写入待访问存储区域，并在历史访问记录中记录待访问存储区域的历史访问信息。具体的，第二写访问请求待访问存储区域的地址信息，存储控制器根据该地址信息，在历史访问记录中创建与地址信息对应的历史访问信息条目。
第二写访问请求为对待访问存储区域从“数据无效”状态到“数据有效”状态的首次写入，在首次写入的时候，记录待访问存储区域的历史访问信息，例如，创建与待访问存储区域对应的历史访问信息条目，并将其历史访问类型记录为写操作。
结合第一方面或第一方面以上任一种可能的实现方式，在第一方面第十种可能的实现方式中，存储控制器将第二写访问请求的待写入数据写入待访问存储区域，包括：存储控制器采用慢速写的形式将第二写访问请求的待写入数据写入待访问存储区域。
第二写访问请求为对待访问存储区域从“数据无效”状态到“数据有效”状态的首次写入，因为不能确定写入的数据的访问类型是否是“只读”特性，所以首次写入采用慢速写的形式进行写入。当然也可以采用其实形式的写操作。
结合第一方面或第一方面以上任一种可能的实现方式，在第一方面第十一种可能的实现方式中，方法还包括：存储控制器在确定待访问存储区域中的数据失效时，将记录的待访问存储区域的历史访问信息删除。例如，存储控制器接收删除通知消息，删除通知消息中携带地址信息；存储控制器根据删除通知消息，待访问存储区域的历史访问信息删除。
具体的，删除通知消息可以为Trim指令，用于指示用户将待访问存储区 域的数据删除，从而使存储控制器将待访问存储区域的地址信息置为无效，以方便后续的垃圾回收。
第二方面，本申请提供了一种闪存设备的访问方法，其中，对闪存设备的访问类型包括写操作和读操作，对闪存设备的写操作的形式包括快速写和慢速写，快速写的写入速度大于慢速写的写入速度，该方法包括：接收对待访问存储区域的第一写访问请求，第一访问请求中携带待访问存储区域的地址信息；根据该地址信息，获取待访问存储区域的历史访问类型，历史访问类型为在第一写访问请求之前待访问存储区域被访问的访问类型；在待访问存储区域的历史访问类型为写操作的情况下，采用快速写的形式将第一写访问请求的待写入数据写入待访问存储区域。
如果待访问存储区域的历史访问类型和本次访问请求的访问类型均为写操作，则说明待访问存储区域中保存的数据具有“只写”特性，则对该待访问存储区域的写操作的频率远远大于读操作的频率，所以采用快速写的形式对该待访问存储区域进行写操作，从而在整体上提升了对闪存设备的访问速度。
结合第二方面，在第二方面第一种可能的实现方式中，获取待访问存储区域的历史访问类型，包括：查找历史访问记录中记录的待访问存储区域的历史访问类型。
具体的，可以维护一个历史访问信息表，历史访问信息表中记录有每一个数据有效的地址信息对应的历史访问信息条目，历史访问信息条目中记录有待访问存储区域的历史访问类型。
结合第二方面或第二方面以上任一种可能的实现方式，在第二方面第二种可能的实现方式中，接收对待访问存储区域的第一写访问请求之前，该方法还包括：接收对待访问存储区域的第二写访问请求，第二写访问请求为对待访问存储区域的首次写访问请求；将第二写访问请求的待写入数据写入待访问存储区域，并在历史访问记录中记录待访问存储区域的历史访问类型。
第二写访问请求为对待访问存储区域从“数据无效”状态到“数据有效”状态的首次写入，在首次写入的时候，创建与待访问存储区域对应的历史访问信息条目，并将其历史访问类型记录为写操作。
结合第二方面或第二方面以上任一种可能的实现方式，在第二方面第三种可能的实现方式中，将第二写访问请求的待写入数据写入待访问存储区域， 包括：采用慢速写的形式将第二写访问请求的待写入数据写入待访问存储区域。
第二写访问请求为对待访问存储区域从“数据无效”状态到“数据有效”状态的首次写入，因为不能确定写入的数据的访问类型是否是“只读”特性，所以首次写入采用慢速写的形式进行写入。当然，首次写入时也可以采用其实形式的写操作。
结合第二方面或第二方面以上任一种可能的实现方式，在第二方面第四种可能的实现方式中，该方法还包括：在确定待访问存储区域中的数据失效时，将记录的待访问存储区域的历史访问类型删除。
具体的，可以在接收到操作系统的Trim指令时，将与待访问存储区域对应的历史访问信息条目删除，Trim指令表明当前待访问存储区域的数据已经被操作系统删除。
结合第二方面或第二方面以上任一种可能的实现方式，在第二方面第五种可能的实现方式中，该方法还包括：在待访问存储区域的历史访问类型不是写操作的情况下，采用慢速写的形式将第一写访问请求的待写入数据写入待访问存储区域，并更新待访问存储区域的历史访问类型。
具体的，若历史访问信息条目中记录了不止一次历史访问类型，只要其中有一种不是写操作，则均认为历史访问类型不是写操作，只有记录的所有历史访问类型均为写操作的时候才认为历史访问类型为写操作。
结合第二方面或第二方面以上任一种可能的实现方式，在第二方面第六种可能的实现方式中，写操作的形式还包括常速写，其中，常速写的写入速度大于慢速写的写入速度，且小于快速写的写入速度；该方法还包括：在待访问存储区域的历史访问类型不是写操作的情况下，采用常速写的形式将第一写访问请求的待写入数据写入待访问存储区域，并更新待访问存储区域的历史访问类型。
如果历史访问类型不是写操作，且本次访问请求的访问类型为写操作，则说明待访问存储区域中保存的数据具有“交叉访问”特性，说明对待访问存储区域的读操作和写操作的频率相当，则可以采用常速写的形式对待访问存储区域进行写操作，从而平衡了读操作和写操作的速度，在整体上提升了对闪存设备的访问速度。
第三方面，本申请提供了一种闪存设备的访问方法，其中，对闪存设备 的访问类型包括写操作和读操作，对闪存设备的写操作的形式包括快速写和慢速写，快速写的写入速度大于慢速写的写入速度，对闪存设备的读操作的形式包括快速读和慢速读，快速读的读取速读大于慢速读的读取速读，该方法包括：接收对待访问存储区域的读访问请求；采用快速读的形式对待访问存储区域进行读操作；获取待访问存储区域的历史访问类型，历史访问类型为在读访问请求之前待访问存储区域被访问的访问类型，在快速读译码失败，且历史访问类型为读操作的情况下，采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域。
如果历史访问类型和本次访问请求的访问类型均为读操作，则说明待访问存储区域中保存的数据具有“只读”特性，对该待访问存储区域的读操作的频率远远大于写操作的频率，所以如果对待访问存储区域采用快速读的形式译码失败，则说明其中保存的数据精确度不够，则采用慢速写的形式将待访问存储区域中保存的数据重新写入该待访问存储区域，从而保证数据的精确性，以加快后续对该待访问存储区域的读操作，从而在整体上提升了对闪存设备的访问速度。
可选的，在另外一种可能的实现方式中，如果待访问存储区域中的数据具有只读特性，在读操作时译码的误码率超过预设的阈值的情况下，采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域。
结合第三方面，在第三方面第一种可能的实现方式中，获取待访问存储区域的历史访问类型，包括：查找历史访问记录中记录的待访问存储区域的历史访问类型。
具体的，可以维护一个历史访问信息表，历史访问信息表中记录有每一个数据有效的地址信息对应的历史访问信息条目，历史访问信息条目中记录有待访问存储区域的历史访问类型。
结合第三方面或第三方面以上任一种可能的实现方式，在第三方面第二种可能的实现方式中，接收对待访问存储区域的读访问请求之前，该方法还包括：接收对待访问存储区域的第二写访问请求，第二写访问请求为对待访问存储区域的首次写访问请求；将第二写访问请求的待写入数据写入待访问存储区域，并在历史访问记录中记录待访问存储区域的历史访问类型。
第二写访问请求为对待访问存储区域从“数据无效”状态到“数据有效”状态的首次写入，在首次写入的时候，创建与待访问存储区域对应的历史访 问信息条目，并将其历史访问类型记录为写操作。
结合第三方面或第三方面以上任一种可能的实现方式，在第三方面第三种可能的实现方式中，将第二写访问请求的待写入数据写入待访问存储区域，包括：采用慢速写的形式将第二写访问请求的待写入数据写入待访问存储区域。
第二写访问请求为对待访问存储区域从“数据无效”状态到“数据有效”状态的首次写入，因为不能确定写入的数据的访问类型是否是“只读”特性，所以首次写入采用慢速写的形式进行写入。当然，首次写入时也可以采用其实形式的写操作。
结合第三方面或第三方面以上任一种可能的实现方式，在第三方面第四种可能的实现方式中，该方法还包括：在确定待访问存储区域中的数据失效时，将记录的待访问存储区域的历史访问类型删除。
具体的，可以在接收到操作系统的Trim指令时，将与待访问存储区域对应的历史访问信息条目删除，Trim指令表明当前待访问存储区域的数据已经被操作系统删除。
结合第三方面或第三方面以上任一种可能的实现方式，在第三方面第五种可能的实现方式中，该方法还包括：在快速读译码失败的情况下，采用慢速读的形式对待访问的存储区域进行读操作。
结合第三方面或第三方面以上任一种可能的实现方式，在第三方面第六种可能的实现方式中，读操作的形式还包括常速读，其中，常速读的读取速读大于慢速读的读取速读，且小于快速读的读取速读；该方法还包括：在快速读译码失败的情况下，采用常速读的形式对待访问的存储区域进行读操作。
具体的，如果快速读译码失败，则通过增加不同状态间阈值电压数目的形式，对待访问存储区域进行更精确的读，从而增加译码的成功率。
结合第三方面或第三方面以上任一种可能的实现方式，在第三方面第七种可能的实现方式中，该方法还包括：在历史访问类型不是读操作的情况下，更新历史访问类型。
具体的，若历史访问信息条目中记录了不止一次历史访问类型，只要其中有一种不是读操作，则均认为历史访问类型不是读操作，只有记录的所有历史访问类型均为读操作的时候才认为历史访问类型为读操作。
结合第三方面或第三方面以上任一种可能的实现方式，在第三方面第八 种可能的实现方式中，采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域之前，该方法还包括：将待访问存储区域的地址信息保存于重写队列；根据重写队列中保存的地址信息，从待访问存储区域中读取待访问存储区域保存的数据。
将需要重写的待访问存储区域的地址信息写入一个重写队列，当闪存设备空闲或负载较小时再进行重写操作，从而避免了重写操作对正常的读写访问的阻塞。
可选的，也可以在本次读操作结束后，直接将读出的数据重写到待访问的存储区域，从而避免了后续重新读取带来的消耗。
第四方面，本申请提供了一种闪存设备的访问方法，其中，对闪存设备的访问类型包括写操作和读操作，对闪存设备的写操作的形式包括快速写和慢速写，快速写的写入速度大于慢速写的写入速度，该方法包括：接收对待访问存储区域的读访问请求；获取待访问存储区域的历史访问信息，历史访问信息中包含待访问存储区域的历史访问类型和写入速度标记，写入速度标记用于指示待访问存储区域中保存的数据的写操作的形式，历史访问类型为在读访问请求之前待访问存储区域被访问的访问类型；在历史访问类型为读操作，且写入速度标记不是慢速写的情况下，采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域。
写入速度标记主要用于指示待访问存储区域中保存的数据是否是以慢速写的形式写入，如果待访问存储区域中保存的数据不是采用慢速写的形式写入，则在很大程度上说明待访问存储区域中保存的数据的精确度不够，如果该数据具有“只读”特性，则采用慢速写的形式将待访问存储区域中保存的数据重新写入该待访问存储区域，从而保证数据的精确性，以加快后续对该待访问存储区域的读操作，从而在整体上提升了对闪存设备的访问速度。
结合第四方面，在第四方面第一种可能的实现方式中，获取待访问存储区域的历史访问信息，包括：查找历史访问记录中记录的待访问存储区域的历史访问信息。
具体的，可以维护一个历史访问信息表，历史访问信息表中记录有每一个数据有效的地址信息对应的历史访问信息条目，历史访问信息条目中记录有待访问存储区域的历史访问信息。
结合第四方面或第四方面以上任一种可能的实现方式，在第四方面第二 种可能的实现方式中，接收对待访问存储区域的读访问请求之前，该方法还包括：接收对待访问存储区域的第二写访问请求，第二写访问请求为对待访问存储区域的首次写访问请求；将第二写访问请求的待写入数据写入待访问存储区域，并在历史访问记录中记录待访问存储区域的历史访问信息。
第二写访问请求为对待访问存储区域从“数据无效”状态到“数据有效”状态的首次写入，在首次写入的时候，创建与待访问存储区域对应的历史访问信息条目，并将其历史访问类型记录为写操作。
结合第四方面或第四方面以上任一种可能的实现方式，在第四方面第三种可能的实现方式中，将第二写访问请求的待写入数据写入待访问存储区域，包括：采用慢速写的形式将第二写访问请求的待写入数据写入待访问存储区域。
第二写访问请求为对待访问存储区域从“数据无效”状态到“数据有效”状态的首次写入，因为不能确定写入的数据的访问类型是否是“只读”特性，所以首次写入采用慢速写的形式进行写入。当然，首次写入时也可以采用其实形式的写操作。
结合第四方面或第四方面以上任一种可能的实现方式，在第四方面第四种可能的实现方式中，该方法还包括：在确定待访问存储区域中的数据失效时，将记录的待访问存储区域的历史访问信息删除。
具体的，可以在接收到操作系统的Trim指令时，将与待访问存储区域对应的历史访问信息条目删除，Trim指令表明当前待访问存储区域的数据已经被操作系统删除。
结合第四方面或第四方面以上任一种可能的实现方式，在第四方面第五种可能的实现方式中，采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域之后，该方法还包括：将写入速度标记更新为慢速写。
结合第四方面或第四方面以上任一种可能的实现方式，在第四方面第六种可能的实现方式中，获取待访问存储区域的历史访问信息之后，该方法还包括：根据写入速度标记对待访问的存储区域进行读操作，其中，快速写对应慢速读，慢速写对应快速读。
根据待访问存储区域中数据写操作的形式，采用相应的读操作的形式，可以在一定程度上减少读操作的时间，在整体上提升了对闪存设备的访问速度。
结合第四方面或第四方面以上任一种可能的实现方式，在第四方面第七种可能的实现方式中，采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域之前，该方法还包括：将待访问存储区域的地址信息保存于重写队列；根据重写队列中保存的地址信息，从待访问存储区域中读取待访问存储区域保存的数据。
将需要重写的待访问存储区域的地址信息写入一个重写队列，当闪存设备空闲或负载较小时再进行重写操作，从而避免了重写操作对正常的读写访问的阻塞。
可选的，也可以在本次读操作结束后，直接将读出的数据重写到待访问的存储区域，从而避免了后续重新读取带来的消耗。
第五方面，本申请提供了一种可读介质，包括执行指令，当存储控制器的处理器执行执行指令时，该存储控制器执行以上任一方面或以上任一方面的任一种可能的实现方式中的方法。
第六方面，本申请提供了一种存储控制器，包括：处理器、存储器和总线；存储器用于存储执行指令，处理器与存储器通过总线连接，当存储控制器运行时，处理器执行存储器存储的执行指令，以使存储控制器执行以上任一方面或以上任一方面的任一种可能的实现方式中的方法。
第七方面，本申请提供了一种闪存设备的访问装置，其中，对闪存设备的访问类型包括写操作和读操作，对闪存设备的写操作的形式包括快速写和慢速写，快速写的写入速度大于慢速写的写入速度，该装置包括：接收单元，用于接收对待访问存储区域的第一写访问请求；获取单元，用于获取待访问存储区域的历史访问类型，历史访问类型为在第一写访问请求之前待访问存储区域被访问的访问类型；写入单元，用于在待访问存储区域的历史访问类型为写操作的情况下，采用快速写的形式将第一写访问请求的待写入数据写入待访问存储区域。
结合第七方面，在第七方面第一种可能的实现方式中，获取单元用于获取待访问存储区域的历史访问类型，包括：获取单元用于查找历史访问记录中记录的待访问存储区域的历史访问类型。
结合第七方面或第七方面以上任一种可能的实现方式，在第七方面第二种可能的实现方式中，接收单元接收对待访问存储区域的第一写访问请求之前，还用于接收对待访问存储区域的第二写访问请求，第二写访问请求为对 待访问存储区域的首次写访问请求；写入单元还用于将第二写访问请求的待写入数据写入待访问存储区域，并在历史访问记录中记录待访问存储区域的历史访问类型。
结合第七方面或第七方面以上任一种可能的实现方式，在第七方面第三种可能的实现方式中，写入单元用于将第二写访问请求的待写入数据写入待访问存储区域，包括：写入单元用于采用慢速写的形式将第二写访问请求的待写入数据写入待访问存储区域。
结合第七方面或第七方面以上任一种可能的实现方式，在第七方面第四种可能的实现方式中，该装置还包括删除单元；在确定待访问存储区域中的数据失效时，删除单元用于将记录的待访问存储区域的历史访问类型删除。
结合第七方面或第七方面以上任一种可能的实现方式，在第七方面第五种可能的实现方式中，写入单元还用于在待访问存储区域的历史访问类型不是写操作的情况下，采用慢速写的形式将第一写访问请求的待写入数据写入待访问存储区域，并更新待访问存储区域的历史访问类型。
结合第七方面或第七方面以上任一种可能的实现方式，在第七方面第六种可能的实现方式中，写操作的形式还包括常速写，其中，常速写的写入速度大于慢速写的写入速度，且小于快速写的写入速度；写入单元还用于在待访问存储区域的历史访问类型不是写操作的情况下，采用常速写的形式将第一写访问请求的待写入数据写入待访问存储区域，并更新待访问存储区域的历史访问类型。
第七方面为第二方面方法对应的装置实现方式，所以第二方面或第二方面任一种可能的实现方式中的描述对应适用于第七方面或第七方面任一种可能的实现方式，在此不再赘述。
第八方面，本申请提供了一种闪存设备的访问装置，其中，对闪存设备的访问类型包括写操作和读操作，对闪存设备的写操作的形式包括快速写和慢速写，快速写的写入速度大于慢速写的写入速度，对闪存设备的读操作的形式包括快速读和慢速读，快速读的读取速读大于慢速读的读取速读，该装置包括：接收单元，用于接收对待访问存储区域的读访问请求；读取单元，用于采用快速读的形式对待访问存储区域进行读操作；获取单元，用于获取待访问存储区域的历史访问类型，历史访问类型为在读访问请求之前待访问存储区域被访问的访问类型；写入单元，则用于在快速读译码失败，且历史 访问类型为读操作的情况下，采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域。
结合第八方面，在第八方面第一种可能的实现方式中，获取单元用于获取待访问存储区域的历史访问类型，包括：获取单元用于查找历史访问记录中记录的待访问存储区域的历史访问类型。
结合第八方面或第八方面以上任一种可能的实现方式，在第八方面第二种可能的实现方式中，接收单元接收对待访问存储区域的读访问请求之前，还用于接收对待访问存储区域的第二写访问请求，第二写访问请求为对待访问存储区域的首次写访问请求；写入单元还用于将第二写访问请求的待写入数据写入待访问存储区域，并在历史访问记录中记录待访问存储区域的历史访问类型。
结合第八方面或第八方面以上任一种可能的实现方式，在第八方面第三种可能的实现方式中，写入单元用于将第二写访问请求的待写入数据写入待访问存储区域，包括：写入单元用于采用慢速写的形式将第二写访问请求的待写入数据写入待访问存储区域。
结合第八方面或第八方面以上任一种可能的实现方式，在第八方面第四种可能的实现方式中，该装置还包括删除单元：在确定待访问存储区域中的数据失效时，删除单元用于将记录的待访问存储区域的历史访问类型删除。
结合第八方面或第八方面以上任一种可能的实现方式，在第八方面第五种可能的实现方式中，读取单元还用于在快速读译码失败的情况下，采用慢速读的形式对待访问的存储区域进行读操作。
结合第八方面或第八方面以上任一种可能的实现方式，在第八方面第六种可能的实现方式中，读操作的形式还包括常速读，其中，常速读的读取速读大于慢速读的读取速读，且小于快速读的读取速读；读取单元还用于在快速读译码失败的情况下，采用常速读的形式对待访问的存储区域进行读操作。
结合第八方面或第八方面以上任一种可能的实现方式，在第八方面第七种可能的实现方式中，写入单元还用于在历史访问类型不是读操作的情况下，更新历史访问类型。
结合第八方面或第八方面以上任一种可能的实现方式，在第八方面第八种可能的实现方式中，写入单元采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域之前，还用于将待访问存储区域的地址信息 保存于重写队列；读取单元还用于根据重写队列中保存的地址信息，从待访问存储区域中读取待访问存储区域保存的数据。
第八方面为第三方面方法对应的装置实现方式，所以第三方面或第三方面任一种可能的实现方式中的描述对应适用于第八方面或第八方面任一种可能的实现方式，在此不再赘述。
第九方面，本申请提供了一种闪存设备的访问装置，其中，对闪存设备的访问类型包括写操作和读操作，对闪存设备的写操作的形式包括快速写和慢速写，快速写的写入速度大于慢速写的写入速度，该装置包括：接收单元，用于接收对待访问存储区域的读访问请求；获取单元，用于获取待访问存储区域的历史访问信息，历史访问信息中包含待访问存储区域的历史访问类型和写入速度标记，写入速度标记用于指示待访问存储区域中保存的数据的写操作的形式，历史访问类型为在读访问请求之前待访问存储区域被访问的访问类型；写入单元，写入单元用于在历史访问类型为读操作，且写入速度标记不是慢速写的情况下，采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域。
结合第九方面，在第九方面第一种可能的实现方式中，获取单元用于获取待访问存储区域的历史访问信息，包括：获取单元用于查找历史访问记录中记录的待访问存储区域的历史访问信息。
结合第九方面或第九方面以上任一种可能的实现方式，在第九方面第二种可能的实现方式中，接收单元接收对待访问存储区域的读访问请求之前，还用于接收对待访问存储区域的第二写访问请求，第二写访问请求为对待访问存储区域的首次写访问请求；写入单元还用于将第二写访问请求的待写入数据写入待访问存储区域，并在历史访问记录中记录待访问存储区域的历史访问信息。
结合第九方面或第九方面以上任一种可能的实现方式，在第九方面第三种可能的实现方式中，写入单元用于将第二写访问请求的待写入数据写入待访问存储区域，包括：写入单元用于采用慢速写的形式将第二写访问请求的待写入数据写入待访问存储区域。
结合第九方面或第九方面以上任一种可能的实现方式，在第九方面第四种可能的实现方式中，该装置还包括删除单元：在确定待访问存储区域中的数据失效时，删除单元用于将记录的待访问存储区域的历史访问信息删除。
结合第九方面或第九方面以上任一种可能的实现方式，在第九方面第五种可能的实现方式中，写入单元采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域之后，还用于将写入速度标记更新为慢速写。
结合第九方面或第九方面以上任一种可能的实现方式，在第九方面第六种可能的实现方式中，该装置还包括读取单元；获取单元获取待访问存储区域的历史访问信息之后，读取单元用于根据写入速度标记对待访问的存储区域进行读操作，其中，快速写对应慢速读，慢速写对应快速读。
结合第九方面或第九方面以上任一种可能的实现方式，在第九方面第二种可能的实现方式中，该装置还包括读取单元；写入单元采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域之前，还用于将待访问存储区域的地址信息保存于重写队列；读取单元用于根据重写队列中保存的地址信息，从待访问存储区域中读取待访问存储区域保存的数据。
第九方面为第四方面方法对应的装置实现方式，所以第四方面或第四方面任一种可能的实现方式中的描述对应适用于第九方面或第九方面任一种可能的实现方式，在此不再赘述。
第十方面，本申请提供了一种闪存设备，其中，对该闪存设备的访问类型包括写操作和读操作，对闪存设备的写操作的形式包括快速写和慢速写，快速写的写入速度大于慢速写的写入速度，该闪存设备包括存储控制器和闪存阵列：闪存阵列用于存储数据；存储控制器用于接收对闪存阵列的待访问存储区域的第一写访问请求，并获取待访问存储区域的历史访问类型，历史访问类型为在第一写访问请求之前待访问存储区域被访问的访问类型，在待访问存储区域的历史访问类型为写操作的情况下，采用快速写的形式将第一写访问请求的待写入数据写入待访问存储区域。
结合第十方面，在第十方面第一种可能的实现方式中，存储控制器还用于：在待访问存储区域的历史访问类型不是写操作的情况下，采用慢速写的形式将第一写访问请求的待写入数据写入待访问存储区域，并更新待访问存储区域的历史访问类型。
结合第十方面，在第十方面第二种可能的实现方式中，写操作的形式还包括常速写，其中，常速写的写入速度大于慢速写的写入速度，且小于快速写的写入速度；存储控制器还用于：在待访问存储区域的历史访问类型不是写操作的情况下，采用常速写的形式将第一写访问请求的待写入数据写入待 访问存储区域，并更新待访问存储区域的历史访问类型。
第十方面为第二方面方法对应的装置实现方式，所以第二方面或第二方面任一种可能的实现方式中的描述对应适用于第十方面或第十方面任一种可能的实现方式，在此不再赘述。
第十一方面，本申请提供了一种闪存设备，其中，对闪存设备的访问类型包括写操作和读操作，对闪存设备的写操作的形式包括快速写和慢速写，快速写的写入速度大于慢速写的写入速度，对闪存设备的读操作的形式包括快速读和慢速读，快速读的读取速读大于慢速读的读取速读，该闪存设备包括存储控制器和闪存阵列：闪存阵列用于存储数据；存储控制器用于接收对存储阵列的待访问存储区域的读访问请求，采用快速读的形式对待访问存储区域进行读操作，并获取待访问存储区域的历史访问类型，历史访问类型为在读访问请求之前待访问存储区域被访问的访问类型，在快速读译码失败，且历史访问类型为读操作的情况下，采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域。
结合第十一方面，在第十一方面第一种可能的实现方式中，存储控制器还用于在快速读译码失败的情况下，采用慢速读的形式对待访问的存储区域进行读操作。
结合第十一方面，在第十一方面第二种可能的实现方式中，读操作的形式还包括常速读，其中，常速读的读取速读大于慢速读的读取速读，且小于快速读的读取速读；存储控制器还用于在快速读译码失败的情况下，采用常速读的形式对待访问的存储区域进行读操作。
第十一方面为第三方面方法对应的装置实现方式，所以第三方面或第三方面任一种可能的实现方式中的描述对应适用于第十一方面或第十一方面任一种可能的实现方式，在此不再赘述。
第十二方面，本申请提供了一种闪存设备，其中，对闪存设备的访问类型包括写操作和读操作，对闪存设备的写操作的形式包括快速写和慢速写，快速写的写入速度大于慢速写的写入速度，该闪存设备包括存储控制器和闪存阵列：闪存阵列用于存储数据；存储控制器用于接收对待访问存储区域的读访问请求，获取待访问存储区域的历史访问信息，历史访问信息中包含待访问存储区域的历史访问类型和写入速度标记，写入速度标记用于指示待访问存储区域中保存的数据的写操作的形式，历史访问类型为在读访问请求之 前待访问存储区域被访问的访问类型，在历史访问类型为读操作，且写入速度标记不是慢速写的情况下，采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域。
结合第十二方面，在第十二方面第一种可能的实现方式中，存储控制器采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域之后，还用于将写入速度标记更新为慢速写。
结合第十二方面或第十二方面以上任一种可能的实现方式，在第十二方面第二种可能的实现方式中，存储控制器获取待访问存储区域的历史访问信息之后，还用于根据写入速度标记对待访问的存储区域进行读操作，其中，对闪存设备的读操作的形式包括快速读和慢速读，快速读的读取速读大于慢速读的读取速读，快速写对应慢速读，慢速写对应快速读。
第十二方面为第四方面方法对应的装置实现方式，所以第四方面或第四方面任一种可能的实现方式中的描述对应适用于第十二方面或第十二方面任一种可能的实现方式，在此不再赘述。
根据本发明实施例公开的技术方案，利用数据的访问特性，将数据分为只读、只写和交叉访问三类，并利用历史访问类型，对三类数据进行区分，从而调制只读特征数据的速度，进行慢速写以实现快速读，因而极大提高读性能而几乎不影响写性能；调制只写特征数据的速度，进行快速写，极大提高写性能而几乎不影响读性能；进一步的，还可以调制交叉访问特性数据的速度，进行常速写，从而在读写速度上取得平衡。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为数据访问系统的逻辑结构示意图；
图2为依据本发明一实施例的存储控制器硬件结构示意图；
图3为依据本发明一实施例的ISPP编程流程示意图；
图4为依据本发明一实施例的硬判决阈值电压分布图；
图5为依据本发明一实施例的软判决阈值电压分布图；
图6为依据本发明一实施例的闪存设备的访问方法的示范性流程图；
图7为依据本发明一实施例的历史访问信息条目的示意图；
图8为依据本发明一实施例的闪存设备的访问方法的示范性流程图；
图9为依据本发明一实施例的历史访问信息条目的示意图；
图10为依据本发明一实施例的闪存设备的访问装置的逻辑结构示意图；
图11为依据本发明一实施例的闪存设备的访问装置的逻辑结构示意图；
图12为依据本发明一实施例的闪存设备的访问装置的逻辑结构示意图。
具体实施方式
下面将结合附图，对本发明实施例进行描述。
图1为依据本发明一实施例的闪存设备访问系统的逻辑结构示意图100，如图1所示，系统100包括操作系统102和闪存设备108。
操作系统102包括用于控制和管理常规系统任务(例如内存管理、存储设备控制、电源管理等等)以及有助于各种软硬件组件之间通信的各种软件组件和/或驱动器。操作系统102可以为Darwin、RTXC、LINUX、UNIX、OS X、MAC OS、WINDOWS或诸如Vxworks之类的嵌入式操作系统，本发明实施例对此不进行限定。
具体的，操作系统102包括文件系统104和驱动程序106。其中，文件系统104是操作系统102用于明确闪存设备108上的文件的方法和数据结构，即在闪存设备108上组织文件的方法。文件系统104可以为FAT、NTFS、exFAT、RAW、Ext2、Ext3、Ext4、Btrfs、ZFS、HFS、HFS+、ReiserFS、JFS、VMFS、XFSUFS或VXFS等之类的任意类型。
操作系统102上运行有用户的应用程序，应用程序以访问底层硬件的形式实现人机交互，驱动程序106是应用程序与硬件交互的桥梁，一方面，应用程序通过对驱动程序106发送相应的指令，实现对硬件的控制，另一方面，驱动程序106将硬件读写的状态、从硬件上获得的数据传送给应用程序，从而实现应用程序与底层硬件间的交互。
操作系统102通过硬盘接口技术(Advanced Technology Attachment，ATA)与闪存设备108相连接。
闪存设备108为基于闪存的存储设备，例如可以为SSD，闪存设备108包括缓存110、存储控制器112和闪存阵列130。
其中，存储控制器112包含主机接口114、闪存转换层(Flash Translation Layer，FTL)116和闪存接口128。
主机接口114用于与主机连接，控制与操作系统102之间的数据传输。
闪存接口128用于与闪存阵列130连接，控制与闪存阵列130之间的数据传输。
闪存转换层116包含坏块管理(Bad Block Management，BBM)模块118、磨损平衡(Wear leveling，WL)模块120、地址转换模块122、校验纠错(Error Checking and Correction，ECC)模块124和垃圾回收(Garbage Collection，GC)模块126。
闪存阵列130可以被分为多个块(Block)，每个块又可以分成多个页面(Page)。数据可以直接以页面为单位写入，但是要想擦除数据却需要以块为单位，而且未擦除就无法写入。但操作系统102读写数据一般是按硬盘(Hard Disk Drive，HDD)的扇区尺寸进行的，这导致操作系统102现在使用的文件系统104无法管理SSD，需要更换更先进、复杂的文件系统去解决这个问题，但这样就会加重操作系统102的负担。为了不加重操作系统102的负担，闪存设备108采用软件的方式把闪存阵列130的操作虚拟成磁盘的独立扇区操作，这就是闪存转换层116的功能。
闪存转换层116存在于文件系统104和物理介质(闪存阵列130)之间，操作系统102只需跟原来一样操作逻辑块地址(Logical Block Address，LBA)即可，而逻辑地址到物理块地址(Physics Block Address，PBA)的所有转换工作，就全交由闪存转换层116负责。
坏块管理模块118用于对闪存阵列130的坏块进行管理，闪存阵列130中不能保证读/写/擦时数据的准确性的不稳定块被称为坏块，坏块管理模块118使用坏块表来管理坏块。当坏块表创建后，坏块管理模块118会把坏块表保存在某个好的块里，每次重启后，从该块里把坏块表载入缓存110中。闪存阵列130的写入是以页为单位操作的，操作时可能影响到整个块里其它页的数据，所以当发现写入出现错误时，坏块管理模块118使用好的块替换这个坏块，重新在新的好块里写入这个数据，并把检测到的坏块里其余的有效页数据全部复制到新的块里去，标记老的块为坏块，更新坏块表里的地址，把原本坏块的地址重新映射到新的好块里。
闪存阵列130的寿命是以编程/擦除次数来计算的，而磨损平衡模块120 就是确保闪存阵列130内每个块被写入的次数相等的一种机制。若没有这个机制，闪存阵列130内的闪存颗粒就无法在同一时间达到生命周期。因为用户在逻辑地址空间里的数据更新速度是不同的，有部分是经常需要更新，而有些却长期不需要变更，因此若没有WL机制，那些经常被更新的数据所在的闪存颗粒寿命会首先被消耗完毕，变更较少的数据所在的闪存颗粒损耗就要小得多。为了避免出现这种状况，便需要WL这个机制来保持闪存阵列130内的每个闪存颗粒的磨损程度在相对一致的状态。
具体的，磨损平衡模块120结合地址转换模块122共同发挥作用，每次操作系统102上应用程序重写或更新相同的逻辑地址时，地址转换模块122动态的映射这一逻辑地址到另一个不同的物理地址，并把这个映射关系存放在一个特定的“地址映射表”里。过期的物理地址就被标记为“无效”并等待随后的擦除操作。而磨损平衡模块120就是在这一映射过程中，控制每一个存储颗粒的编程/擦除频率，这样一来，所有的物理块就能被控制在一个相同磨损范围，并同时“老化”。
校验纠错模块124用于数据读取时的差错检测和修正。当数据写入的时候，存储控制器112内部的校验纠错模块124根据数据生成ECC签名。ECC签名一般保存于闪存页后部的备用区(Spare Area，SA)，当从闪存页读取数据的时候，纠错校验模块124读取ECC签名，并根据读取的数据和ECC签名判断是否出现数据错误。如果检测到读取的数据包含错误比特，就需要使用ECC算法来修正检测到的错误。ECC算法可以为BCH编码或LDPC编码等，本发明实施例以LDPC编码对方案进行描述说明，但应了解，本发明实施例并不对ECC采用的编码算法进行限定。
垃圾回收模块126具体用于把一个闪存块里的“有效”页数据复制到另一个数据块里，然后将之前的数据块完全擦除。与传统HDD不同，闪存阵列130并不能直接覆盖原来的数据，闪存设备108必须要把旧的数据先擦除，然后才可以把新的数据写入。对于闪存阵列130来说，垃圾回收就是指把现存数据重新转移到其他闪存位置，并且把一些无用的数据彻底擦除的过程。闪存阵列130数据可以直接以页面为单位写入，但是要想擦除数据却需要以块为单位。因此要擦除无用的数据，闪存阵列130首先需要把一个块内包含有用的数据先拷贝到另一个块中的页面内，这样原来块中包含的无用数据才能够以块为单位擦除。擦除后，才能够写入新的数据。
可选的，闪存设备108还支持修剪(Trim)功能，Trim是一个ATA指令，操作系统102发送此指令给存储控制器112，以通知它哪些数据占用的地址是“无效”的。当用户在操作系统102中删除一个文件时，操作系统102并没有真正删掉这个文件的数据，它只是把这些数据占用的地址标记为“无效”，即可以覆盖使用。但这只是在文件系统104层面的操作，闪存设备108本身并不知道哪些地址的数据已经“无效”，直至操作系统102通知它要在这些地址写入新的数据。闪存阵列130不允许覆盖，只能先擦除再写入，要得到“空闲”的闪存块来进行写入，在没有Trim机制的情况下，存储控制器112无法事先知道哪些被“删除”的数据页已经是“无效”的，必须到操作系统102要求在相同的位置写入数据时才知道哪些数据可以被擦除，这样就无法在最适当的时机做出最好的优化，既影响GC的效率，又影响闪存阵列130的寿命。
缓存110用于在启动时存储坏块表或逻辑地址到物理地址的“地址映射表”等数据，存储控制器112将坏块表和“地址映射表”等保存在闪存阵列130中，每次重启后，从闪存阵列130中把坏块表和“地址映射表”等数据载入缓存110中。
闪存阵列130可以被分为多个Block(块)，每个块(block)又可以分成多个页面(pages)，数据可以直接以页面为单位写入，以块为单位进行擦除，写入前需要擦除。
闪存阵列130可以使用单阶存储单元(Single-level cell，SLC)或多阶存储单元(Multi-level cell，MLC)，其中，每个SLC单元存储1比特的信息，每个MLC单元则可以存储1比特以上的数据。本发明实施例对此并不进行限定。
应理解，图1的目的仅仅是示例性的引入系统100的参与者以及它们的相互关系。因此，所描绘的系统100被大大地简化，本发明实施例仅仅对其进行概括性的说明，系统100在实际使用时可以包含更多或更少的组件，本发明实施例并不对其实现方式进行任何的限定。
图2是依据本发明一实施例的存储控制器200的硬件结构示意图。如图2所示，存储控制器200包括处理器202、存储器204、输入/输出接口206、通信接口208和总线210。其中，处理器202、存储器204、输入/输出接口206和通信接口208通过总线210实现彼此之间的通信连接。
处理器202是存储控制器200的控制中心，用于执行相关程序，以实现本发明实施例所提供的技术方案。处理器202可以采用通用的中央处理器 (Central Processing Unit，CPU)，微处理器，应用专用集成电路(Application Specific Integrated Circuit，ASIC)，或者一个或多个集成电路，用于执行相关程序，以实现本发明实施例所提供的技术方案。除非另有说明，在本发明中，一个用于执行特定功能的组件，例如，处理器202或存储器204，可以通过配置一个通用的组件来执行相应功能来实现，也可以通过一个专门执行特定功能的专用组件来实现，本申请并不对此进行限定。
存储器204可以是只读存储器(Read Only Memory，ROM)，静态存储设备，动态存储设备或者随机存取存储器(Random Access Memory，RAM)。存储器204可以存储操作系统和其他应用程序。在通过软件或者固件来实现本发明实施例提供的技术方案时，用于实现本发明实施例提供的技术方案的程序代码保存在存储器204中，并由处理器202来执行。存储器204可以与处理器202集成在一起或集成在处理器202的内部，也可以是独立于处理器202的一个或多个存储单元。
供处理器202执行的程序代码可以存储在与其连接的闪存中或存储器204中。可选的，存储器204为RAM，存储在闪存内部的程序代码(例如，通信模块或访问控制模块等)被拷贝到存储器204中，以供处理器202执行。
存储器204还用于存储本发明实施例的坏块表、地址映射表或其他映射表，更具体的，系统启动时，存储控制器200将存储于闪存中的坏块表、地址映射表或其他映射表载入存储器204，以供处理器202使用。
如图2所示，存储控制器200的存储器204中包含访问控制模块，处理器202执行该访问控制模块程序代码，实现对闪存设备的访问。
可选的，存储器204还包含图1存储控制器112中的坏块管理模块118、磨损平衡模块120、地址转换模块122、校验纠错模块124和垃圾回收模块126中的一种或多种。
输入/输出接口206用于接收输入的数据和信息，输出操作结果等数据。
通信接口208使用例如但不限于收发器一类的收发装置，来实现存储控制器200与其他设备或通信网络之间的通信。
总线210可包括一通路，在存储控制器200各个部件(例如处理器202、存储器204、输入/输出接口206和通信接口208)之间传送信息。
应注意，尽管图2所示的计存储控制器200仅仅示出了处理器202、存储器204、输入/输出接口206、通信接口208以及总线210，但是在具体实现过程中， 本领域的技术人员应当明白，存储控制器200还包含实现正常运行所必须的其他器件。同时，根据具体需要，本领域的技术人员应当明白，存储控制器200还可包含实现其他附加功能的硬件器件。此外，本领域的技术人员应当明白，存储控制器200也可仅仅包含实现本发明实施例所必须的器件，而不必包含图2中所示的全部器件。
图2所示的硬件结构以及上述描述适用于本发明实施例所提供的各种闪存设备的访问装置和系统，适用于执行本发明实施例所提供的各种闪存设备的访问方法。
闪存以页为单位对数据进行写入，一个写操作的时间主要包括数据的传输时间和数据的写入时间(即编程操作)两部分。一页数据在总线上的传输时间不变，写操作的时间主要取决于编程操作的时间。闪存一般采用ISPP编程的方式写入数据，要使得存储元达到预定的电压，通过逐步增加步幅电压来改变每一轮的编程电压，对存储元充电直到存储元达到预定的电压值大小，其中，步幅电压固定。
具体的，ISPP编程操作每一轮迭代包括两个部分：编程和核实。如图3所示，编程对存储元施加一个编程电压，使存储元中电荷量增加，每一次的编程电压在存储元持续一段时间。核实则加一个较小电压来判断存储元是否达到预定值。如果达到，则充电完成，停止编程；否则编程电压增加一个步幅电压继续对存储元充电，直到数据完成写入。
这样的迭代过程与步幅电压存在比例关系。一方面，步幅电压越大，需要迭代较少的次数就能达到预定电压值，因此，编程时间与步幅电压成反比。另一方面，编程步幅电压与错误率之间则呈现另一种关系。步幅电压越大，编程精确性越差，后续错误率越高；步幅电压越小，编程精确性越好，后续错误率越低。因此，写操作时的ISPP编程的步幅电压会影响到后续读操作时的数据错误率。
在本发明实施例中，根据ISPP编程的步幅电压不同，将闪存设备的写操作的形式进行了划分，写操作包括快速写和慢速写，其中，快速写的写入速度大于慢速写的写入速度，即快速写的ISPP编程的步幅电压大于慢速写的ISPP编程的步幅电压。
更具体的，对闪存的写操作的形式还可以包含常速写，其中，常速写的写入速度大于慢速写的写入速度，且小于快速写的写入速度，即常速写的ISPP 编程的步幅电压大于慢速写的ISPP编程的步幅电压，且小于快速写的ISPP编程的步幅电压。
应理解，此处的“快速写”可以指闪存设备支持的快速的写操作，“慢速写”可以指指闪存设备支持的慢速的写操作，常速写”是速度介于“慢速写”和“快速写”之间的写操作。在本发明实施例中，闪存设备支持至少两种写操作的速度，写操作的速度一般由编程步幅电压决定，编程步幅电压大的对应快速的写操作，编程步幅电压小的对应慢速的写操作。本实施例中的快速写对应该闪存设备的写操作速度中的最快的或者较快的速度，本实施例中的慢速写对应该闪存设备的写操作速度中的最慢的或者较慢的速度，例如，对于支持两种写操作速度的闪存设备，快速写是指速度快的写操作，慢速写是指速度慢的写操作，对于支持两种以上写操作速度的闪存设备，快速写是指速度最快或者次快或者相对较快的写操作，慢速写是指速度最慢或者次慢或者相对较慢的写操作。
一个读操作的时间主要包括从数据的读取时间和数据的传输时间两部分。其中，读取时间与阈值电压数目呈正相关关系，而传输时间与传输的数据量呈正相关关系。假设有N个阈值电压，将闪存存储元中的电压值分为N+1个区域，则需要ceil(Log2(N+1))个bit来表示N+1个电压区域，其中，读取时间与N呈正相关关系，传输时间与ceil(Log2(N+1))呈正相关关系，ceil()表示向上取整。
以采用LDPC编码作为校验码，单位存储元存储2bit数据进行举例说明，读操作的方案一般是先采取LDPC硬判决译码，图4为LDPC硬判决的阈值电压分布，相邻两个状态之间只有1个阈值电压，在4个状态之间总共有3个阈值电压，读操作时，将读取的数据页的每一个存储元的电压与3个阈值电压进行比较，以确定存储元中电压所处的状态，因为只有3个阈值电压，所以读取时间较短。由于存储元的电压被分为4个状态，需要ceil(Log2(4))＝2个bit来记录信息，传输时间较短。
如果校验成功，则读取成功，反之如果校验不成功，再使用软判决进行译码，图5为LDPC软判决的阈值电压分布，相邻两个状态之间有多个阈值电压，图5中以两个状态之间有7个阈值电压进行举例说明，则四个状态共有21个阈值电压，将存储元的电压分成22个区域。读操作时，将读取的数据页的每一个存储元的电压与21个阈值电压进行比较，以确定存储元中电压所处的状态， 其读取时间较长。同时，由于存储元的电压被分为22个状态，需要ceil(Log2(22))＝5个bit来记录信息，传输时间也相对较长。如果仍然译码失败，软判决通过逐次增加相邻状态之间阈值电压的数目来提高读取精度，直到正确译码出信息。
应理解，软判决的阈值电压分布不限于图5中的示例，相邻两个状态之间的阈值电压数目是可变的，决定了LDPC译码能容忍的数据的错误率大小，阈值电压数目越多，可正确译码能容忍的错误率越高。
由以上描述可知，慢速写的步幅电压较小，数据写入准确性高，进行读取操作的时候，从闪存中读取数据的正确性就越高，比较容易译码成功，但写入的速度慢；快速写的步幅电压较大，写入速度快，但数据写入准确性较低，进行读取操作的时候，从闪存中读取数据的正确性相对较低，要经过多轮读取或迭代，才能准确读取闪存中的数据。
在本发明实施例中，根据相邻状态间阈值电压数目的不同，对闪存的读操作的形式包括快速读和慢速读，其中，快速读的读取速读大于慢速读的读取速读，即快速读的阈值电压的数目小于慢速读的阈值电压的数目。
更具体的，对闪存的读操作的形式还可以包含常速读，其中，常速读的读取速读大于慢速读的读取速读，且小于快速读的读取速读，即常速读的阈值电压的数目小于慢速读的阈值电压的数目，且大于快速读的阈值电压的数目。
在本发明实施例中，闪存设备支持至少两种读操作的速度，读操作的速度一般由根据相邻状态间阈值电压数目决定，相邻状态间阈值电压数目少的对应快速的读操作，相邻状态间阈值电压数目多的对应慢速的读操作。本实施例中的快速读对应该闪存设备的读操作速度中的最快的或者较快的速度，本实施例中的慢速读对应该闪存设备的读操作速度中的最慢的或者较慢的速度，例如，对于支持两种读操作速度的闪存设备，快速读是指速度快的读操作，慢速读是指速度慢的读操作，对于支持两种以上读操作速度的闪存设备，快速读是指速度最快或者次快或者相对较快的读操作，慢速读是指速度最慢或者次慢或者相对较慢的读操作。
根据本发明实施例，通过对多个数据的访问行为进行分析，发现闪存的访问存在一定的特征。主要分为以下三种特征：
1)只读特征。在一段时间内，发生在一个数据页上的几乎所有访问均为 读访问，则这些读访问具有只读特征。例如，媒体文件在写入之后一般情况不会再发生写访问，只会多次读取。
2)只写特征。在一段时间内，发生在一个数据页上的几乎所有访问均为写访问，则这些写访问具有只写特征。例如，日志文件和元数据等，一般情况会反复写，几乎很少的读访问。
3)交错访问特征。在一段时间内，数据页上的访问读写均有，则这些访问具有交错访问特征。
结合闪存快速写入的数据读取慢，慢速写入的数据读取快这一特点，本发明实施例根据闪存页的访问特征实现对闪存页写入速度的调整，以实现提高闪存的读写性能的目的。具体方法在以下实施例进行描述。
图6为依据本发明一实施例的闪存设备的访问方法600的流程图。其中，对闪存设备的访问类型包括写操作和读操作，对闪存设备的写操作的形式包括快速写和慢速写，快速写的写入速度大于慢速写的写入速度，对闪存设备的读操作的形式包括快速读和慢速读，快速读的读取速读大于慢速读的读取速读。如图6所示，方法600包括：
S602：存储控制器接收来自操作系统的访问请求。
访问请求指示了待访问存储区域。具体的，访问请求中携带待访问存储区域的地址信息。该地址信息为待访问存储区域的逻辑地址。本发明实施例的待访问存储区域是指逻辑地址指示的存储区域。因为闪存的闪存页不能直接覆盖原来的数据，必须要把旧的数据先擦除，才可以把新的数据写入，所以本发明实施例的地址信息为待访问区域的逻辑地址，待访问存储区域与逻辑地址关联，因为闪存无法进行覆盖重写，同一个逻辑地址对应的实际物理地址是可以处于变化状态的。
S604：存储控制器判断访问请求的访问类型。其中，闪存设备的访问类型包含写操作和读操作。如果访问请求的访问类型为写操作，则执行步骤S606，如果访问请求的访问类型为读操作，则执行步骤S616。
S606：存储控制器判断是否存在待访问存储区域的历史访问信息，如果不存在，则执行S608，如果存在，则执行步骤S610。
存储控制器在历史访问记录中查找待访问存储区域的历史访问信息，其中，历史访问信息中包含待访问存储区域的历史访问类型，历史访问类型为待访问存储区域在本次访问请求之前被访问的访问类型。
具体的，历史访问信息可以记录该待访问存储区域的前一次的历史访问类型，例如，可以使用一个bit位进行区分，“0”表示上一次历史访问类型为写操作，“1”表示上一次历史访问操作的类型为读操作。
可选的，历史访问信息可以记录对待访问存储区域之前N次的历史访问类型，其中N为大于1的正整数。
例如，当N为2时，可以使用两个bit位进行区分，“00”表示前2次历史访问类型均为写操作；“01”表示前2次历史访问类型依次为写操作和读操作；“10”表示前2次历史访问类型依次为读操作和写操作；“11”表示前2次历史访问类型均为读操作。当N为其他正整数时，依次类推。
应理解，本发明实施例在举例说明的时候用“0”表示写操作，用“1”表示读操作，在实际操作中，可以使用其他的表示方法对历史访问类型进行记录，本发明实施例对此并不进行限定。
在具体实现过程中，历史访问信息记录有待存储区域的地址信息与历史访问类型之间的对应关系，历史访问信息可以记录在逻辑地址到物理地址的地址映射表里，这样就可以节省了多余的记录待访问存储区域的地址信息的空间消耗。当然，也可以单独的对历史访问信息进行记录，本发明实施例并不对历史访问信息的形式进行限定。
具体的，存储控制器维护历史访问信息表，历史访问信息表中包含多个有效地址信息对应的历史访问信息条目，历史访问信息条目保存有存储区域的地址信息与历史访问类型之间的对应关系。
具体实现过程中，可以以闪存页为粒度对历史访问信息进行记录，或者使用其他算法，以较高的粒度对历史访问信息进行记录，本发明实施例对此并不进行限定。
图7为依据本发明实施例的历史访问信息条目的示意图，历史访问信息条目中记录有待访问存储区域的地址信息和历史访问类型。
S608：存储控制器记录待访问存储区域的历史访问信息。
如果存储控制器没有在历史访问记录中查找到到待访问存储区域的历史访问信息，更具体的，如果存储控制器没有在历史访问信息表中查找到与该地址信息对应的历史访问信息条目，表明操作系统对该待访问存储区域是首次写，则存储控制器将待写入数据写入该待访问存储区域，并在历史访问记录中记录待访问存储区域的历史访问信息，更具体的，存储控制器在历史访 问信息表中创建历史访问信息条目，并将待访问存储区域的历史访问类型设置为写操作。
应理解，此处的首次写是指对待访问存储区域的首次写访问请求，是指对待访问存储区域从“数据无效”状态到“数据有效”状态的首次写入，在首次写入的时候，创建与待访问存储区域对应的历史访问信息条目，并将其历史访问类型记录为写操作。
优选的，首次写入时，存储控制器采用慢速写的形式将待写入数据写入该待访问存储区域，其中，写操作的形式包括慢速写和快速写。因为数据是首次写入，写入的时候并不知道对该数据后续的访问特征如何，即不清楚数据是只读特性、只写特性、还是交叉访问特性。所以首次写入的时候可以统一的采用慢速写的形式对待写入数据进行写入。
写操作的形式还可以包含常速写，初次写入也可以采用常速写或快速写的形式，但可能该数据具有只读特性，则后续不利于数据读取操作。本发明实施例并不对数据首次写入的形式进行限定。
S610：存储控制器判断待访问存储区域的历史访问类型是否为写操作，如果是则执行步骤S612，否则执行步骤S614。
具体的，存储控制器判断待访问存储区域对应的历史访问信息条目中记录的历史访问类型是否是写操作。历史访问类型为写操作是指历史访问类型全部为写操作，若待访问存储区域的历史访问类型为写操作，因本次访问请求的访问类型也为写操作，说明该待访问存储区域中的数据具有只写特性；如果历史访问类型不全部为写操作，则历史访问类型不是写操作，因本次访问请求的访问类型为写操作，说明待访问存储区域中的数据具有交叉访问特性。
S612：存储控制器采用快速写的形式将待写入的数据写入待访问存储区域。
因为待访问存储区域的历史访问类型为写操作，且本次访问请求的类型为写操作，则表明待访问存储区域中的数据具有只写特性，很少会对该待访问存储区域中的数据进行读取操作，为了节省写操作带来的消耗，则采用快速写的形式对待写入的数据进行写操作。
因为历史访问类型为写操作，本次访问请求的访问类型也为写操作，则本次访问请求没有改变历史访问类型，可以不对历史访问信息进行更新，保 持该历史访问信息条目中的历史访问类型不变。
具体实现过程中，因为闪存无法覆盖原来的数据，所以对该地址信息指示的待访问存储区域的写操作之前，存储控制器首先修改逻辑地址到物理地址的地址映射表，将逻辑地址重新指向一个新的物理地址，然后将待写入数据写入新的物理地址，原来的物理地址中的数据被存储控制器置于“无效”状态，等待后续的垃圾回收机制进行擦除后，才能被重新进行写操作。
S614：存储控制器采用常速写的形式对待访问存储区域进行写操作，并更新待访问存储区域的历史访问信息。
因为历史访问类型不是写操作，说明该地址信息指示的待访问存储区域具有交叉访问特性，则采用常速写的形式对待访问存储区域进行写操作，从而平衡读写代价。
可选的，步骤S614中，存储控制器也可以采用慢速写或快速写的形式对待访问存储区域进行写操作，但是采用慢速写需要较大的写入代价，采用快速写则需要较大的读取代价。
因为历史访问类型不是写操作，而本次访问请求的访问类型为写操作，所以需要对历史访问类型进行更新。如果只使用一个bit记录了上一次历史访问类型，则只需将历史访问类型更新为写操作即可，如果记录了前N个历史访问类型，则根据实际情况，可以采用“移位”的方式对历史访问类型进行更新。例如，N为2时，历史访问类型的标记为“11”，表示前2次历史访问类型均为读操作(用“0”表示写操作，用“1”表示读操作)，因为本次是“0”，只需将“11”修改为“10”即可。
S616：存储控制器对待访问存储区域进行读操作。
首先采用快速读的方式对待访问存储区域进行读操作，例如，可以采用硬判决，或者采用相邻状态之间阈值电压数目较少的软判决，如果译码成功，则读操作结束；如果译码不成功，则减慢读操作的速度，增加读操作的精度，进行重新读取，并译码。例如，可以由硬判决转为软判决，或增加软判决的相邻状态之间阈值电压的数目。
具体的，存储控制器可以采用LDPC作为校验码，读操作可以先采取LDPC硬判决译码，如果校验成功，则读操作成功；反之如果校验不成功，译码失败，再使用软判决进行译码，如果仍不成功，则通过逐次增加软判决的相邻状态之间阈值电压的数目，直到正确译码出信息。
应理解，本发明实施例的以上描述仅仅是举例说明，本发明实施例并不对读操作的形式以及采用的ECC编码进行限定。
S618：存储控制器判断待访问存储区域的历史访问类型是否为读操作，如果是读操作，则执行步骤S622，否则，则执行步骤S620。
具体的，存储控制器判断待访问存储区域对应的历史访问信息条目中记录的历史访问类型是否是读操作。历史访问类型为读操作是指历史访问类型全部为读操作，若历史访问类型为读操作，因为本次访问请求的类型也为读操作，则说明该地址信息指示的待访问存储区域具有只读特性；如果历史访问类型不全部为读操作，则历史访问类型不是读操作，说明该地址信息指示的待访问存储区域具有交叉访问特性。
S620：存储控制器更新历史访问信息。
因为历史访问类型不是读操作，而本次访问请求的访问类型为读操作，所以需要对历史访问类型进行更新。如果只使用一个bit记录了上一次历史访问类型，则只需将历史访问类型更新为读操作即可，如果记录了前N个历史访问类型，则根据实际情况，可以采用“移位”的方式对历史访问类型进行更新。例如，N为2时，历史访问类型的标记为“00”，表示前2次历史访问类型均为写操作(用“0”表示写操作，用“1”表示读操作)，因为本次是“1”，只需将“00”修改为“01”即可。
S622：存储控制器确定读操作过程中，快速读是否译码失败，如果失败则执行步骤S624，如果没有失败，则结束流程。
因为待访问存储区域的历史访问类型为读操作，且本次访问请求的类型为读操作，则表明该地址信息指示的待访问存储区域具有只读访问特性，对该待访问存储区域的访问大都为读操作。存储控制器采用快速读的形式读取失败，说明待访问存储区域中保存的数据精度不高。
S624：存储控制器采用慢速写的形式对待访问存储区域进行重写操作。
如果待访问存储区域中的数据具有只读特性，且检测到对该待访问存储区域的快速读译码失败，则存储控制器采用慢速写的形式对该待访问存储区域进行重写操作，以提高后续对该待访问存储区域的读操作的速度。即，在快速读译码失败，且历史访问类型为读操作的情况下，采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域。
因为闪存的闪存页不能直接覆盖原来的数据，必须要把旧的数据先擦除， 然后才可以把新的数据写入。此处的重写操作是指对逻辑地址的重写，存储控制器修改逻辑地址到物理地址的地址映射关系，使逻辑地址指向新的可用物理地址，并在新的物理地址上重写数据，原来的物理地址被标记为“无效”状态，等待后续擦除后，才能被重新使用。
可选的，在本发明实施例另外一种可能的实现方式中，如果待访问存储区域中的数据具有只读特性，在读操作时译码的误码率超过预设的阈值的情况下，采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域。
为了不阻塞对闪存的正常访问操作，存储控制器可以将待访问存储区域的地址信息保存于重写队列，等空闲时，根据重写队列中包含的该地址信息，从待访问存储区域中读取数据，并采用慢速写的形式将读取的数据重写入该待访问存储区域。
具体的，可以将需要重写的地址信息组织成一个LRU(Least Recently Used)链表，并将LRU链表保存于缓存中，当存储控制器检测到系统空闲时，从缓存中读取LRU链表，并从LRU链表中获取地址信息，去对应地址信息处读取需要重写的数据，并调整写操作的步幅电压，采用慢速写的形式将带重写的数据重新写入闪存，并将该逻辑地址从重写队列中删除。
可以优先重写LRU链表头的数据，即最近加入链表的数据或者是最近一次访问的数据。当链表中记录的数据在重写之前已经被主机的写访问更新，则可以直接从链表中删除该数据的地址信息，无需再重写。
可选的，存储控制器也可以在读操作成功后，直接根据读取成功的数据，对待访问存储区域进行重写操作，这样避免了对数据的多次读取，但是有可能会阻塞对闪存的正常访问操作。
存储控制器在确定待访问存储区域中的数据失效时，将与待访问存储区域对应的历史访问信息删除。例如，存储控制器可以从操作系统接收删除通知消息，该删除通知消息用于指示待访问存储区域中的数据已经无效，则存储控制器删除待访问存储区域的历史访问信息条目，待访问存储区域从有效状态变为无效状态。
具体的，如果闪存设备支持Trim功能，则存储控制器还可以接收Trim指令，Trim指令中携带地址信息，用于指示该地址信息上的数据被操作系统删除，则存储控制器可以在历史信息表中将该地址信息对应的历史访问信息条 目删除，并将该地址信息对应的物理块地址上的数据标记为“无效”，等待后续的擦除操作。
可选的，历史访问信息中还包含写入速度标记，用于详细记录写操作的速度，则存储控制器还可以建立写操作的速度与读操作的速度的对应关系，则在交叉访问的场景下，根据写入速度标记对待访问的存储区域进行读操作，其中，快速写对应慢速读，慢速写对应快速读。
应理解，方法600仅仅是对闪存设备的方法进行示例性说明，其中，具体步骤可以不分先后顺序或可以合并执行，本发明的步骤序号仅仅是为了更加清楚的描述本方案流程，并不限定步骤的执行顺序。
根据本发明实施例公开的技术方案，利用数据的访问特性，将数据分为只读、只写和交叉访问三类，并利用历史访问类型，对三类数据进行区分，从而调制只读特征数据的速度，进行慢速写以实现快速读，因而极大提高读性能而几乎不影响写性能；调制只写特征数据的速度，进行快速写，极大提高写性能而几乎不影响读性能；进一步的，还可以调制交叉访问特性数据的速度，进行常速写，从而在读写速度上取得平衡。
图8为依据本发明一实施例的闪存设备的访问方法800的流程图。其中，历史访问信息中还包含写入速度标记，写入速度标记用于记录写操作的形式，用于指示待访问存储区域中保存的数据是否是以慢速写的形式写入的。
具体的，存储控制器可以用一个bit的写入速度标记记录数据是否是以慢速写的形式写入的，例如，“0”表示数据是以慢速写的形式写入的，“1”表示数据不是以慢速写的形式写入的。
更进一步的，存储控制器也可以详细记录写操作的速度，如果写操作的速度分为M个等级，则共需要ceil(Log2 M)个bit的写入速度标记记录写操作的速度，例如，写操作的速度分为慢速写、常速写和快速写三个等级，则需要ceil(Log2 3)＝2个bit来记录写操作的速度，例如，可以用“00”表示慢速写，“01”表示常速写，“10”表示快速写，“11”状态作为保留位。
图9为依据本发明实施例的历史访问信息条目的示意图，历史访问信息条目中记录有待访问存储区域对应的历史访问信息。
如图8所示，方法800包括：
S802-S814的特征描述参照步骤S602-S614，更进一步的，存储控制器在进行写操作时，会进一步记录写操作的形式是否是慢速写，或详细记录写操 作的速度等级，其余部分参照S602-S614，在此不再赘述。
S816：存储控制器判断待访问存储区域的历史访问类型是否为读操作，如果是则执行步骤S820，否则执行步骤S818。
具体描述参照步骤S618，在此不再赘述。
S818：存储控制器更新历史访问类型。
具体描述参照步骤S620，在此不再赘述。
S820：存储控制器判断写操作的形式是否是慢速写，如果是，则执行步骤S824，否则执行步骤S822。
具体的，因为历史访问类型为读操作，且本次访问请求的访问类型也为读操作，说明该地址信息指示的待访问存储区域具有只读特性，为了减小读操作的代价，存储控制器判断该地址信息对应的历史访问信息条目中的速度标记是否是慢速写，如果是慢速写，则直接进行读操作，如果不是慢速写，则说明不能保证能够快速读取数据，则需要对该待访问存储区域进行慢速重写操作。
S822：存储控制器采用慢速写的形式对待访问存储区域进行重写操作。
如果待访问存储区域中的数据具有只读特性，且待访问存储区域中保存的数据不是以慢速写的形式写入，则说明待访问存储区域中保存的数据写入精度较低，则存储控制器需要采用慢速写的形式对该待访问存储区域进行重写操作，以提高后续对该待访问存储区域的读操作的速度。即，在待访问存储区域的历史访问类型为读操作，且写入速度标记不是慢速写的情况下，采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域。
具体描述参见步骤S624，在此不再赘述。
采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域之后，存储控制器将写入速度标记更新为慢速写。
S824：存储控制器对该地址信息指示的待访问存储区域进行读操作。
步骤S824的具体描述参照步骤S616，在此步骤赘述。
如果存储控制器使用写入速度标记详细记录写操作的速度，则还可以建立写操作的速度与读操作的速度的对应关系，根据写入速度标记对待访问的存储区域进行读操作，其中，快速写对应慢速读，慢速写对应快速读。
更进一步的，写操作可以分为慢速写、常速写和快速写三个等级，读操作可以对应的分为快速读、常速读和慢速读三个等级，其中，慢速写对应快 速读，常速写对应常速读，快速写对应慢速读。
则存储控制器在对该地址信息指示的待访问存储区域进行读操作时，可以根据历史访问信息中记录的写操作的形式，直接选取对应的读操作的形式进行读取。
存储控制器在确定待访问存储区域中的数据失效时，将与待访问存储区域对应的历史访问信息删除。具体描述参照图6实施例部分的描述，在此不再赘述。
应理解，方法800仅仅是对闪存设备的方法进行示例性说明，其中，具体步骤可以不分先后顺序或可以合并执行，本发明的步骤序号仅仅是为了更加清楚的描述本方案流程，并不限定步骤的执行顺序。
根据本发明实施例公开的技术方案，利用数据的访问特性，将数据分为只读、只写和交叉访问三类，并利用历史访问类型，对三类数据进行区分，从而调制只读特征数据的速度，进行慢速写以实现快速读，因而极大提高读性能而几乎不影响写性能；调制只写特征数据的速度，进行快速写，极大提高写性能而几乎不影响读性能；进一步的，还可以调制交叉访问特性数据的速度，进行常速写，从而在读写速度上取得平衡。
图10为依据本发明一实施例的闪存设备访问装置1000的逻辑结构示意图，如图10所示，装置1000包括接收单元1002、获取单元1004和写入单元1006，其中，
接收单元1002，用于接收对待访问存储区域的第一写访问请求。
在具体实现过程中，接收单元1002可以由图2所示的处理器202，存储器204和通信接口208来实现。更具体的，可以由处理器202执行处理器204中的通信模块，以使通信接口208接收接收来自操作系统的第一写访问请求。
获取单元1004，用于获取待访问存储区域的历史访问类型，历史访问类型为在第一写访问请求之前待访问存储区域被访问的访问类型，其中，对闪存设备的访问类型包括写操作和读操作。
在具体实现过程中，获取单元1004可以由图2所示的处理器202和存储器204来实现。更具体的，可以由处理器202执行存储器204中的访问控制模块，以根据待访问存储区域的地址信息，获取待访问存储区域的历史访问类型。
写入单元1006，用于在待访问存储区域的历史访问类型为写操作的情况下，采用快速写的形式将第一写访问请求的待写入数据写入待访问存储区域，其中，对闪存设备的写操作的形式包括快速写和慢速写，快速写的写入速度 大于慢速写的写入速度。
在具体实现过程中，写入单元1006可以由图2所示的处理器202和存储器204来实现。更具体的，可以由处理器202执行存储器204中的访问控制模块，以采用快速写的形式将第一写访问请求的待写入数据写入待访问存储区域。
获取单元1004用于获取待访问存储区域的历史访问类型，包括：获取单元1004用于查找历史访问记录中记录的待访问存储区域的历史访问类型。
接收单元1002接收对待访问存储区域的第一写访问请求之前，还用于接收对待访问存储区域的第二写访问请求，第二写访问请求为对待访问存储区域的首次写访问请求；写入单元1006还用于将第二写访问请求的待写入数据写入待访问存储区域，并在历史访问记录中记录待访问存储区域的历史访问类型。
写入单元1006用于将第二写访问请求的待写入数据写入待访问存储区域，包括：写入单元1006用于采用慢速写的形式将第二写访问请求的待写入数据写入待访问存储区域。
装置1000还包括删除单元1008；在确定待访问存储区域中的数据失效时，删除单元1008用于将记录的待访问存储区域的历史访问类型删除。
在具体实现过程中，删除单元1008可以由图2所示的处理器202和存储器204来实现。更具体的，可以由处理器202执行存储器204中的访问控制模块，以根据接收单元1002从操作系统接收到的删除通知消息，将记录的待访问存储区域的历史访问类型删除。
可选的，写入单元1006还用于在待访问存储区域的历史访问类型不是写操作的情况下，采用慢速写的形式将第一写访问请求的待写入数据写入待访问存储区域，并更新待访问存储区域的历史访问类型。
可选的，写操作的形式还包括常速写，其中，常速写的写入速度大于慢速写的写入速度，且小于快速写的写入速度；写入单元1006还用于在待访问存储区域的历史访问类型不是写操作的情况下，采用常速写的形式将第一写访问请求的待写入数据写入待访问存储区域，并更新待访问存储区域的历史访问类型。
应理解，为了描述方便，本发明实施例的获取单元1004、写入单元1006和删除单元1008的功能可以集合在图2所示的访问控制器模块内，由处理器202执行访问控制模块的不同部分，实现不同的功能，但在具体实现中，可以 将访问控制器模块进行进一步的细化，本发明实施例对此不进行限定。
本发明实施例是存储控制器112的装置实施例，图6和图8实施例部分的特征描述，适用于本发明实施例，在此不再赘述。
图11为依据本发明一实施例的闪存设备访问装置1100的逻辑结构示意图，如图11所示，装置1100包括接收单元1102、读取单元1104、获取单元1106和写入单元1108，其中，
接收单元1102，用于接收对待访问存储区域的读访问请求。
在具体实现过程中，接收单元1102可以由图2所示的处理器202，存储器204和通信接口208来实现。更具体的，可以由处理器202执行处理器204中的通信模块，以使通信接口208接收接收来自操作系统的读访问请求。
读取单元1104，用于采用快速读的形式对待访问存储区域进行读操作，其中，对闪存设备的读操作的形式包括快速读和慢速读，快速读的读取速读大于慢速读的读取速读。
在具体实现过程中，读取单元1104可以由图2所示的处理器202和存储器204来实现。更具体的，可以由处理器202执行存储器204中的访问控制模块，以对待访问存储区域进行读操作。
获取单元1106，用于获取待访问存储区域的历史访问类型，历史访问类型为在读访问请求之前待访问存储区域被访问的访问类型，其中，对闪存设备的访问类型包括写操作和读操作。
在具体实现过程中，获取单元1106可以由图2所示的处理器202和存储器204来实现。更具体的，可以由处理器202执行存储器204中的访问控制模块，以根据待访问存储区域的地址信息，获取待访问存储区域的历史访问类型。
写入单元1108，用于在快速读译码失败，且历史访问类型为读操作的情况下，采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域，其中，对闪存设备的写操作的形式包括快速写和慢速写，快速写的写入速度大于慢速写的写入速度。
在具体实现过程中，写入单元1108可以由图2所示的处理器202和存储器204来实现。更具体的，可以由处理器202执行存储器204中的访问控制模块，以采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域。
获取单元1106用于获取待访问存储区域的历史访问类型，包括：获取单 元1106用于查找历史访问记录中记录的待访问存储区域的历史访问类型。
接收单元1102接收对待访问存储区域的读访问请求之前，还用于接收对待访问存储区域的第二写访问请求，第二写访问请求为对待访问存储区域的首次写访问请求；写入单元1108还用于将第二写访问请求的待写入数据写入待访问存储区域，并在历史访问记录中记录待访问存储区域的历史访问类型。
写入单元1108用于将第二写访问请求的待写入数据写入待访问存储区域，包括：写入单元1108用于采用慢速写的形式将第二写访问请求的待写入数据写入待访问存储区域。
装置1100还包括删除单元1110：在确定待访问存储区域中的数据失效时，删除单元1110用于将记录的待访问存储区域的历史访问类型删除。
在具体实现过程中，删除单元1110可以由图2所示的处理器202和存储器204来实现。更具体的，可以由处理器202执行存储器204中的访问控制模块，以根据接收单元1102从操作系统接收到的删除通知消息，将记录的待访问存储区域的历史访问类型删除。
可选的，读取单元1104还用于在快速读译码失败的情况下，采用慢速读的形式对待访问的存储区域进行读操作。
可选的，读操作的形式还包括常速读，其中，常速读的读取速读大于慢速读的读取速读，且小于快速读的读取速读；读取单元1104还用于在快速读译码失败的情况下，采用常速读的形式对待访问的存储区域进行读操作。
写入单元1108还用于在历史访问类型不是读操作的情况下，更新历史访问类型。
可选的，写入单元1108采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域之前，还用于将待访问存储区域的地址信息保存于重写队列；读取单元1104还用于根据重写队列中保存的地址信息，从待访问存储区域中读取待访问存储区域保存的数据。
应理解，为了描述方便，本发明实施例的读取单元1104、获取单元1106、写入单元1108和删除单元1110的功能可以集合在图2所示的访问控制器模块内，由处理器202执行访问控制模块的不同部分，实现不同的功能，但在具体实现中，可以将访问控制器模块进行进一步的细化，本发明实施例对此不进行限定。
本发明实施例是存储控制器112的装置实施例，图6和图8实施例部分的特 征描述，适用于本发明实施例，在此不再赘述。
图12为依据本发明一实施例的闪存设备访问装置1200的逻辑结构示意图，如图12所示，装置1200包括接收单元1202、获取单元1204和写入单元1206，其中，
接收单元1202，用于接收对待访问存储区域的读访问请求。
在具体实现过程中，接收单元1202可以由图2所示的处理器202，存储器204和通信接口208来实现。更具体的，可以由处理器202执行处理器204中的通信模块，以使通信接口208接收接收来自操作系统的读访问请求。
获取单元1204，用于获取待访问存储区域的历史访问信息，历史访问信息中包含待访问存储区域的历史访问类型和写入速度标记，写入速度标记用于指示待访问存储区域中保存的数据的写操作的形式，历史访问类型为在读访问请求之前待访问存储区域被访问的访问类型，其中，对闪存设备的访问类型包括写操作和读操作，对闪存设备的写操作的形式包括快速写和慢速写，快速写的写入速度大于慢速写的写入速度。
在具体实现过程中，获取单元1204可以由图2所示的处理器202和存储器204来实现。更具体的，可以由处理器202执行存储器204中的访问控制模块，以根据待访问存储区域的地址信息，获取待访问存储区域的历史访问信息。
写入单元1206，写入单元1206用于在历史访问类型为读操作，且写入速度标记不是慢速写的情况下，采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域。
在具体实现过程中，写入单元1206可以由图2所示的处理器202和存储器204来实现。更具体的，可以由处理器202执行存储器204中的访问控制模块，以采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域。
获取单元1204用于获取待访问存储区域的历史访问信息，包括：获取单元1204用于查找历史访问记录中记录的待访问存储区域的历史访问信息。
接收单元1202接收对待访问存储区域的读访问请求之前，还用于接收对待访问存储区域的第二写访问请求，第二写访问请求为对待访问存储区域的首次写访问请求；写入单元1206还用于将第二写访问请求的待写入数据写入待访问存储区域，并在历史访问记录中记录待访问存储区域的历史访问信息。
写入单元1206用于将第二写访问请求的待写入数据写入待访问存储区 域，包括：写入单元1206用于采用慢速写的形式将第二写访问请求的待写入数据写入待访问存储区域。
装置1200还包括删除单元1208：在确定待访问存储区域中的数据失效时，删除单元1208用于将记录的待访问存储区域的历史访问信息删除。
在具体实现过程中，删除单元1208可以由图2所示的处理器202和存储器204来实现。更具体的，可以由处理器202执行存储器204中的访问控制模块，以根据接收单元1202从操作系统接收到的删除通知消息，将记录的待访问存储区域的历史访问信息删除。
写入单元1206采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域之后，还用于将写入速度标记更新为慢速写。
装置1200还包括读取单元1210；读操作包括快速读和慢速读，获取单元1204获取待访问存储区域的历史访问信息之后，读取单元1210用于根据写入速度标记对待访问的存储区域进行读操作，其中，快速写对应慢速读，慢速写对应快速读。
在具体实现过程中，读取单元1210可以由图2所示的处理器202和存储器204来实现。更具体的，可以由处理器202执行存储器204中的访问控制模块，以根据写入速度标记对待访问的存储区域进行读操作。
可选的，写入单元1206采用慢速写的形式将待访问存储区域中保存的数据重新写入待访问存储区域之前，还用于将待访问存储区域的地址信息保存于重写队列；读取单元1210用于根据重写队列中保存的地址信息，从待访问存储区域中读取待访问存储区域保存的数据。
应理解，为了描述方便，本发明实施例的获取单元1204、写入单元1206、删除单元1208和读取单元1210的功能可以集合在图2所示的访问控制器模块内，由处理器202执行访问控制模块的不同部分，实现不同的功能，但在具体实现中，可以将访问控制器模块进行进一步的细化，本发明实施例对此不进行限定。
本发明实施例是存储控制器112的装置实施例，图6和图8实施例部分的特征描述，适用于本发明实施例，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，设备和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述模块的划分，仅仅为一种逻辑功能划分，实现时可以有 另外的划分方式，例如多个模块或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或模块的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理模块，即可以位于一个地方，或者也可以分布到多个网络模块上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能模块可以集成在一个处理模块中，也可以是各个模块单独物理存在，也可以两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用硬件加软件功能模块的形式实现。
上述以软件功能模块的形式实现的集成的模块，可以存储在一个计算机可读取存储介质中。上述软件功能模块存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述方法的部分步骤。而前述的存储介质包括：移动硬盘、只读存储器、随机存取存储器、磁碟或者光盘等各种可以存储程序代码的介质。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的保护范围。

Claims (59)

  1. 一种闪存设备的访问方法，其特征在于，所述闪存设备的访问类型包括写操作和读操作，所述写操作的形式包括快速写和慢速写，所述方法包括：
    接收对待访问存储区域的第一写访问请求；
    获取所述待访问存储区域的历史访问类型，所述历史访问类型为在所述第一写访问请求之前所述待访问存储区域被访问的访问类型；
    在所述待访问存储区域的历史访问类型为写操作的情况下，采用快速写的形式将所述第一写访问请求的待写入数据写入所述待访问存储区域。
  2. 根据权利要求1所述的方法，其特征在于，所述获取所述待访问存储区域的历史访问类型，包括：
    查找历史访问记录中记录的所述待访问存储区域的历史访问类型。
  3. 根据权利要求2所述的方法，其特征在于，所述接收对待访问存储区域的第一写访问请求之前，所述方法还包括：
    接收对待访问存储区域的第二写访问请求，所述第二写访问请求为对所述待访问存储区域的首次写访问请求；
    将所述第二写访问请求的待写入数据写入所述待访问存储区域，并在所述历史访问记录中记录所述待访问存储区域的历史访问类型。
  4. 根据权利要求3所述的方法，其特征在于，所述将所述第二写访问请求的待写入数据写入所述待访问存储区域，包括：
    采用慢速写的形式将所述第二写访问请求的待写入数据写入所述待访问存储区域。
  5. 根据权利要求2-4任一项所述的方法，其特征在于，所述方法还包括：
    在确定所述待访问存储区域中的数据失效时，将记录的所述待访问存储区域的历史访问类型删除。
  6. 根据权利要求1-5任一项所述的方法，其特征在于，所述方法还包括：
    在所述待访问存储区域的历史访问类型不是写操作的情况下，采用慢速写的形式将所述第一写访问请求的待写入数据写入所述待访问存储区域，并更新所述待访问存储区域的历史访问类型。
  7. 根据权利要求1-5任一项所述的方法，其特征在于，所述写操作的形式还包括常速写，其中，所述常速写的写入速度大于所述慢速写的写入速度， 且小于所述快速写的写入速度；
    所述方法还包括：
    在所述待访问存储区域的历史访问类型不是写操作的情况下，采用常速写的形式将所述第一写访问请求的待写入数据写入所述待访问存储区域，并更新所述待访问存储区域的历史访问类型。
  8. 一种闪存设备的访问方法，其特征在于，闪存设备的访问类型包括写操作和读操作，所述写操作的形式包括快速写和慢速写，所述读操作的形式包括快速读和慢速读，所述方法包括：
    接收对待访问存储区域的读访问请求；
    采用快速读的形式对所述待访问存储区域进行读操作；
    获取所述待访问存储区域的历史访问类型，所述历史访问类型为在所述读访问请求之前所述待访问存储区域被访问的访问类型；
    在所述快速读译码失败，且所述历史访问类型为读操作的情况下，采用慢速写的形式将所述待访问存储区域中保存的数据重新写入所述待访问存储区域。
  9. 根据权利要求8所述的方法，其特征在于，所述获取所述待访问存储区域的历史访问类型，包括：
    查找历史访问记录中记录的所述待访问存储区域的历史访问类型。
  10. 根据权利要求9所述的方法，其特征在于，所述接收对待访问存储区域的读访问请求之前，所述方法还包括：
    接收对待访问存储区域的第二写访问请求，所述第二写访问请求为对所述待访问存储区域的首次写访问请求；
    将所述第二写访问请求的待写入数据写入所述待访问存储区域，并在所述历史访问记录中记录所述待访问存储区域的历史访问类型。
  11. 根据权利要求10所述的方法，其特征在于，所述将所述第二写访问请求的待写入数据写入所述待访问存储区域，包括：
    采用慢速写的形式将所述第二写访问请求的待写入数据写入所述待访问存储区域。
  12. 根据权利要求9-11任一项所述的方法，其特征在于，所述方法还包括：
    在确定所述待访问存储区域中的数据失效时，将记录的所述待访问存储 区域的历史访问类型删除。
  13. 根据权利要求8-12任一项所述的方法，其特征在于，所述方法还包括：
    在所述快速读译码失败的情况下，采用所述慢速读的形式对所述待访问的存储区域进行读操作。
  14. 根据权利要求8-12任一项所述的方法，其特征在于，所述读操作的形式还包括常速读，其中，所述常速读的读取速读大于所述慢速读的读取速读，且小于所述快速读的读取速读；
    所述方法还包括：
    在所述快速读译码失败的情况下，采用所述常速读的形式对所述待访问的存储区域进行读操作。
  15. 根据权利要求8-14任一项所述的方法，其特征在于，所述方法还包括：
    在所述历史访问类型不是读操作的情况下，更新所述历史访问类型。
  16. 根据权利要求8-15任一项所述的方法，其特征在于，所述采用慢速写的形式将所述待访问存储区域中保存的数据重新写入所述待访问存储区域之前，所述方法还包括：
    将所述待访问存储区域的地址信息保存于重写队列；
    根据所述重写队列中保存的所述地址信息，从所述待访问存储区域中读取所述待访问存储区域保存的数据。
  17. 一种闪存设备的访问方法，其特征在于，闪存设备的访问类型包括写操作和读操作，所述写操作的形式包括快速写和慢速写，所述方法包括：
    接收对待访问存储区域的读访问请求；
    获取所述待访问存储区域的历史访问信息，所述历史访问信息中包含所述待访问存储区域的历史访问类型和写入速度标记，所述写入速度标记用于指示所述待访问存储区域中保存的数据的写操作的形式，所述历史访问类型为在所述读访问请求之前所述待访问存储区域被访问的访问类型；
    在所述历史访问类型为读操作，且所述写入速度标记不是慢速写的情况下，采用慢速写的形式将所述待访问存储区域中保存的数据重新写入所述待访问存储区域。
  18. 根据权利要求17所述的方法，其特征在于，所述获取所述待访问存 储区域的历史访问信息，包括：
    查找历史访问记录中记录的所述待访问存储区域的历史访问信息。
  19. 根据权利要求18所述的方法，其特征在于，所述接收对待访问存储区域的读访问请求之前，所述方法还包括：
    接收对待访问存储区域的第二写访问请求，所述第二写访问请求为对所述待访问存储区域的首次写访问请求；
    将所述第二写访问请求的待写入数据写入所述待访问存储区域，并在所述历史访问记录中记录所述待访问存储区域的历史访问信息。
  20. 根据权利要求19所述的方法，其特征在于，所述将所述第二写访问请求的待写入数据写入所述待访问存储区域，包括：
    采用慢速写的形式将所述第二写访问请求的待写入数据写入所述待访问存储区域。
  21. 根据权利要求18-20任一项所述的方法，其特征在于，所述方法还包括：
    在确定所述待访问存储区域中的数据失效时，将记录的所述待访问存储区域的历史访问信息删除。
  22. 根据权利要求17-21任一项所述的方法，其特征在于，所述采用慢速写的形式将所述待访问存储区域中保存的数据重新写入所述待访问存储区域之后，所述方法还包括：
    将所述写入速度标记更新为慢速写。
  23. 根据权利要求17-22任一项所述的方法，其特征在于，所述读操作包括快速读和慢速读，所述获取所述待访问存储区域的历史访问信息之后，所述方法还包括：
    根据所述写入速度标记对所述待访问的存储区域进行读操作，其中，所述快速写对应所述慢速读，所述慢速写对应所述快速读。
  24. 根据权利要求17-23任一项所述的方法，其特征在于，所述采用慢速写的形式将所述待访问存储区域中保存的数据重新写入所述待访问存储区域之前，所述方法还包括：
    将所述待访问存储区域的地址信息保存于重写队列；
    根据所述重写队列中保存的所述地址信息，从所述待访问存储区域中读取所述待访问存储区域保存的数据。
  25. 一种闪存设备的访问装置，其特征在于，所述闪存设备的访问类型包括写操作和读操作，所述写操作的形式包括快速写和慢速写，所述装置包括：
    接收单元，用于接收对待访问存储区域的第一写访问请求；
    获取单元，用于获取所述待访问存储区域的历史访问类型，所述历史访问类型为在所述第一写访问请求之前所述待访问存储区域被访问的访问类型；
    写入单元，用于在所述待访问存储区域的历史访问类型为写操作的情况下，采用快速写的形式将所述第一写访问请求的待写入数据写入所述待访问存储区域。
  26. 根据权利要求25所述的装置，其特征在于，所述获取单元用于获取所述待访问存储区域的历史访问类型，包括：
    所述获取单元用于查找历史访问记录中记录的所述待访问存储区域的历史访问类型。
  27. 根据权利要求26所述的装置，其特征在于，所述接收单元接收对待访问存储区域的第一写访问请求之前，还用于接收对待访问存储区域的第二写访问请求，所述第二写访问请求为对所述待访问存储区域的首次写访问请求；
    所述写入单元还用于将所述第二写访问请求的待写入数据写入所述待访问存储区域，并在所述历史访问记录中记录所述待访问存储区域的历史访问类型。
  28. 根据权利要求27所述的装置，其特征在于，所述写入单元用于将所述第二写访问请求的待写入数据写入所述待访问存储区域，包括：
    所述写入单元用于采用慢速写的形式将所述第二写访问请求的待写入数据写入所述待访问存储区域。
  29. 根据权利要求26-28任一项所述的装置，其特征在于，所述装置还包括删除单元；
    在确定所述待访问存储区域中的数据失效时，所述删除单元用于将记录的所述待访问存储区域的历史访问类型删除。
  30. 根据权利要求25-29任一项所述的装置，其特征在于，所述写入单元还用于在所述待访问存储区域的历史访问类型不是写操作的情况下，采用 慢速写的形式将所述第一写访问请求的待写入数据写入所述待访问存储区域，并更新所述待访问存储区域的历史访问类型。
  31. 根据权利要求25-29任一项所述的装置，其特征在于，所述写操作的形式还包括常速写，其中，所述常速写的写入速度大于所述慢速写的写入速度，且小于所述快速写的写入速度；
    所述写入单元还用于在所述待访问存储区域的历史访问类型不是写操作的情况下，采用常速写的形式将所述第一写访问请求的待写入数据写入所述待访问存储区域，并更新所述待访问存储区域的历史访问类型。
  32. 一种闪存设备的访问装置，其特征在于，闪存设备的访问类型包括写操作和读操作，所述写操作的形式包括快速写和慢速写，所述读操作的形式包括快速读和慢速读，所述装置包括：
    接收单元，用于接收对待访问存储区域的读访问请求；
    读取单元，用于采用快速读的形式对所述待访问存储区域进行读操作；
    获取单元，用于获取所述待访问存储区域的历史访问类型，所述历史访问类型为在所述读访问请求之前所述待访问存储区域被访问的访问类型；
    写入单元，用于在所述快速读译码失败，且所述历史访问类型为读操作的情况下，采用慢速写的形式将所述待访问存储区域中保存的数据重新写入所述待访问存储区域。
  33. 根据权利要求32所述的装置，其特征在于，所述获取单元用于获取所述待访问存储区域的历史访问类型，包括：
    所述获取单元用于查找历史访问记录中记录的所述待访问存储区域的历史访问类型。
  34. 根据权利要求33所述的装置，其特征在于，所述接收单元接收对待访问存储区域的读访问请求之前，还用于接收对待访问存储区域的第二写访问请求，所述第二写访问请求为对所述待访问存储区域的首次写访问请求；
    所述写入单元还用于将所述第二写访问请求的待写入数据写入所述待访问存储区域，并在所述历史访问记录中记录所述待访问存储区域的历史访问类型。
  35. 根据权利要求34所述的装置，其特征在于，所述写入单元用于将所述第二写访问请求的待写入数据写入所述待访问存储区域，包括：
    所述写入单元用于采用慢速写的形式将所述第二写访问请求的待写入数 据写入所述待访问存储区域。
  36. 根据权利要求33-35任一项所述的装置，其特征在于，所述装置还包括删除单元：
    在确定所述待访问存储区域中的数据失效时，所述删除单元用于将记录的所述待访问存储区域的历史访问类型删除。
  37. 根据权利要求32-36任一项所述的装置，其特征在于，所述读取单元还用于在所述快速读译码失败的情况下，采用所述慢速读的形式对所述待访问的存储区域进行读操作。
  38. 根据权利要求32-36任一项所述的装置，其特征在于，所述读操作的形式还包括常速读，其中，所述常速读的读取速读大于所述慢速读的读取速读，且小于所述快速读的读取速读；
    所述读取单元还用于在所述快速读译码失败的情况下，采用所述常速读的形式对所述待访问的存储区域进行读操作。
  39. 根据权利要求32-38任一项所述的装置，其特征在于，所述写入单元还用于在所述历史访问类型不是读操作的情况下，更新所述历史访问类型。
  40. 根据权利要求32-39任一项所述的装置，其特征在于，所述写入单元采用慢速写的形式将所述待访问存储区域中保存的数据重新写入所述待访问存储区域之前，还用于将所述待访问存储区域的地址信息保存于重写队列；
    所述读取单元还用于根据所述重写队列中保存的所述地址信息，从所述待访问存储区域中读取所述待访问存储区域保存的数据。
  41. 一种闪存设备的访问装置，其特征在于，闪存设备的访问类型包括写操作和读操作，所述写操作的形式包括快速写和慢速写，所述装置包括：
    接收单元，用于接收对待访问存储区域的读访问请求；
    获取单元，用于获取所述待访问存储区域的历史访问信息，所述历史访问信息中包含所述待访问存储区域的历史访问类型和写入速度标记，所述写入速度标记用于指示所述待访问存储区域中保存的数据的写操作的形式，所述历史访问类型为在所述读访问请求之前所述待访问存储区域被访问的访问类型；
    写入单元，用于在所述历史访问类型为读操作，且所述写入速度标记不是慢速写的情况下，采用慢速写的形式将所述待访问存储区域中保存的数据重新写入所述待访问存储区域。
  42. 根据权利要求41所述的装置，其特征在于，所述获取单元用于获取所述待访问存储区域的历史访问信息，包括：
    所述获取单元用于查找历史访问记录中记录的所述待访问存储区域的历史访问信息。
  43. 根据权利要求42所述的装置，其特征在于，所述接收单元接收对待访问存储区域的读访问请求之前，还用于接收对待访问存储区域的第二写访问请求，所述第二写访问请求为对所述待访问存储区域的首次写访问请求；
    所述写入单元还用于将所述第二写访问请求的待写入数据写入所述待访问存储区域，并在所述历史访问记录中记录所述待访问存储区域的历史访问信息。
  44. 根据权利要求43所述的装置，其特征在于，所述写入单元用于将所述第二写访问请求的待写入数据写入所述待访问存储区域，包括：
    所述写入单元用于采用慢速写的形式将所述第二写访问请求的待写入数据写入所述待访问存储区域。
  45. 根据权利要求42-44任一项所述的装置，其特征在于，所述装置还包括删除单元：
    在确定所述待访问存储区域中的数据失效时，所述删除单元用于将记录的所述待访问存储区域的历史访问信息删除。
  46. 根据权利要求41-45任一项所述的装置，其特征在于，所述写入单元采用慢速写的形式将所述待访问存储区域中保存的数据重新写入所述待访问存储区域之后，还用于将所述写入速度标记更新为慢速写。
  47. 根据权利要求41-46任一项所述的装置，其特征在于，所述读操作包括快速读和慢速读，所述装置还包括读取单元；
    所述获取单元获取所述待访问存储区域的历史访问信息之后，所述读取单元用于根据所述写入速度标记对所述待访问的存储区域进行读操作，其中，所述快速写对应所述慢速读，所述慢速写对应所述快速读。
  48. 根据权利要求41-47任一项所述的装置，其特征在于，所述装置还包括读取单元；
    所述写入单元采用慢速写的形式将所述待访问存储区域中保存的数据重新写入所述待访问存储区域之前，还用于将所述待访问存储区域的地址信息保存于重写队列；
    所述读取单元用于根据所述重写队列中保存的所述地址信息，从所述待访问存储区域中读取所述待访问存储区域保存的数据。
  49. 一种可读介质，其特征在于，包括执行指令，当存储控制器的处理器执行所述执行指令时，所述存储控制器执行权利要求1-24任一项所述的方法。
  50. 一种存储控制器，其特征在于，包括：处理器、存储器和总线；
    所述存储器用于存储执行指令，所述处理器与所述存储器通过所述总线连接，当所述存储控制器运行时，所述处理器执行所述存储器存储的所述执行指令，以使所述存储控制器执行权利要求1-24任一项所述的方法。
  51. 一种闪存设备，其特征在于，所述闪存设备的访问类型包括写操作和读操作，所述写操作的形式包括快速写和慢速写，所述闪存设备包括存储控制器和闪存阵列：
    所述闪存阵列用于存储数据；
    所述存储控制器用于接收对所述闪存阵列的待访问存储区域的第一写访问请求，并获取所述待访问存储区域的历史访问类型，所述历史访问类型为在所述第一写访问请求之前所述待访问存储区域被访问的访问类型，在所述待访问存储区域的历史访问类型为写操作的情况下，采用快速写的形式将所述第一写访问请求的待写入数据写入所述待访问存储区域。
  52. 根据权利要求51所述的闪存设备，其特征在于，所述存储控制器还用于：
    在所述待访问存储区域的历史访问类型不是写操作的情况下，采用慢速写的形式将所述第一写访问请求的待写入数据写入所述待访问存储区域，并更新所述待访问存储区域的历史访问类型。
  53. 根据权利要求51所述的闪存设备，其特征在于，所述写操作的形式还包括常速写，其中，所述常速写的写入速度大于所述慢速写的写入速度，且小于所述快速写的写入速度；
    所述存储控制器还用于：
    在所述待访问存储区域的历史访问类型不是写操作的情况下，采用常速写的形式将所述第一写访问请求的待写入数据写入所述待访问存储区域，并更新所述待访问存储区域的历史访问类型。
  54. 一种闪存设备，其特征在于，闪存设备的访问类型包括写操作和读 操作，所述写操作的形式包括快速写和慢速写，所述读操作的形式包括快速读和慢速读，所述闪存设备包括存储控制器和闪存阵列：
    所述闪存阵列用于存储数据；
    所述存储控制器用于接收对所述存储阵列的待访问存储区域的读访问请求，采用快速读的形式对所述待访问存储区域进行读操作，并获取所述待访问存储区域的历史访问类型，所述历史访问类型为在所述读访问请求之前所述待访问存储区域被访问的访问类型，在所述快速读译码失败，且所述历史访问类型为读操作的情况下，采用慢速写的形式将所述待访问存储区域中保存的数据重新写入所述待访问存储区域。
  55. 根据权利要求54所述的闪存设备，其特征在于，所述存储控制器还用于在所述快速读译码失败的情况下，采用所述慢速读的形式对所述待访问的存储区域进行读操作。
  56. 根据权利要求54所述的闪存设备，其特征在于，所述读操作的形式还包括常速读，其中，所述常速读的读取速读大于所述慢速读的读取速读，且小于所述快速读的读取速读；
    所述存储控制器还用于在所述快速读译码失败的情况下，采用所述常速读的形式对所述待访问的存储区域进行读操作。
  57. 一种闪存设备，其特征在于，闪存设备的访问类型包括写操作和读操作，所述写操作的形式包括快速写和慢速写，所述闪存设备包括存储控制器和闪存阵列：
    所述闪存阵列用于存储数据；
    所述存储控制器用于接收对待访问存储区域的读访问请求，获取所述待访问存储区域的历史访问信息，所述历史访问信息中包含所述待访问存储区域的历史访问类型和写入速度标记，所述写入速度标记用于指示所述待访问存储区域中保存的数据的写操作的形式，所述历史访问类型为在所述读访问请求之前所述待访问存储区域被访问的访问类型，在所述历史访问类型为读操作，且所述写入速度标记不是慢速写的情况下，采用慢速写的形式将所述待访问存储区域中保存的数据重新写入所述待访问存储区域。
  58. 根据权利要求57所述的闪存设备，其特征在于，所述存储控制器采用慢速写的形式将所述待访问存储区域中保存的数据重新写入所述待访问存储区域之后，还用于将所述写入速度标记更新为慢速写。
  59. 根据权利要求57或58所述的方法，其特征在于，所述读操作包括快速读和慢速读，所述存储控制器获取所述待访问存储区域的历史访问信息之后，还用于根据所述写入速度标记对所述待访问的存储区域进行读操作，其中，对所述闪存设备的读操作的形式包括快速读和慢速读，快速读的读取速读大于慢速读的读取速读，所述快速写对应所述慢速读，所述慢速写对应所述快速读。
PCT/CN2016/074140 2016-02-19 2016-02-19 一种闪存设备的访问方法和装置 WO2017139973A1 (zh)

Priority Applications (9)

Application Number Priority Date Filing Date Title
PCT/CN2016/074140 WO2017139973A1 (zh) 2016-02-19 2016-02-19 一种闪存设备的访问方法和装置
SG11201806099WA SG11201806099WA (en) 2016-02-19 2016-02-19 Method and apparatus for accessing flash memory device
CN201680000818.0A CN107710169B (zh) 2016-02-19 2016-02-19 一种闪存设备的访问方法和装置
KR1020187023110A KR102114256B1 (ko) 2016-02-19 2016-02-19 플래시 메모리 디바이스 액세스 방법 및 장치
CA3012236A CA3012236C (en) 2016-02-19 2016-02-19 Method and apparatus for accessing flash memory device
EP16890206.2A EP3399421B1 (en) 2016-02-19 2016-02-19 Flash memory device access method and apparatus
AU2016393275A AU2016393275B2 (en) 2016-02-19 2016-02-19 Method and apparatus for accessing flash memory device
JP2018543654A JP6817318B2 (ja) 2016-02-19 2016-02-19 フラッシュメモリデバイスにアクセスするための方法および装置
US16/105,723 US10732898B2 (en) 2016-02-19 2018-08-20 Method and apparatus for accessing flash memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2016/074140 WO2017139973A1 (zh) 2016-02-19 2016-02-19 一种闪存设备的访问方法和装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/105,723 Continuation US10732898B2 (en) 2016-02-19 2018-08-20 Method and apparatus for accessing flash memory device

Publications (1)

Publication Number Publication Date
WO2017139973A1 true WO2017139973A1 (zh) 2017-08-24

Family

ID=59624787

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/074140 WO2017139973A1 (zh) 2016-02-19 2016-02-19 一种闪存设备的访问方法和装置

Country Status (9)

Country Link
US (1) US10732898B2 (zh)
EP (1) EP3399421B1 (zh)
JP (1) JP6817318B2 (zh)
KR (1) KR102114256B1 (zh)
CN (1) CN107710169B (zh)
AU (1) AU2016393275B2 (zh)
CA (1) CA3012236C (zh)
SG (1) SG11201806099WA (zh)
WO (1) WO2017139973A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110083545A (zh) * 2018-01-25 2019-08-02 爱思开海力士有限公司 数据存储装置及其操作方法
CN111061433A (zh) * 2019-12-17 2020-04-24 深圳佰维存储科技股份有限公司 冷热数据处理方法及装置
CN111208940A (zh) * 2019-12-24 2020-05-29 华东师范大学 一种基于多通道闪存的读写分离方法

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11106391B2 (en) * 2018-04-25 2021-08-31 Micron Technology, Inc. Managing a memory system including memory devices with different characteristics
US11061762B2 (en) * 2019-02-04 2021-07-13 Intel Corporation Memory programming techniques
JP2020149123A (ja) * 2019-03-11 2020-09-17 キオクシア株式会社 メモリシステム、及びメモリシステムの制御方法
KR20210017401A (ko) * 2019-08-08 2021-02-17 에스케이하이닉스 주식회사 데이터 저장 장치 및 그 동작 방법과, 이를 위한 컨트롤러
WO2021079535A1 (ja) * 2019-10-23 2021-04-29 株式会社ソニー・インタラクティブエンタテインメント 情報処理装置
CN111104066B (zh) 2019-12-17 2021-07-27 华中科技大学 数据写入方法、装置及存储服务器和计算机可读存储介质
US11573621B2 (en) * 2020-07-25 2023-02-07 International Business Machines Corporation Reduction of performance impacts of storage power control by migration of write-intensive extent
US11625297B2 (en) 2020-08-28 2023-04-11 Samsung Electronics Co., Ltd. Storage device and operating method thereof
KR20220092021A (ko) * 2020-12-24 2022-07-01 삼성전자주식회사 스토리지 컨트롤러 및 이를 포함하는 스토리지 시스템
US11868642B2 (en) * 2021-08-31 2024-01-09 Micron Technology, Inc. Managing trim commands in a memory sub-system
JP2023136816A (ja) 2022-03-17 2023-09-29 キオクシア株式会社 メモリシステム
CN116303125B (zh) * 2023-05-16 2023-09-29 太初(无锡)电子科技有限公司 请求调度方法、缓存、装置、计算机设备及存储介质
CN117234434B (zh) * 2023-11-14 2024-02-20 苏州元脑智能科技有限公司 存储设备的操作控制方法及装置
CN118012355A (zh) * 2024-04-10 2024-05-10 上海朔集半导体科技有限公司 模拟eeprom及其控制方法、模拟控制器、存储介质

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102073592A (zh) * 2009-11-19 2011-05-25 中兴通讯股份有限公司 一种闪存快速读写方法和装置
CN102667739A (zh) * 2010-01-13 2012-09-12 株式会社东芝 存储装置管理装置及用于管理存储装置的方法
CN104503710A (zh) * 2015-01-23 2015-04-08 福州瑞芯微电子有限公司 一种提高闪存写入速度的方法和装置

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5848621A (en) 1996-03-22 1998-12-15 Illinois Tool Works Inc. Cutter for steel strapping tool
JP3930074B2 (ja) * 1996-09-30 2007-06-13 株式会社ルネサステクノロジ 半導体集積回路及びデータ処理システム
JP2007102267A (ja) * 2005-09-30 2007-04-19 Toshiba Corp アクセス履歴管理方法、アクセス履歴管理装置、アクセス履歴管理プログラム、記憶装置及び情報処理装置
JP4749255B2 (ja) * 2006-07-03 2011-08-17 株式会社日立製作所 複数種類の記憶デバイスを備えたストレージシステムの制御装置
KR101397549B1 (ko) * 2007-08-16 2014-05-26 삼성전자주식회사 고속 프로그램이 가능한 불휘발성 반도체 메모리 시스템 및그것의 독출 방법
US8706951B2 (en) * 2008-07-18 2014-04-22 Marvell World Trade Ltd. Selectively accessing faster or slower multi-level cell memory
US8627017B2 (en) * 2008-12-30 2014-01-07 Intel Corporation Read and write monitoring attributes in transactional memory (TM) systems
US8473677B2 (en) * 2009-09-29 2013-06-25 Cleversafe, Inc. Distributed storage network memory access based on memory state
JP5815388B2 (ja) * 2011-12-02 2015-11-17 株式会社メガチップス メモリアクセス制御装置および方法
US20130318418A1 (en) * 2012-05-22 2013-11-28 Politecncio di Milano Adaptive error correction for phase change memory
JP2014086062A (ja) * 2012-10-29 2014-05-12 Sony Corp 記憶制御装置、記憶装置、情報処理システム、および、記憶制御方法
KR102053953B1 (ko) * 2013-02-04 2019-12-11 삼성전자주식회사 불휘발성 메모리 장치를 포함하는 메모리 시스템 및 그것의 프로그램 방법
US9646705B2 (en) * 2013-06-12 2017-05-09 Samsung Electronics Co., Ltd. Memory systems including nonvolatile memory devices and dynamic access methods thereof
KR20140146333A (ko) * 2013-06-17 2014-12-26 삼성전자주식회사 메모리 컨트롤러와 이의 동작 방법
US10656842B2 (en) * 2014-05-30 2020-05-19 Sandisk Technologies Llc Using history of I/O sizes and I/O sequences to trigger coalesced writes in a non-volatile storage device
US10146448B2 (en) * 2014-05-30 2018-12-04 Sandisk Technologies Llc Using history of I/O sequences to trigger cached read ahead in a non-volatile storage device
CN105242871B (zh) * 2014-06-06 2018-06-05 华为技术有限公司 一种数据写入方法及装置
CN104331252B (zh) * 2014-10-10 2017-08-25 上海新储集成电路有限公司 异构nand固态硬盘结构及其数据读取管理方法
CN104575618B (zh) * 2015-01-13 2017-08-08 重庆大学 一种基于闪存错误校验的读写调制方法
US9792191B2 (en) * 2015-08-19 2017-10-17 Nxp Usa, Inc. Fast write mechanism for emulated electrically erasable (EEE) system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102073592A (zh) * 2009-11-19 2011-05-25 中兴通讯股份有限公司 一种闪存快速读写方法和装置
CN102667739A (zh) * 2010-01-13 2012-09-12 株式会社东芝 存储装置管理装置及用于管理存储装置的方法
CN104503710A (zh) * 2015-01-23 2015-04-08 福州瑞芯微电子有限公司 一种提高闪存写入速度的方法和装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3399421A4 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110083545A (zh) * 2018-01-25 2019-08-02 爱思开海力士有限公司 数据存储装置及其操作方法
CN110083545B (zh) * 2018-01-25 2023-08-18 爱思开海力士有限公司 数据存储装置及其操作方法
CN111061433A (zh) * 2019-12-17 2020-04-24 深圳佰维存储科技股份有限公司 冷热数据处理方法及装置
CN111208940A (zh) * 2019-12-24 2020-05-29 华东师范大学 一种基于多通道闪存的读写分离方法

Also Published As

Publication number Publication date
EP3399421A4 (en) 2019-02-13
EP3399421B1 (en) 2023-03-22
KR20180103106A (ko) 2018-09-18
AU2016393275A1 (en) 2018-08-09
CA3012236C (en) 2021-02-16
JP6817318B2 (ja) 2021-01-20
CN107710169B (zh) 2024-03-26
JP2019512832A (ja) 2019-05-16
CA3012236A1 (en) 2017-08-24
EP3399421A1 (en) 2018-11-07
US10732898B2 (en) 2020-08-04
SG11201806099WA (en) 2018-08-30
US20180357013A1 (en) 2018-12-13
AU2016393275B2 (en) 2019-10-10
KR102114256B1 (ko) 2020-05-22
CN107710169A (zh) 2018-02-16

Similar Documents

Publication Publication Date Title
WO2017139973A1 (zh) 一种闪存设备的访问方法和装置
CN108369818B (zh) 一种闪存设备的刷新方法和装置
EP2940691B1 (en) Storage controller, storage device, storage system and method of operating the storage controller
US9384123B2 (en) Memory system
TWI584125B (zh) 輸入／輸出裝置及計算主機相互運作
CN111752487B (zh) 一种数据恢复方法、装置及固态硬盘
US10936203B2 (en) Memory storage device and system employing nonvolatile read/write buffers
KR20210070379A (ko) 메모리 서브-시스템의 요구 시 리프레시 동작을 수행하는 방법
US11526438B2 (en) Memory system capable of increasing storage efficiency and operation method thereof
CN110968522B (zh) 存储器系统及其操作方法、包括存储器系统的数据库系统
KR102281750B1 (ko) 비-휘발성 메모리에서 데이터 유효성 추적
KR20200122522A (ko) 컨트롤러 및 그 동작 방법
US10303397B1 (en) Read disturb handling in storage devices
KR20220041225A (ko) 메모리 구성요소의 동일한 평면 내에서 데이터 압축
US11698742B2 (en) Garbage collection in a memory component using an adjusted parameter
US20240143211A1 (en) Storage device, host device and computing system

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 201680000818.0

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16890206

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 11201806099W

Country of ref document: SG

WWE Wipo information: entry into national phase

Ref document number: 3012236

Country of ref document: CA

WWE Wipo information: entry into national phase

Ref document number: 2016890206

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2016393275

Country of ref document: AU

Date of ref document: 20160219

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 2016890206

Country of ref document: EP

Effective date: 20180803

Ref document number: 20187023110

Country of ref document: KR

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 1020187023110

Country of ref document: KR

ENP Entry into the national phase

Ref document number: 2018543654

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE