WO2017128755A1 - 像素单元、阵列基板及其制作方法 - Google Patents

像素单元、阵列基板及其制作方法 Download PDF

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WO2017128755A1
WO2017128755A1 PCT/CN2016/100742 CN2016100742W WO2017128755A1 WO 2017128755 A1 WO2017128755 A1 WO 2017128755A1 CN 2016100742 W CN2016100742 W CN 2016100742W WO 2017128755 A1 WO2017128755 A1 WO 2017128755A1
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partitions
slit
pixel unit
pixel
adjacent
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PCT/CN2016/100742
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English (en)
French (fr)
Inventor
邵喜斌
陈东川
廖燕平
张振宇
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US15/541,427 priority Critical patent/US10247987B2/en
Publication of WO2017128755A1 publication Critical patent/WO2017128755A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures

Definitions

  • the present invention relates to the field of display, and in particular, to a pixel unit, an array substrate, and a method of fabricating the same.
  • a pixel unit is usually disposed in a region of a minimum cell surrounded by two adjacent gate lines and two adjacent data lines (where the gate lines intersect the data lines).
  • the slits of the slit electrodes (for example, the pixel electrodes) in the pixel unit are inclined in the same direction, the light transmittance can be increased, but the color deviations in the left, right, and upper and lower viewing angles are caused.
  • the technical solution of the present invention has been proposed in view of the above problems in the prior art.
  • the present invention provides a pixel unit structure having a plurality of domain regions and an array substrate having the pixel unit structure, which is capable of eliminating the problem of color deviation to the utmost extent and having good light transmittance.
  • a pixel unit includes a slit electrode including four partitions, and slit electrodes in the four partitions are electrically connected to each other.
  • the slit unit of the slit electrode in each of the four partitions has a slit oblique direction, and the slit of the pixel unit in any two adjacent partitions of the four partitions The slits of the electrodes are inclined in different directions.
  • the pixel unit is located at a position where the gate line intersects the data line, and the four partitions of the pixel unit are divided by the corresponding gate line and data line.
  • the slit tilt direction of the slit electrode of the pixel unit in the four partitions is mirror symmetrical with respect to the gate line and/or the data line.
  • an acute angle between a slit oblique direction of the slit electrode of the pixel unit and the gate line is between 3 and 20 degrees.
  • an acute angle between a slit oblique direction of the slit electrode of the pixel unit and the data line is between 3 and 20 degrees.
  • the area enclosed by two adjacent gate lines and two adjacent data lines is a minimum unit, and the four partitions of the pixel unit are respectively included in four adjacent In the smallest unit, and each of the smallest units includes four partitions respectively belonging to four adjacent pixel units.
  • the slit electrodes included in the four partitions within the same minimum unit are electrically isolated from each other, and the slit electrodes included in the four partitions within the same minimum unit have the same slit tilt direction .
  • the four zones occupy an equal area of the opening.
  • the slit electrode is a pixel electrode.
  • the pixel unit further includes a common electrode and a thin film transistor at an intersection of the gate line and the data line, wherein a source of the thin film transistor is electrically connected to the data line, and a drain of the thin film transistor The slit electrode is electrically connected through the via.
  • the slit electrode is a common electrode.
  • the pixel unit according to the present invention is disposed at a position where the gate line intersects the data line, and includes four partitions electrically connected to each other by the gate line and the data line. Since the slit direction of the slit electrodes in any two adjacent partitions of the pixel unit according to the present invention is different, the pixel unit according to the present invention includes a plurality of domains in the upper and lower directions and the left and right directions. Area. Thus, the pixel unit according to the present invention not only improves the upper and lower color deviations, but also improves the left and right color deviations, thus eliminating the problem of color deviation to the utmost extent.
  • the pixel unit according to the present invention is disposed at a position where the gate line intersects the data line
  • the smallest unit surrounded by the adjacent two gate lines and the adjacent two data lines may include four adjacent Four partitions of the pixel unit.
  • the slit electrodes included in the four partitions included in the same minimum unit are disposed to have the same slit tilt direction, and thus the liquid crystal molecules in the same minimum unit are aligned uniformly, thereby providing good light transmittance.
  • an array substrate includes a plurality of gate lines and a plurality of data lines disposed at intersections, and a plurality of pixel units disposed at intersections of the respective gate lines and the respective data lines, each of the pixel units including a slit electrode, and Each of the pixel units includes four partitions divided by gate lines and data lines, and slit electrodes in the four partitions are electrically connected to each other, wherein each pixel unit is in each of the four partitions
  • the slits of the slit electrodes are inclined in the same direction, and the slit direction of the slit electrodes in any two adjacent ones of the four partitions is different.
  • the area enclosed by two adjacent gate lines and two adjacent data lines The domain is a minimum unit, four partitions of the pixel unit are respectively included in four adjacent minimum units, and each minimum unit includes four partitions respectively belonging to four adjacent pixel units.
  • the slit electrodes included in the four partitions within the same minimum unit are electrically isolated from each other, and the slit electrodes included in the four partitions within the same minimum unit have the same slit tilt direction .
  • the four zones occupy an equal area of the opening.
  • the slit electrode is a pixel electrode.
  • the array substrate according to the present invention includes a plurality of gate lines and a plurality of data lines arranged in a cross, and a plurality of pixel units disposed at intersections of the respective gate lines and the respective data lines. Since each pixel unit of the array substrate includes four partitions electrically connected to each other by the gate line and the data line, the pixel unit includes two domain regions in the upper and lower directions, and includes two in the left and right directions. Domain area. Therefore, the array substrate not only improves the upper and lower color deviations as a whole, but also improves the left and right color deviations, thereby eliminating the problem of chromatic aberration deviation to the greatest extent.
  • the slit electrodes in the four partitions included in each of the smallest cells of the array substrate are disposed to have the same slit tilt direction such that the liquid crystal molecules in the same minimum unit are oriented uniformly, thereby making the array
  • the substrate provides good light transmission as a whole.
  • a method of fabricating an array substrate includes the steps of: forming a plurality of gate lines and a plurality of data lines disposed in a crossover manner; and providing a plurality of pixel units at intersections of the respective gate lines and the respective data lines.
  • Each of the pixel units includes slit electrodes, and each of the pixel units includes four partitions divided by gate lines and data lines, and slit electrodes in the four partitions are electrically connected to each other.
  • the slit direction of the slit electrode in each of the four partitions of each pixel unit is uniform, and the slit of each pixel unit in any two adjacent partitions of the four partitions
  • the slits of the electrodes are inclined in different directions.
  • the area enclosed by two adjacent gate lines and two adjacent data lines is a minimum unit, and the four partitions of the pixel unit are respectively included in four adjacent minimum units. And each of the smallest units includes four partitions respectively belonging to four adjacent pixel units.
  • the slits are included in four partitions within the same smallest unit
  • the electrodes are electrically isolated from each other, and the slit electrodes included in the four partitions within the same minimum unit have the same slit tilt direction.
  • the four zones occupy an equal area of the opening.
  • FIG. 1 is a schematic structural diagram of a pixel unit according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural view of an array substrate according to an embodiment of the present invention.
  • FIG. 3 schematically illustrates a flow chart of a method of fabricating an array substrate in accordance with one embodiment of the present invention.
  • spatially relative terms such as “below”, “above”, “on the left”, “on the right”, etc. may be used herein to describe the The relationship of one element or feature to another (some) element or feature. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. For example, an element that is described as “under other elements or features” will be &quot Thus, the exemplary term “below” can encompass both the “under” and “in”.
  • the device may be oriented (rotated 90 degrees or at other orientations) in other ways, and the spatially relative descriptors used herein will be interpreted accordingly.
  • FIG. 1 is a schematic structural diagram of a pixel unit in accordance with one embodiment of the present invention.
  • the pixel unit 10 (the portion enclosed by a broken line in FIG. 1) is located at the gate line. 20 is at a position intersecting the data line 30.
  • the pixel unit 10 includes four sections a1, b1, c1, and d1 divided by the gate line 20 and the data line 30, and the slit electrodes in the four sections a1, b1, c1, and d1 are electrically connected to each other.
  • the slit direction of the slit electrodes in the pixel unit 10 in any two adjacent partitions is different. For example, as shown in FIG.
  • the partition a1 and the partition b1 are two adjacent partitions, and the slit direction of the slit electrode of the pixel unit 10 in the partition a1 is oblique to the slit of the slit electrode in the partition b1.
  • the partition a1 and the partition c1 are two adjacent partitions, and the slit direction of the slit electrode of the pixel unit 10 in the partition a1 is different from the slit tilt direction of the slit electrode in the partition c1.
  • the pixel unit 10 is disposed at a position where the gate line 20 intersects the data line 30, and includes four partitions a1, b1, c1, and d1 electrically connected to each other by the gate line 20 and the data line 30. Since the slit direction of the slit electrodes of the pixel unit 10 in any two adjacent partitions is different, the pixel unit 10 includes a plurality of domain regions in the upper and lower directions and the left and right directions. That is, the four partitions a1, b1, c1, and d1 of the pixel unit 10 are formed as four domain regions, and the pixel unit 10 includes two domain regions in the upper and lower directions, and includes two in the left and right directions. Domain area. Thus, the pixel unit 10 not only improves the color deviation in the upper and lower directions, but also improves the color deviation in the left and right directions, thereby eliminating the problem of color deviation to the greatest extent.
  • the acute angle between the slit oblique direction of the slit electrode in the four sections a1, b1, c1, and d1 and the gate line 20 of the pixel unit 10 is ⁇ 1, ⁇ 2, ⁇ 3, and ⁇ 4, respectively.
  • the slit tilt direction of the slit electrodes of the pixel unit 10 in the four sections a1, b1, c1, and d1 is mirror-symmetrical with respect to the gate line 20 and/or the data line 30, and the force of the liquid crystal molecules in the pixel unit 10 can be made. It is even.
  • the acute angles ⁇ 1, ⁇ 2, ⁇ 3, and ⁇ 4 between the slit oblique direction of the slit electrode of the pixel unit 10 in the four sections a1, b1, c1, and d1 and the gate line 20 may be 3- Between 20 degrees.
  • the acute angle between the slit oblique direction of the slit electrode of the pixel unit 10 in the four sections a1, b1, c1, and d1 and the data line 30 may be between 3 and 20 degrees.
  • the four partitions a1, b1, c1, and d1 of the pixel unit 10 are respectively included in four.
  • each of the smallest units includes four partitions respectively belonging to four adjacent pixel units.
  • the partition a1 of the pixel unit 10 is included in the minimum unit A, while the smallest unit A further includes three partitions a2, a3, and a4 belonging to the other three pixel units, respectively;
  • the partition b1 of the pixel unit 10 is included in the minimum unit In B, the minimum unit B also includes three partitions b2, b3, and b4 respectively belonging to the other three pixel units;
  • the partition c1 of the pixel unit 10 is included in the minimum unit C, and the minimum unit C further includes three other The three partitions c2, c3, and c4 of the pixel unit;
  • the partition d1 of the pixel unit 10 are included in the minimum unit D, while the smallest unit D further includes three partitions d2, d3, and d4 respectively belonging to the other three pixel units.
  • the slit electrodes included in the four partitions in the same minimum unit are electrically isolated from each other, and the slit electrodes included in the four partitions in the same minimum unit have the same slit tilt direction.
  • the slit electrodes included in the four partitions a1, a2, a3, and a4 in the minimum unit A are electrically isolated from each other because the four partitions a1, a2, a3, and a4 belong to four phases, respectively. Adjacent pixel unit.
  • the slit electrodes in the four sections a1, a2, a3, and a4 have the same slit tilt direction, so that the respective slit electrodes in the minimum unit A have the same slit tilt direction.
  • the slit electrodes included in the four partitions included in the same minimum unit are set to have the same slit tilt direction so that the liquid crystal molecules in the same minimum unit are aligned uniformly, thereby providing good light transmittance.
  • the opening areas occupied by the four partitions a1, b1, c1, and d1 of the pixel unit 10 may be equal. Further, the opening areas of the four partitions included in each of the smallest units may be equal (for example, the opening areas of the four partitions a1, a2, a3, and a4 included in the minimum unit A are equal).
  • the slit electrode may be a pixel electrode.
  • the pixel unit 10 further includes a common electrode and a thin film transistor located at an intersection of the gate line 20 and the data line 30, wherein a source of the thin film transistor is electrically connected to the data line 30, a drain of the thin film transistor and the narrow
  • the slit electrodes are electrically connected through the via holes.
  • the slit electrode may also be a common electrode.
  • the slit electrode is a common electrode for a high aperture ratio HADS display mode. Since the common electrode layer is fabricated and connected to the same common electrode signal, the connection between the partitions is not required, and the problem of the color deviation is eliminated to the greatest extent by partitioning the plate-shaped pixel electrode in the aforementioned manner.
  • An insulating layer is disposed between the pixel electrode and the corresponding common electrode, and the pixel is electrically The poles are placed above or below the corresponding common electrode.
  • FIG. 2 is a schematic structural view of an array substrate in accordance with an embodiment of the present invention.
  • the array substrate 100 includes a plurality of gate lines 20 and a plurality of data lines 30 disposed in a crosswise manner, and a plurality of pixel units 10 disposed at intersections of the respective gate lines 20 and the respective data lines 30.
  • Each of the pixel units 10 includes four sections a1, b1, c1, and d1 divided by the gate lines 20 and the data lines 30, and the slit electrodes in the four sections a1, b1, c1, and d1 are electrically connected to each other.
  • the slit electrodes of the slit electrodes in any two adjacent partitions of each pixel unit 10 are inclined in different directions.
  • the area enclosed by the adjacent two gate lines 20 and the adjacent two data lines 30 formed on the array substrate 100 is a minimum unit.
  • the four partitions a1, b1, c1, and d1 of the respective pixel units 10 of the array substrate 100 may be included in four adjacent minimum units A, B, C, and D, respectively, and each of the minimum units may include four respectively.
  • slit electrodes included in four partitions within the same minimum unit are electrically isolated from each other, and slit electrodes included in four partitions within the same minimum unit have the same slit tilt direction.
  • the four sections a1, b1, c1, and d1 of the pixel unit 10 occupy the same opening area. Further, the area of the opening occupied by all the partitions formed on the array substrate 100 is equal.
  • the slit of the slit electrode according to the present invention may be in the form of an opening or a closed form.
  • the array substrate 100 includes a plurality of gate lines 20 and a plurality of data lines 30 disposed in a crosswise manner, and a plurality of pixel units 10 disposed at intersections of the respective gate lines 20 and the respective data lines 30. Since each of the pixel units 10 of the array substrate 100 includes four partitions a1, b1, c1, and d1 electrically connected to each other by the gate lines 20 and the data lines 30, the pixel unit 10 is caused to include two domains in the upper and lower directions. Zone, and includes two domain regions in the left and right directions. Therefore, the array substrate 100 not only improves the upper and lower color deviations as a whole, but also improves the left and right color deviations, thereby eliminating the problem of chromatic aberration deviation to the utmost extent.
  • the slit electrodes included in the four partitions in each of the smallest cells of the array substrate 100 are disposed to have the same slit tilt direction such that liquid crystal molecules in the same minimum cell are aligned uniformly, thereby making The array substrate 100 provides a good light transmittance as a whole.
  • FIG. 3 schematically illustrates a flow chart of a method of fabricating an array substrate in accordance with one embodiment of the present invention.
  • the method of fabricating an array substrate according to the present invention includes the steps of:
  • each of the pixel units includes four partitions divided by the gate lines and the data lines, and the slit electrodes in the four partitions Electrically connected to each other,
  • the slit direction of the slit electrodes in any two adjacent partitions of each pixel unit is different.
  • a region surrounded by adjacent two gate lines and adjacent two data lines formed on the array substrate is a minimum unit.
  • the four partitions of the pixel unit may each be included in four adjacent minimum units, and each of the minimum units may include four partitions respectively belonging to four adjacent pixel units.
  • the slit electrodes included in the four partitions within the same minimum unit may be electrically isolated from each other, and the slit electrodes included in the four partitions within the same minimum unit may have the same slit tilt direction.
  • the opening area occupied by the four partitions of the pixel unit may be equal.
  • a method of fabricating an array substrate according to the present invention places each pixel unit at an intersection of each of the gate lines and each of the data lines such that each of the pixel units includes four partitions divided by the gate lines and the data lines. Since each pixel unit includes four partitions electrically connected to each other by gate lines and data lines, the pixel unit is included in the upper and lower directions by two domain regions, and two domain regions are included in the left and right directions. . Therefore, not only the color deviation in the upper and lower directions is improved, but also the color deviation in the left and right directions is improved, so that the problem of color deviation is eliminated to the utmost extent.
  • the slit electrodes included in the four partitions included in the same minimum unit are set to have the same slit tilt direction so that the liquid crystal molecules in the same minimum unit are aligned uniformly, thereby providing good light transmittance.

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Abstract

一种像素单元（10）、阵列基板及其制作方法。所述像素单元（10）包括狭缝电极，并且所述像素单元（10）包括四个分区（a1，b1，c1，d1），所述四个分区（a1，b1，c1，d1）中的狭缝电极之间相互电连接，所述像素单元（10）在所述四个分区（a1，b1，c1，d1）中的每一个分区中的狭缝电极的狭缝倾斜方向一致，并且所述像素单元（10）在所述四个分区（a1，b1，c1，d1）中的任意两个相邻分区中的狭缝电极的狭缝倾斜方向不同。具有多个畴区的像素单元（10）结构以及具有该像素单元（10）结构的阵列基板，能够在最大程度上消除色彩偏差的问题，并且具有良好的光透过率。

Description

像素单元、阵列基板及其制作方法 技术领域
本发明涉及显示领域，尤其涉及像素单元、阵列基板及其制作方法。
背景技术
现有技术中，像素单元通常设置在由相邻两条栅线和相邻两条数据线(其中，栅线与数据线交叉)所围成的最小单元的区域中。当像素单元中的狭缝电极(例如，像素电极)的狭缝倾斜方向相同时，可以提高光透过率，但是会造成左、右和上、下视角下的色彩偏差。
发明内容
针对现有技术中的上述问题，提出了本发明的技术方案。本发明提供了一种具有多个畴区的像素单元结构以及具有该像素单元结构的阵列基板，其能够在最大程度上消除色彩偏差的问题，并且具有良好的光透过率。
根据本发明的一个方面，提供了一种像素单元。所述像素单元包括狭缝电极，该像素单元包括四个分区，所述四个分区中的狭缝电极之间相互电连接。所述像素单元在所述四个分区中的每一个分区中的狭缝电极的狭缝倾斜方向一致，并且所述像素单元在所述四个分区中的任意两个相邻分区中的狭缝电极的狭缝倾斜方向不同。
在一个实施例中，所述像素单元位于栅线与数据线交叉的位置处，并且所述像素单元的四个分区由相应的栅线和数据线划分。
在一个实施例中，所述像素单元在所述四个分区中的狭缝电极的狭缝倾斜方向关于所述栅线和/或数据线呈镜像对称。
在一个实施例中，所述像素单元的狭缝电极的狭缝倾斜方向与所述栅线之间的锐角角度在3-20度之间。
在一个实施例中，所述像素单元的狭缝电极的狭缝倾斜方向与所述数据线之间的锐角角度在3-20度之间。
在一个实施例中，由相邻两条栅线和相邻两条数据线所围成的区域为一个最小单元，所述像素单元的四个分区分别包括在四个相邻的 最小单元中，并且每个最小单元包括分别属于四个相邻像素单元的四个分区。
在一个实施例中，包括在同一个最小单元内的四个分区中的狭缝电极相互电隔离，并且包括在同一个最小单元内的四个分区中的狭缝电极具有相同的狭缝倾斜方向。
在一个实施例中，所述四个分区所占的开口面积相等。
在一个实施例中，所述狭缝电极是像素电极。
在一个实施例中，所述像素单元还包括公共电极以及位于栅线和数据线交点处的薄膜晶体管，其中所述薄膜晶体管的源极与所述数据线电连接，所述薄膜晶体管的漏极与所述狭缝电极通过过孔电连接。
在一个实施例中，所述狭缝电极是公共电极。
根据本发明的像素单元设置在栅线与数据线交叉的位置处，并且包括了由栅线和数据线划分的彼此电连接的四个分区。由于根据本发明的像素单元在任意两个相邻分区中的狭缝电极的狭缝倾斜方向不同，因此根据本发明的像素单元在上、下方向和左、右方向上均包括了多个畴区。因而，根据本发明的像素单元不仅改善了上、下色彩偏差，还改善了左、右色彩偏差，因此在最大程度上消除了色彩偏差的问题。
此外，由于根据本发明的像素单元设置在栅线与数据线交叉的位置处，所以由相邻两条栅线和相邻两条数据线所围成的最小单元可以包括分别属于四个相邻像素单元的四个分区。将包括在同一个最小单元内的四个分区中的狭缝电极设置为具有相同的狭缝倾斜方向，因此在同一最小单元内的液晶分子取向一致，从而提供了良好的光透过率。
根据本发明的另一个方面，提供了一种阵列基板。所述阵列基板包括交叉设置的多条栅线和多条数据线，以及设置在各条栅线与各条数据线的交叉位置处的多个像素单元，每个像素单元包括狭缝电极，并且每个像素单元包括由栅线和数据线划分的四个分区，所述四个分区中的狭缝电极之间相互电连接，其中，每个像素单元在所述四个分区中的每一个分区中的狭缝电极的狭缝倾斜方向一致，并且每个像素单元在所述四个分区中的任意两个相邻分区中的狭缝电极的狭缝倾斜方向不同。
在一个实施例中，由相邻两条栅线和相邻两条数据线所围成的区 域为一个最小单元，所述像素单元的四个分区分别包括在四个相邻的最小单元中，并且每个最小单元包括分别属于四个相邻像素单元的四个分区。
在一个实施例中，包括在同一个最小单元内的四个分区中的狭缝电极相互电隔离，并且包括在同一个最小单元内的四个分区中的狭缝电极具有相同的狭缝倾斜方向。
在一个实施例中，所述四个分区所占的开口面积相等。
在一个实施例中，所述狭缝电极是像素电极。
根据本发明的阵列基板包括交叉设置的多条栅线和多条数据线，以及设置在各条栅线与各条数据线的交叉位置处的多个像素单元。由于阵列基板的各个像素单元包括由栅线和数据线划分的彼此电连接的四个分区，因此使得像素单元在上、下方向上包括了两个畴区，并且在左、右方向上包括了两个畴区。因而，阵列基板在整体上不仅改善了上、下色彩偏差，还改善了左、右色彩偏差，因此在最大程度上消除色差偏差的问题。
将包括在阵列基板的各个最小单元中的每一个最小单元内的四个分区中的狭缝电极设置为具有相同的狭缝倾斜方向，使得在同一最小单元内的液晶分子取向一致，从而使得阵列基板在整体上提供了良好的光透过率。
根据本发明的另一个方面，提供了一种制作阵列基板的方法。所述制作阵列基板的方法包括步骤：形成交叉设置的多条栅线和多条数据线；以及在各条栅线与各条数据线的交叉位置处设置多个像素单元。每个像素单元包括狭缝电极，并且每个像素单元包括由栅线和数据线划分的四个分区，所述四个分区中的狭缝电极之间相互电连接。每个像素单元在所述四个分区中的每一个分区中的狭缝电极的狭缝倾斜方向一致，并且每个像素单元在所述四个分区中的任意两个相邻分区中的狭缝电极的狭缝倾斜方向不同。
在一个实施例中，由相邻两条栅线和相邻两条数据线所围成的区域为一个最小单元，所述像素单元的四个分区分别包括在四个相邻的最小单元中，并且每个最小单元包括分别属于四个相邻像素单元的四个分区。
在一个实施例中，包括在同一个最小单元内的四个分区中的狭缝 电极相互电隔离，并且包括在同一个最小单元内的四个分区中的狭缝电极具有相同的狭缝倾斜方向。
在一个实施例中，所述四个分区所占的开口面积相等。
附图说明
通过以下结合附图的详细描述，将更加清楚地理解本发明的以上和其它特征和优点，其中：
图1是根据本发明的一个实施例的像素单元的示意性结构图；
图2是根据本发明的一个实施例的阵列基板的示意性结构图；以及
图3示意性地示出了根据本发明的一个实施例的制造阵列基板的方法流程图。
具体实施方式
下文中，将参照附图详细描述本发明构思的示例性实施例。
然而，本发明构思可按照许多不同形式例示，并且不应理解为限于本文阐述的特定实施例。此外，提供这些实施例是为了使得本公开将是彻底和完整的，并且将把本发明构思的范围完全传递给本领域技术人员。
为了清楚起见，在附图中可夸大示出元件的形状和尺寸。并且相同的附图标记将用于始终指代相同或相似的元件。
为了方便描述，本文中可使用诸如“在……下方”、“在……上方”、“在……左侧”、“在……右侧”等的空间相对术语，以描述附图中所示的一个元件或特征与另一个(一些)元件或特征的关系。应该理解，空间相对术语旨在涵盖使用或操作中的装置的除图中所示的取向之外的不同取向。例如，如果图中的装置颠倒，则被描述为“在其它元件或特征下方”的元件将因此被取向为“在其它元件或特征上方”。这样，示例性术语“在……下方”可涵盖“在……下方”和“在……上方”这两个取向。装置可按照其它方式取向(旋转90度或位于其它取向)，并且本文所用的空间相对描述语将相应地解释。
图1是根据本发明一个实施例的像素单元的示意性结构图。
如图1所示，像素单元10(图1中由虚线所围成的部分)位于栅线 20与数据线30交叉的位置处。像素单元10包括由栅线20和数据线30划分的四个分区a1、b1、c1和d1，四个分区a1、b1、c1和d1中的狭缝电极之间相互电连接。像素单元10在任意两个相邻分区中的狭缝电极的狭缝倾斜方向不同。例如，如图1所示，分区a1与分区b1为两个相邻分区，像素单元10在分区a1中的狭缝电极的狭缝倾斜方向与在分区b1中的狭缝电极的狭缝倾斜方向不同；分区a1与分区c1为两个相邻分区，像素单元10在分区a1中的狭缝电极的狭缝倾斜方向与在分区c1中的狭缝电极的狭缝倾斜方向不同。
像素单元10设置在栅线20与数据线30交叉的位置处，并且包括由栅线20和数据线30划分的彼此电连接的四个分区a1、b1、c1和d1。由于像素单元10在任意两个相邻分区中的狭缝电极的狭缝倾斜方向不同，因此像素单元10在上、下方向和左、右方向上均包括了多个畴区。也就是说，像素单元10的四个分区a1、b1、c1和d1形成为四个畴区，像素单元10在上、下方向上包括了两个畴区，并且在左、右方向上包括了两个畴区。因而，像素单元10不仅改善了上、下方向上的色彩偏差，还改善了左、右方向上的色彩偏差，因此在最大程度上消除色彩偏差的问题。
如图1所示，像素单元10在四个分区a1、b1、c1和d1中的狭缝电极的狭缝倾斜方向与栅线20之间的锐角分别为α1、α2、α3和α4。像素单元10在四个分区中的狭缝电极的狭缝倾斜方向可以关于栅线20呈镜像对称，即，α1＝α3且α2＝α4。此外，像素单元在四个分区中的狭缝电极的狭缝倾斜方向可以关于数据线30呈镜像对称，即，α1＝α2且α3＝α4。再者，像素单元10在四个分区中的狭缝电极的狭缝倾斜方向可以关于栅线20和数据线30均呈镜像对称，即，α1＝α2＝α3＝α4。
像素单元10在四个分区a1、b1、c1和d1中的狭缝电极的狭缝倾斜方向关于栅线20和/或数据线30呈镜像对称，可以使得液晶分子在像素单元10中的受力是均匀的。
根据本发明的实施例，像素单元10在四个分区a1、b1、c1和d1中的狭缝电极的狭缝倾斜方向与栅线20之间的锐角α1、α2、α3和α4可以在3-20度之间。可替换地，像素单元10在四个分区a1、b1、c1和d1中的狭缝电极的狭缝倾斜方向与数据线30之间的锐角可以在3-20度之间。
如图1所示，像素单元10的四个分区a1、b1、c1和d1分别包括在四 个相邻的最小单元A、B、C和D中，并且每个最小单元包括分别属于四个相邻像素单元的四个分区。具体而言，像素单元10的分区a1包括在最小单元A中，同时最小单元A还包括分别属于另外三个像素单元的三个分区a2、a3和a4；像素单元10的分区b1包括在最小单元B中，同时最小单元B还包括分别属于另外三个像素单元的三个分区b2、b3和b4；像素单元10的分区c1包括在最小单元C中，同时最小单元C还包括分别属于另外三个像素单元的三个分区c2、c3和c4；并且像素单元10的分区d1包括在最小单元D中，同时最小单元D还包括分别属于另外三个像素单元的三个分区d2、d3和d4。
如图1所示，包括在同一个最小单元内的四个分区中的狭缝电极相互电隔离，并且包括在同一个最小单元内的四个分区中的狭缝电极具有相同的狭缝倾斜方向。具体而言，例如，包括在最小单元A中的四个分区a1、a2、a3和a4中的狭缝电极相互电隔离，这是因为四个分区a1、a2、a3和a4分别属于四个相邻的像素单元。此外，四个分区a1、a2、a3和a4中的狭缝电极具有相同的狭缝倾斜方向，从而使得在最小单元A内的各个狭缝电极具有相同的狭缝倾斜方向。
将包括在同一个最小单元内的四个分区中的狭缝电极设置为具有相同的狭缝倾斜方向，使得在同一最小单元内的液晶分子取向一致，从而提供了良好的光透过率。
像素单元10的四个分区a1、b1、c1和d1所占的开口面积可以相等。此外，每个最小单元中包含的四个分区的开口面积也可以相等(例如，最小单元A中包含的四个分区a1、a2、a3和a4的开口面积相等)。
针对高级超维场转换技术(Advanced Super Dimension Switch，ADS)显示模式，狭缝电极可以是像素电极。像素单元10还包括公共电极以及位于栅线20和数据线30交点处的薄膜晶体管，其中所述薄膜晶体管的源极与所述数据线30电连接，所述薄膜晶体管的漏极与所述狭缝电极通过过孔电连接。
可替换地，狭缝电极也可以是公共电极。狭缝电极为公共电极针对的是高开口率HADS显示模式。由于公共电极一层制作且接相同的公共电极信号，不需要进行分区间的连接，通过对板状像素电极按照前述方式进行分区，最大程度消除色彩偏差的问题。
像素电极与对应的公共电极之间设置有绝缘层，并且所述像素电 极设置在对应的公共电极上方或者下方。
图2是根据本发明的一个实施例的阵列基板的示意性结构图。
如图2所示，阵列基板100包括交叉设置的多条栅线20和多条数据线30，以及设置在各条栅线20与各条数据线30的交叉位置处的多个像素单元10。每个像素单元10包括由栅线20和数据线30划分的四个分区a1、b1、c1和d1，四个分区a1、b1、c1和d1中的狭缝电极之间相互电连接。每个像素单元10在任意两个相邻分区中的狭缝电极的狭缝倾斜方向不同。
根据本发明的实施例，由形成在阵列基板100上的相邻两条栅线20和相邻两条数据线30所围成的区域为一个最小单元。阵列基板100的各个像素单元10的四个分区a1、b1、c1和d1可以分别包括在四个相邻的最小单元A、B、C和D中，并且每个最小单元可以包括分别属于四个相邻像素单元的四个分区。
根据本发明的实施例，包括在同一个最小单元内的四个分区中的狭缝电极相互电隔离，并且包括在同一个最小单元内的四个分区中的狭缝电极具有相同的狭缝倾斜方向。
根据本发明的实施例，像素单元10的四个分区a1、b1、c1和d1所占的开口面积相等。进而，形成在阵列基板100上的所有分区所占的开口面积相等。
如图2所示，根据本发明的狭缝电极的狭缝可以为开口形式，也可以为封闭形式。
阵列基板100包括交叉设置的多条栅线20和多条数据线30，以及设置在各条栅线20与各条数据线30的交叉位置处的多个像素单元10。由于阵列基板100的各个像素单元10包括由栅线20和数据线30划分的彼此电连接的四个分区a1、b1、c1和d1，因此使得像素单元10在上、下方向上包括了两个畴区，并且在左、右方向上包括了两个畴区。因而，阵列基板100在整体上不仅改善了上、下色彩偏差，还改善了左、右色彩偏差，因此在最大程度上消除色差偏差的问题。
将包括在阵列基板100的各个最小单元中的每一个最小单元内的四个分区中的狭缝电极设置为具有相同的狭缝倾斜方向，使得在同一最小单元内的液晶分子取向一致，从而使得阵列基板100在整体上提供了良好的光透过率。
图3示意性地示出了根据本发明的一个实施例的制造阵列基板的方法流程图。
如图3所示，根据本发明的制作阵列基板的方法包括步骤：
S1、形成交叉设置的多条栅线和多条数据线；以及
S2、在各条栅线与各条数据线的交叉位置处设置多个像素单元，每个像素单元包括由栅线和数据线划分的四个分区，所述四个分区中的狭缝电极之间相互电连接，
其中，每个像素单元在任意两个相邻分区中的狭缝电极的狭缝倾斜方向不同。
根据本发明的实施例，由形成在阵列基板上的相邻两条栅线和相邻两条数据线所围成的区域为一个最小单元。像素单元的四个分区分别可以包括在四个相邻的最小单元中，并且每个最小单元可以包括分别属于四个相邻像素单元的四个分区。此外，包括在同一个最小单元内的四个分区中的狭缝电极可以相互电隔离，并且包括在同一个最小单元内的四个分区中的狭缝电极可以具有相同的狭缝倾斜方向。像素单元的四个分区所占的开口面积可以相等。
根据本发明的制作阵列基板的方法将各个像素单元设置在各条栅线与各条数据线的交叉位置处，使得每个像素单元包括由栅线和数据线划分的四个分区。由于各个像素单元包括由栅线和数据线划分的彼此电连接的四个分区，因此使得像素单元在上、下方向上包括了两个畴区，并且在左、右方向上包括了两个畴区。因而，不仅改善了上、下方向上的色彩偏差，还改善了左、右方向上的色彩偏差，因此在最大程度上消除了色彩偏差的问题。
将包括在同一个最小单元内的四个分区中的狭缝电极设置为具有相同的狭缝倾斜方向，使得在同一最小单元内的液晶分子取向一致，从而提供了良好的光透过率。
虽然已经示出并说明了根据本发明的各个实施例，但本领域普通技术人员应当理解的是，可以对这些示例性实施例在形式和细节方面做出各种改变而不背离由所附权利要求书限定的本发明构思的精神和范围。

Claims (20)

  1. 一种像素单元，包括狭缝电极，其特征在于，该像素单元包括四个分区，所述四个分区中的狭缝电极之间相互电连接，
    所述像素单元在所述四个分区中的每一个分区中的狭缝电极的狭缝倾斜方向一致，并且所述像素单元在所述四个分区中的任意两个相邻分区中的狭缝电极的狭缝倾斜方向不同。
  2. 根据权利要求1所述的像素单元，其特征在于，所述像素单元位于栅线与数据线交叉的位置处，并且所述像素单元的四个分区由相应的栅线和数据线划分。
  3. 根据权利要求2所述的像素单元，其特征在于，所述像素单元在所述四个分区中的狭缝电极的狭缝倾斜方向关于所述栅线和/或数据线呈镜像对称。
  4. 根据权利要求2或3所述的像素单元，其特征在于，所述像素单元的狭缝电极的狭缝倾斜方向与所述栅线之间的锐角角度在3-20度之间。
  5. 根据权利要求2或3所述的像素单元，其特征在于，所述像素单元的狭缝电极的狭缝倾斜方向与所述数据线之间的锐角角度在3-20度之间。
  6. 根据权利要求1至3任一所述的像素单元，其特征在于，由相邻两条栅线和相邻两条数据线所围成的区域为一个最小单元，所述像素单元的四个分区分别包括在四个相邻的最小单元中，并且每个最小单元包括分别属于四个相邻像素单元的四个分区。
  7. 根据权利要求6所述的像素单元，其特征在于，包括在同一个最小单元内的四个分区中的狭缝电极相互电隔离，并且包括在同一个最小单元内的四个分区中的狭缝电极具有相同的狭缝倾斜方向。
  8. 根据权利要求1至3任一所述的像素单元，其特征在于，所述四个分区所占的开口面积相等。
  9. 根据权利要求1至3任一所述的像素单元，其特征在于，所述狭缝电极是像素电极。
  10. 根据权利要求9所述的像素单元，其特征在于，所述像素单元还包括公共电极以及位于栅线和数据线交点处的薄膜晶体管，其中所述 薄膜晶体管的源极与所述数据线电连接，所述薄膜晶体管的漏极与所述狭缝电极通过过孔电连接。
  11. 根据权利要求1至3任一所述的像素单元，其特征在于，所述狭缝电极是公共电极。
  12. 一种阵列基板，包括交叉设置的多条栅线和多条数据线，以及设置在各条栅线与各条数据线的交叉位置处的多个像素单元，每个像素单元包括狭缝电极，并且每个像素单元包括由栅线和数据线划分的四个分区，所述四个分区中的狭缝电极之间相互电连接，
    其中，每个像素单元在所述四个分区中的每一个分区中的狭缝电极的狭缝倾斜方向一致，并且每个像素单元在所述四个分区中的任意两个相邻分区中的狭缝电极的狭缝倾斜方向不同。
  13. 根据权利要求12所述的阵列基板，其中，由相邻两条栅线和相邻两条数据线所围成的区域为一个最小单元，所述像素单元的四个分区分别包括在四个相邻的最小单元中，并且每个最小单元包括分别属于四个相邻像素单元的四个分区。
  14. 根据权利要求13所述的阵列基板，其中，包括在同一个最小单元内的四个分区中的狭缝电极相互电隔离，并且包括在同一个最小单元内的四个分区中的狭缝电极具有相同的狭缝倾斜方向。
  15. 根据权利要求12至14任一所述的阵列基板，其中，所述四个分区所占的开口面积相等。
  16. 根据权利要求12至14任一所述的阵列基板，其中，所述狭缝电极是像素电极。
  17. 一种制作阵列基板的方法，包括步骤：
    形成交叉设置的多条栅线和多条数据线；以及
    在各条栅线与各条数据线的交叉位置处设置多个像素单元，每个像素单元包括狭缝电极，并且每个像素单元包括由栅线和数据线划分的四个分区，所述四个分区中的狭缝电极之间相互电连接，
    其中，每个像素单元在所述四个分区中的每一个分区中的狭缝电极的狭缝倾斜方向一致，并且每个像素单元在所述四个分区中的任意两个相邻分区中的狭缝电极的狭缝倾斜方向不同。
  18. 根据权利要求17所述的方法，其中，由相邻两条栅线和相邻两条数据线所围成的区域为一个最小单元，所述像素单元的四个分区分 别包括在四个相邻的最小单元中，并且每个最小单元包括分别属于四个相邻像素单元的四个分区。
  19. 根据权利要求18所述的方法，其中，包括在同一个最小单元内的四个分区中的狭缝电极相互电隔离，并且包括在同一个最小单元内的四个分区中的狭缝电极具有相同的狭缝倾斜方向。
  20. 根据权利要求17至19任一所述的方法，其中，所述四个分区所占的开口面积相等。
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