WO2016141676A1 - 阵列基板和显示面板 - Google Patents

阵列基板和显示面板 Download PDF

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WO2016141676A1
WO2016141676A1 PCT/CN2015/087339 CN2015087339W WO2016141676A1 WO 2016141676 A1 WO2016141676 A1 WO 2016141676A1 CN 2015087339 W CN2015087339 W CN 2015087339W WO 2016141676 A1 WO2016141676 A1 WO 2016141676A1
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sub
array substrate
pixel electrode
pixel electrodes
pixel
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PCT/CN2015/087339
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English (en)
French (fr)
Inventor
程鸿飞
先建波
乔勇
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京东方科技集团股份有限公司
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Priority to US14/908,378 priority Critical patent/US9690158B2/en
Publication of WO2016141676A1 publication Critical patent/WO2016141676A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a display panel including the array substrate.
  • Liquid crystal display technology has been widely used in television, mobile phones and public information display.
  • the liquid crystal display can be mainly divided into a twisted nematic (TN) mode, a vertically aligned (VA) mode, and an in-plane switching (IPS) mode.
  • TN twisted nematic
  • VA vertically aligned
  • IPS in-plane switching
  • the contrast of the display is high, and 8-domain liquid crystal alignment can be realized in one pixel, so that a wide viewing angle can be obtained. Therefore, the liquid crystal display of the vertical alignment mode is obtained in the large-size liquid crystal television. Widely used.
  • the liquid crystal display panel is mainly composed of an array substrate and a color film substrate pair box.
  • the array substrate includes a plurality of gate lines and a plurality of data lines, and the gate lines and the data lines vertically intersect (because they are located in different layers, so they do not conduct when crossing), and the array substrate is divided into a plurality of pixel units, each A thin film transistor (including a gate, a source, and a drain) is disposed in each pixel unit, and a signal voltage on the data line is written into the pixel electrode through the thin film transistor.
  • the current array substrate inevitably has the following problems in practical applications:
  • a pixel electrode For a pixel electrode that realizes multi-domain liquid crystal, it generally has a rhizome portion and a branch portion, wherein the branch portion is used to control alignment of liquid crystal molecules, for example, control of alignment direction and orientation stability of liquid crystal molecules, etc., but the branch portion
  • the electric field tends to interfere with the electric field of the data line or the gate line, causing abnormal alignment of the liquid crystal molecules, resulting in a decrease in transmittance and a decrease in contrast of the array substrate.
  • An object of the present invention is to provide an array substrate and a display including the array substrate A panel which can reduce interference between an electric field of a branch portion of the pixel electrode and an electric field of the data line and/or the gate line, so that alignment of the liquid crystal molecules can be better controlled.
  • an array substrate which includes a plurality of data lines and a plurality of gate lines disposed in a cross, a plurality of data lines are arranged in parallel, and a plurality of gate lines are arranged in parallel.
  • the gate line and the data line vertically intersect to divide the array substrate into a plurality of pixel units, each of which is provided with a pixel electrode, the pixel electrode includes a sub-pixel electrode, and the sub-pixel electrode includes a root stem and is connected thereto a branching group consisting of a plurality of branching portions, and adjacent branching portions are separated by slits; the branching portion group partially overlapping the data lines and/or the gate lines.
  • the number of the sub-pixel electrodes in each of the pixel electrodes is one or more, and in a case where the number of the sub-pixel electrodes in each of the pixel electrodes is plural, A plurality of the sub-pixel electrodes are arranged in a direction parallel to the data lines.
  • At least one of the sub-pixel electrodes of each of the pixel electrodes further includes a connection portion for directing all of the branch portions of the sub-pixel electrode toward the end of the data line The portions are connected to each other; or, the end portions of the adjacent branch portions of the sub-pixel electrode facing the data line are connected to each other.
  • a branching group of at least one of the sub-pixel electrodes of each of the pixel electrodes partially overlaps a gate line adjacent thereto.
  • At least one of the sub-pixel electrodes of each of the pixel electrodes partially overlaps at least one of the two data lines adjacent thereto.
  • Each slit in the electrode is disposed oppositely.
  • each of the at least one of the sub-pixel electrodes of each of the pixel electrodes may be sub-divided with the sub-pixel electrode and defined by the same gate line and different data lines.
  • Each of the slits in the pixel electrode is alternately arranged.
  • the array substrate further includes a resin layer disposed between the pixel electrode and the data line.
  • the thickness of the resin layer ranges from 0.5 to 5 ⁇ m.
  • the array substrate further includes a color film layer, and the color film layer is disposed on the Between the pixel electrode and the data line.
  • the thickness of the color film layer ranges from 0.5 to 3 ⁇ m.
  • a display panel comprising an array substrate and a counter substrate disposed with the array substrate, the array substrate being the array substrate provided by the present invention.
  • the electric field and the data line and/or the gate of the branch portion group of the sub-pixel electrode can be reduced.
  • the interference between the electric fields of the wires can better control the alignment of the liquid crystal molecules, thereby improving the transmittance of the array substrate and increasing the contrast, thereby improving the display quality of the display panel including the array substrate.
  • the display panel provided by the embodiment of the invention can better control the arrangement of the liquid crystal molecules by using the array substrate, thereby improving the transmittance of the display panel, increasing the contrast, and improving the display quality of the display panel.
  • FIG. 1A is a schematic plan view showing a single pixel electrode of an array substrate according to an embodiment of the present invention.
  • Fig. 1B is a cross-sectional view taken along line A1-A2 of Fig. 1A.
  • 1C is a cross-sectional view taken along line B1-B2 of FIG. 1A.
  • FIG. 2 is a schematic plan view showing a single pixel electrode of another array substrate according to an embodiment of the present invention.
  • FIG. 3A is a schematic plan view showing still another single pixel electrode of an array substrate according to an embodiment of the present invention.
  • FIG. 3B is a schematic plan view showing a single pixel electrode of another array substrate according to an embodiment of the present invention.
  • 4A is a schematic plan view of two adjacent pixel electrodes of an array substrate according to an embodiment of the present invention.
  • FIG. 4B is a schematic plan view showing two adjacent pixel electrodes of another array substrate according to an embodiment of the present invention.
  • the array substrate provided by the invention comprises a plurality of data lines and a plurality of gate lines arranged in a cross, a plurality of gate lines are arranged in parallel, a plurality of data lines are also arranged in parallel, and the gate lines and the data lines are vertically intersected to divide the array substrate into a plurality of a pixel unit, each of which is provided with a pixel electrode, the pixel electrode includes a sub-pixel electrode, and the sub-pixel electrode includes a root stem portion and a branch portion group connected thereto, the branch portion group is composed of a plurality of branch portions, and the phase The adjacent branches are separated by slits. Multi-domain liquid crystal alignment can be achieved by means of the root stem portion and the branching group connected thereto.
  • the branch portion group of the sub-pixel electrode partially overlaps the data line and/or the gate line, which can reduce interference between the electric field of the branch portion group of the sub-pixel electrode and the electric field of the data line and/or the gate line, thereby
  • the alignment of the liquid crystal molecules can be better controlled, and the transmittance of the array substrate can be improved, and the contrast can be increased, thereby improving the display quality of the display panel including the array substrate.
  • the number of sub-pixel electrodes may be one or more, and in the case where the number of sub-pixel electrodes in each pixel electrode is plural, a plurality of The sub-pixel electrodes are arranged in a direction parallel to the data lines.
  • FIG. 1A is a schematic plan view of a single pixel electrode of an array substrate according to an embodiment of the present invention.
  • Fig. 1B is a cross-sectional view taken along line A1-A2 of Fig. 1A.
  • 1C is a cross-sectional view taken along line B1-B2 of FIG. 1A.
  • the array substrate of the embodiment includes a plurality of data lines 30 and a plurality of gate lines 10 arranged in a cross, wherein the plurality of gate lines 10 are 10 1 , 10 2 , ...
  • the gate line 10 may be of a single layer structure, or may be of a multi-layer structure and made of materials such as Mo ⁇ Al ⁇ Mo, Ti ⁇ Cu ⁇ Ti or MoTi ⁇ Cu.
  • the plurality of data lines 30 are data lines 30 1 , 30 2 , ... 30 j , 30 j+1 , .
  • the pixel electrode is defined by a gate line 10 i and two adjacent data lines 30 j and 30 j+1 , the pixel electrode including two sub-pixel electrodes arranged in a direction parallel to the data line 30 And a first sub-pixel electrode 50 and a second sub-pixel electrode 51, respectively, each of which includes a rhizome portion and a branch portion group connected thereto.
  • the rhizome portion of the first sub-pixel electrode 50 includes a rhizome portion 50a parallel to the gate line 10 and a rhizome portion 50b parallel to the data line 30, and the two have a crisscross shape.
  • the root portion of the second sub-pixel electrode 51 includes a rhizome portion 51a parallel to the gate line 10 and a rhizome portion 51b parallel to the data line 30, which are in a crisscross shape.
  • the branch portion group of the first sub-pixel electrode 50 is composed of a plurality of branch portions 50c, each of which is connected to the root stem portion 50a or the root stem portion 50b, and the adjacent branch portions 50c are separated by the slit 50d.
  • the branch portion group of the second sub-pixel electrode 51 is composed of a plurality of branch portions 51c, each of which is connected to the root stem portion 51a or the root stem portion 51b, and the adjacent branch portions 51c are separated by the slit 51d.
  • the 8-domain liquid crystal alignment can be realized by the above-mentioned root stem portion and the branch portion group connected thereto, as shown in Fig. 1A.
  • the branch groups of the two sub-pixel electrodes (50, 51) are partially overlapped with the two data lines (30 j , 30 j+1 ) adjacent thereto to reduce the two Interference between the electric field of the branching group of the sub-pixel electrode and the electric field of the two data lines (30 j , 30 j+1 ).
  • the partial overlap of the branch portion with the data line means that the orthographic projection of the two on the substrate of the array substrate has overlapping portions and non-overlapping portions, and the manner in which the branch portion group partially overlaps the data lines includes the following Two, the first way is: the outer end of the branch extends beyond the outer edge of the data line, as shown in Figure 1A; the second way is: the outer end of the branch extends only beyond the inner edge of the data line Without exceeding the outer edge of the data line.
  • branch portions of the first sub-pixel electrode 50 or the second sub-pixel electrode 51 may be separate and adjacent to the two data lines (30 j , 30 j+1 ) portions according to different needs.
  • the branch portions of the first sub-pixel electrode 50 and/or the second sub-pixel electrode 51 may partially overlap the data line 30 j or the data line 30 j+1 .
  • the first sub-pixel electrode 50 is electrically connected to the data line 30 j through the first thin film transistor T1; the second sub-pixel electrode 51 passes through the second thin film transistor T2 and the data line 30 j+ adjacent thereto. 1 electrical connection.
  • the source 31 of the first thin film transistor T1 is connected to the data line 30 j
  • the drain 33 of the first thin film transistor T1 is connected to the first sub-pixel electrode 50 through the via 40
  • the source of the second thin film transistor T2 is The adjacent data lines 30 j+1 are connected
  • the drain of the second thin film transistor T2 is connected to the second sub-pixel electrode 51 through the via 41.
  • the array substrate further includes a substrate 1 and a gate insulating layer 15 and a passivation layer 38 which are sequentially disposed from bottom to top, wherein the gate line 10 and the common electrode 151 are disposed on the substrate 1 and the gate. Between the layers 15; the active layer 25, the source 31 and the drain 33 of the thin film transistor are disposed between the gate insulating layer 15 and the passivation layer 38; the sub-pixel electrodes (50, 51) are disposed on the passivation layer 38 .
  • the array substrate may further include a resin layer, which may be disposed between the pixel electrode and the data line 30, for example, between the pixel electrode and the passivation layer 38, or may be disposed on the data line 30 and the passivation layer. Between 38, the thickness of the resin layer ranges from 0.5 to 5 ⁇ m, preferably from 1 to 3 ⁇ m. With this resin layer, it is possible to further reduce the influence of the electric field of the data line 30 on the pixel electrode.
  • a color film layer may be disposed on the array substrate, and the color film layer may be disposed between the pixel electrode and the data line 30, for example, between the pixel electrode and the passivation layer 38, or may be disposed.
  • the thickness of the color filter layer ranges from 0.5 to 3 ⁇ m, preferably from 1 to 2.5 ⁇ m.
  • FIG. 2 is a schematic plan view showing a single pixel electrode of another array substrate according to an embodiment of the present invention.
  • the array substrate is further improved on the basis of the array substrate in the foregoing embodiment, that is, the first sub-pixel electrode 50 further includes a connecting portion 50e.
  • the connecting portion 50e is configured to connect the ends of all the branch portions 50c of the first sub-pixel electrode 50 toward the data line 30 j and the data line 30 j+1 , that is, the first sub-pixel electrode
  • the respective branch portions 50c of 50 are connected to each other at the edges of the left and right sides of the first sub-pixel electrode 50 in FIG. 2 through the connection portion 50e.
  • the electric field generated by the branch portion 50c can be adjusted by the connecting portion 50e.
  • the connection portion may be provided only on the first sub-pixel electrode 50 or the second sub-pixel electrode 51 according to different needs, or may be simultaneously on the first sub-pixel electrode 50 and the second sub-pixel electrode 51. Set the connection on the top.
  • the connecting portion 50e may connect all the end portions of the branch portion 50c of the first sub-pixel electrode 50 toward only the data line 30j or the data line 30j+1 .
  • the connecting portion 50e connects the ends of all the branch portions 50c of the first sub-pixel electrode 50 toward the ends of the data line 30j and the data line 30j+1 , respectively.
  • the present invention is not limited thereto, and in actual use, the connecting portion 50e may connect only the end portions of the adjacent sub-pixel electrodes 50 that face the data lines to each other.
  • FIG. 3A is a schematic plan view showing still another single pixel electrode of an array substrate according to an embodiment of the present invention.
  • the array substrate is further improved on the basis of the array substrate in any of the foregoing embodiments.
  • the branch portion group of the first sub-pixel electrode 50 is adjacent to the gate line 10 i , and the branch portion group of the first sub-pixel electrode 50 partially overlaps the gate line 10 i to reduce The interference between the electric field of the branch portion group of the small first sub-pixel electrode 50 and the electric field of the gate line 10 i .
  • the branch portion group of the second sub-pixel electrode 51 and the gate line 10 i-1 adjacent to the second sub-pixel electrode 51 may be partially overlapped.
  • the branch portions of the first sub-pixel electrode 50 and the second sub-pixel electrode 51 may be partially overlapped with the gate line 10 i and the gate line 10 i-1 , respectively.
  • the partial overlap of the branch portion and the gate line means that the orthographic projections of the two on the substrate of the array substrate have overlapping portions and non-overlapping portions, and the branch portions and the gate lines are partially partially
  • the manner of overlapping includes the following two methods.
  • the first mode is that the outer end of the branch portion extends only beyond the inner edge of the gate line without exceeding the outer edge of the gate line, as shown in FIGS. 3A and 3B; The way is that the outer end of the branch portion extends beyond the outer edge of the grid line.
  • the first sub-pixel electrode 50L and the second sub-pixel electrode 51L are defined by one gate line 10 i and two adjacent data lines 30 j and 30 j+1 ; the first sub-pixel electrode 50R and the second sub-pixel The electrode 51R is defined by one gate line 10 i and two adjacent data lines 30 j+2 and 30 j+3 ; wherein the first sub-pixel electrode 50L and the first sub-pixel electrode 50R are adjacent to each other and have the same gate line (ie, gate line 10 i ) and different data lines (30 j and 30 j+1 and 30 j+2 and 30 j+3 ) are defined, and the slits in both are slit 50dL and slit 50dR, respectively.
  • the slit 50dL and the slit 50dR are opposed to each other, that is, the opening of the slit 50dL faces the opening of the slit 50dR.
  • the second sub-pixel electrode 51L and the second sub-pixel electrode 51R are adjacent to each other and have the same gate line (ie, gate line 10 i ) and different data lines (30 j and 30 j+1 and 30 j+2 and 30 j+3 ) is defined, and the slits in both are the slit 51dL and the slit 51dR, respectively, and the slit 51dL and the slit 51dR are opposed to each other.
  • the slit 50dL and the slit 50dR may be alternately arranged, that is, the opening of the slit 50dL and the opening of the slit 50dR are staggered with each other; at the same time, the slit 51dL and the slit 51dR are interlaced.
  • the setting is such that the electric field of the adjacent two pixel electrodes is better prevented from interfering.
  • slits of any two adjacent sub-pixel electrodes defined by the same gate line and different data lines may be oppositely disposed or staggered according to specific conditions.
  • the number of sub-pixel electrodes disposed in each pixel electrode is two, but the present invention is not limited thereto, and in practical applications, the sub-units are disposed in each pixel electrode.
  • the number of the pixel electrodes may also be one or three or more, and in the case where the number of sub-pixel electrodes provided in each of the pixel electrodes is plural, the plurality of sub-pixel electrodes may be arranged in a direction parallel to the data lines, Or arrange in any other way as needed.
  • the root stem portion is crisscrossed, and the branch portion group is connected to the cross-shaped root stem portion, but the present invention is not limited thereto.
  • the rhizome portion and the branch portion group of any other structure may also be employed, and the present invention is not particularly limited thereto.
  • the branch portion group of the sub-pixel electrode in the array substrate provided by each of the above embodiments of the present invention, by making the branch portion group of the sub-pixel electrode partially overlap the data line and/or the gate line, the branch portion group of the sub-pixel electrode can be reduced. Interference between the electric field and the electric field of the data line and/or the grid line, thereby better controlling the alignment of the liquid crystal molecules, thereby improving the transmittance of the array substrate and increasing the contrast, thereby improving the display panel including the array substrate The quality of the display.
  • an embodiment of the present invention further provides a display panel including an array substrate and a counter substrate disposed with the array substrate, wherein the array substrate is an array substrate provided by an embodiment of the present invention.
  • the alignment of the liquid crystal molecules can be better controlled, thereby improving the transmittance of the display panel and increasing the contrast. Improve the display quality of the display panel.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Liquid Crystal (AREA)

Abstract

一种阵列基板和显示面板，阵列基板包括交叉设置的多条数据线（30）和多条栅线（10），多条数据线（30）平行排列，多条栅线（10）平行排列，栅线（10）和数据线（30）垂直交叉而将阵列基板划分为多个像素单元，每个像素单元内设置有像素电极，像素电极包括亚像素电极，亚像素电极包括根茎部（50b）和与之连接的分支部组，分支部组由多个分支部（51c）组成，且相邻的分支部（51c）由狭缝（51d）隔开；并且，分支部组与数据线（30）和/或栅线（10）部分地重叠。阵列基板可以减小像素电极的分支部（51c）的电场与数据线（30）和/或栅线（10）的电场之间的干扰，从而可以更好地控制液晶分子的排列。

Description

阵列基板和显示面板 技术领域
本发明涉及显示技术领域，尤其涉及阵列基板和包含该阵列基板的显示面板。
背景技术
液晶显示技术已广泛应用在电视、手机以及公共信息显示等领域。目前，液晶显示主要可以分为扭曲向列相(TN，twisted nematic)模式、垂直排列(VA，vertical-aligned)模式、面内开关(IPS，in-plane switching)模式。对于垂直排列模式的液晶显示而言，其显示的对比度较高、且在一个像素内可实现8畴液晶排列，从而可以得到宽视角，因此，垂直排列模式的液晶显示在大尺寸液晶电视方面得到了广泛应用。
液晶显示面板主要由阵列基板和彩膜基板对盒组成。该阵列基板包括多条栅线和多条数据线，栅线与数据线垂直交叉(因它们位于不同的层中，故交叉时不会导通)而将阵列基板分为多个像素单元，每个像素单元内设置有薄膜晶体管(包括栅极、源极和漏极)，数据线上的信号电压通过薄膜晶体管写入像素电极。
目前的阵列基板在实际应用中不可避免地存在以下问题：
对于实现多畴液晶的像素电极，其通常具有根茎部和分支部，其中，分支部用于控制液晶分子的排列，例如控制液晶分子的取向方向和取向稳定性等等，但是，该分支部的电场往往会与数据线或栅线的电场产生干扰，造成液晶分子的排列异常，从而造成阵列基板的透过率下降、对比度降低。
实用新型内容
本发明的目的在于提供一种阵列基板和包括该阵列基板的显示 面板，其可以减小像素电极的分支部的电场与数据线和/或栅线的电场之间的干扰，从而可以更好地控制液晶分子的排列。
为解决上述技术问题，作为本发明的第一个方面，提供一种阵列基板，其包括交叉设置的多条数据线和多条栅线，多条数据线平行排列，多条栅线平行排列，栅线和数据线垂直交叉而将阵列基板划分为多个像素单元，每个像素单元内设置有像素电极，所述像素电极包括亚像素电极，所述亚像素电极包括根茎部和与之连接的分支部组，所述分支部组由多个分支部组成，且相邻的分支部由狭缝隔开；所述分支部组与所述数据线和/或所述栅线部分地重叠。
在实施例中，每个所述像素电极中的所述亚像素电极的数量为一个或多个，且在每个所述像素电极中的所述亚像素电极的数量为多个的情况下，多个所述亚像素电极沿平行于所述数据线的方向排列。
优选的，每个所述像素电极中的至少一个所述亚像素电极还包括连接部，所述连接部用于将所述亚像素电极的所有的所述分支部的朝向所述数据线的端部相互连接；或者，将所述亚像素电极的一部分相邻分支部的朝向所述数据线的端部相互连接。
优选的，每个所述像素电极中的至少一个所述亚像素电极的分支部组和与之相临近的所述栅线部分地重叠。
优选的，每个所述像素电极中的至少一个所述亚像素电极的分支部组和与之相邻的两条数据线中的至少一条数据线部分地重叠。
优选的，每个所述像素电极中的至少一个所述亚像素电极中的各个狭缝和与该亚像素电极相邻的、且由同一所述栅线和不同所述数据线界定的亚像素电极中的各个狭缝相对设置。
作为替换，每个所述像素电极中的至少一个所述亚像素电极中的各个狭缝可以和与该亚像素电极相邻的、且由同一所述栅线和不同所述数据线界定的亚像素电极中的各个狭缝交错设置。
优选的，所述阵列基板还包括树脂层，所述树脂层设置在所述像素电极与所述数据线之间。
进一步优选的，所述树脂层的厚度的取值范围为0.5～5μm。
优选的，所述阵列基板还包括彩膜层，所述彩膜层设置在所述 像素电极与所述数据线之间。
进一步优选的，所述彩膜层的厚度的取值范围为0.5～3μm。
作为本发明的第二个方面，还提供一种显示面板，其包括阵列基板和与该阵列基板对盒设置的对盒基板，所述阵列基板为本发明提供的阵列基板。
本发明实施例提供的阵列基板中，通过使亚像素电极的分支部组与数据线和/或栅线部分地重叠，可以减小亚像素电极的分支部组的电场与数据线和/或栅线的电场之间的干扰，从而可以更好地控制液晶分子的排列，进而可以提高阵列基板的透过率，增加对比度，从而提高包括该阵列基板的显示面板的显示质量。
本发明实施例提供的显示面板通过采用上述阵列基板，可以更好地控制液晶分子的排列，从而可以提高该显示面板的透过率，增加对比度，提高该显示面板的显示质量。
附图说明
附图是用来提供对本发明的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本发明，但并不构成对本发明的限制。
图1A为本发明的实施例提供的一种阵列基板的单个像素电极的平面示意图。
图1B为图1A的沿A1-A2线的剖视图。
图1C为图1A的沿B1-B2线的剖视图。
图2为本发明的实施例提供的另一种阵列基板的单个像素电极的平面示意图。
图3A为本发明的实施例提供的又一种阵列基板的单个像素电极的平面示意图。
图3B为本发明的实施例提供的再一种阵列基板的单个像素电极的平面示意图。
图4A为本发明的实施例提供的一种阵列基板的相邻的两个像素电极的平面示意图。
图4B为本发明的实施例提供的另一种阵列基板的相邻的两个像素电极的平面示意图。
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本发明，并不用于限制本发明。
本发明提供的阵列基板包括交叉设置的多条数据线和多条栅线，多条栅线平行排列，多条数据线也平行排列，栅线和数据线垂直交叉而将阵列基板划分为多个像素单元，每个像素单元内设置有像素电极，所述像素电极包括亚像素电极，亚像素电极包括根茎部和与之连接的分支部组，该分支部组由多个分支部组成，且相邻的分支部由狭缝隔开。借助根茎部和与之连接的分支部组，可以实现多畴液晶排列。并且，亚像素电极的分支部组与数据线和/或栅线部分地重叠，这可以减小亚像素电极的分支部组的电场与数据线和/或栅线的电场之间的干扰，从而可以更好地控制液晶分子的排列，进而可以提高阵列基板的透过率、增加对比度，从而提高包含该阵列基板的显示面板的显示质量。
在实际应用中，对于每个像素单元的像素电极，其亚像素电极的数量可以为一个或多个，且在每个像素电极中的亚像素电极的数量为多个的情况下，多个所述亚像素电极沿平行于数据线的方向排列。
下面对本实施例所采用的像素电极的具体实施方式进行详细描述。具体地，图1A为本发明的实施例提供的一种阵列基板的单个像素电极的平面示意图。图1B为图1A的沿A1-A2线的剖视图。图1C为图1A的沿B1-B2线的剖视图。同时参阅图1A至图1C，本实施例的阵列基板包括交叉设置的多条数据线30和多条栅线10，其中，多条栅线10分别为101、102、…10i、10i+1、…，并且栅线10可以采用单层结构，或者也可以采用多层结构，且采用Mo\Al\Mo、Ti\Cu\Ti或者MoTi\Cu等材料制作。多条数据线30分别为数据线301、302、…30j、30j+1、…。
在本实施例中，由一条栅线10i和相邻的两条数据线30j和30j+1界定像素电极，该像素电极包括沿平行于数据线30的方向排列的两个亚像素电极，分别为第一亚像素电极50和第二亚像素电极51，二者各自包括根茎部和与之连接的分支部组。第一亚象素电极50的根茎部包括与栅线10相互平行的根茎部50a、与数据线30平行的根茎部50b，二者呈十字交叉状。与之相类似的，第二亚象素电极51的根茎部包括与栅线10相互平行的根茎部51a、与数据线30平行的根茎部51b，二者呈十字交叉状。
第一亚象素电极50的分支部组由多个分支部50c组成，各个分支部50c连接到根茎部50a或根茎部50b，且相邻的分支部50c由狭缝50d隔开。第二亚象素电极51的分支部组由多个分支部51c组成，各个分支部51c连接到根茎部51a或根茎部51b，且相邻的分支部51c由狭缝51d隔开。借助上述根茎部和与之连接的分支部组，可以实现8畴液晶排列，如图1A所示。
在本实施例中，两个亚像素电极(50，51)的分支部组均和与之相邻的两条数据线(30j，30j+1)部分地重叠，以减小这两个亚像素电极的分支部组的电场与两条数据线(30j，30j+1)的电场之间的干扰。所谓分支部组与数据线部分地重叠，是指二者在阵列基板的衬底上的正投影具有相重叠的部分和非重叠的部分，并且分支部组与数据线部分地重叠的方式包括以下两种，第一种方式为：分支部的外端延伸至数据线外侧边缘之外，如图1A所示；第二种方式为：分支部的外端仅延伸至超出数据线内侧边缘的位置，而未超出数据线的外侧边缘。
在实际应用中，根据不同的需要，仅第一亚像素电极50或者第二亚像素电极51的分支部组可以单独和与之相邻的两条数据线(30j，30j+1)部分地重叠；或者，第一亚像素电极50和/或第二亚像素电极51的分支部组可以单独与数据线30j或者数据线30j+1部分地重叠。
在本实施例中，第一亚像素电极50通过第一薄膜晶体管T1与数据线30j电性连接；第二亚像素电极51通过第二薄膜晶体管T2和与之相邻的数据线30j+1电性连接。具体地，第一薄膜晶体管T1的源 极31与数据线30j连接，第一薄膜晶体管T1的漏极33通过过孔40与第一亚像素电极50连接；第二薄膜晶体管T2的源极与相邻的数据线30j+1连接，第二薄膜晶体管T2的漏极通过过孔41与第二亚像素电极51连接。
在本实施例中，阵列基板还包括由下而上依次设置的衬底1、栅极绝缘层15和钝化层38，其中，栅线10和公共电极151设置在衬底1与栅极绝缘层15之间；有源层25、薄膜晶体管的源极31和漏极33设置在栅极绝缘层15和钝化层38之间；亚像素电极(50，51)设置在钝化层38上。优选的，阵列基板还可以包括树脂层，该树脂层可以设置在像素电极与数据线30之间，例如设置于像素电极和钝化层38之间，也可以设置于数据线30与钝化层38之间，且该树脂层的厚度的取值范围为0.5～5μm，优选为1～3μm。借助该树脂层，可以起到进一步降低数据线30的电场对像素电极的影响的作用。
在本实施例中，在阵列基板上还可以设置有彩膜层，该彩膜层可以设置在像素电极与数据线30之间，例如设置于像素电极和钝化层38之间，也可以设置于数据线30与钝化层38之间，且该彩膜层的厚度的取值范围为0.5～3μm，优选为1～2.5μm。借助上述彩膜层，不仅可以减少阵列基板和对置基板的对位公差，而且还可以起到进一步降低数据线30的电场对像素电极的影响的作用。
图2为本发明的实施例提供的另一种阵列基板的单个像素电极的平面示意图。参阅图2，该阵列基板在前述实施例中的阵列基板的基础上做出了进一步改进，即：第一亚像素电极50还包括连接部50e。
具体地，连接部50e用于将第一亚像素电极50的所有的分支部50c的分别朝向数据线30j和数据线30j+1两侧的端部相互连接，即，第一亚像素电极50的各个分支部50c通过连接部50e在图2中第一亚像素电极50的左右两侧的边缘处相互连接。借助连接部50e，可以起到对分支部50c所产生的电场进行调整的作用。在实际应用中，根据不同的需要，可以仅在第一亚像素电极50或者第二亚像素电极51上设置连接部，或者，也可以同时在第一亚像素电极50和第二亚像素电极51上设置连接部。另外，在实际应用中，也可以使连接部 50e将第一亚像素电极50的分支部50c的仅朝向数据线30j或者数据线30j+1的所有端部相互连接。
需要说明的是，在本实施例中，连接部50e将第一亚像素电极50的所有的分支部50c的分别朝向数据线30j和数据线30j+1两侧的端部相互连接。但是，本发明并不局限于此，在实际应用中，也可以使连接部50e仅将第一亚像素电极50的一部分相邻分支部的朝向数据线的端部相互连接。
图3A为本发明的实施例提供的又一种阵列基板的单个像素电极的平面示意图。参阅图3A，该阵列基板在前述任意一个实施例中的阵列基板的基础上做出了进一步改进。具体地，在本实施例中，第一亚像素电极50的分支部组与栅线10i相临近，且第一亚像素电极50的分支部组与该栅线10i部分地重叠，以减小第一亚像素电极50的分支部组的电场与栅线10i的电场之间的干扰。
当然，在实际应用中，如图3B所示，也可以使第二亚像素电极51的分支部组和与该第二亚像素电极51相临近的栅线10i-1部分地重叠。或者，还可以同时使第一亚像素电极50和第二亚像素电极51各自的分支部组分别与栅线10i和栅线10i-1部分地重叠。
需要说明的是，所谓分支部组与栅线部分地重叠，是指二者在阵列基板的衬底上的正投影具有相重叠的部分和非重叠的部分，并且分支部组与栅线部分地重叠的方式包括以下两种，第一种方式为：分支部的外端仅延伸至超出栅线内侧边缘的位置，而未超出栅线的外侧边缘，如图3A和3B所示；第二种方式为：分支部的外端延伸至栅线外侧边缘之外。
图4A为本发明的实施例提供的一种阵列基板的相邻的两个像素电极的平面示意图。参阅图4A，该阵列基板在前述任意一个实施例中的阵列基板的基础上做出了进一步改进。具体地，第一亚像素电极50L和第二亚像素电极51L由一条栅线10i以及相邻的两条数据线30j和30j+1界定；第一亚像素电极50R和第二亚像素电极51R由一条栅线10i以及相邻的两条数据线30j+2和30j+3界定；其中，第一亚像素电极50L和第一亚像素电极50R相邻、且由同一栅线(即，栅线 10i)和不同数据线(30j和30j+1以及30j+2和30j+3)界定，并且二者中的狭缝分别为狭缝50dL和狭缝50dR，且狭缝50dL和狭缝50dR相对设置，即，狭缝50dL的开口正对狭缝50dR的开口。类似的，第二亚像素电极51L和第二亚像素电极51R相邻、且由同一栅线(即，栅线10i)和不同数据线(30j和30j+1以及30j+2和30j+3)界定，并且二者中的狭缝分别为狭缝51dL和狭缝51dR，且狭缝51dL和狭缝51dR相对设置。
优选的，如图4B所示，还可以使上述狭缝50dL和狭缝50dR交错设置，即，狭缝50dL的开口与狭缝50dR的开口相互交错；同时，上述狭缝51dL和狭缝51dR交错设置，这样可以更好地防止相邻的两个像素电极的电场产生干扰。
在实际应用中，根据具体情况，可以使任意相邻的、且由同一栅线和不同数据线界定的两个亚像素电极中的狭缝相对设置或者交错设置。
需要说明的是，在上述各个实施例中，每个像素电极中设置的亚像素电极的数量为两个，但是本发明并不局限于此，在实际应用中，每个像素电极中设置的亚像素电极的数量还可以为一个或者三个及以上，并且在每个像素电极中设置的亚像素电极的数量为多个的情况下，多个亚像素电极可以沿平行于数据线的方向排列，或者根据需要采用其他任意方式排列。
还需要说明的是，在本实施例中，对于每个亚像素电极，其根茎部呈十字交叉状，分支部组连接到十字交叉状的根茎部，但是本发明并不局限于此。在实际应用中，还可以采用其他任意结构的根茎部以及分支部组，本发明对此没有特别的限制。
综上所述，本发明的上述各个实施例提供的阵列基板中，通过使亚像素电极的分支部组与数据线和/或栅线部分地重叠，可以减小亚像素电极的分支部组的电场与数据线和/或栅线的电场之间的干扰，从而可以更好地控制液晶分子的排列，进而可以提高阵列基板的透过率、且增加对比度，从而提高包含该阵列基板的显示面板的显示质量。
作为另一个技术方案，本发明的实施例还提供一种显示面板，其包括阵列基板和与该阵列基板对盒设置的对盒基板，其中，阵列基板为本发明的实施例提供的阵列基板。
本发明的实施例提供的显示面板中，通过采用本发明的上述各个实施例提供的阵列基板，可以更好地控制液晶分子的排列，从而可以提高显示面板的透过率、且增加对比度，从而提高显示面板的显示质量。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (13)

  1. 一种阵列基板，其包括交叉设置的多条数据线和多条栅线，其中，
    多条数据线平行排列，多条栅线平行排列，栅线和数据线垂直交叉而将阵列基板划分为多个像素单元，每个像素单元内设置有像素电极，
    所述像素电极包括亚像素电极，所述亚像素电极包括根茎部和与之连接的分支部组，所述分支部组由多个分支部组成，且相邻的分支部由狭缝隔开，以及
    所述分支部组与所述数据线和/或所述栅线部分地重叠。
  2. 根据权利要求1所述的阵列基板，其中，每个所述像素电极中的所述亚像素电极的数量为一个或多个，
    在每个所述像素电极中的所述亚像素电极的数量为多个的情况下，多个所述亚像素电极沿平行于所述数据线的方向排列。
  3. 根据权利要求2所述的阵列基板，其中，每个所述像素电极中的至少一个所述亚像素电极还包括连接部，所述连接部用于将所述亚像素电极的所有的所述分支部的朝向所述数据线的端部相互连接。
  4. 根据权利要求2所述的阵列基板，其中，每个所述像素电极中的至少一个所述亚像素电极还包括连接部，所述连接部用于将所述亚像素电极的一部分相邻分支部的朝向所述数据线的端部相互连接。
  5. 根据权利要求2所述的阵列基板，其中，每个所述像素电极中的至少一个所述亚像素电极的分支部组和与之相临近的所述栅线部分地重叠。
  6. 根据权利要求2所述的阵列基板，其中，每个所述像素电极 中的至少一个所述亚像素电极的分支部组和与之相邻的两条数据线中的至少一条数据线部分地重叠。
  7. 根据权利要求2所述的阵列基板，其中，每个所述像素电极中的至少一个所述亚像素电极中的各个狭缝和与该亚像素电极相邻的、且由同一所述栅线和不同所述数据线界定的亚像素电极中的各个狭缝相对设置。
  8. 根据权利要求2所述的阵列基板，其中，每个所述像素电极中的至少一个所述亚像素电极中的各个狭缝和与该亚像素电极相邻的、且由同一所述栅线和不同所述数据线界定的亚像素电极中的各个狭缝交错设置。
  9. 根据权利要求1所述的阵列基板，还包括树脂层，所述树脂层设置在所述像素电极与所述数据线之间。
  10. 根据权利要求9所述的阵列基板，其中，所述树脂层的厚度的取值范围为0.5～5μm。
  11. 根据权利要求1所述的阵列基板，还包括彩膜层，所述彩膜层设置在所述像素电极与所述数据线之间。
  12. 根据权利要求11所述的阵列基板，其中，所述彩膜层的厚度的取值范围为0.5～3μm。
  13. 一种显示面板，包括权利要求1-11中任意一项所述的阵列基板和与该阵列基板对盒设置的对盒基板。
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