WO2017128558A1 - 阵列基板及阵列基板的制备方法 - Google Patents

阵列基板及阵列基板的制备方法 Download PDF

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WO2017128558A1
WO2017128558A1 PCT/CN2016/082106 CN2016082106W WO2017128558A1 WO 2017128558 A1 WO2017128558 A1 WO 2017128558A1 CN 2016082106 W CN2016082106 W CN 2016082106W WO 2017128558 A1 WO2017128558 A1 WO 2017128558A1
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layer
disposed
common electrode
gate
array substrate
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English (en)
French (fr)
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徐向阳
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/101,884 priority Critical patent/US10114245B2/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13336—Combining plural substrates to produce large-area displays, e.g. tiled displays
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs

Definitions

  • the present invention relates to the field of display, and in particular, to a method for preparing an array substrate and an array substrate.
  • a display device such as a liquid crystal display (LCD) is a commonly used electronic device that is favored by users because of its low power consumption, small size, and light weight.
  • a trans-flective liquid crystal display device has both transmissive and reflective characteristics.
  • the transflective liquid crystal panel includes a transmissive region with a transparent electrode and a reflective region with a reflective layer in one pixel domain. .
  • the transmission area and the backlight of the pixel area can be used to display the image, and the reflection area of the pixel area and the external light can be used to display the image in a bright place. Therefore, the transflective liquid crystal display device can be widely applied to adapt to different bright and dark environments.
  • the transflective liquid crystal display device has a weak ability to reflect external light, thereby causing the transflective liquid crystal display device to have poor display quality when displaying a picture when reflecting external light.
  • the present invention provides an array substrate including a substrate and a plurality of gate lines and a plurality of data lines disposed on the same side of the substrate, the substrate including a first surface, and the plurality of gate lines are disposed On the first surface, and the plurality of gate lines extend in a first direction and are spaced apart in a second direction, the plurality of data lines and the plurality of gate lines are insulated by a first insulating layer And the plurality of data lines extend toward the second direction and are arranged along the first direction, the array substrate further includes a plurality of common electrode lines, the plurality of common electrode lines and the plurality of The gate lines are parallel, one common electrode line is disposed between the adjacent two gate lines, and the common electrode line and the data line are insulated by the first insulating layer, and the adjacent two gates A pixel area is defined between the polar line and the adjacent two data lines
  • the array substrate further includes a thin film transistor, a common electrode, a pixel electrode and a storage capacitor disposed in the pixel region, the
  • the common electrode line and the common electrode are metal layers for reflecting light incident on the common electrode line and the common electrode, respectively.
  • the first conductive portion and the second conductive portion are metal layers.
  • the thin film transistor further includes a first ohmic contact layer disposed between the channel layer and the source for reducing the channel layer and the source Contact resistance between.
  • the thin film transistor further includes a second ohmic contact layer disposed between the channel layer and the drain for reducing the channel layer and the drain Contact resistance between.
  • the first insulating layer includes a first through hole corresponding to the gate line
  • the second insulating layer includes a second through hole corresponding to the first through hole and corresponding to the data line.
  • a third through hole, a gate terminal electrically connecting the gate line through the first through hole and the second through hole, and a data terminal is electrically connected to the data line through the third through hole, wherein The gate terminal and the data terminal are electrically conductive.
  • the invention also provides a method for preparing an array substrate, and the method for preparing the array substrate comprises:
  • the step of forming a channel layer corresponding to the gate on the surface of the first insulating layer away from the substrate includes:
  • the method for preparing the array substrate further includes:
  • a first through hole corresponding to the gate line is formed on the first insulating layer, and a second through hole corresponding to the first through hole and a corresponding portion of the data line are formed on the second insulating layer
  • Patterning the conductive material layer retaining a conductive material layer corresponding to the second through hole and the first through hole, and a conductive material layer corresponding to the third through hole, wherein the second through hole and The conductive material layer of the first through hole is a gate terminal, and the conductive material layer corresponding to the third through hole is a data terminal.
  • the ion doping is N-type ion doping.
  • the method for preparing an array substrate of the present invention is prepared by preparing a source electrode and a drain electrode in a pixel electrode and a thin film transistor in a preparation process, thereby saving a preparation process, and the pixel electrode is made of metal and can be incident on the pixel.
  • the light of the pixel electrode when the liquid crystal display panel to which the array substrate is applied is in a bright place, the image can be displayed by the light reflected by the pixel electrode, thereby improving the display when the liquid crystal display device displays the screen. quality.
  • the common electrode line and the common electrode and the gate are prepared in the same preparation process, which saves the preparation process.
  • the common electrode line and the common electrode are metal layers for reflecting light incident on the common electrode line and the common electrode, respectively, and therefore, the liquid crystal display panel applied to the array substrate is bright In the place, the image can be displayed by the light reflected by the pixel electrode, thereby improving the display quality when the liquid crystal display device displays the picture.
  • the first conductive portion of the storage capacitor is prepared in the same preparation process as the gate, thereby saving the preparation process.
  • the second conductive portion of the storage capacitor is prepared in the same preparation process as the source and the drain, thereby saving the preparation process.
  • FIG. 1 is a top plan view of an array substrate in accordance with a preferred embodiment of the present invention.
  • Figure 2 is a schematic cross-sectional view taken along line I-I of Figure 1.
  • FIG. 3 is a flow chart of a method of fabricating an array substrate according to a preferred embodiment of the present invention.
  • FIG. 1 is a plan view of an array substrate according to a preferred embodiment of the present invention
  • FIG. 2 is a cross-sectional structural view taken along line I-I of FIG.
  • the array substrate 100 can be applied to an In-Plane Switching (IPS) panel device.
  • the array substrate 10 includes a substrate 100 and a plurality of gate lines 200 and a plurality of data lines 300 disposed on the same side of the substrate 100.
  • the substrate 100 includes a first surface 110, the plurality of gate lines 200 are disposed on the first surface 110, and the plurality of gate lines 200 extend in a first direction D1 and along the second direction D2 is arranged at intervals.
  • the plurality of data lines 300 are spaced apart from the plurality of gate lines 200 by a first insulating layer 820, and the plurality of data lines 300 extend toward the second direction D2 and are spaced along the first direction D1 Arrange.
  • the array substrate 10 further includes a plurality of common electrode lines 400, the plurality of common electrode lines 400 are parallel to the plurality of gate lines 200, and one common electrode line 400 is disposed on the adjacent two gate lines 200. And the common electrode line 400 and the data line 300 are insulated from the first insulating layer 820.
  • a pixel area is defined between two adjacent gate lines 200 and two adjacent data lines 300.
  • the array substrate 10 further includes a thin film transistor 800, a common electrode 500, a pixel electrode 600, and a storage capacitor 700 disposed in the pixel region.
  • the thin film transistor 800 includes a gate 810, the first insulating layer 820, a channel layer 830, a source 840, and a drain 850.
  • the gate 810 is disposed on the first surface 110
  • the common electrode 500 is electrically connected to the common electrode line 400
  • the common electrode 500 and the common electrode line 400 are disposed on the first surface 110.
  • the storage capacitor 700 includes a first conductive portion 710 and a second conductive portion 720.
  • the first conductive portion 710 is disposed on the first surface 110, and the first conductive portion 710 is disposed on the first conductive layer 710. 820.
  • the second conductive portion 720 is disposed on the first insulating layer 820 and corresponds to the first conductive portion 710.
  • the channel layer 830, the source 840, and the drain 850 are disposed on the first insulating layer 820, and the source 840 and the drain 850 are disposed opposite to the channel layer 830. Both ends.
  • the pixel electrode 600 is disposed on the first insulating layer 820, and the pixel electrode 600 is a metal layer for reflecting light incident to the pixel electrode 600.
  • a second insulating layer 860 covers the channel layer 830, the source 840, the pixel electrode 600, the second portion 720, and the data line 300.
  • the first direction D1 may be an X-axis direction
  • the second direction D2 may be a Y-axis direction.
  • the substrate 100 may be, but not limited to, a glass substrate or an insulating substrate such as a plastic substrate.
  • the common electrode line 400 and the common electrode 500 are metal layers for reflecting light incident on the common electrode line 400 and the common electrode 500, respectively.
  • the first conductive portion 710 and the second conductive portion 720 are metal layers.
  • the thin film transistor 800 further includes a first ohmic contact layer 870 disposed between the channel layer 830 and the source 840 for reducing the channel layer 830 and Contact resistance between the sources 840.
  • the thin film transistor 800 further includes a second ohmic contact layer 880 disposed between the channel layer 830 and the drain 850 for reducing the channel layer 830 and Contact resistance between the drains 850.
  • the first insulating layer 820 includes a first through hole 821 corresponding to the gate line 200
  • the second insulating layer 860 includes a second through hole 861 corresponding to the first through hole 821 and corresponding to the
  • the third through hole 862 is formed in the data line 300.
  • a gate terminal 210 is connected to the gate line 200 through the first through hole 821 and the second through hole 861
  • a data terminal 310 is connected to the data line 300 through the third through hole 862, wherein
  • the gate terminal 210 and the data terminal 310 are electrically conductive.
  • the gate terminal 210 and the data terminal 310 can be electrically connected to an integrated chip to receive signals of the integrated chip.
  • the pixel electrode 600 in the array substrate 10 of the present invention is a metal layer, and therefore, the light incident on the pixel electrode 600 can be reflected. Therefore, the liquid crystal display device applied to the array substrate 10 When it is in a bright place, it is possible to display an image by the light reflected by the pixel electrode 600, thereby improving the display quality when the liquid crystal display device displays a picture.
  • the common electrode line 400 and the common electrode 500 are metal layers for reflecting light incident on the common electrode line 400 and the common electrode 500, respectively, and thus applied to the array substrate 10
  • the image reflected by the pixel electrode 600 can be used to display an image, thereby improving the display quality when the liquid crystal display device displays a picture.
  • FIG. 3 is a flowchart of a method for fabricating an array substrate according to a preferred embodiment of the present invention.
  • the preparation method of the array substrate includes, but is not limited to, the following steps.
  • the substrate 110 is provided.
  • the substrate 110 may be, but not limited to, a glass substrate or an insulating substrate such as a plastic substrate.
  • a first layer of the first metal layer is disposed on the first surface 111 of the substrate 110.
  • the first metal layer includes, but is not limited to, any one or more of aluminum (Al), molybdenum (Mo), and copper (Cu).
  • the first metal layer may be formed by physical vapor deposition (PVD), and the first metal layer may have a thickness of 3000 angstroms to 6000 angstroms.
  • Step S130 patterning the first metal layer to form a plurality of gate lines 200 extending along the first direction D1 and spaced apart along the second direction D2, and disposed on the adjacent two gate lines 200 And spaced apart gates 810, first conductive portions 710, common electrode lines 400 corresponding to and parallel to each of the gate lines 200, and connected to the common electrode lines 400 and extending away from the gate lines 200
  • the common electrode 500 can be performed by exposure, development, etching, and glassing through a mask.
  • Step S140 forming a first insulating layer 820 covering the gate 810, the first conductive portion 710, the gate line 200, the common electrode line 400, and the common electrode 500.
  • the first insulating layer 820 may deposit an insulating material having a film thickness of 3000 ⁇ to 6000 ⁇ by a plasma enhanced chemical vapor deposition (PECVD) to form the first insulating layer 820.
  • PECVD plasma enhanced chemical vapor deposition
  • the insulating layer material may be, but not limited to, silicon nitride (SiNx).
  • Step S150 forming a channel layer 830 disposed corresponding to the gate 810 on a surface of the first insulating layer 820 away from the substrate 110. Specifically, the step S150 further includes the following steps.
  • Step S151 forming an entire layer of amorphous silicon layer on the surface of the first insulating layer 820 away from the substrate 110.
  • the amorphous silicon layer may form an amorphous silicon material having a film thickness of 1500 angstroms to 3000 angstroms by plasma enhanced chemical vapor deposition to form the amorphous silicon layer.
  • Step S152 patterning the amorphous silicon layer to retain the amorphous silicon layer disposed corresponding to the gate 810.
  • Step S153 performing ion doping on both ends of the remaining amorphous silicon layer to form a first ohmic contact layer 870 and a second ohmic contact layer 880, respectively, and the amorphous silicon layer not ion-doped is The channel layer 830.
  • the ion doping is N-type ion doping.
  • Step S160 forming a second metal layer covering the first insulating layer 820 and the channel layer 830.
  • the second metal layer includes, but is not limited to, any one or more of Al, Mo, and Cu.
  • the second metal layer may be formed by PVD, and the second metal layer may have a thickness of 3000 ⁇ to 6000 ⁇ .
  • Step S170 patterning the second metal layer to form a plurality of extending along the second direction D2 And a data line 300 arranged along the first direction D1, and a source 840 and a drain 850 disposed between the adjacent two data lines 300 and corresponding to the two ends of the channel layer 830
  • a pixel electrode 600 having a drain 850 spacing and a second conductive portion 720 corresponding to the first conductive portion 710 are described.
  • the patterning of the second metal layer can be performed by exposure, development, etching, and glassing through a mask.
  • a second insulating layer 860 covering the channel layer 830, the source 840, the drain 850, the pixel electrode 600, the second conductive portion 720, and the data line 300 is formed.
  • the second insulating layer 860 may deposit an insulating material having a film thickness of 2000 ⁇ to 56,000 ⁇ by PECVD to form the second insulating layer 860.
  • the insulating layer material may be, but not limited to, silicon nitride (SiNx). ).
  • the method for preparing the thin film transistor array substrate further includes the following steps.
  • Step 1 a first through hole 821 corresponding to the gate line 200 is formed on the first insulating layer 820 , and a second through hole corresponding to the first through hole 821 is defined in the second insulating layer 860 . 861 and a third through hole 862 corresponding to the data line 300.
  • a layer of conductive material is formed on the second insulating layer 860.
  • the conductive material layer is a transparent conductive material layer, and the conductive material layer may be, but not limited to, Indium Tin Oxide (ITO).
  • ITO Indium Tin Oxide
  • the conductive material layer has a thickness of 400 angstroms to 1000 angstroms.
  • Step III patterning the conductive material layer, and retaining a conductive material layer corresponding to the second through hole 861 and the first through hole 821 and a conductive material layer corresponding to the third through hole 862, wherein
  • the conductive material layer of the second through hole 861 and the first through hole 821 is a gate terminal 210, and the conductive material layer corresponding to the third through hole 862 is a data terminal 310.
  • the method for fabricating the array substrate of the present invention prepares the pixel electrode 600 and the source 840 and the drain 850 of the thin film transistor 800 in a preparation process, which saves the preparation process, and the pixel electrode 600 is metal.
  • the light incident on the pixel electrode 600 can be reflected. Therefore, when the liquid crystal display panel to which the array substrate is applied is in a bright place, the light reflected by the pixel electrode 600 can be used to display an image, thereby improving the liquid crystal.
  • the common electrode line 400 and the common electrode 500 are prepared in the same preparation process as the gate electrode 810, which saves the preparation process.
  • the common electrode line 400 and the common electrode 500 are metal layers for reflecting incident on the common electrode line 400 and the common electrode 500, respectively. Therefore, when the liquid crystal display panel to which the array substrate 10 is applied is in a bright place, the light reflected by the pixel electrode 600 can display an image, thereby improving the display quality when the liquid crystal display device displays a screen.
  • first conductive portion 710 of the storage capacitor 700 is prepared in the same preparation process as the gate 810, thereby saving the preparation process.
  • the second conductive portion 720 of the storage capacitor 700 is prepared in the same preparation process as the source 840 and the drain 850, thereby saving the preparation process.

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Abstract

一种阵列基板及阵列基板的制备方法。阵列基板（100）包括基板（110）及设置在基板（110）同侧的交错且绝缘设置的多个栅极线（200）及多个数据线（300），以及多个与栅极线（200）平行且与数据线（300）绝缘的多个公共电极线（400），基板（110）包括第一表面（111），栅极线（200）设置在第一表面（111）上，相邻的两条栅极线（200）及相邻的两条数据线（300）之间限定一个像素区域，像素区域内设置薄膜晶体管（800），公共电极（500），像素电极（600）及存储电容（700），薄膜晶体管（800）包括栅极（810）、沟道层（830）、源极（840）及漏极（850），存储电容（700）包括第一导电部（710）及第二导电部（720），栅极（810）、公共电极线（400）、公共电极（500）及第一导电部（710）设置在第一表面（111），且公共电极（500）与公共电极线（400）电连接，沟道层（830）、源极（840）、漏极（850）、第二导电部（720）及像素电极（600）设置在第一绝缘层（820）上且源极（840）与漏极（850）设置在沟道层（830）相对的两端，且像素电极（600）为金属层。

Description

阵列基板及阵列基板的制备方法
本发明要求2016年1月29日递交的发明名称为“阵列基板及阵列基板的制备方法”的申请号201610066589.4的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示领域，尤其涉及一种阵列基板及阵列基板的制备方法。
背景技术
显示设备，比如液晶显示器(Liquid Crystal Display,LCD)是一种常用的电子设备，由于其具有功耗低、体积小、重量轻等特点，因此备受用户的青睐。半透半反式液晶显示装置(Trans-flective Liquid Crystal Display)同时具有透射式和反射式特性，半透半反式液晶面板在一个像素域内包括有透明电极的透射区和有反射层的反射区。在黑暗的地方可以利用像素区域的透射区和背光源来显示画像，在明亮的地方利用像素区域的反射区和外光来显示画像。因此，半透半反式液晶显示装置可以适应不同的亮暗环境而得到广泛应用。现有技术中，所述半透半反式液晶显示装置中反射外来光线的能力较弱，从而导致半透半反式液晶显示装置在反射外来光线时显示画面时的显示质量较差。
发明内容
本发明提供一种阵列基板，所述阵列基板包括基板及设置在所述基板同侧的多个栅极线及多个数据线，所述基板包括第一表面，所述多个栅极线设置在所述第一表面上，且所述多个栅极线向第一方向延伸且沿第二方向间隔排布，所述多个数据线与所述多个栅极线通过第一绝缘层绝缘设置，且所述多个数据线向所述第二方向延伸且沿所述第一方向间隔排布，所述阵列基板还包括多个公共电极线，所述多个公共电极线与所述多个栅极线平行，一个公共电极线设置于相邻的两个栅极线之间，且所述公共电极线与所述数据线通过所述第一绝缘层绝缘设置，相邻的两条栅极线及相邻的两条数据线之间限定一个像素区 域，所述阵列基板还包括设置在所述像素区域内的薄膜晶体管，公共电极，像素电极及存储电容，所述薄膜晶体管包括栅极、所述第一绝缘层、沟道层、源极及漏极，所述栅极设置在所述第一表面上，所述公共电极与所述公共电极线电连接且所述公共电极与所述公共电极线设置在所述第一表面上，所述存储电容包括第一导电部及第二导电部，所述第一导电部设置在所述第一表面上，所述第一导电部上设置所述第一绝缘层，所述第二导电部设置在所述第一绝缘层上且与所述第一导电部对应，所述沟道层、所述源极及所述漏极设置在所述第一绝缘层上且所述源极与所述漏极设置在所述沟道层相对的两端，所述像素电极设置在所述第一绝缘层上，且所述像素电极为金属层，用于反射入射至所述像素电极的光线，一第二绝缘层覆盖所述沟道层、所述源极、所述漏极、所述像素电极、所述第二部分及所述数据线。
其中，所述公共电极线及所述公共电极为金属层，分别用于反射入射至所述公共电极线及所述公共电极的光线。
其中，所述第一导电部及所述第二导电部为金属层。
其中，所述薄膜晶体管还包括第一欧姆接触层，所述第一欧姆接触层设置在所述沟道层与所述源极之间，用于减小所述沟道层与所述源极之间的接触电阻。
其中，所述薄膜晶体管还包括第二欧姆接触层，所述第二欧姆接触层设置在所述沟道层与所述漏极之间，用于减小所述沟道层与所述漏极之间的接触电阻。
其中，所述第一绝缘层包括对应所述栅极线开设的第一贯孔，所述第二绝缘层包括对应所述第一贯孔开设的第二贯孔及对应所述数据线开设的第三贯孔，一栅极端子通过所述第一贯孔及所述第二贯孔电连接所述栅极线，一数据端子通过所述第三贯孔电连接所述数据线，其中，所述栅极端子及所述数据端子为导电的。
本发明还提供了一种阵列基板的制备方法，所述阵列基板的制备方法包括：
提供基板；
在所述基板的第一表面设置整层的第一金属层；
图案化所述第一金属层，以形成多个沿第一方向延伸且沿第二方向间隔排布的栅极线，以及设置在相邻的两条栅极线之间的且间间隔设置的栅极、第一导电部、与每个栅极线对应且平行的公共电极线以及与公共电极线连接且朝远离所述栅极线延伸的公共电极；
形成覆盖所述栅极、所述第一导电部、所述栅极线、所述公共电极线及所述公共电极的第一绝缘层；
在所述第一绝缘层远离所述基板的表面形成与所述栅极对应设置的沟道层；
形成覆盖所述第一绝缘层及所述沟道层的第二金属层；
图案化所述第二金属层，以形成多个沿所述第二方向延伸且沿所述第一方向排布的数据线，以及设置在相邻的两条数据线之间且对应所述沟道层两端设置的源极及漏极、与所述漏极间隔的像素电极、与所述第一导电部对应的第二导电部；
形成覆盖所述沟道层、所述源极、所述漏极、所述像素电极、所述第二导电部及所述数据线的第二绝缘层。
其中，在所述步骤“在所述第一绝缘层远离所述基板的表面形成与所述栅极对应设置的沟道层”包括：
在所述第一绝缘层远离所述基板的表面形成整层的非晶硅层；
图案化所述非晶硅层，保留对应所述栅极设置的所述非晶硅层；
对保留的所述非晶硅层的两端进行离子掺杂，以分别形成第一欧姆接触层及第二欧姆接触层，未进行离子掺杂的所述非晶硅层为所述沟道层。
其中，所述阵列基板的制备方法还包括：
在所述第一绝缘层上开设对应所述栅极线的第一贯孔，在所述第二绝缘层上开设对应所述第一贯孔的第二贯孔及对应所述数据线的第三贯孔；
在所述第二绝缘层层形成导电材料层；
图案化所述导电材料层，保留对应所述第二贯孔及所述第一贯孔的导电材料层以及对应所述第三贯孔的导电材料层，其中，对应所述第二贯孔及所述第一贯孔的导电材料层为栅极端子，对应所述第三贯孔的导电材料层为数据端子。
其中，所述离子掺杂为N型离子掺杂。
相较于现有技术，本发明的阵列基板的制备方法将像素电极与薄膜晶体管中的源极和漏极在一制备工序中制备，节约了制备工序，且像素电极为金属，可以反射入射至所述像素电极的光线，因此，制备出的所述阵列基板所应用的液晶显示面板处于明亮的地方时，能够利用所述像素电极反射的光线显示图像，从而提升液晶显示装置显示画面时的显示质量。
进一步地，所述公共电极线和所述公共电极与所述栅极在同一制备工序中制备，节约了制备工序。且所述公共电极线和所述公共电极为金属层，分别用于反射入射至所述公共电极线和所述公共电极的光线，因此，在所述阵列基板所应用的液晶显示面板处于明亮的地方时，能够利用所述像素电极反射的光线显示图像，从而提升液晶显示装置显示画面时的显示质量。
进一步地，所述存储电容的所述第一导电部与所述栅极在同一制备工序中制备，从而节约了制备工序。所述存储电容的第二导电部与所述源极及所述漏极在同一制备工序中制备，从而节约了制备工序。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的阵列基板的俯视图。
图2为图1中沿I-I线的剖面结构示意图。
图3为本发明一较佳实施方式的阵列基板的制备方法的流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1及图2，图1为本发明一较佳实施方式的阵列基板的俯视图；图2为图1中沿I-I线的剖面结构示意图。所述阵列基板100可应用于半透半反式平面转换(In-Plane Switching，IPS)面板装置。所述阵列基板10包括基板100及设置在所述基板100同侧的多个栅极线200及多个数据线300。所述基板100包括第一表面110，所述多个栅极线200设置在所述第一表面110上，且所述多个栅极线200向第一方向D1延伸且沿所述第二方向D2间隔排布。所述多个数据线300与所述多个栅极线200通过第一绝缘层820间隔设置，且所述多个数据线300向所述第二方向D2延伸且沿所述第一方向D1间隔排布。所述阵列基板10还包括多个公共电极线400，所述多个公共电极线400与所述多个栅极线200平行，一个公共电极线400设置于相邻的两个栅极线200之间，且所述公共电极线400与所述数据线300通过所述第一绝缘层820绝缘设置。相邻的两条栅极线200及相邻的两条数据线300之间限定一个像素区域。所述阵列基板10还包括设置在所述像素区域内的薄膜晶体管800、公共电极500、像素电极600及存储电容700。所述薄膜晶体管800包括栅极810、所述第一绝缘层820、沟道层830、源极840及漏极850。所述栅极810设置在所述第一表面110上，所述公共电极500与所述公共电极线400电连接且所述公共电极500与所述公共电极线400设置在所述第一表面110上。所述存储电容700包括第一导电部710和第二导电部720，所述第一导电部710设置在所述第一表面110上，所述第一导电部710上设置所述第一绝缘层820，所述第二导电部720设置在所述第一绝缘层820上且与所述第一导电部710对应。所述沟道层830、所述源极840及所述漏极850设置在所述第一绝缘层820上且所述源极840与所述漏极850设置在所述沟道层830相对的两端。所述像素电极600设置在所述第一绝缘层820上，且所述像素电极600为金属层，用于反射入射至所述像素电极600的光线。一第二绝缘层860覆盖所述沟道层830、所述源极840、所述像素电极600、所述第二部分720及所述数据线300。其中，所述第一方向D1可以为X轴方向，所述第二方向D2可以为Y轴方向。
所述基板100可以为但不仅限于为玻璃基板或者为塑料基板等绝缘基板。
在本实施方式中，所述公共电极线400及所述公共电极500为金属层，分别用于反射入射至所述公共电极线400及所述公共电极500的光线。
在本实施方式中，所述第一导电部710与所述第二导电部720为金属层。
所述薄膜晶体管800还包括第一欧姆接触层870，所述第一欧姆接触层870设置在所述沟道层830与所述源极840之间，用于减小所述沟道层830与所述源极840之间的接触电阻。
所述薄膜晶体管800还包括第二欧姆接触层880，所述第二欧姆接触层880设置在所述沟道层830与所述漏极850之间，用于减小所述沟道层830与所述漏极850之间的接触电阻。
所述第一绝缘层820包括对应所述栅极线200开设的第一贯孔821，所述第二绝缘层860包括对应所述第一贯孔821开设的第二贯孔861及对应所述数据线300开设的第三贯孔862。一栅极端子210通过所述第一贯孔821及所述第二贯孔861连接所述栅极线200，一数据端子310通过所述第三贯孔862连接所述数据线300，其中，所述栅极端子210及所述数据端子310为导电的。所述栅极端子210及所述数据端子310可与一集成芯片电连接，以接收所述集成芯片的信号。
相较于现有技术，本发明的阵列基板10中的像素电极600为金属层，因此，能反射入射至所述像素电极600的光线，因此，在所述阵列基板10所应用的液晶显示装置处于明亮的地方时，能够利用所述像素电极600反射的光线显示图像，从而提升液晶显示装置显示画面时的显示质量。
进一步地，所述公共电极线400和所述公共电极500为金属层，分别用于反射入射至所述公共电极线400和所述公共电极500的光线，因此，在所述阵列基板10所应用的液晶显示面板处于明亮的地方时，能够利用所述像素电极600反射的光线显示图像，从而提升液晶显示装置显示画面时的显示质量。
下面结合图1和图2以及前面对所述阵列基板10的描述，对本发明的阵列基板的制备方法进行介绍。请一并参阅图3，图3为本发明一较佳实施方式的阵列基板的制备方法的流程图。所述阵列基板的制备方法包括但不仅限于以下步骤。
步骤S110，提供基板110。所述基板110可以为但不仅限于为玻璃基板或者为塑料基板等绝缘基板。
步骤S120，在所述基板110的第一表面111设置整层的第一金属层。所 述第一金属层包括但不仅限于铝(Al)，钼(Mo)，铜(Cu)中的任意一种或者多种。所述第一金属层可以通过物理气相沉积(Physical Vapor Deposition，PVD)的方式形成，所述第一金属层的厚度可以为3000埃～6000埃。
步骤S130，图案化所述第一金属层，以形成多个沿第一方向D1延伸且沿第二方向D2间隔排布的栅极线200，以及设置在相邻的两条栅极线200之间的且间隔设置的栅极810、第一导电部710、与每个栅极线200对应且平行的公共电极线400以及与所述公共电极线400连接且朝远离所述栅极线200延伸的公共电极500。所述第一金属层的图案化可以通过掩膜板进行曝光，显影，蚀刻及玻璃的方式进行。
步骤S140，形成覆盖所述栅极810、所述第一导电部710、所述栅极线200、所述公共电极线400及所述公共电极500的第一绝缘层820。所述第一绝缘层820可以通过等离子体增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)沉积一层膜厚为3000埃～6000埃的绝缘材料以形成所述第一绝缘层820，所述绝缘层材料可以为但不仅限于为氮化硅(SiNx)。
步骤S150，在所述第一绝缘层820远离所述基板110的表面形成与所述栅极810对应设置的沟道层830。具体地，所述步骤S150还包括如下步骤。
步骤S151，在所述第一绝缘层820远离所述基板110的表面形成整层的非晶硅层。所述非晶硅层可以通过等离子体增强化学气相沉积法形成膜厚为1500埃～3000埃的非晶硅材料以形成所述非晶硅层。
步骤S152，图案化所述非晶硅层，保留对应所述栅极810设置的所述非晶硅层。
步骤S153，对保留的所述非晶硅层的两端进行离子掺杂，以分别形成第一欧姆接触层870及第二欧姆接触层880，未进行离子掺杂的所述非晶硅层为所述沟道层830。在一实施方式中，所述离子掺杂为N型离子掺杂。
步骤S160，形成覆盖所述第一绝缘层820及所述沟道层830的第二金属层。所述第二金属层包括但不仅限于Al，Mo，Cu中的任意一种或者多种。所述第二金属层可以通过PVD的方式形成，所述第二金属层的厚度可以为3000埃～6000埃。
步骤S170，图案化所述第二金属层，以形成多个沿所述第二方向D2延伸 且沿所述第一方向D1排布的数据线300，以及设置在相邻的两条数据线300之间且对应所述沟道层830两端设置的源极840及漏极850、与所述漏极850间隔的像素电极600、与所述第一导电部710对应的第二导电部720。所述第二金属层的图案化可以通过掩膜板进行曝光，显影，蚀刻及玻璃的方式进行。
步骤S180，形成覆盖所述沟道层830、所述源极840、所述漏极850、所述像素电极600、所述第二导电部720及所述数据线300的第二绝缘层860。所述第二绝缘层860可以通过PECVD沉积一层膜厚为2000埃～56000埃的绝缘材料以形成所述第二绝缘层860，所述绝缘层材料可以为但不仅限于为氮化硅(SiNx)。
所述薄膜晶体管阵列基板的制备方法还包括如下步骤。
步骤I，在所述第一绝缘层820上开设对应所述栅极线200的第一贯孔821，在所述第二绝缘层860上开设对应所述第一贯孔821的第二贯孔861及对应所述数据线300的第三贯孔862。
步骤II，在所述第二绝缘层层860形成导电材料层。所述导电材料层为透明导电材料层，所述导电材料层可以为但不仅限于为氧化铟锡(Indium Tin Oxide，ITO)。所述导电材料层的厚度为400埃～1000埃。
步骤III，图案化所述导电材料层，保留对应所述第二贯孔861及所述第一贯孔821的导电材料层以及对应所述第三贯孔862的导电材料层，其中，对应所述第二贯孔861及所述第一贯孔821的导电材料层为栅极端子210，对应所述第三贯孔862的导电材料层为数据端子310。
相较于现有技术，本发明的阵列基板的制备方法将像素电极600与薄膜晶体管800中的源极840和漏极850在一制备工序中制备，节约了制备工序，且像素电极600为金属，可以反射入射至所述像素电极600的光线，因此，制备出的所述阵列基板所应用的液晶显示面板处于明亮的地方时，能够利用所述像素电极600反射的光线显示图像，从而提升液晶显示装置显示画面时的显示质量。
进一步地，所述公共电极线400和所述公共电极500与所述栅极810在同一制备工序中制备，节约了制备工序。且所述公共电极线400和所述公共电极500为金属层，分别用于反射入射至所述公共电极线400和所述公共电极500 的光线，因此，在所述阵列基板10所应用的液晶显示面板处于明亮的地方时，能够利用所述像素电极600反射的光线显示图像，从而提升液晶显示装置显示画面时的显示质量。
进一步地，所述存储电容700的所述第一导电部710与所述栅极810在同一制备工序中制备，从而节约了制备工序。所述存储电容700的第二导电部720与所述源极840及所述漏极850在同一制备工序中制备，从而节约了制备工序。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (10)

  1. 一种阵列基板，其中，所述阵列基板包括基板及设置在所述基板同侧的多个栅极线及多个数据线，所述基板包括第一表面，所述多个栅极线设置在所述第一表面上，且所述多个栅极线向第一方向延伸且沿第二方向间隔排布，所述多个数据线与所述多个栅极线通过第一绝缘层绝缘设置，且所述多个数据线向所述第二方向延伸且沿所述第一方向间隔排布，所述阵列基板还包括多个公共电极线，所述多个公共电极线与所述多个栅极线平行，一个公共电极线设置于相邻的两个栅极线之间，且所述公共电极线与所述数据线通过所述第一绝缘层绝缘设置，相邻的两条栅极线及相邻的两条数据线之间限定一个像素区域，所述阵列基板还包括设置在所述像素区域内的薄膜晶体管，公共电极，像素电极及存储电容，所述薄膜晶体管包括栅极、所述第一绝缘层、沟道层、源极及漏极，所述栅极设置在所述第一表面上，所述公共电极与所述公共电极线电连接且所述公共电极与所述公共电极线设置在所述第一表面上，所述存储电容包括第一导电部及第二导电部，所述第一导电部设置在所述第一表面上，所述第一导电部上设置所述第一绝缘层，所述第二导电部设置在所述第一绝缘层上且与所述第一导电部对应，所述沟道层、所述源极及所述漏极设置在所述第一绝缘层上且所述源极与所述漏极设置在所述沟道层相对的两端，所述像素电极设置在所述第一绝缘层上，且所述像素电极为金属层，用于反射入射至所述像素电极的光线，一第二绝缘层覆盖所述沟道层、所述源极、所述漏极、所述像素电极、所述第二部分及所述数据线。
  2. 如权利要求1所述的阵列基板，其中，所述公共电极线及所述公共电极为金属层，分别用于反射入射至所述公共电极线及所述公共电极的光线。
  3. 如权利要求1所述的阵列基板，其中，所述第一导电部及所述第二导电部为金属层。
  4. 如权利要求1所述的阵列基板，其中，所述薄膜晶体管还包括第一欧姆 接触层，所述第一欧姆接触层设置在所述沟道层与所述源极之间，用于减小所述沟道层与所述源极之间的接触电阻。
  5. 如权利要求1所述的阵列基板，其中，所述薄膜晶体管还包括第二欧姆接触层，所述第二欧姆接触层设置在所述沟道层与所述漏极之间，用于减小所述沟道层与所述漏极之间的接触电阻。
  6. 如权利要求1所述的阵列基板，其中，所述第一绝缘层包括对应所述栅极线开设的第一贯孔，所述第二绝缘层包括对应所述第一贯孔开设的第二贯孔及对应所述数据线开设的第三贯孔，一栅极端子通过所述第一贯孔及所述第二贯孔电连接所述栅极线，一数据端子通过所述第三贯孔电连接所述数据线，其中，所述栅极端子及所述数据端子为导电的。
  7. 一种阵列基板的制备方法，其中，所述阵列基板的制备方法包括：
    提供基板；
    在所述基板的第一表面设置整层的第一金属层；
    图案化所述第一金属层，以形成多个沿第一方向延伸且沿第二方向间隔排布的栅极线，以及设置在相邻的两条栅极线之间的且间间隔设置的栅极、第一导电部、与每个栅极线对应且平行的公共电极线以及与公共电极线连接且朝远离所述栅极线延伸的公共电极；
    形成覆盖所述栅极、所述第一导电部、所述栅极线、所述公共电极线及所述公共电极的第一绝缘层；
    在所述第一绝缘层远离所述基板的表面形成与所述栅极对应设置的沟道层；
    形成覆盖所述第一绝缘层及所述沟道层的第二金属层；
    图案化所述第二金属层，以形成多个沿所述第二方向延伸且沿所述第一方向排布的数据线，以及设置在相邻的两条数据线之间且对应所述沟道层两端设置的源极及漏极、与所述漏极间隔的像素电极、与所述第一导电部对应的第二导电部；
    形成覆盖所述沟道层、所述源极、所述漏极、所述像素电极、所述第二导电部及所述数据线的第二绝缘层。
  8. 如权利要求7所述的阵列基板的制备方法，其中，在所述步骤“在所述第一绝缘层远离所述基板的表面形成与所述栅极对应设置的沟道层”包括：
    在所述第一绝缘层远离所述基板的表面形成整层的非晶硅层；
    图案化所述非晶硅层，保留对应所述栅极设置的所述非晶硅层；
    对保留的所述非晶硅层的两端进行离子掺杂，以分别形成第一欧姆接触层及第二欧姆接触层，未进行离子掺杂的所述非晶硅层为所述沟道层。
  9. 如权利要求7所述的阵列基板的制备方法，其中，所述阵列基板的制备方法还包括：
    在所述第一绝缘层上开设对应所述栅极线的第一贯孔，在所述第二绝缘层上开设对应所述第一贯孔的第二贯孔及对应所述数据线的第三贯孔；
    在所述第二绝缘层层形成导电材料层；
    图案化所述导电材料层，保留对应所述第二贯孔及所述第一贯孔的导电材料层以及对应所述第三贯孔的导电材料层，其中，对应所述第二贯孔及所述第一贯孔的导电材料层为栅极端子，对应所述第三贯孔的导电材料层为数据端子。
  10. 如权利要求8所述的阵列基板的制备方法，其中，所述离子掺杂为N型离子掺杂。
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