WO2017127091A1 - Contrôleur à jeu d'instructions réduit pour capteur de lacunes d'azote de diamant - Google Patents

Contrôleur à jeu d'instructions réduit pour capteur de lacunes d'azote de diamant Download PDF

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Publication number
WO2017127091A1
WO2017127091A1 PCT/US2016/014376 US2016014376W WO2017127091A1 WO 2017127091 A1 WO2017127091 A1 WO 2017127091A1 US 2016014376 W US2016014376 W US 2016014376W WO 2017127091 A1 WO2017127091 A1 WO 2017127091A1
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WO
WIPO (PCT)
Prior art keywords
controller
digital control
waveform generator
waveform
single chip
Prior art date
Application number
PCT/US2016/014376
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English (en)
Inventor
David N. Coar
Jon C. Russo
Boris Shishkin
Original Assignee
Lockheed Martin Corporation
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Publication date
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Publication of WO2017127091A1 publication Critical patent/WO2017127091A1/fr

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R33/00—Arrangements or instruments for measuring magnetic variables
    • G01R33/02—Measuring direction or magnitude of magnetic fields or magnetic flux
    • G01R33/032—Measuring direction or magnitude of magnetic fields or magnetic flux using magneto-optic devices, e.g. Faraday or Cotton-Mouton effect
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/25—Pc structure of the system
    • G05B2219/25126—Synchronize communication based on internal clock of microprocessor

Definitions

  • the subject technology generally relates to magnetometry, and more particularly, to synchronous control, radio-frequency (RF) synthesis, and fluorescence acquisition processor for diamond nitrogen-vacancy (DNV).
  • RF radio-frequency
  • DNV diamond nitrogen-vacancy
  • Atomic-sized nitrogen-vacancy (NV) centers in diamond lattices have been shown to have excellent sensitivity for magnetic field measurement and enable fabrication of small magnetic sensors that can readily replace existing-technology (e.g., Hall-effect) systems and devices.
  • the diamond NV (DNV) sensors are maintained in room temperature and atmospheric pressure and can be even used in liquid environments.
  • a green optical source e.g., a laser or a micro-LED
  • the distance between the two spin resonance frequencies is a measure of the strength of the external magnetic field.
  • a photo detector can measure the fluorescence (red light) emitted by the optically excited NV centers and a DNV system is used to control the laser and microwave timings and perform the data acquisition.
  • One implementation relates to a controller for a DNV sensor that includes a RF waveform generator for generating a RF waveform for a RF signal for a DNV sensor and a digital control for controlling a laser for the DNV sensor.
  • the RF waveform generator and the digital control are formed in a single chip.
  • the single chip is a field-programmable gate array or an application specific integrated circuit.
  • the RF waveform generator and the digital control operate on single-cycle instructions or two-cycle instructions.
  • the RF waveform generator and the digital control operate on single-cycle instructions of a reduced instruction set.
  • the RF waveform generator includes a coordinate rotation digital computer.
  • the RF waveform generator utilizes a frequency base and a frequency increment to generate the RF waveform.
  • the RF waveform generated by the RF waveform generator is processed through an upconverter to generate the RF signal.
  • the digital control includes RF gating.
  • the digital control includes general inputs or outputs. In some implementations, the digital control is configured to control the generation of the RF waveform. In some implementations, the digital control is configured to control optic pulsing of the laser. In some implementations, the single chip is configured to be integrated into one of a geo-location system, an anomaly detection system, a distributed measure point system, a communication system, an unmanned air vehicle, a micro unmanned air vehicle, a missile, an unmanned sea vehicle, an unmanned underground vehicle, or a satellite.
  • Another implementation relates to a controller for a DNV sensor that includes a RF waveform generator for generating a RF waveform for a RF signal for a DNV sensor, a digital control for controlling a laser for the DNV sensor, and an acquisition processor.
  • the RF waveform generator, the digital control, and the acquisition processor are formed in a single chip.
  • the single chip is a field-programmable gate array or an application specific integrated circuit.
  • the RF waveform generator, the digital control, and the acquisition processor operate on single-cycle instructions or two-cycle instructions.
  • the RF waveform generator, the digital control, and the acquisition processor operate on single-cycle instructions of a reduced instruction set.
  • the acquisition processor preprocesses data received from a photo detector of the DNV sensor.
  • the acquisition processor decimates the data received from the photo detector of the DNV sensor.
  • the single chip is configured to be integrated into one of a geo-location system, an anomaly detection system, a distributed measure point system, a communication system, an unmanned air vehicle, a micro unmanned air vehicle, a missile, an unmanned sea vehicle, an unmanned underground vehicle, or a satellite.
  • Yet another implementation relates to a controller for a DNV sensor that includes a RF waveform generator for generating a RF waveform for a RF signal for a DNV sensor, a digital control for controlling a laser for the DNV sensor, an acquisition processor, a host interface for interfacing with an external system, a program counter, a program memory, and a jump control.
  • the the RF waveform generator, the digital control, the acquisition processor, the host interface, the program counter, the program memory, and the jump control are formed in a single chip
  • the single chip is a field-programmable gate array or an application specific integrated circuit.
  • the RF waveform generator, the digital control, and the acquisition processor operate on single-cycle instructions or two-cycle instructions.
  • the RF waveform generator, the digital control, and the acquisition processor operate on single-cycle instructions of a reduced instruction set.
  • the single chip is configured to be integrated into one of a geo-location system, an anomaly detection system, a distributed measure point system, a communication system, an unmanned air vehicle, a micro unmanned air vehicle, a missile, an unmanned sea vehicle, an unmanned underground vehicle, or a satellite.
  • FIG. 1 is a block diagram of an overview of a single-cycle synthesis, control, and acquisition system for a diamond nitrogen vacancy sensor
  • FIG. 2 is a block circuit diagram of the single-cycle control, synthesis, and acquisition processor for a diamond nitrogen vacancy sensor of FIG. 1;
  • FIG. 3 A is a block circuit diagram of the host interface of FIG. 2;
  • FIG. 3B is a block circuit diagram of the program counter of FIG. 2;
  • FIG. 3C is a block circuit diagram of the program memory of FIG. 2;
  • FIG. 3D is a block circuit diagram of a first portion of the jump control with delay of
  • FIG. 2
  • FIG. 3E is a block circuit diagram of a second portion of the jump control FIG. 2;
  • FIG. 3F is a block circuit diagram of the RF waveform generator of FIG. 2;
  • FIG. 3G is a block circuit diagram of the digital control of FIG. 2;
  • FIG. 3H is a block circuit diagram of the acquisition processor of FIG. 2;
  • FIG. 4 is a block diagram depicting a general architecture for a computer system that may be employed to interact various elements of the systems and methods described and illustrated herein.
  • the disclosed system includes a reduced instruction set (RISC) processor that is coupled to a configurable signal synthesizer.
  • RISC reduced instruction set
  • the configurable signal synthesizer may be configured to perform single-cycle commands for frequency shifts, digital outputs, and initial synchronous preprocessing of received data such that the digital control, acquisition, and waveform generation may be performed on the same clock cycle for synchronization.
  • the specially designed single-cycle operations of the subject technology may provide more precise and deterministic timing for digital control, acquisition, and waveform generation.
  • the RF waveform generation and digital control outputs are coordinated in configurable patterns that can range from simple sequences to complex adaptive control patterns.
  • FIG. 1 is a block diagram depicting an overview of an implementation of a single-cycle synthesis, control, and acquisition system 100.
  • the system 100 is configured to control multiple RF signals and digital output signals for magnetometry, such as for a diamond nitrogen vacancy (DNV) sensor.
  • the system 100 may be implemented as a field- programmable gate array (FPGA) or may be implemented as an application specific integrated circuit (ASIC).
  • FPGA field- programmable gate array
  • ASIC application specific integrated circuit
  • the system 100 is implemented as a single single-cycle integrated circuit for RF waveform synthesis, digital control, and acquisition.
  • a more detailed implementation of the single-cycle synthesis, control, and acquisition system is shown as the system 200 in FIG. 2.
  • the system 100 includes a host interface 110 that receives DNV sensing information from an external system, such as a data processing or acquisition system (not shown), and is communicatively coupled to a program counter 120, a program memory 130, and an acquisition processor 180.
  • the host interface 110 may be coupled to a data processing system, such as system 300 of FIG. 3, that can communicate with the system 100 via the host interface 110.
  • the data processing system can output instructions, such as control instructions from the reduced instruction set, to the system 100 via the host interface 110 for the program memory 130.
  • the data acquisition system can also receive output from the acquisition processor 180 via the host interface 110, such as pulse processed data from a DNV sensor.
  • the host interface 110 provides communication between the components of the system 100 and an external system.
  • a more detailed depiction of the host interface 110 is shown as host interface 210 in FIGS. 2 and 3 A.
  • the host interface 110 is communicatively coupled to the program counter 120, which is in communication with the program memory 130 and thejump control 170.
  • a more detailed implementation of the program counter 120 is shown as program counter 220 in FIGS. 2 and 3B.
  • a more detailed implementation of the program memory 130 is shown as program memory 230a, 230b in FIGS. 2 and 3C.
  • a more detailed implementation of thejump control 170 is shown as jump control with delay 240a and the jump control 240b in FIGS. 2 and 3D-E.
  • the program memory 130 provides outputs through a decoder 140 to a RF waveform generator of the
  • CORDIC Coordinat Rotation Digital Computer
  • the CORDIC synthesis 150 provides digital up or down conversion and can have a runtime configurable base frequency and increment for the RF waveform generation.
  • the RF waveform generator of the CORDIC synthesis 150 utilizes a frequency base value and a frequency increment that outputs a single value for a slope of a ramp that is used by an accumulator to generate a sine wave for the RF waveform.
  • the sine wave is processed through an upconverter to generate the RF waveform signal to be applied to the magnetometry component, such as a DNV sensor.
  • the CORDIC synthesis 150 may phase shift the RF waveform. For instance, an analog or digital switch may be used for arbitrary waveform generation.
  • a more detailed implementation of the RF waveform generator and CORDIC synthesis 150 is shown as RF waveform generator 250 in FIGS. 2 and 3F.
  • the digital control 150 provides timing control for a number of aspects of a
  • the digital control 150 includes RF gating or switches and may include additional general inputs or outputs for additional control.
  • the digital control 150 may output signals to control the activation of a magnetometry component, such as a laser for exciting a nitrogen vacancies of a DNV sensor.
  • the digital control can also convert the CORDIC output to 0 via a multiplexer (MUX) such that no RF signal is applied to the DNV sensor.
  • MUX multiplexer
  • the digital control 150 can be used for an acousto-optic modulator (AOM) to control optic pulsing of the laser and/or can be used for phase shift control.
  • the digital control 150 may further provide an output to an I/Q component, such as a digital I/Q.
  • a more detailed implementation of the digital control 160 is shown as digital control 260 in FIGS. 2 and 3G.
  • the acquisition processor 180 provides initial synchronous preprocessing of data received from a magnetometry component, such as data received from a photo detector of a DNV sensor.
  • the acquisition processor 180 can include two coherent channels for simultaneous collection of data, such as the collection of red light, infrared, laser, etc. data. In some implementations, the channels may be chainable up to four. In an implementation with a photo detector, data received by the acquisition processor 180 may be at a rate of 50 MHz, 100 MHz, 200 MHz, or greater. To reduce the amount of data transferred to an external system from the system 100, the acquisition processor can preprocess the data to reduce the size of the data outputted.
  • the acquisition processor 180 synchronously gathers samples from a magnetometry component, such as the photo detector of a DNV sensor, and preprocesses the data, such as decimation of the data.
  • the acquisition process 180 may include a digital output to trigger an accumulator for a predetermined number of clock cycles and then will subtract from two integration windows for processing of the data.
  • the acquisition processor 180 may include a digitally controllable offset for effects similar to a DC block or AC coupling. A more detailed implementation of the acquisition processor 180 is shown as acquisition processor 270 in FIGS. 2 and 3H.
  • the system 100 is configured for single-cycle instructions for the components of the system 100 such that the RF waveform generator of the CORDIC synthesis 150 for generating the RF waveform, the digital control 160 for controlling the laser on/off timing, and the acquisition processor 180 operate on the same clock cycle.
  • a main counter (not shown) drives the RF waveform generation while the program counter 120 allows for delays to be implemented for the digital control 150 and the acquisition processor 180.
  • the single-cycle can provide laser and/or microwave deterministic timing control for coordination of the
  • the single-cycle tightly ties in the digital control 160 for controlling the laser and acquisition processor with the RF waveform generation of the CORDIC synthesis 150.
  • the single-cycle permits synchronous stepped-frequency complex waveform synthesis by the CORDIC synthesis 150 and permits coordinated large-range frequency retuning (e.g., >1 GHz) without losing base time.
  • the single-cycle system 100 can also provide synchronous reduced instruction set program control of the frequency for the RF waveform synthesis.
  • the system 100 of FIG. 1 with a single- cycle also reduces redundant components compared to systems that utilize separate components for the RF waveform generator, digital control, and/or acquisition processor. In some
  • the single-cycle synthesis, control, and acquisition system 100 may also be configured for two-cycle implementations as well.
  • the system 100 can utilize a reduced instruction set (RISC) engine that issues one instruction per clock cycle, including for conditional branching.
  • the reduced instruction set can include commands for an unconditional jump (jmp), a conditional jump (cjmp), setting of a loop counter (setc ⁇ counter value>), setting of a frequency (set/ value>), setting of a digital control output field (seto ⁇ output field value>), a frequency increment (incf ⁇ increment value>), and a delay for a specified cycle count (del ⁇ cycle count value>).
  • the single-cycle synthesis, control, and acquisition system 100 can provide lock-step precision for laser on/off timing via the digital control 160, sequenced microwave waveform synthesis and delivery via the RF waveform generator and CORDIC synthesis 150, data acquisition via the acquisition processor 170, and laser and /or microwave deterministic timing control.
  • the single-cycle synthesis, control, and acquisition system 100 can facilitate effective experimentation by enabling rapid coordination of excitation signals and tuning across broad frequency ranges without losing timing.
  • Not all of the depicted components may be required, however, and one or more implementations may include additional components not shown in the figure. Variations in the arrangement and type of the components may be made, and additional components, different components, or fewer components may be provided.
  • FIG. 2 is a circuit diagram illustrating an example implementation of the single-cycle synthesis, control, and acquisition system 200.
  • the single-cycle synthesis, control, and acquisition system 200 as implemented by the circuit of FIG. 2, is a dedicated hardware configured for DNV applications that are customized to the unique requirements of controlling multiple, diverse instruments and sensors across the RF to optical domain.
  • the reduced instruction set (RISC) engine is configured to issue one instruction per clock cycle, even for conditional branches.
  • the RF waveform generator uses a run-time configurable base frequency and increment to provide the CORDIC synthesis with an RF waveform for digital up/down conversion.
  • the digital control block is responsible for providing laser timing, RF gating, and additional general control input/output (I/O).
  • the acquisition processor block is configured to provide two coherent channels (potentially chainable up to 4) for simultaneous red, infra-red (IR), laser, and other types of light collection.
  • the acquisition processing block is further configured to synchronously collect samples and to provide digitally controllable analog offset that allows effects like DC blocking or AC coupling.
  • Examples of advantageous features of the single-cycle synthesis, control, and acquisition system 200 include, but are not limited to, single-cycle deterministic timing coordination of RF waveform generation, laser control, and data acquisition, synchronous stepped-frequency for complex waveform synthesis, synchronous RISC program control of frequency, coordinated large-range (e.g., >lGHz) frequency retuning without losing time base, and a minimal instruction set.
  • the system 100, 200 can be incorporated into a variety of settings and configurations where DNV magnetometers are employed.
  • Examples of applications of the single-cycle synthesis, control, and acquisition system 100, 200 include, but are not limited to incorporating the single chip into a DNV sensor, incorporating the single chip into DNV-based geolocation systems, incorporating the single chip into DNV anomaly detection systems, incorporating the single chip into covert communications systems, incorporating the single chip into distributed measure point systems, incorporating the single chip into small form factor unmanned systems for air (e.g., unmanned air vehicle (UAV), micro unmanned air vehicle ( ⁇ ), missiles), sea, underground, and surveillance (e.g., satellites, cluster satellites, etc.), incorporating the single chip into low SWAP (size, weight, and power) applications, and utilizing the single chip, single-cycle synthesis, control, and acquisition system 100, 200 for automatic experimental optimization.
  • UAV unmanned air vehicle
  • ⁇ micro unmanned air vehicle
  • missiles sea, underground
  • surveillance e.g., satellites, cluster satellites, etc.
  • FIG. 3 is a diagram illustrating an example of a system 300 for implementing some aspects of the subject technology.
  • the system 300 includes a processing system 302, which may include one or more processors or one or more processing systems.
  • a processor can be one or more processors.
  • the processing system 302 may include a general-purpose processor or a specific-purpose processor for executing instructions and may further include a machine- readable medium 319, such as a volatile or non-volatile memory, for storing data and/or instructions for software programs.
  • the instructions which may be stored in a machine-readable medium 310 and/or 319, may be executed by the processing system 302 to control and manage access to the various networks, as well as provide other communication and processing functions.
  • the instructions may also include instructions executed by the processing system 302 for various user interface devices, such as a display 312 and a keypad 314.
  • the processing system 302 may include an input port 322 and an output port 324.
  • Each of the input port 322 and the output port 324 may include one or more ports.
  • the input port 322 and the output port 324 may be the same port (e.g., a bi-directional port) or may be different ports.
  • the processing system 302 may be implemented using software, hardware, or a combination of both.
  • the processing system 302 may be implemented with one or more processors.
  • a processor may be a general-purpose microprocessor, a
  • DSP Digital Signal Processor
  • ASIC Application Specific Integrated Circuit
  • FPGA Field Programmable Gate Array
  • PLD Programmable Logic Device
  • controller a state machine, gated logic, discrete hardware components, or any other suitable device that can perform calculations or other manipulations of information.
  • a machine-readable medium can be one or more machine-readable media.
  • Software shall be construed broadly to mean instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Instructions may include code (e.g., in source code format, binary code format, executable code format, or any other suitable format of code).
  • Machine-readable media may include storage integrated into a processing system such as might be the case with an ASIC.
  • Machine-readable media may also include storage external to a processing system, such as a Random Access Memory (RAM), a flash memory, a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable PROM (EPROM), registers, a hard disk, a removable disk, a CD-ROM, a DVD, or any other suitable storage device.
  • RAM Random Access Memory
  • ROM Read Only Memory
  • PROM Erasable PROM
  • registers a hard disk, a removable disk, a CD-ROM, a DVD, or any other suitable storage device.
  • a machine-readable medium is a computer-readable medium encoded or stored with instructions and is a computing element, which defines structural and functional interrelationships between the instructions and the rest of the system, which permit the instructions' functionality to be realized.
  • Instructions may be executable, for example, by the processing system 302 or one or more processors. Instructions can be, for example, a computer program including code for performing methods of the subject technology.
  • a network interface 316 may be any type of interface to a network (e.g., an Internet network interface), and may reside between any of the components shown in FIG. 3 and coupled to the processor via the bus 304.
  • a network e.g., an Internet network interface
  • a device interface 318 may be any type of interface to a device and may reside between any of the components shown in FIG. 3.
  • a device interface 318 may, for example, be an interface to an external device (e.g., USB device) that plugs into a port (e.g., USB port) of the system 300.
  • the device interface 318 may be the host interface of FIG. 1, where at least some of the functionalities of the apparatus of FIG. 1 are performed by the processing system 302.
  • One or more of the above-described features and applications may be implemented as software processes that are specified as a set of instructions recorded on a computer readable storage medium (alternatively referred to as computer-readable media, machine-readable media, or machine-readable storage media).
  • a computer readable storage medium alternatively referred to as computer-readable media, machine-readable media, or machine-readable storage media.
  • processing unit(s) e.g., one or more processors, cores of processors, or other processing units
  • the computer readable media does not include carrier waves and electronic signals passing wirelessly or over wired connections, or any other ephemeral signals.
  • the computer readable media may be entirely restricted to tangible, physical objects that store information in a form that is readable by a computer.
  • the computer readable media is non-transitory computer readable media, computer readable storage media, or non-transitory computer readable storage media.
  • a computer program product also known as a program, software, software application, script, or code
  • a computer program product can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object, or other unit suitable for use in a computing
  • a computer program may, but need not, correspond to a file in a file system.
  • a program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code).
  • a computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.
  • ASICs application specific integrated circuits
  • FPGAs field programmable gate arrays
  • integrated circuits execute instructions that are stored on the circuit itself.
  • the subject technology is directed to method and systems for providing precisely timed laser actuation, RF waveform control, and synchronous acquisition of fluorescence information from a DNV magnetometer.
  • the subject technology may be used in various markets, including for example and without limitation, advanced sensors.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Automation & Control Theory (AREA)
  • Position Fixing By Use Of Radio Waves (AREA)

Abstract

L'invention concerne des systèmes, des contrôleurs et des configurations pour assurer un actionnement laser précisément cadencé, une commande de forme d'onde RF, et une acquisition synchrone d'informations de fluorescence à partir de composants de magnétométrie, tels qu'un capteur de lacunes d'azote de diamant (DNV). Un contrôleur pour un capteur DNV peut comprendre un générateur de forme d'onde RF pour générer une forme d'onde RF pour un signal RF pour un capteur DNV et une commande numérique pour commander un laser pour le capteur DNV. Le générateur de forme d'onde RF et la commande numérique peuvent être formés dans une même puce, telle qu'un FPGA ou ASIC.
PCT/US2016/014376 2016-01-21 2016-01-21 Contrôleur à jeu d'instructions réduit pour capteur de lacunes d'azote de diamant WO2017127091A1 (fr)

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US15/003,336 2016-01-21
US15/003,336 US20170212181A1 (en) 2016-01-21 2016-01-21 Reduced instruction set controller for diamond nitrogen vacancy sensor

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