WO2017124879A1 - 一种半极性led结构及其制备方法 - Google Patents

一种半极性led结构及其制备方法 Download PDF

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WO2017124879A1
WO2017124879A1 PCT/CN2016/111663 CN2016111663W WO2017124879A1 WO 2017124879 A1 WO2017124879 A1 WO 2017124879A1 CN 2016111663 W CN2016111663 W CN 2016111663W WO 2017124879 A1 WO2017124879 A1 WO 2017124879A1
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semi
sapphire substrate
semiconductor
polar
led epitaxial
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PCT/CN2016/111663
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English (en)
French (fr)
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杜成孝
郑建森
张洁
徐宸科
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厦门市三安光电科技有限公司
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Priority claimed from CN201610030333.8A external-priority patent/CN105489724B/zh
Priority claimed from CN201610030332.3A external-priority patent/CN105679903B/zh
Application filed by 厦门市三安光电科技有限公司 filed Critical 厦门市三安光电科技有限公司
Publication of WO2017124879A1 publication Critical patent/WO2017124879A1/zh
Priority to US15/870,949 priority Critical patent/US20180138332A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02366—Special surface textures of the substrate or of a layer on the substrate, e.g. textured ITO/glass substrate or superstrate, textured polymer layer on glass substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/0304—Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L31/03044—Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds comprising a nitride compounds, e.g. GaN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
    • H01L31/1856—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP comprising nitride compounds, e.g. GaN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to the field of semiconductor optoelectronic devices, and more particularly to a semi-polar LED structure and a method of fabricating the same.
  • An LED is a semiconductor solid-state light-emitting device that utilizes a semiconductor PN junction as a light-emitting material to directly convert electricity into light.
  • the polar GaN-based LED technology has been industrialized for more than 20 years, and its performance has been greatly improved since its development.
  • the performance bottleneck of polar LEDs has gradually emerged. After the photoelectric conversion efficiency reaches 60%, it is difficult to have a large Continue to improve.
  • polar LED devices have an insurmountable polarization effect, which affects the luminous efficiency of LEDs.
  • research and literature reports on semi-polar and non-polar materials and devices have been reported in recent years. The main problem is that it is difficult to grow GaN materials on semi-polar or non-polar surfaces.
  • the object of the present invention is to provide a C-plane sapphire substrate in-situ growth preparation semi-polar LED epitaxial structure and a preparation method thereof, which can control the surface of the semiconductor underlayer during epitaxial growth using a sapphire plane or a pattern substrate Forming a V-shaped pit (including a nano-V-shaped pit), and then preparing a half on the side of the V-shaped pit.
  • the conductor functional layer finally obtains the semi-polar LED epitaxial structure.
  • a first aspect of the present invention provides a semi-polar LED epitaxial structure including, in order from bottom to top, a sapphire substrate, a semiconductor underlayer structure, and a semiconductor functional layer, wherein: the semiconductor underlayer structure The surface has a V-shaped pit, and the side of the V-shaped pit is a semi-polar surface corresponding to the (1-101) crystal plane family.
  • the sapphire substrate is a patterned sapphire substrate or a flat sapphire substrate.
  • the sapphire substrate is a patterned sapphire substrate, and the pattern density thereof is consistent with the density of the V-shaped pit.
  • the semiconductor underlayer structure comprises a buffer layer or a uGaN layer or an nGaN layer or any combination of the foregoing.
  • the semiconductor functional layer material comprises a GaN-based semiconductor material.
  • a method for fabricating a semi-polar LED epitaxial structure includes the following process steps:
  • the sapphire substrate is a patterned sapphire substrate or a flat sapphire substrate.
  • the density of the V-shaped pit is adjusted by the pattern density of the patterned sapphire substrate.
  • the semiconductor underlayer structure comprises a buffer layer or a uGaN layer or an nGaN layer or any combination of the foregoing
  • the step (2) is to control the growth temperature to be relatively low (within 1100 ° C), and the growth rate is relatively fast (3 ⁇ m / 1 or more), so that the surface of the semiconductor underlying structure forms a V-shaped pit.
  • the step (3) increases the growth rate on the semi-polar surface to 5 to 10 times of the regular polar surface or 5 to 10 times the growth growth period to the conventional polar surface.
  • the semiconductor functional layer material comprises a GaN-based semiconductor material.
  • a semi-polar LED epitaxial structure comprising, in order from bottom to top, a sapphire substrate, a semiconductor underlayer structure, and a semiconductor functional layer, wherein: the semiconductor underlayer
  • the semiconductor underlayer The surface of the structure has a nano V-shaped pit, and the side of the V-shaped pit is a semi-polar surface corresponding to (1-101) crystal Face family.
  • the sapphire substrate is a nano-patterned sapphire substrate or a flat sapphire substrate.
  • the sapphire substrate is a nano-patterned sapphire substrate, and the nano-V-shaped pit has a wire diameter of 100 to 1000 nm.
  • the sapphire substrate is a plain sapphire substrate, and the diameter of the nano V-shaped pit conforms to a normal distribution, and the peak size of the normal distribution corresponds to 550 ⁇ 10 nm.
  • the semiconductor underlayer structure comprises a buffer layer or a uGaN layer or an nGaN layer or any combination of the foregoing
  • the semiconductor functional layer material comprises a GaN-based semiconductor material.
  • the semiconductor functional layer comprises a first semiconductor functional layer and a second semiconductor functional layer, wherein the surface of the first semiconductor functional layer has a nano V-pit.
  • a method for fabricating a semi-polar LED epitaxial structure includes the following process steps:
  • the side of the V-shaped pit is a semi-polar surface corresponding to the (1-101) crystal face family
  • the sapphire substrate is a nano-patterned sapphire substrate or a flat sapphire substrate.
  • the density of the V-pits is adjusted by the pattern density of the nanopatterned sapphire substrate.
  • the sapphire substrate is a nano-patterned sapphire substrate, and the nano-V-shaped pit has a wire diameter of 100 to 1000 nm.
  • the sapphire substrate is a flat sapphire substrate, and the diameter of the nano V-shaped pit conforms to a normal distribution, and the peak size of the normal distribution corresponds to 550 ⁇ 10 nm.
  • the semiconductor underlying structure comprises a buffer layer or a uGaN layer or an nGaN layer or any combination of the foregoing
  • the step (2) is to control the growth temperature to be relatively low (within 1100 ° C), and the growth rate is relatively fast (3 ⁇ m / 1 or more), so that the surface of the semiconductor underlayer structure forms a nano V-shaped pit.
  • the semiconductor functional layer material comprises a GaN-based semiconductor material.
  • the semiconductor functional layer comprises a first semiconductor functional layer and a second semiconductor functional layer, wherein the surface of the first semiconductor functional layer has a nano V-pit.
  • the nano V-shaped pit of the first semiconductor functional layer is accelerated by a growth rate on a semipolar plane to 5 to 10 times of a regular polar surface or an extended growth period to a conventional polar surface. 5 to 10 times.
  • the conduction band and the valence band of the LED epitaxial structure of the conventional polar face (001) face are bent due to the existence of the polarization electric field, and the conduction band bottom and the valence band collapse space are not in the same
  • the position similar to the indirect bandgap semiconductor luminescence (the AlInGaN system material is a direct bandgap luminescent material), the radiation composite luminescence efficiency is reduced, and the non-radiation recombination probability is increased.
  • the present invention at least includes the following technical effects:
  • the semipolar plane is a (1-101) crystal plane family, and the smooth conduction band bottom and the valence band top have a large overlapping area in the inverted space, and the radiation recombination efficiency is greatly increased;
  • a semiconductor functional layer is formed on the surface of the semiconductor underlayer structure having the nano V-pit, and the epitaxial structure thus obtained can be fused with the existing chip process to facilitate fabrication of a semiconductor light emitting device such as an LED chip.
  • FIG. 1 The figure indicates: 11, 21, 31, 41, 51, 61: sapphire substrate; 12, 22, 32, 42, 52, 62: buffer layer; 13, 23, 33, 43, 53, 63: First uGaN layer; 14, 24, 34, 44, 54, 64: second uGaN layer; 15, 25, 35, 45, 55, 65: nGaN layer; 16, 26, 36, 46, 56, 66: semiconductor Functional layer; 17, 27, 37, 47, 57, 67: side of V-shaped pit (corresponding to (1-101) crystal family
  • FIG. 5 are schematic cross-sectional views showing an epitaxial structure of an LED fabricated in Embodiments 1 and 2.
  • 6 is a cross-sectional view showing an epitaxial structure of an LED fabricated in Embodiment 3 of the present invention.
  • FIG. 7 to FIG. 11 are schematic cross-sectional views showing an epitaxial structure of an LED fabricated in Embodiments 4 and 5 of the present invention.
  • FIG. 12 is a cross-sectional view showing an epitaxial structure of an LED fabricated in Embodiment 6 of the present invention.
  • FIG. 13 is a cross-sectional view showing an epitaxial structure of an LED fabricated in Embodiment 7 of the present invention.
  • FIG. 14 is a cross-sectional view showing an epitaxial structure of an LED fabricated in Embodiment 8 of the present invention.
  • the embodiment provides a method for fabricating a GaN semi-polar LED epitaxial structure, which can avoid the problem that the semi-polar material does not grow well and the homogenous semi-polar material is expensive.
  • the following technical scheme takes a sapphire pattern substrate as an example, and the manufacturing method includes the following steps:
  • a sapphire substrate 11 (Sapphire) is provided and placed in a metal organic chemical vapor deposition (MOCVD) apparatus to raise the temperature to 1000 to 1200 ° C for 3 to 10 minutes under a hydrogen atmosphere;
  • MOCVD metal organic chemical vapor deposition
  • a patterned sapphire substrate (PSS) can obtain a regular array of surface V-pits (pits) corresponding to the bumps (islands) of each patterned substrate. The density of the V-pits can pass through the pattern density of the patterned substrate.
  • the density of the V-shaped pit is the same, and the size of each V-shaped pit is also determined, that is, the PSS pattern density is consistent with the density of the V-shaped pit;
  • Semi-polar surface LEDs can also be obtained using a flat sapphire substrate (F SS ) with different V-shaped pits on the surface and relatively random distribution, but the density is affected by the thickness of the buffer layer and the annealing conditions of the buffer layer: The thicker the buffer layer The lower the annealing temperature, the shorter the annealing time, the higher the island density, the greater the density of the subsequent V-pits; and vice versa.
  • a semiconductor underlayer structure having a V-shaped pit is epitaxially grown on the low temperature buffer layer 12, and the side surface 17 of the V-shaped pit is a semipolar plane corresponding to the (1-101) crystal plane family, specifically , heating to 1000 ⁇ 1100 ° C, annealing at this temperature for 1 to 5 minutes, and then introducing trimethylgallium to grow a non-tacky gallium nitride 13 (first uGaN layer) having a thickness of 1 to 2 ⁇ m.
  • the layer is called a three-dimensional mode GaN growth layer; the growth temperature is controlled within 1 050 ° C, the chamber pressure is 500 torr, and the growth rate is controlled above 3 ⁇ /1 ⁇ , a large number of V-shaped pits can be obtained, and the V-shaped pit can occupy the entire epitaxial surface. The C-face completely disappears, and the V-shaped pit can also partially occupy the surface. In this embodiment, it is preferable that the V-shaped pit occupies the entire epitaxial surface without the C-plane.
  • the temperature is controlled within 1100 ° C
  • the chamber pressure is 300 torr
  • the non-tacky gallium nitride 14 (second uGaN layer) of 1 ⁇ 2 ⁇ thick is grown, and the layer is called a two-dimensional mode.
  • GaN growth layer growth rate is controlled above 4 ⁇ /1 ⁇ , V-shaped pits occupy the entire surface.
  • the temperature is lowered to about 1050 ° C, the chamber pressure is 300 torr, and the gallium nitride having a thickness of 1.5 to 4 ⁇ m is grown, and silane is introduced into the silane to form a bismuth gallium nitride 15 (nGaN layer); It is also possible to grow a uGaN/nGaN superlattice instead of the completely cumbersome nGaN to provide electron injection; the growth rate is controlled to be above 5 ⁇ /1 ⁇ ; after the growth of nGa N, the epitaxial surface is completely filled by the V-type pit.
  • the semiconductor functional layer is continuously grown on the surface of the semiconductor underlayer structure forming the V-shaped pit.
  • a GaN-based semiconductor material is preferable, and the structural layer is SLs/MQWs/pAlGaN/pGaN/p++ as a functional layer.
  • the InGaN/GaN superlattice layer (S Ls ) is cooled to 770-870 ° C and grown for 15 to 30 cycles.
  • the thickness of InGaN ranges from 1 to 3 nm in each cycle, and the thickness of GaN ranges from 2.5 to 8 nm.
  • the superlattice layer acts as a low temperature stress release layer and exerts a stress release effect; since the epitaxial deposition rate on the semipolar surface is only 1/10 to 1/5 of the polar surface, the preparation is equivalent to the conventional method (polar surface growth).
  • the thickness of the epitaxial layer, the growth rate on the semi-polar surface can be accelerated by 5 to 10 times by adjusting the source gas flow rate or prolonging the growth period to 5 to 10 times of the conventional time; the temperature is controlled between 750 and 900 ° C.
  • Commonly used transparent electrodes form an ohmic contact, and the growth rate is the same as that of the low temperature stress relief layer (InGaN/GaN superlattice layer).
  • the p-type GaN layer and the heavily p-type GaN contact layer (p++) are different from the p-type layer of the conventional C-plane LED, and the p-type layer of the conventional C-side LED is grown with a large amount of hydrogen.
  • the utility model has the function of filling (filling) the V-shaped pit, and the pGaN of the embodiment needs to be grown under nitrogen conditions or a small amount of hydrogen gas to avoid filling the V-shaped pit.
  • an LED epitaxial structure provided in this embodiment includes, in order from bottom to top, a sapphire substrate 11, a buffer layer 12, a first u-GaN layer 13, and a second u-GaN layer 14. a semiconductor underlayer structure having a V-pit of the nGaN layer 15 and a semiconductor functional layer 1 including SLs/MQW S /pAlG a N/pGaN/p++
  • the sapphire substrate 11 of the embodiment may be a patterned sapphire substrate (PSS, Patterned Sapphire Substrate) or a flat sapphire substrate (FSS, Flat Sapphire).
  • PSS patterned sapphire substrate
  • FSS Flat Sapphire
  • the PSS substrate is preferred in this embodiment, and the feature size (period) is limited to 1 to 10 ⁇ m, but is not limited thereto.
  • the buffer layer 12 is made of an AlInGaN semiconductor material and formed on the sapphire substrate 11 to reduce lattice mismatch caused by a difference in lattice constant between the sapphire substrate 11 and the first conductive type semiconductor layer. Epitaxial growth quality.
  • SLs, MQWs, pAlGaN, pGaN, p++ constitute a semiconductor functional layer 16, which is sequentially formed on the nGaN surface of the V-pit.
  • the difference between this embodiment and Embodiment 1 is that: the three-dimensional mode grown first uGaN layer 13 of the patterned sapphire substrate in Embodiment 1 forms two between sapphire patterns (at the pitch). Dimensional film, The V-shaped pit is formed on the top of the pattern.
  • the temperature is raised to 1000-1100 ° C, and annealing is performed at this temperature for 1 to 5 minutes, using a sapphire substrate.
  • the nucleation island of the surface (not shown) is used as the nucleation center of the first uGaN layer 23, and is grown in a three-dimensional mode, so that a large number of V-shaped pits of different sizes and relatively randomly distributed can be formed; the subsequent steps are the same as in the first embodiment. .
  • the present invention does not require epitaxial extension, does not require secondary epitaxy, and simplifies the fabrication process;
  • the semipolar plane is a (1-101) crystal plane family, a smooth conduction band bottom and a valence band. The top overlaps in the inverted space
  • the radiation recombination efficiency is greatly increased; the bareness of the semi-polar surface is adjusted by the material growth process, and the semi-polar surface material is prepared without being controlled by the substrate geometry, and the operability is high and the cost is low.
  • the embodiment provides a method for fabricating a GaN semi-polar LED epitaxial structure, which can avoid the problem that the semi-polar material does not grow well and the homogenous semi-polar material is expensive.
  • the following technical scheme takes a nano sapphire pattern substrate as an example, and the manufacturing method includes the following steps:
  • a nano-patterned sapphire substrate 31 (Sapphire) is provided and placed in a metal organic chemical vapor deposition (MOCVD) apparatus to raise the temperature to 1000 to 1200 ° C, and to treat 3 to 10 in a hydrogen atmosphere. Minutes; a regular surface V-pit (pit) array can be obtained using a nano-patterned Sapphire Substrate (PSS).
  • the pattern diameter of the PSS is 100-1000 nm, the height of the pattern is 300 20 OOnm, and the pitch is periodic.
  • the pattern under this size does not affect the existing chip process to prepare the chip, that is, it does not affect the lithography process such as subsequent chip electrode preparation, if the pattern wire size is too small ( ⁇ 10 Onm)
  • the V-shaped pit is small, the low-temperature functional layers deposited on the bottom of the V-shaped pit overlap, and the superimposed part is not well illuminated.
  • the overlapping part occupies a relatively high proportion of the inner wall of the entire V-shaped pit, which affects the luminous efficiency of the device, so the size should not be too Small, if the pattern wire size is too large (>1000nm), the epitaxial structure and the existing chip process are reduced in degree of fusion, and it is not easy to make LED devices; corresponding to the protrusion (island) of each PSS, the density of V-pits It can be adjusted by the pattern density of the graphic substrate.
  • the pattern density of the patterned substrate is determined, the density of the V-shaped pit is the same, and the size of each V-shaped pit is also determined. The diameter of the V-shaped pit is determined.
  • semi-polar surface LEDs can also be obtained by using a planar substrate.
  • the surface V-pits are different in size and relatively randomly distributed, but the density is affected by the thickness of the buffer layer and the annealing conditions of the buffer layer: Thick, the lower the annealing temperature, the shorter the annealing time, the higher the island density, the greater the density of the subsequent V-pits; and vice versa.
  • the epitaxial growth method can also use CVD (chemical vapor deposition) method, PECVD (plasma enhanced chemical vapor deposition) method, MBE (molecular beam epitaxy) Method, HVPE (Hydride Vapor Phase Epitaxy) Method, This embodiment is preferably MOCVD, but is not limited thereto.
  • a semiconductor underlayer structure having a V-shaped pit is epitaxially grown on the low temperature buffer layer 32.
  • the side surface 17 of the V-shaped pit is a semipolar plane corresponding to the (1-101) crystal plane family, specifically Heating to 870 ⁇ 970 °C, annealing at this temperature for 5 seconds to 2 minutes, then introducing trimethylgallium, growing non-tacky gallium nitride 33 (first uGaN layer) with a thickness of 1 ⁇ 2 ⁇ ,
  • This layer is called a three-dimensional mode GaN growth layer; the growth temperature is controlled within 1 050 ° C, the chamber pressure is 500 torr, and the growth rate is controlled at 3 ⁇ /1 ⁇ or more.
  • the V-shaped pit can occupy the entire On the epitaxial surface, the C-face completely disappears, and the V-shaped pit can also partially occupy most of the surface.
  • the temperature is controlled within 1100 ° C, the chamber pressure is 300 torr, and the non-tacky gallium nitride 34 (second uGaN layer) having a thickness of 1 to 2 ⁇ m is grown, and the layer is called a two-dimensional mode.
  • the temperature is lowered to about 1050 ° C, the chamber pressure is 300 torr, and the gallium nitride having a thickness of 1.5 to 4 ⁇ m is grown, and silane is implanted to form a germanium-type gallium nitride 35 (nGaN layer); It is also possible to grow a uGaN/nGa N superlattice instead of the completely cumbersome nGaN to provide electron injection; the growth rate is controlled to be above 5 ⁇ / 1 ⁇ ; after the growth of nG aN is completed, the epitaxial surface is completely filled by the nano V-shaped pit.
  • the semiconductor functional layer 36 is continuously grown on the surface of the semiconductor underlying structure forming the nano V-pit.
  • the embodiment is preferably a GaN-based semiconductor material, and the structural layer is SLs/MQWs/pAlGaN/pGaN/p++ as a function. Floor.
  • the InGaN/GaN superlattice layer (SLs) is cooled to 770-870 ° C and grown for 15 to 30 cycles.
  • the thickness of InGaN ranges from 1 to 3 nm in each cycle, and the thickness of GaN ranges from 2.5 to 8 nm.
  • the superlattice layer acts as a low temperature stress release layer and exerts a stress release effect; since the epitaxial deposition rate on the semipolar surface is only 1/10 to 1/5 of the polar surface, the preparation is equivalent to the conventional method (polar surface growth).
  • the epitaxial layer the growth rate on the semi-polar surface can be accelerated by 5 to 10 times by adjusting the gas flow rate or prolonging the growth period to 5 to 10 times of the conventional time; the temperature is controlled between 750 and 900 ° C, continue InGaN/GaN multiple quantum well layers (MQWs) with 5 ⁇ 15 cycles are grown as light-emitting layers; growth rate is treated with low-temperature stress-relieving layer (InGaN/GaN superlattice layer); temperature is controlled at 800 ⁇ 950° Between C, growth p type AlGaN electron blocking layer (pAlGaN), blocking electron expansion; growth rate in the same way as low temperature stress relief layer; heating to 900 ⁇ 1050 °C, growing p-type GaN
  • the p-type GaN layer and the heavily p-type GaN contact layer (p+ +) are different from the p-type layer of the conventional C-plane LED, and the p-type layer growth of the conventional C-side LED is large.
  • Hydrogen has the function of filling the V-shaped pit.
  • the pGaN of this embodiment is grown under nitrogen conditions or a small amount of hydrogen is grown to avoid filling the V-shaped pit.
  • an LED epitaxial structure provided in this embodiment includes, in order from bottom to top, a sapphire substrate 31, a buffer layer 32, and a first u-GaN layer 33 and a second u-GaN layer 34.
  • the sapphire substrate 31 of the embodiment may be a patterned sapphire substrate (PSS, Patterned Sapphire Substrate) or a flat sapphire substrate (FSS, Flat Sapphire).
  • PSS patterned sapphire substrate
  • FSS Flat Sapphire
  • this embodiment preferably has a PSS substrate with a pattern diameter of 100 to 1000 nm, a pattern height of 300 to 2000 nm, and a pitch of 1/5 to 1/2 of the period size.
  • the pattern at this size does not affect the existing chip process.
  • the chip is prepared, that is, the lithography process such as the subsequent chip electrode preparation is not affected. If the pattern wire diameter is too small ( ⁇ lOOnm), the V-shaped pit is small, and the low-temperature functional layers deposited at the bottom of the V-pit are overlapped, and the superimposed portion is overlapped.
  • the overlapping part occupies a relatively high proportion of the inner wall of the entire V-shaped pit, which affects the luminous efficiency of the device, so the size should not be too small. If the pattern wire size is too large (>1000nm), the epitaxial structure and the existing chip process The degree of integration is reduced and it is not easy to make LED devices.
  • the buffer layer 32 is made of an AlInGaN semiconductor material and formed on the sapphire substrate 31 to reduce lattice mismatch caused by a difference in lattice constant between the sapphire substrate 31 and the first conductive type semiconductor layer. Epitaxial growth quality.
  • a semiconductor underlayer structure having a nano V-shaped pit is formed on the buffer layer 32, wherein the semiconductor underlayer structure includes, in order from bottom to top, a non-tacky gallium nitride 33 (first uGaN layer) having a thickness of 1 to 2 ⁇ m, 1 ⁇ 2 ⁇ Non-tideous gallium nitride 34 (second uGaN layer) and 1.5 ⁇ 4 ⁇ thick N-type gallium nitride 35 (nGaN layer), nano V-shaped pits are formed on the surface of each structural layer, and the side of the V-shaped pit is a half pole Sexual surface, corresponding to the (1-101) crystal face family, the V-shaped pit has a wire diameter of 100 to 1000 nm.
  • SLs, MQWs, pAlGaN, pGaN, p++ constitute a semiconductor functional layer 36, which is sequentially formed on the nGaN surface of the nano V-pit, and the surface of the semiconductor functional layer 36 is obtained with a corresponding nano V-pit, and the epitaxial structure thus formed remains It can be integrated with the existing chip process, and the structure has a surface roughening effect, and the light extraction efficiency is relatively high.
  • the difference between this embodiment and Embodiment 4 is that: the surface of the semiconductor functional layer 36 of Embodiment 4 has a nano V-pit, and the semiconductor functional layer 46 of the present embodiment includes the first semiconductor functional layer 461. And a second semiconductor functional layer 462, wherein the first semiconductor functional layer 461 comprises SLs, MQWs, and pAlGaN, and the growth method is the same as in Embodiment 4, that is, by increasing the growth rate on the semipolar plane to 5 to 10 times of the conventional polar surface Or extending the growth period to 5 to 10 times of the regular polar surface to obtain a nano V-pit on the surface of the first semiconductor functional layer; the second semiconductor functional layer 462 includes pGaN and p++, using a conventional p-type GaN growth mode ( The growth temperature is around 950 ° C, a large amount of H 2 is introduced , which is expressed as a two-dimensional mode growth, and the surface of the nano V-shaped pit in which the first semiconductor functional layer is grown is
  • the difference between this embodiment and Embodiment 4 is that: the three-dimensional mode grown first uGaN layer of the nano-patterned sapphire substrate (PSS) in Embodiment 4 is between the sapphire patterns (at the interval) A two-dimensional film is formed, and a nano V-shaped pit is formed on the top of the pattern; in this embodiment, after the buffer layer 52 is deposited on the flat sapphire substrate (FSS) 5 1 , the temperature is raised to 990 to 1000 ° C, and the temperature is raised at this temperature.
  • PSS nano-patterned sapphire substrate
  • the density of the nano-V-pits has a direct corresponding relationship with the sapphire pattern period; and the nano-V-pit density on the flat-plate sapphire substrate depends on the growth conditions of the buffer layer, and is controlled by There are a large number of random nano-V-shaped pits of different sizes in growth temperature and velocity. The diameter of the V-shaped pits conforms to the normal distribution.
  • V-shaped pits such as less than 100 nm
  • the luminous efficiency is weak
  • some oversized V-shaped pits such as about 100 Onm
  • the difference between this embodiment and the embodiment 6 is that the sapphire substrate 41 of the embodiment 6 is a patterned sapphire substrate (PSS), and the sapphire substrate 61 of the embodiment is a plain sapphire lining. Bottom (FSS).
  • PSS patterned sapphire substrate
  • FSS plain sapphire lining. Bottom
  • the present invention controls the size/distribution of the V-shaped pit by controlling the growth conditions of the underlying structure, and is matched with the subsequent semiconductor functional layer design, and is integrated with the conventional chip process, without the need for epitaxy or quadratic Epitaxy, simplifying the manufacturing process; semi-polar surface is (1-101) crystal plane family, smooth conduction band bottom and valence band top have large overlap area in inverted space, radiation compounding efficiency is greatly increased; adjustment by material growth process The bareness of the semi-polar surface is realized, and the semi-polar surface material is prepared without being made into the substrate geometry, and the operability is strong and the cost is low.

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Abstract

一种半极性LED外延结构及其制作方法，包括工艺步骤：提供一蓝宝石衬底（11）；在该蓝宝石衬底上生长半导体底层结构（14和15），使得其表面形成V型坑，V型坑的侧面（17）为半极性面，对应(1-101)晶面族；在该半导体底层结构的半极性面上生长半导体功能层（16）。不需要选区外延，不需要二次外延，简化制作工艺流程；半极性面为(1-101)晶面族，平滑的导带底和价带顶在倒空间交叠面积很大，辐射复合效率大大增加；通过材料生长工艺调节实现半极性面的裸露，而不受制于衬底几何形状，实现制备半极性面材料，可操作性强，成本低廉。

Description

说明书 发明名称：一种半极性 LED结构及其制备方法 技术领域
[0001] 本发明涉及半导体光电器件领域， 尤其涉及一种半极性 LED结构及其制备方法 背景技术
[0002] LED是一种半导体固体发光器件， 其利用半导体 PN结作为发光材料， 可以直接 将电转换为光。 目前， 极性 GaN基 LED技术产业化已经 20余年， 发展至今其性能 取得了极大的改善； 但是也逐渐显现出了极性 LED的性能瓶颈， 光电转换效率达 到 60%之后很难再有大幅的继续提升。 目前， 普遍认为极性 LED器件有难以克服 的极化效应， 从而影响着 LED的发光效率。 关于半极性和非极性材料和器件的研 究和文献报道近些年非常多， 主要存在的问题是在半极性面或者非极性面上生 长 GaN材料比较困难。
[0003] 半极性和非极性 GaN材料的获得一般有两种常见的方式： 一是通过非极性和半 极性的蓝宝石获得半极性或者非常 GaN薄膜； 二是通过切割同质衬底的半极性和 非极性面同质外延出相应的器件。 第一种技术路线较难获得比较好的材料质量 ； 第二种技术路线虽能获得较高的材料质量， 但是成本很高。 此外， 还有一种 工艺相对复杂的技术是通过选区外延来实现半极性面或者非极性面的生长， 然 后在这些原位生长出来的半极性面上生长制备半极性或者非极性器件； 工艺相 对复杂， 往往需要一些辅助材料和二次外延生长工艺设计。 由此来看， 半极性 和非极性 LED路线的主要障碍就在于如何获得高质量材料。
技术问题
问题的解决方案
技术解决方案
[0004] 本发明的目的在于： 提供一种 C面蓝宝石衬底原位生长制备半极性 LED外延结 构及其制备方法， 利用蓝宝石平面或者图形衬底在外延生长过程中可以控制半 导体底层结构表面形成 V型坑 （包括纳米 V型坑） ， 进而在 V型坑的侧面制备半 导体功能层， 最终获得半极性 LED外延结构。
[0005] 本发明的第一方面， 提供一种半极性 LED外延结构， 该外延结构从下至上依次 包括： 蓝宝石衬底、 半导体底层结构以及半导体功能层， 其特征在于： 所述半 导体底层结构表面具有 V型坑， V型坑的侧面为半极性面， 对应 (1-101)晶面族。
[0006] 优选地， 所述蓝宝石衬底为图形化蓝宝石衬底或者平片蓝宝石衬底。
[0007] 优选地， 所述蓝宝石衬底为图形化蓝宝石衬底， 其图形密度与所述 V型坑的密 度一致。
[0008] 优选地， 所述半导体底层结构包括缓冲层或 uGaN层或 nGaN层或前述任意组合 [0009] 优选地， 所述半导体功能层材料包括 GaN系半导体材料。
[0010] 本发明的第二方面， 还提供一种半极性 LED外延结构的制作方法， 包括以下工 艺步骤：
[0011] (1) 提供一蓝宝石衬底；
[0012] (2) 在所述蓝宝石衬底上生长半导体底层结构， 使得其表面形成 V型坑， V型 坑的侧面为半极性面， 对应 (1-101)晶面族；
[0013] (3) 在所述半导体底层结构上生长半导体功能层。
[0014] 优选地， 所述蓝宝石衬底为图形化蓝宝石衬底或者平片蓝宝石衬底。
[0015] 优选地， 所述 V型坑的密度通过图形化蓝宝石衬底的图形密度来调节。
[0016] 优选地， 所述半导体底层结构包括缓冲层或 uGaN层或 nGaN层或前述任意组合
[0017] 优选地， 所述步骤 （2) 通过控制生长温度比较低 （1100°C以内） ， 生长速率 比较快 （3μηι/1ι以上） ， 使得半导体底层结构表面形成 V型坑。
[0018] 优选地， 所述步骤 （3) 在半极性面上生长速率加快至常规极性面的 5~10倍或 者延长生长吋间至常规极性面的 5~10倍。
[0019] 优选地， 所述半导体功能层材料包括 GaN系半导体材料。
[0020] 本发明的第三方面， 再提供一种半极性 LED外延结构， 该外延结构从下至上依 次包括： 蓝宝石衬底、 半导体底层结构以及半导体功能层， 其特征在于： 所述 半导体底层结构表面具有纳米 V型坑， V型坑的侧面为半极性面， 对应 (1-101)晶 面族。
[0021] 优选地， 所述蓝宝石衬底为纳米图形化蓝宝石衬底或者平片蓝宝石衬底。
[0022] 优选地， 所述蓝宝石衬底为纳米图形化蓝宝石衬底， 所述纳米 V型坑的线径尺 寸为 100~1000nm。
[0023] 优选地， 所述蓝宝石衬底为平片蓝宝石衬底， 所述纳米 V型坑的线径尺寸符合 正态分布， 正态分布的峰值尺寸对应于 550±10nm。
[0024] 优选地， 所述半导体底层结构包括缓冲层或 uGaN层或 nGaN层或前述任意组合
[0025] 优选地， 所述半导体功能层材料包括 GaN系半导体材料。
[0026] 优选地， 所述半导体功能层包括第一半导体功能层和第二半导体功能层， 其中 第一半导体功能层表面具有纳米 V型坑。
[0027] 本发明的第四方面， 又提供一种半极性 LED外延结构的制作方法， 包括以下工 艺步骤：
[0028] (1) 提供一蓝宝石衬底；
[0029] (2) 在所述蓝宝石衬底上生长半导体底层结构， 使得其表面形成纳米 V型坑，
V型坑的侧面为半极性面， 对应 (1-101)晶面族；
[0030] (3) 在所述半导体底层结构上生长半导体功能层。
[0031] 优选地， 所述蓝宝石衬底为纳米图形化蓝宝石衬底或者平片蓝宝石衬底。
[0032] 优选地， 所述 V型坑的密度通过纳米图形化蓝宝石衬底的图形密度来调节。
[0033] 优选地， 所述蓝宝石衬底为纳米图形化蓝宝石衬底， 所述纳米 V型坑的线径尺 寸为 100~1000nm。
[0034] 优选地， 所述蓝宝石衬底为平片蓝宝石衬底， 所述纳米 V型坑的线径尺寸符合 正态分布， 正态分布的峰值尺寸对应于 550±10nm。
[0035] 优选地， 所述半导体底层结构包括缓冲层或 uGaN层或 nGaN层或前述任意组合
[0036] 优选地， 所述步骤 （2) 通过控制生长温度比较低 （1100°C以内） ， 生长速率 比较快 （3μηι/1ι以上） ， 使得半导体底层结构表面形成纳米 V型坑。
[0037] 优选地， 所述半导体功能层材料包括 GaN系半导体材料。 [0038] 优选地， 所述半导体功能层包括第一半导体功能层和第二半导体功能层， 其中 第一半导体功能层表面具有纳米 V型坑。
[0039] 优选地， 所述第一半导体功能层的纳米 V型坑是通过在半极性面上生长速率加 快至常规极性面的 5~10倍或者延长生长吋间至常规极性面的 5~10倍获得。
发明的有益效果
有益效果
[0040] 相对于现有技术， 常规的极性面 （001) 面的 LED外延结构的导带和价带由于 极化电场的存在而弯曲， 导致导带底和价带顶倒空间不在同一个位置， 类似变 成间接带隙半导体发光 （AlInGaN体系材料为直接带隙发光材料） ， 辐射复合发 光效率降低， 非辐射复合概率增加， 本发明至少包括以下技术效果：
[0041] (1) 不需要选区外延， 不需要二次外延， 简化制作工艺流程；
[0042] (2) 半极性面为 (1-101)晶面族， 平滑的导带底和价带顶在倒空间交叠面积很 大， 辐射复合效率大大增加；
[0043] (3) 通过材料生长工艺调节实现半极性面的裸露， 而不受制于衬底几何形状 ， 实现制备半极性面材料， 可操作性强， 成本低廉。
[0044] (4) 在具有纳米 V型坑的半导体底层结构表面形成半导体功能层， 如此获得的 外延结构可以与现有的芯片制程相融合， 便于制作 LED芯片等半导体发光器件。 对附图的简要说明
附图说明
[0045] 附图用来提供对本发明的进一步理解， 并且构成说明书的一部分， 与本发明实 施例一起用于解释本发明， 并不构成对本发明的限制。 此外， 附图数据是描述 概要， 不是按比例绘制。
[0046] 图中标示： 11， 21， 31， 41， 51， 61： 蓝宝石衬底； 12， 22， 32， 42， 52， 62 ： 缓冲层； 13， 23， 33， 43， 53， 63： 第一 uGaN层； 14， 24， 34， 44， 54， 64 ： 第二 uGaN层； 15， 25， 35， 45， 55， 65： nGaN层； 16， 26， 36， 46， 56， 66 ： 半导体功能层； 17， 27， 37， 47， 57， 67： V型坑的侧面 （对应 (1-101)晶面族
) ； 461： 661： 第一半导体功能层； 462: 662： 第二半导体功能层。
[0047] 图 1~图5为本发明实施例 1、 2制作的 LED外延结构的剖视示意图。 [0048] 图 6为本发明实施例 3制作的 LED外延结构的剖视示意图。
[0049] 图 7~图11为本发明实施例 4、 5制作的 LED外延结构的剖视示意图。
[0050] 图 12为本发明实施例 6制作的 LED外延结构的剖视示意图。
[0051] 图 13为本发明实施例 7制作的 LED外延结构的剖视示意图。
[0052] 图 14为本发明实施例 8制作的 LED外延结构的剖视示意图。
本发明的实施方式
[0053] 下面结合示意图对本发明进行详细的描述， 在进一步介绍本发明之前， 应当理 解， 由于可以对特定的实施例进行改造， 因此， 本发明并不限于下述的特定实 施例。 还应当理解， 由于本发明的范围只由所附权利要求限定， 因此所采用的 实施例只是介绍性的， 而不是限制性的。 除非另有说明， 否则这里所用的所有 技术和科学用语与本领域的普通技术人员所普遍理解的意义相同。
[0054] 实施例 1
[0055] 请参照图 1~图5， 本实施例提供一种 GaN半极性 LED外延结构的制作方法， 可 以规避半极性材料不好生长以及同质半极性材料价格昂贵的问题。 以下技术方 案以蓝宝石图形衬底为例， 制作方法包括以下步骤：
[0056] 请参照图 1， 提供一蓝宝石衬底 11 (Sapphire) ， 并放入金属有机化学气相沉积 (MOCVD)设备中升温至 1000~1200°C， 在氢气氛围下处理 3~10分钟； 使用图形化 蓝宝石衬底 （PSS) 可以获得规则的表面 V型坑 （凹坑） 阵列， 对应于每一个图 形化衬底的凸起 （岛） ， V型坑的密度可以通过图形衬底的图形密度来调节， 当 图形化衬底的图形密度确定后， V型坑的密度与之相同， 每个 V型坑的大小也随 之确定， 即 PSS图形密度与所述 V型坑的密度保持一致； 使用平面蓝宝石衬底 （F SS) 也可以获得半极性面 LED, 其表面 V型坑的大小不一且相对随机分布， 但是 密度受到缓冲层厚度和缓冲层退火条件的影响： 缓冲层越厚， 退火温度越低， 退火吋间越短， 岛密度越高， 后续 V型坑密度越大； 反之亦然。 降温至 500~600 °C， 通入氨气和三甲基镓， 生长 20~50nm的 AlInGaN低温缓冲层 12 (buffer) ， 起 到应力释放的作用， 然后关闭三甲基镓； 其中外延生长方法还可以选用 CVD ( 化学气相沉积） 方法、 PECVD (等离子体增强化学气相沉积） 方法、 MBE (分 子束外延） 方法、 HVPE (氢化物气相外延） 方法， 本实施例优选 MOCVD, 但 不限于此。
[0057] 请参照图 2， 在低温缓冲层 12上外延生长具有 V型坑的半导体底层结构， V型坑 的侧面 17为半极性面， 对应 (1-101)晶面族， 具体来说， 升温至 1000~1100°C， 在 此温度下进行退火处理 1~5分钟， 然后通入三甲基镓， 生长 1~2μηι厚度的非惨杂 氮化镓 13 (第一 uGaN层） ， 该层称为三维模式的 GaN生长层； 生长温度控制在 1 050°C以内， 腔室压力为 500torr， 生长速率控制在 3μη /1ι以上， 可以获得大量 V型 坑， V型坑可以占据整个外延表面， C面完全消失， V型坑也可以部分占据表面 ， 本实施例优选 V型坑占据整个外延表面， 无 C面。
[0058] 请参照图 3， 温度控制在 1100°C以内， 腔室压力为 300torr， 生长 1~2μηι厚的非惨 杂氮化镓 14 (第二 uGaN层） ， 该层称为二维模式的 GaN生长层； 生长速率控制 在 4μη /1ι以上， V型坑占据整个表面。
[0059] 请参照图 4， 降温至 1050°C左右， 腔室压力为 300torr， 生长 1.5~4μηι厚的氮化镓 ， 通入硅烷进行惨杂， 形成 Ν型氮化镓 15 (nGaN层） ； 也可以生长 uGaN/nGaN 超晶格代替完全惨杂的 nGaN， 提供电子注入； 生长速率控制在 5μη /1ι以上； nGa N生长结束之后， 外延表面被 V型坑全部占满。
[0060] 请参照图 5， 在形成 V型坑的半导体底层结构表面上继续生长半导体功能层， 本 实施例优选 GaN系半导体材料， 结构层为 SLs/MQWs/pAlGaN/pGaN/p++作为功能 层。 具体来说， 降温至 770~870°C， 生长 15~30个周期的 InGaN/GaN超晶格层 （S Ls) ， 每个周期内 InGaN的厚度范围 l~3nm， GaN厚度范围 2.5~8nm， 该超晶格 层作为低温应力释放层， 发挥应力释放作用； 由于半极性面上的外延沉积速率 只有极性面的 1/10~1/5， 制备与常规方式 （极性面生长） 相当厚度的外延层， 在 半极性面上的生长速率可以通过调整源气体流量等方式加快 5~10倍或者延长生 长吋间至常规的 5~10倍； 温度控制在 750~900°C之间， 继续生长 5~15个周期的 In GaN/GaN多量子阱层 （MQWs) ， 作为发光层； 生长速率方面同低温应力释放 层 （InGaN/GaN超晶格层） 的处理方式； 温度控制在 800~950°C之间， 生长 p型 A1 GaN电子阻挡层 （pAlGaN) ， 阻挡电子扩充； 生长速率方面同低温应力释放层 的处理方式； 升温至 900~1050°C， 生长 p型 GaN层 （pGaN) ， 提供空穴注入， 生 长速率方面同低温应力释放层 （InGaN/GaN超晶格层） 的处理方式； 在 900~1050 °C下， 生长重惨杂 p型 GaN接触层 （p++) ， 更易于后续制作 LED器件常用的透明 电极 （如 ITO) 形成欧姆接触， 生长速率方面同低温应力释放层 （InGaN/GaN超 晶格层） 的处理方式。 需要强调的是， p型 GaN层和重惨杂 p型 GaN接触层 （p++ ) 要采用和常规 C面 LED的 p型层不同的生长条件， 常规 C面 LED的 p型层生长通 入大量氢气， 具有填充 （填平） V型坑的作用， 本实施例的 pGaN要采用氮气条 件生长或者少量氢气生长， 避免填平 V型坑。
[0061] 实施例 2
[0062] 请参照图 5， 本实施例提供的一种 LED外延结构， 从下至上依次包括： 蓝宝石 衬底 11、 缓冲层 12、 包括第一 u-GaN层 13和第二 u-GaN层 14、 nGaN层 15的具有 V 型坑的半导体底层结构以及包括 SLs/MQWS/pAlGaN/pGaN/p++的半导体功能层 1
6。
[0063] 具体来说， 本实施例的蓝宝石衬底 11， 可以是图形化蓝宝石衬底 (PSS , Patter ned Sapphire Substrate) ， 也可以是平片蓝宝石衬底 （FSS， Flat Sapphire
Substrate) ， 本实施例优选 PSS衬底， 特征尺寸 （周期） 限定范围为 1~10μηι， 但 不限于此。
[0064] 缓冲层 12材质选用 AlInGaN半导体材料， 形成在蓝宝石衬底 11上， 以减少由于 蓝宝石衬底 11和第一导电类型半导体层之间的晶格常数差而导致的晶格错配， 改善外延生长质量。
[0065] 具有 V型坑的半导体底层结构， 形成于缓冲层 12上， 其中半导体底层结构从下 至上依次包括： 1~2μηι厚度的非惨杂氮化镓 13 (第一 uGaN层） 、 1~2μηι厚的非 惨杂氮化镓 14 (第二 uGaN层） 以及 1.5~4μηι厚的 N型氮化镓 15 (nGaN层） ， 各 结构层表面上形成 V型坑， V型坑的侧面为半极性面， 对应 (1-101)晶面族。
[0066] SLs、 MQWs、 pAlGaN、 pGaN、 p++构成半导体功能层 16， 依次形成于 V型坑 的 nGaN表面上。
[0067] 实施例 3
[0068] 请参照图 6， 本实施例与实施例 1的区别在于： 实施例 1中的图形化蓝宝石衬底 的三维模式生长的第一 uGaN层 13在蓝宝石图形之间 （间距处） 形成二维薄膜， 而图形顶部形成 V型坑； 而本实施例是在平片蓝宝石衬底上沉积缓冲层 22之后， 升温至 1000~1100°C， 在此温度下进行退火处理 1~5分钟， 利用蓝宝石衬底表面 的成核岛 （图中未示出） 作为第一uGaN层 23的成核中心， 采用三维模式生长， 从而可以形成大量大小不一且相对随机分布的 V型坑； 后续步骤同实施例 1。
[0069] 综上实施例所述， 本发明不需要选区外延， 不需要二次外延， 简化制作工艺流 程； 半极性面为 (1-101)晶面族， 平滑的导带底和价带顶在倒空间交叠面积很大
， 辐射复合效率大大增加； 通过材料生长工艺调节实现半极性面的裸露， 而不 受制于衬底几何形状， 实现制备半极性面材料， 可操作性强， 成本低廉。
[0070] 实施例 4
[0071] 请参照图 7~图12， 本实施例提供一种 GaN半极性 LED外延结构的制作方法， 可 以规避半极性材料不好生长以及同质半极性材料价格昂贵的问题。 以下技术方 案以纳米蓝宝石图形衬底为例， 制作方法包括以下步骤：
[0072] 请参照图 7， 提供一纳米图形化蓝宝石衬底 31 (Sapphire) ， 并放入金属有机化 学气相沉积 (MOCVD)设备中升温至 1000~1200°C， 在氢气氛围下处理 3~10分钟； 使用纳米图形化蓝宝石衬底 (PSS , Patterned Sapphire Substrate) 可以获得规则 的表面 V型坑 （凹坑） 阵列， PSS的图形线径为 100~1000nm， 图形高度为 300 20 OOnm, 间距为周期尺寸的 1/5~1/2， 该尺寸下的图案不影响现有芯片制程制备芯 片， 也即不影响后续芯片电极制备等光刻工艺， 如果图形线径尺寸过小吋 （<10 Onm) ， V型坑很小， V型坑底部沉积的低温功能层有交叠， 叠加部分发光不好 ， 交叠的部分占据整个 V型坑的内壁比例比较高， 影响器件发光效率， 所以尺寸 不宜太小， 如果图形线径尺寸过大吋 （>1000nm) ， 外延结构与现有芯片制程融 合度降低， 不易制作成 LED器件； 对应于每一个 PSS的凸起 （岛） ， V型坑的密 度可以通过图形衬底的图形密度来调节， 当图形化衬底的图形密度确定后， V型 坑的密度与之相同， 每个 V型坑的大小也随之确定， V型坑的线径尺寸为 100~10 OOnm; 使用平面衬底也可以获得半极性面 LED , 其表面 V型坑的大小不一且相对 随机分布， 但是密度受到缓冲层厚度和缓冲层退火条件的影响： 缓冲层越厚， 退火温度越低， 退火吋间越短， 岛密度越高， 后续 V型坑密度越大； 反之亦然。 降温至 500~600°C， 通入氨气和三甲基镓， 生长 20~50nm的 AlInGaN低温缓冲层 3 2 (buffer) ， 起到应力释放的作用， 然后关闭三甲基镓； 其中外延生长方法还可 以选用 CVD (化学气相沉积） 方法、 PECVD (等离子体增强化学气相沉积） 方 法、 MBE (分子束外延） 方法、 HVPE (氢化物气相外延） 方法， 本实施例优选 MOCVD, 但不限于此。
[0073] 请参照图 8， 在低温缓冲层 32上外延生长具有 V型坑的半导体底层结构， V型坑 的侧面 17为半极性面， 对应 (1-101)晶面族， 具体来说， 升温至 870~970°C， 在此 温度下进行退火处理 5秒~2分钟， 然后通入三甲基镓， 生长 1~2μηι厚度的非惨杂 氮化镓 33 (第一 uGaN层） ， 该层称为三维模式的 GaN生长层； 生长温度控制在 1 050°C以内， 腔室压力为 500torr， 生长速率控制在 3μη /1ι以上， 可以获得大量纳 米 V型坑， V型坑可以占据整个外延表面， C面完全消失， V型坑也可以部分占据 大部分表面， 本实施例优选纳米 V型坑占据整个外延表面， 无 C面。
[0074] 请参照图 9， 温度控制在 1100°C以内， 腔室压力为 300torr， 生长 1~2μηι厚的非惨 杂氮化镓 34 (第二 uGaN层） ， 该层称为二维模式的 GaN生长层； 生长速率控制 在 4μη /1ι以上， 纳米 V型坑占据整个表面。
[0075] 请参照图 10， 降温至 1050°C左右， 腔室压力为 300torr， 生长 1.5~4μηι厚的氮化 镓， 通入硅烷进行惨杂， 形成 Ν型氮化镓 35 (nGaN层） ； 也可以生长 uGaN/nGa N超晶格代替完全惨杂的 nGaN， 提供电子注入； 生长速率控制在 5μη /1ι以上； nG aN生长结束之后， 外延表面被纳米 V型坑全部占满。
[0076] 请参照图 11， 在形成纳米 V型坑的半导体底层结构表面上继续生长半导体功能 层 36， 本实施例优选 GaN系半导体材料， 结构层为 SLs/MQWs/pAlGaN/pGaN/p++ 作为功能层。 具体来说， 降温至 770~870°C， 生长 15~30个周期的 InGaN/GaN超晶 格层 （SLs) ， 每个周期内 InGaN的厚度范围 l~3nm， GaN厚度范围 2.5~8nm， 该 超晶格层作为低温应力释放层， 发挥应力释放作用； 由于半极性面上的外延沉 积速率只有极性面的 1/10~1/5， 制备与常规方式 （极性面生长） 相当厚度的外延 层， 在半极性面上的生长速率可以通过调整气体流量等方式加快 5~10倍或者延 长生长吋间至常规的 5~10倍； 温度控制在 750~900°C之间， 继续生长 5~15个周期 的 InGaN/GaN多量子阱层 （MQWs) ， 作为发光层； 生长速率方面同低温应力释 放层 （InGaN/GaN超晶格层） 的处理方式； 温度控制在 800~950°C之间， 生长 p型 AlGaN电子阻挡层 （pAlGaN) ， 阻挡电子扩充； 生长速率方面同低温应力释放 层的处理方式； 升温至 900~1050°C， 生长 p型 GaN层 （pGaN) ， 提供空穴注入， 生长速率方面同低温应力释放层 （InGaN/GaN超晶格层） 的处理方式； 在 900 10 50°C下， 生长重惨杂 p型 GaN接触层 （p++) ， 更易于后续制作 LED器件常用的透 明电极 （如 ITO) 形成欧姆接触， 生长速率方面同低温应力释放层 （InGaN/GaN 超晶格层） 的处理方式。 需要强调的是， p型 GaN层和重惨杂 p型 GaN接触层 （p+ +) 要采用和常规 C面 LED的 p型层不同的生长条件， 常规 C面 LED的 p型层生长 通入大量氢气， 具有填充 V型坑的作用， 本实施例的 pGaN要采用氮气条件生长 或者少量氢气生长， 避免填充 V型坑。
[0077] 实施例 5
[0078] 请参照图 11， 本实施例提供的一种 LED外延结构， 从下至上依次包括： 蓝宝石 衬底 31、 缓冲层 32、 包括第一 u-GaN层 33和第二 u-GaN层 34、 nGaN层 35的具有纳 米 V型坑的半导体底层结构、 包括 SLs/MQWs/pAlGaN/pGaN/p++的半导体功能层 36以及电极结构 （图中未示出） 。
[0079] 具体来说， 本实施例的蓝宝石衬底 31， 可以是图形化蓝宝石衬底 (PSS , Patter ned Sapphire Substrate) ， 也可以是平片蓝宝石衬底 （FSS， Flat Sapphire
Substrate) ， 本实施例优选 PSS衬底， 图形线径为 100~1000nm， 图形高度为 300~ 2000nm, 间距为周期尺寸的 1/5~1/2， 该尺寸下的图案不影响现有芯片制程制备 芯片， 也即不影响后续芯片电极制备等光刻工艺， 如果图形线径尺寸过小吋 （< lOOnm) ， V型坑很小， V型坑底部沉积的低温功能层有交叠， 叠加部分发光不 好， 交叠的部分占据整个 V型坑的内壁比例比较高， 影响器件发光效率， 所以尺 寸不宜太小， 如果图形线径尺寸过大吋 （>1000nm) ， 外延结构与现有芯片制程 融合度降低， 不易制作成 LED器件。
[0080] 缓冲层 32材质选用 AlInGaN半导体材料， 形成在蓝宝石衬底 31上， 以减少由于 蓝宝石衬底 31和第一导电类型半导体层之间的晶格常数差而导致的晶格错配， 改善外延生长质量。
[0081] 具有纳米 V型坑的半导体底层结构， 形成于缓冲层 32上， 其中半导体底层结构 从下至上依次包括： 1~2μηι厚度的非惨杂氮化镓 33 (第一 uGaN层） 、 1~2μηι厚 的非惨杂氮化镓 34 (第二 uGaN层） 以及 1.5~4μηι厚的 N型氮化镓 35 (nGaN层） ， 各结构层表面上形成纳米 V型坑， V型坑的侧面为半极性面， 对应 (1-101)晶面 族， V型坑的线径尺寸为 100~1000nm。
[0082] SLs、 MQWs、 pAlGaN、 pGaN、 p++构成半导体功能层 36， 依次形成于纳米 V 型坑的 nGaN表面上， 半导体功能层 36的表面获得相应的纳米 V型坑， 如此形成 的外延结构仍然可以与现有的芯片制程相融合， 而且， 该结构具有表面粗化效 应， 光提取效率会比较高。
[0083] 实施例 6
[0084] 请参照图 12， 本实施例与实施例 4的区别在于： 实施例 4的半导体功能层 36表面 具有纳米 V型坑， 而本实施例的半导体功能层 46包括第一半导体功能层 461和第 二半导体功能层 462， 其中第一半导体功能层 461包括 SLs、 MQWs以及 pAlGaN, 生长方法同实施例 4， 即通过在半极性面上生长速率加快至常规极性面的 5~10倍 或者延长生长吋间至常规极性面的 5~10倍从而在第一半导体功能层表面获得纳 米 V型坑； 第二半导体功能层 462包括 pGaN以及 p++， 采用常规的 p型 GaN的生长 模式 （生长温度在 950°C附近， 通入大量的 H 2， 表现为二维模式生长） ， 将生长 完第一半导体功能层的纳米 V型坑表面都填平， 如此则外延结构完全可以与常规 的芯片制程相融合。
[0085] 实施例 7
[0086] 请参照图 13， 本实施例与实施例 4的区别在于： 实施例 4中的纳米图形化蓝宝石 衬底 （PSS) 的三维模式生长的第一 uGaN层在蓝宝石图形之间 （间距处） 形成 二维薄膜， 图形顶部形成纳米 V型坑； 而本实施例是在平片蓝宝石衬底 （FSS) 5 1上沉积缓冲层 52之后， 升温至 990~1000°C， 在此温度下进行退火处理 5秒〜 5分 钟， 利用蓝宝石衬底表面的成核岛 （图中未示出） 作为第一 uGaN层 53的成核中 心， 采用三维模式生长， 从而可以形成大量大小不一且相对随机分布的纳米 V型 坑。 对于纳米蓝宝石图形衬底而言， 纳米 V型坑的密度和蓝宝石图形周期有直接 对应的关系； 而平片蓝宝石衬底上的纳米 V型坑密度， 则取决于缓冲层的生长条 件， 通过控制生长温度和速率可以存在大量随机的大小不一的纳米 V型坑， V型 坑的线径尺寸符合正态分布， 正态分布的峰值尺寸对应于 550±10nm， 部分过小 的 V型坑 （比如小于 lOOnm) ， 发光效率较弱； 部分过大的 V型坑 （比如大约 100 Onm) ， 会对芯片制程带来负面影响， 也影响了发光器件性能； 后续实施步骤同 实施例 4。
[0087] 实施例 8
[0088] 请参照图 14， 本实施例与实施例 6的区别在于： 实施例 6的蓝宝石衬底 41为图形 化蓝宝石衬底 （PSS) ， 本实施例的蓝宝石衬底 61为平片蓝宝石衬底 （FSS) 。
[0089] 综上实施例所述， 本发明通过控制底层结构的生长条件控制 V型坑的大小 /分布 ， 并搭配后续半导体功能层设计， 与常规芯片制程融合， 不需要选区外延或是 二次外延， 简化制作工艺流程； 半极性面为 (1-101)晶面族， 平滑的导带底和价 带顶在倒空间交叠面积很大， 辐射复合效率大大增加； 通过材料生长工艺调节 实现半极性面的裸露， 而不受制于衬底几何形状， 实现制备半极性面材料， 可 操作性强， 成本低廉。
[0090] 以上所述仅是本发明的优选实施方式， 应当指出， 对于本技术领域的普通技术 人员， 在不脱离本发明原理的前提下， 还可以做出若干改进和润饰， 这些改进 和润饰也应视为本发明的保护范围。

Claims

权利要求书
[权利要求 1] 一种半极性 LED外延结构， 从下至上依次包括： 蓝宝石衬底、 半导体 底层结构以及半导体功能层， 其特征在于： 所述半导体底层结构表面 具有 V型坑， V型坑的侧面为半极性面， 对应 (1-101)晶面族。
[权利要求 2] 根据权利要求 1所述的一种半极性 LED外延结构， 其特征在于： 所述 蓝宝石衬底为图形化蓝宝石衬底或者平片蓝宝石衬底。
[权利要求 3] 根据权利要求 1所述的一种半极性 LED外延结构， 其特征在于： 所述 蓝宝石衬底为图形化蓝宝石衬底， 其图形密度与所述 V型坑的密度一 致。
[权利要求 4] 根据权利要求 1所述的一种半极性 LED外延结构， 其特征在于： 所述 半导体底层结构包括缓冲层或 uGaN层或 nGaN层或前述任意组合。
[权利要求 5] 根据权利要求 1所述的一种半极性 LED外延结构， 其特征在于： 所述 半导体功能层材料包括 GaN系半导体材料。
[权利要求 6] —种半极性 LED外延结构的制作方法， 包括以下工艺步骤：
(1) 提供一蓝宝石衬底；
(2) 在所述蓝宝石衬底上生长半导体底层结构， 使得其表面形成 V 型坑， V型坑的侧面为半极性面， 对应 (1-101)晶面族；
(3) 在所述半导体底层结构的半极性面上生长半导体功能层。
[权利要求 7] 根据权利要求 6所述的一种半极性 LED外延结构的制作方法， 其特征 在于： 所述蓝宝石衬底为图形化蓝宝石衬底， V型坑的密度通过图形 化蓝宝石衬底的图形密度来调节。
[权利要求 8] 根据权利要求 6所述的一种半极性 LED外延结构的制作方法， 其特征 在于： 所述半导体底层结构包括缓冲层或 uGaN层或 nGaN层或前述任 意组合。
[权利要求 9] 根据权利要求 6所述的一种半极性 LED外延结构的制作方法， 其特征 在于： 所述步骤 （2) 通过控制生长温度比较低 （1100°C以内） ， 生 长速率比较快 （3μη /1ι以上） ， 使得半导体底层结构表面形成 V型坑
[权利要求 10] 根据权利要求 6所述的一种半极性 LED外延结构的制作方法， 其特征 在于： 所述步骤 （3) 在半极性面上生长速率加快至常规极性面的 5~1 0倍或者延长生长吋间至常规极性面的 5~10倍。
[权利要求 11] 一种半极性 LED外延结构， 从下至上依次包括： 蓝宝石衬底、 半导体 底层结构以及半导体功能层， 其特征在于： 所述半导体底层结构表面 具有纳米 V型坑， V型坑的侧面为半极性面， 对应 (1-101)晶面族。
[权利要求 12] 根据权利要求 11所述的一种半极性 LED外延结构， 其特征在于： 所述 蓝宝石衬底为纳米图形化蓝宝石衬底， 所述纳米 V型坑的线径尺寸为 100~1000nm。
[权利要求 13] 根据权利要求 11所述的一种半极性 LED外延结构， 其特征在于： 所述 蓝宝石衬底为平片蓝宝石衬底， 所述纳米 V型坑的线径尺寸符合正态 分布， 正态分布的峰值尺寸对应于 550±10nm。
[权利要求 14] 根据权利要求 11所述的一种半极性 LED外延结构， 其特征在于： 所述 半导体功能层包括第一半导体功能层和第二半导体功能层， 其中第一 半导体功能层表面具有纳米 V型坑。
[权利要求 15] —种半极性 LED外延结构的制作方法， 包括以下工艺步骤：
(1) 提供一蓝宝石衬底；
(2) 在所述蓝宝石衬底上生长半导体底层结构， 使得其表面形成纳 米 V型坑， V型坑的侧面为半极性面， 对应 (1-101)晶面族；
(3) 在所述半导体底层结构的半极性面上生长半导体功能层。
[权利要求 16] 根据权利要求 15所述的一种半极性 LED外延结构的制作方法， 其特征 在于： 所述蓝宝石衬底为纳米图形化蓝宝石衬底， V型坑的密度通过 纳米图形化蓝宝石衬底的图形密度来调节。
[权利要求 17] 根据权利要求 15所述的一种半极性 LED外延结构的制作方法， 其特征 在于： 所述蓝宝石衬底为纳米图形化蓝宝石衬底， 所述纳米 V型坑的 线径尺寸为 100~1000nm。
[权利要求 18] 根据权利要求 15所述的一种半极性 LED外延结构的制作方法， 其特征 在于： 所述蓝宝石衬底为平片蓝宝石衬底， 所述纳米 V型坑的线径尺 寸符合正态分布， 正态分布的峰值尺寸对应于 550±10nm。
[权利要求 19] 根据权利要求 15所述的一种半极性 LED外延结构的制作方法， 其特征 在于： 所述步骤 （2) 通过控制生长温度比较低 （1100°C以内） ， 生 长速率比较快 （3μη /1ι以上） ， 使得半导体底层结构表面形成纳米 V 型坑。
[权利要求 20] 根据权利要求 15所述的一种半极性 LED外延结构的制作方法， 其特征 在于： 所述半导体功能层包括第一半导体功能层和第二半导体功能层 ， 其中第一半导体功能层表面具有纳米 V型坑。
[权利要求 21] 根据权利要求 20所述的一种半极性 LED外延结构的制作方法， 其特征 在于： 所述第一半导体功能层的纳米 V型坑是通过在半极性面上生长 速率加快至常规极性面的 5~10倍或者延长生长吋间至常规极性面的 5~ 10倍获得。
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