Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L1/00—Arrangements for detecting or preventing errors in the information received
  • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

• Wireless mobile communication technology uses various standards and protocols to transmit data between a node (e.g., a transmission station) and a wireless device (e.g., a mobile device).
• Some wireless devices communicate using orthogonal frequency-division multiple access (OFDMA) in a downlink (DL) transmission and single carrier frequency division multiple access (SC-FDMA) in uplink (UL).
• OFDMA orthogonal frequency-division multiple access
• SC-FDMA single carrier frequency division multiple access
• OFDM orthogonal frequency-division multiplexing
• 3 GPP third generation partnership project
• LTE long term evolution
• IEEE Institute of Electrical and Electronics Engineers
• 702.16 standard e.g., 702.16e, 702.16m
• WiMAX Worldwide interoperability for Microwave Access
• IEEE 702.11 which is commonly known to industry groups as WiFi.
• the node can be a 3GPP radio access network (RAN) LTE systems.
• RAN radio access network
• E-UTRAN Evolved Universal Terrestrial Radio Access Network
• Node Bs also commonly denoted as evolved Node Bs, enhanced Node Bs, eNodeBs, or eNBs
• RNCs Radio Network Controllers
• UE user equipment
• the downlink (DL) transmission can be a
• the communication from the node (e.g., eNodeB) to the wireless device (e.g., UE), and the uplink (UL) transmission can be a communication from the wireless device to the node.
• the node e.g., eNodeB
• the wireless device e.g., UE
• the uplink (UL) transmission can be a communication from the wireless device to the node.
• FIGS. 1 A to 1H illustrate matrix prototypes corresponding to a coding rate of 8/9 and sub-block sizes of 12, 24, 36, 48, 60, 72, 84 and 96, respectively, in accordance with an example;
• FIG. 2 illustrates a technique for encoding information using a selected matrix prototype in accordance with an example
• FIG. 3 illustrates a technique for decoding information using a selected matrix prototype in accordance with an example
• FIG. 4 depicts functionality of a user equipment (UE) operable to encode information for transmission to an eNodeB in accordance with an example
• FIG. 5 depicts functionality of a user equipment (UE) operable to decode information received from an eNodeB in accordance with an example
• FIG 6 depicts a flowchart of a machine readable storage medium having instructions embodied thereon for encoding and decoding information at an eNodeB in accordance with an example
• FIG. 7 illustrates a diagram of a wireless device (e.g., UE) and a node (e.g., eNodeB) in accordance with an example
• FIG 8 illustrates a diagram of a wireless device (e.g., UE) in accordance with an example.
• Information can be transmitted from a transmitter to a receiver over a
• redundancy can be included in the transmission, and the redundancy can enable the receiver to accurately reconstruct original information despite the noise in the communication channel.
• the redundancy allows the receiver to detect a limited number of errors that can occur during transmission, and often to correct these errors without retransmission.
• a number of possible coding schemes can be used for determining an amount and nature of the redundancy to include in the transmitted information.
• the redundancy can be in the form of redundant bits, which are added to the transmitted information.
• the coding schemes can vary depending on the desired level of error correction, decoding complexity, the ability to locate/correct or recover from the errors, the ability to correct burst errors, and other various characteristics.
• a number of codes can be available for a particular coding scheme, wherein the codes can vary in terms of the number of information bits and the number of redundant bits (or sometimes also known as parity bits).
• the codes can be systematic or non-systematic. With respect to systematic codes, redundant bits can be added to, for example, the end of a stream of information bits. With respect to non-systematic codes, some or all of the information bits may not be present in a transmitted bit stream.
• the coding scheme and actual codes can be selected for use based on various criteria. For example, these criteria include an expected block error rate (BLER) of the transmission system, a desired BLER, an amount of transmission overhead associated with a particular code, an amount of processing to process the code, etc. In addition, a maximum fraction of errors (or missing bits that can be corrected) can be determined based on the coding scheme used, so different coding schemes can be suitable for different conditions.
• BLER block error rate
• a desired BLER an amount of transmission overhead associated with a particular code
• an amount of processing to process the code etc.
• a maximum fraction of errors can be determined based on the coding scheme used, so different coding schemes can be suitable for different conditions.
• LDPC codes are error correcting codes (i.e., codes that can be used for forward error correction or channel coding).
• the transmitter can encode data in a redundant manner using an LDPC code
• the receiver can decode the data using the LDPC decoding algorithm (e.g., belief propagation) such that any errors in the transmission are corrected.
• LDPC codes are parity check codes with a parity check matrix containing binary 0s and Is.
• the parity check matrix can be defined in terms of a matrix dimension (e.g., information block length and number of parity-checks), a number of Is per column, and a number of Is per row.
• the Is in the parity check matrix can be randomly distributed within the parity check matrix.
• the parity check matrix can be formed using submatrices having only a single 1 per column and per row.
• a number of parity check matrixes can be formed with varying block lengths by selecting different dimensions for the submatrices.
• LDPC codes can be used for 3GPP systems, such as fifth generation (5G) cellular systems.
• the LDPC codes can include parity check matrices that support a defined coding rate.
• the defined code rate can indicate a proportion of a data-stream that is useful (non-redundant). For example, if the code rate is k/n, for every k bits of useful information, the coder generates n bits of total codeword, of which n-k are redundancy bits or parity bits.
• the present technology describes LDPC codes with parity check matrices that offer a coding rate of 8/9 and can support a data rate of 5 gigabits per second (Gbps).
• the parity check matrices can be used for supporting different block sizes. In addition, these parity check matrices can be specifically targeted for 5G applications, and therefore, superior to simply reusing 802.11 ⁇ LDPC parity check matrices.
• the 3GPP LTE standard supports adaptive modulation and coding schemes.
• the 3GPP LTE standard supports a granular set of resource allocations, modulation and coding schemes, packet sizes (or transport block sizes), and rate-compatible channel coding.
• the adaptive modulation and coding schemes can be based on turbo codes with circular buffer rate-matching for incremental redundancy (IR) hybrid automatic repeat request (HARQ) support.
• IR incremental redundancy
• HARQ hybrid automatic repeat request
• the supported set of spectral efficiencies can range from 0.1 bits per second per Hertz (bps/Hz) to 7.6 bps/Hz for 256 quadrature amplitude modulation (QAM).
• bps/Hz bits per second per Hertz
• QAM quadrature amplitude modulation
• Modulation and coding scheme (MCS) levels can be defined to correspond to
• Rate-compatible channel coding can be used to encode a packet or transport block (TB) at an arbitrary coding rate according to a selected MCS level, and multiple redundancy versions can be defined to support HARQ operation.
• 802.1 ln/1 lac LDPC code design is based on a limited set of code rates and block sizes.
• PHY protocol data unit (PPDU) encoding rules can be used to encode and transmit a packet on available channel resources.
• the PPDU encoding rules can include mechanisms for shortening and puncturing with respect to encoding the transmitting the packet.
• a packet of small size can be zero- padded and encoded with a parity-check matrix, and the zero-padding can be removed after encoding to achieve an effective lower code rate.
• the puncturing mechanism a packet can be encoded with a parity-check matrix, and the parity bits after encoding can be punctured to increase the effective code rate.
• structured LDPC codes have been adopted in wireless technology standards, such as IEEE802.11n, IEEE802.11ac, and IEEE802. i l ad. Structured LDPC codes based on shifted identity matrices can allow for vectorized operations that facilitate high throughput encoding and decoding. In addition, structured LDPC codes provide a framework to support a wide range of block sizes and code rates.
• the LDPC code can have a particular code rate, and for a given number of information bits, parity check bits can be added to the information bits.
• each parity check matrix can be partitioned into square blocks, or sub matrices, of size z x z, wherein z is an integer.
• These sub matrices can be cyclic permutations of an identity matrix (or shifted identity matrix) or null matrices.
• a cyclic permutation matrix Pi can be obtained from the zxz identity matrix by cyclically shifting the columns to the right by i elements.
• the matrix Po is shifted right by a value of 0.
• the matrix P4 indicates an identity matrix that is shifted right by a value of 4. In other words, each row of matrix Po is rotated cyclically by 4 to yield Po.
• P2 is shifted right by a value of 2.
• each row of matrix Po is rotated cyclically by 2 to yield P 2 .
• a null matrix can be used when every element of the sub matrix is 0.
• a matrix H_r89_z96 is shown below.
• the matrix H_r89_z96 is for a coding rate of 8/9 with a sub matrix dimension (or z) that is equal to 96 and a code word length equal to 3456.
• each non-negative integer i denotes the cyclic permutation matrix Pi and negative integer entries (-1) or null entries (-) denote null or zero submatrices.
• the matrix H_r89_z96 has 4 rows and 36 columns.
• the parity-check matrix can encode an information size of 32*96 to get a codeword of 36*96 of which 32*96 are information bits, and 4*96 are codeword bits.
• the first entry in the matrix H_r89_z96 is 31.
• the 31 is akin to P31.
• a 96x96 identity matrix is rotated to the right by a value of 31, and this sub matrix corresponds to the 31 in the matrix H_r89_z96.
• the second entry in the matrix H_r89_z96 is 1, which indicates that the 96x96 identity matrix is rotated to the right by a value of 1, and this sub matrix corresponds to the 1 in the matrix H_r89_z96.
• the matrix H_r89_z96 can be referred to as a matrix prototype.
• the matrix prototype is essentially used as a short hand notation.
• supported codeword sizes can be defined for different shift sizes.
• the supported shift sizes (z) can include 12, 24, 36, 48, 60, 72, 84 and 96.
• the 4 x 36 matrix yields a coding rate of (36 - 4) / 36 or 8/9.
• a matrix prototype can be provided.
• FIGS.1 A to 1H illustrate matrix prototypes corresponding to a coding rate of 8/9 and sub-block sizes of 12, 24, 36, 48, 60, 72, 84 and 96, respectively.
• the matrix H_r89_zl2 with a sub block size or shift size (z) of 12 is a 4x36 matrix as follows:
• the matrix H_r89_z24 with a sub block size or shift size (z) of 24 is a 4x36 matrix as follows:
• the matrix H_r89_z36 with a sub block size or shift size (z) of 36 is a 4x36 matrix as follows:
• the matrix H_r89_z48 with a sub block size or shift size (z) of 48 is a 4x36 matrix as follows:
• the matrix H_r89_z60 with a sub block size or shift size (z) of 60 is a 4x36 matrix as follows:
• the matrix H_r89_z72 with a sub block size or shift size (z) of 72 is a 4x36 matrix as follows:
• the matrix H_r89_z84 with a sub block size or shift size (z) of 84 is a 4x36 matrix as follows:
• the matrix H_r89_z96 with a sub block size or shift size (z) of 96 is a 4x36 matrix as follows:
• the prototype matrices can be designed to reduce a number of length-4 and length-6 cycles in a Tanner graph corresponding to the prototype matrices.
• the algorithm when assigning a shift size for each entry, the algorithm can run through different candidate values and select a suitable value that minimizes the number of cycles.
• Tanner graphs are bipartite graphs used to state constraints or equations which specify error correcting codes.
• Tanner graphs can be used to construct longer codes from smaller codes, and both encoders and decoders can employ Tanner graphs. Since the prototype matrices reduce the number of length-4 and length-6 cycles in the Tanner graph corresponding to the prototype matrices, the LDPC codes corresponding to these prototype matrices have favorable block error rate performance and relatively low error floors.
• FIG 2 illustrates an exemplary technique for encoding information using a selected matrix prototype.
• a transmitting device can acquire an information block for transmission.
• the information block can include information bits (i).
• the transmitting device can identify a modulation and coding scheme associated with the transmission.
• the transmitting device can determine a matrix prototype and a sub block size based on a size of the information block and the modulation and coding scheme. In some cases, the matrix prototype and subblock sizes to be used may be explicitly indicated by the entity requesting the transmission.
• the matrix prototype and corresponding sub block size that is selected can be one of the matrix prototypes shown in FIGS. 1 A-1H.
• the transmitting device can encode at least a portion of the information block based on the matrix prototype and the sub block size to obtain an encoded code word (c).
• the transmitting device can select a set of bits (d) from the encoded code word for transmission to a receiving device. As a non-limiting example, starting bits of the encoded code word can be selected for transmission.
• the information block size can be 3072 bits
• the transmitting device can select a set of bits (e.g., 3072/0.9 rounded off to a nearest multiple of 6, which is the modulation order for 64-QAM) from the codeword bits to obtain bits for transmission.
• the bits can correspond to an MCS of 5.4 bits per symbol per Hertz.
• the transmitting device can transmit the set of bits to the receiving device.
• FIG 3 illustrates an exemplary technique for decoding information using a selected matrix prototype.
• a receiving device can acquire a received block of bits (y), a length of information block size, and an associated modulation and coding scheme.
• the receiving device can receive the block of bits (y) from the transmitting device.
• the receiving device can determine a matrix prototype and a subblock size based on the modulation and coding scheme and the information block size.
• the matrix prototype and corresponding sub block size that is selected can be one of the matrix prototypes shown in FIGS. 1A-1H.
• the receiving block can decode the received block of bits based on the matrix prototype and the subblock size to obtain an estimated information block (i).
• the receiving device can decode the received block of bits using a layered belief propagation scheme or another decoding technique used to decode LDPC codes.
• the layered belief propagation scheme can be used to decode the parity check matrices. If there are a defined number of rows in the parity check matrix, each row can be considered as a layer.
• the belief propagation can solve the parity check equation on a row-by -row basis. The first row can process its parity check equation, and results of the first row can be passed on to the second row. The second row can process its parity check equation using the previous results, and the second row can pass its results to the third row, and so on.
• the UE can comprise one or more processors and memory configured to: acquire, at the UE, a block of information bits, as in block 410.
• the UE can comprise one or more processors and memory configured to: select, at the UE, a modulation and coding scheme, as in block 420.
• the UE can comprise one or more processors and memory configured to: determine, at the UE, a matrix prototype and a code word sub-block size based on a size of the block of information bits and the modulation and coding scheme, as in block 430.
• the UE can comprise one or more processors and memory configured to: encode, at the UE, at least a portion of the block of information bits to obtain an encoded code word block, wherein at least the portion of the block of information bits is encoded based on the matrix prototype and the code word sub-block size, as in block 440.
• the UE can comprise one or more processors and memory configured to: select, at the UE, a subset of bits from the encoded code word block, as in block 450.
• the UE can comprise one or more processors and memory configured to: generate, at the UE, the subset of bits for transmission to an eNodeB, as in block 460.
• the UE can comprise one or more processors and memory configured to: identify, at the UE, a block of bits received from the eNodeB, wherein the block of bits is associated with a block size length and a modulation and coding scheme, as in block 510.
• the UE can comprise one or more processors and memory configured to: determine, at the UE, a matrix prototype and a code word sub-block size based on the block size length and the modulation and coding scheme, as in block 520.
• the UE can comprise one or more processors and memory configured to: decode, at the UE, the block of bits received from the eNodeB to obtain a decoded block of information bits, wherein the decoded block of information bits is obtained based on the matrix prototype and the code word sub-block size, as in block 530.
• Another example provides at least one machine readable storage medium having instructions 600 embodied thereon for encoding and decoding information at an eNodeB, as shown in FIG 6.
• the instructions can be executed on a machine, where the instructions are included on at least one computer readable medium or one non-transitory machine readable storage medium.
• the instructions when executed perform: identifying, using one or more processors of the eNodeB, a block of information bits for transmission from the eNodeB to a user equipment (UE), as in block 610.
• UE user equipment
• the instructions when executed perform: determining, using the one or more processors of the eNodeB, a low density parity check (LDPC) matrix and a code word sub-block size based on a size of the block of information bits and a modulation and coding scheme, as in block 620.
• the instructions when executed perform: encoding, using the one or more processors of the eNodeB, at least a portion of the block of information bits to obtain an encoded code word block, wherein at least the portion of the block of information bits is encoded based on the LDPC matrix and the code word sub-block size, as in block 630.
• LDPC low density parity check
• the instructions when executed perform: selecting, using the one or more processors of the eNodeB, a subset of bits from the encoded code word block, as in block 640.
• the instructions when executed perform: formatting, using the one or more processors of the eNodeB, the subset of bits for transmission to the UE in the E-UTRAN, as in block 650.
• FIG 7 provides an example illustration of a user equipment (UE) device 700 and a nose 720.
• the UE device 700 can include a wireless device, a mobile station (MS), a mobile wireless device, a mobile communication device, a tablet, a handset, or other type of wireless device.
• the UE device 700 can include one or more antennas configured to communicate with the node 720 or transmission station, such as a base station (BS), an evolved Node B (eNB), a baseband unit (BBU), a remote radio head (RRH), a remote radio equipment (RRE), a relay station (RS), a radio equipment (RE), a remote radio unit (RRU), a central processing module (CPM), or other type of wireless wide area network (WWAN) access point.
• BS base station
• eNB evolved Node B
• BBU baseband unit
• RRH remote radio head
• RRE remote radio equipment
• RS relay station
• RE radio equipment
• RRU remote radio unit
• CCM central processing module
• the node 720 can include one or more processors 722 and memory 724.
• the UE device 700 can be configured to communicate using at least one wireless communication standard including 3GPP LTE, WiMAX, High Speed Packet Access (HSPA), Bluetooth, and WiFi.
• the UE device 700 can communicate using separate antennas for each wireless communication standard or shared antennas for multiple wireless communication standards.
• the UE device 700 can communicate in a wireless local area network (WLAN), a wireless personal area network (WPAN), and/or a WWAN.
• WLAN wireless local area network
• WPAN wireless personal area network
• WWAN wireless wide area network
• the UE device 700 may include application circuitry 702, baseband circuitry 704, Radio Frequency (RF) circuitry 706, front-end module (FEM) circuitry 708 and one or more antennas 710, coupled together at least as shown.
• RF Radio Frequency
• FEM front-end module
• the application circuitry 702 may include one or more application processors.
• the application circuitry 702 may include circuitry such as, but not limited to, one or more single-core or multi-core processors.
• the processor(s) may include any combination of general-purpose processors and dedicated processors (e.g., graphics processors, application processors, etc.).
• the processors may be coupled with and/or may include a storage medium, and may be configured to execute instructions stored in the storage medium to enable various applications and/or operating systems to run on the system.
• the baseband circuitry 704 may include circuitry such as, but not limited to, one or more single-core or multi-core processors.
• the baseband circuitry 704 may include one or more baseband processors and/or control logic to process baseband signals received from a receive signal path of the RF circuitry 706 and to generate baseband signals for a transmit signal path of the RF circuitry 706.
• Baseband processing circuity 704 may interface with the application circuitry 702 for generation and processing of the baseband signals and for controlling operations of the RF circuitry 706.
• the baseband circuitry 704 may include a second generation (2G) baseband processor 704a, third generation (3G) baseband processor 704b, fourth generation (4G) baseband processor 704c, and/or other baseband processor(s) 704d for other existing generations, generations in development or to be developed in the future (e.g., fifth generation (5G), 6Q etc.).
• the baseband circuitry 704 e.g., one or more of baseband processors 704a-d
• the radio control functions may include, but are not limited to, signal
• modulation/demodulation circuitry of the baseband circuitry 704 may include Fast-Fourier Transform (FFT), precoding, and/or constellation
• encoding/decoding circuitry of the baseband circuitry 704 may include convolution, tail-biting convolution, turbo, Viterbi, and/or Low Density Parity Check (LDPC) encoder/decoder functionality.
• LDPC Low Density Parity Check
• Embodiments of modulation/demodulation and encoder/decoder functionality are not limited to these examples and may include other suitable functionality in other embodiments.
• the baseband circuitry 704 may include elements of a protocol stack such as, for example, elements of an evolved universal terrestrial radio access network (EUTRAN) protocol including, for example, physical (PHY), media access control (MAC), radio link control (RLC), packet data convergence protocol
• EUTRAN evolved universal terrestrial radio access network
• PHY physical
• MAC media access control
• RLC radio link control
• a central processing unit (CPU) 704e of the baseband circuitry 704 may be configured to run elements of the protocol stack for signaling of the PHY, MAC, RLC, PDCP and/or RRC layers.
• the baseband circuitry may include one or more audio digital signal processor(s) (DSP) 704f.
• the audio DSP(s) 104f may be include elements for compression/decompression and echo cancellation and may include other suitable processing elements in other embodiments.
• Components of the baseband circuitry may be suitably combined in a single chip, a single chipset, or disposed on a same circuit board in some embodiments.
• some or all of the constituent components of the baseband circuitry 704 and the application circuitry 702 may be implemented together such as, for example, on a system on a chip (SOC).
• SOC system on a chip
• the baseband circuitry 704 may provide for
• the baseband circuitry 704 may support communication with an evolved universal terrestrial radio access network (EUTRAN) and/or other wireless metropolitan area networks (WMAN), a wireless local area network (WLAN), a wireless personal area network (WPAN).
• EUTRAN evolved universal terrestrial radio access network
• WMAN wireless metropolitan area networks
• WLAN wireless local area network
• WPAN wireless personal area network
• multi-mode baseband circuitry Embodiments in which the baseband circuitry 704 is configured to support radio communications of more than one wireless protocol.
• the RF circuitry 706 may enable communication with wireless networks using modulated electromagnetic radiation through a non-solid medium.
• the RF circuitry 706 may include switches, filters, amplifiers, etc. to facilitate the communication with the wireless network.
• RF circuitry 706 may include a receive signal path which may include circuitry to down-convert RF signals received from the FEM circuitry 708 and provide baseband signals to the baseband circuitry 704.
• RF circuitry 706 may also include a transmit signal path which may include circuitry to up-convert baseband signals provided by the baseband circuitry 704 and provide RF output signals to the FEM circuitry 708 for transmission.
• the RF circuitry 706 may include a receive signal path and a transmit signal path.
• the receive signal path of the RF circuitry 706 may include mixer circuitry 706a, amplifier circuitry 706b and filter circuitry 706c.
• the transmit signal path of the RF circuitry 706 may include filter circuitry 706c and mixer circuitry 706a.
• RF circuitry 706 may also include synthesizer circuitry 706d for synthesizing a frequency for use by the mixer circuitry 706a of the receive signal path and the transmit signal path.
• the mixer circuitry 706a of the receive signal path may be configured to down-convert RF signals received from the FEM circuitry 708 based on the synthesized frequency provided by synthesizer circuitry 706d.
• the amplifier circuitry 706b may be configured to amplify the down-converted signals and the filter circuitry 706c may be a low-pass filter (LPF) or band-pass filter (BPF) configured to remove unwanted signals from the down-converted signals to generate output baseband signals.
• LPF low-pass filter
• BPF band-pass filter
• Output baseband signals may be provided to the baseband circuitry 704 for further processing.
• the output baseband signals may be zero-frequency baseband signals, although this is not a necessity.
• mixer circuitry 706a of the receive signal path may comprise passive mixers, although the scope of the embodiments is not limited in this respect.
• the mixer circuitry 706a of the transmit signal path may be configured to up-convert input baseband signals based on the synthesized frequency provided by the synthesizer circuitry 706d to generate RF output signals for the FEM circuitry 708.
• the baseband signals may be provided by the baseband circuitry 704 and may be filtered by filter circuitry 706c.
• the filter circuitry 706c may include a low-pass filter (LPF), although the scope of the embodiments is not limited in this respect.
• LPF low-pass filter
• the mixer circuitry 706a of the receive signal path and the mixer circuitry 706a of the transmit signal path may include two or more mixers and may be arranged for quadrature down-conversion and/or up-conversion respectively.
• the mixer circuitry 706a of the receive signal path and the mixer circuitry 706a of the transmit signal path may include two or more mixers and may be arranged for image rejection (e.g., Hartley image rejection).
• the mixer circuitry 706a of the receive signal path and the mixer circuitry 706a may be arranged for direct down-conversion and/or direct up-conversion, respectively.
• the mixer circuitry 706a of the receive signal path and the mixer circuitry 706a of the transmit signal path may be configured for super-heterodyne operation.
• the output baseband signals and the input baseband signals may be analog baseband signals, although the scope of the embodiments is not limited in this respect.
• the output baseband signals and the input baseband signals may be digital baseband signals.
• the RF circuitry 706 may include analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuitry and the baseband circuitry 704 may include a digital baseband interface to communicate with the RF circuitry 706.
• ADC analog-to-digital converter
• DAC digital-to-analog converter
• a separate radio IC circuitry may be provided for processing signals for each spectrum, although the scope of the embodiments is not limited in this respect.
• the synthesizer circuitry 706d may be a fractional-N synthesizer or a fractional N/N+l synthesizer, although the scope of the embodiments is not limited in this respect as other types of frequency synthesizers may be suitable.
• synthesizer circuitry 706d may be a delta-sigma synthesizer, a frequency multiplier, or a synthesizer comprising a phase-locked loop with a frequency divider.
• the synthesizer circuitry 706d may be configured to synthesize an output frequency for use by the mixer circuitry 706a of the RF circuitry 706 based on a frequency input and a divider control input.
• the synthesizer circuitry 706d may be a fractional N/N+l synthesizer.
• frequency input may be provided by a voltage controlled oscillator (VCO), although that is not a necessity.
• VCO voltage controlled oscillator
• Divider control input may be provided by either the baseband circuitry 704 or the applications processor 702 depending on the desired output frequency.
• a divider control input (e.g., N) may be determined from a look-up table based on a channel indicated by the applications processor 702.
• Synthesizer circuitry 706d of the RF circuitry 706 may include a divider, a delay- locked loop (DLL), a multiplexer and a phase accumulator.
• the divider may be a dual modulus divider (DMD) and the phase accumulator may be a digital phase accumulator (DPA).
• the DMD may be configured to divide the input signal by either N or N+l (e.g., based on a carry out) to provide a fractional division ratio.
• the DLL may include a set of cascaded, tunable, delay elements, a phase detector, a charge pump and a D-type flip-flop.
• the delay elements may be configured to break a VCO period up into Nd equal packets of phase, where Nd is the number of delay elements in the delay line.
• Nd is the number of delay elements in the delay line.
• synthesizer circuitry 706d may be configured to generate a carrier frequency as the output frequency, while in other embodiments, the output frequency may be a multiple of the carrier frequency (e.g., twice the carrier frequency, four times the carrier frequency) and used in conjunction with quadrature generator and divider circuitry to generate multiple signals at the carrier frequency with multiple different phases with respect to each other.
• the output frequency may be a LO frequency (fLO).
• the RF circuitry 706 may include an IQ/polar converter.
• FEM circuitry 708 may include a receive signal path which may include circuitry configured to operate on RF signals received from one or more antennas 710, amplify the received signals and provide the amplified versions of the received signals to the RF circuitry 706 for further processing.
• FEM circuitry 708 may also include a transmit signal path which may include circuitry configured to amplify signals for transmission provided by the RF circuitry 706 for transmission by one or more of the one or more antennas 710.
• the FEM circuitry 708 may include a TX/RX switch to switch between transmit mode and receive mode operation.
• the FEM circuitry may include a receive signal path and a transmit signal path.
• the receive signal path of the FEM circuitry may include a low-noise amplifier (LNA) to amplify received RF signals and provide the amplified received RF signals as an output (e.g., to the RF circuitry 706).
• LNA low-noise amplifier
• the transmit signal path of the FEM circuitry 708 may include a power amplifier (PA) to amplify input RF signals (e.g., provided by RF circuitry 706), and one or more filters to generate RF signals for subsequent transmission (e.g., by one or more of the one or more antennas 710.
• PA power amplifier
• FIG. 8 provides an example illustration of the wireless device, such as a user equipment (UE), a mobile station (MS), a mobile wireless device, a mobile
• the wireless device can include one or more antennas configured to communicate with a node, macro node, low power node (LPN), or, transmission station, such as a base station (BS), an evolved Node B (eNB), a baseband processing unit (BBU), a remote radio head (RRH), a remote radio equipment (RRE), a relay station (RS), a radio equipment (RE), or other type of wireless wide area network (WWAN) access point.
• the wireless device can be configured to communicate using at least one wireless communication standard such as, but not limited to, 3 GPP LTE, WiMAX, High Speed Packet Access (HSPA), Bluetooth, and WiFi.
• the wireless device can communicate using separate antennas for each wireless communication standard or shared antennas for multiple wireless communication standards.
• the wireless device can communicate in a wireless local area network
• the wireless device can also comprise a wireless modem.
• the wireless modem can comprise, for example, a wireless radio transceiver and baseband circuitry (e.g., a baseband processor).
• the wireless modem can, in one example, modulate signals that the wireless device transmits via the one or more antennas and demodulate signals that the wireless device receives via the one or more antennas.
• FIG. 8 also provides an illustration of a microphone and one or more speakers that can be used for audio input and output from the wireless device.
• the display screen can be a liquid crystal display (LCD) screen, or other type of display screen such as an organic light emitting diode (OLED) display.
• the display screen can be configured as a touch screen.
• the touch screen can use capacitive, resistive, or another type of touch screen technology.
• An application processor and a graphics processor can be coupled to internal memory to provide processing and display capabilities.
• a non-volatile memory port can also be used to provide data input/output options to a user.
• the non-volatile memory port can also be used to expand the memory capabilities of the wireless device.
• a keyboard can be integrated with the wireless device or wirelessly connected to the wireless device to provide additional user input.
• a virtual keyboard can also be provided using the touch screen.
• Example 1 includes an apparatus of a user equipment (UE) operable to encode information for transmission to an eNodeB, the apparatus comprising one or more processors and memory configured to: acquire, at the UE, a block of information bits; select, at the UE, a modulation and coding scheme; determine, at the UE, a matrix prototype and a code word sub-block size based on a size of the block of information bits and the modulation and coding scheme; encode, at the UE, at least a portion of the block of information bits to obtain an encoded code word block, wherein at least the portion of the block of information bits is encoded based on the matrix prototype and the code word sub-block size; select, at the UE, a subset of bits from the encoded code word block; and generate, at the UE, the subset of bits for transmission to an eNodeB.
• UE user equipment
• Example 2 includes the apparatus of Example 1, further comprising a baseband processor operable to: determine the matrix prototype and the code word sub-block size based on the size of the block of information bits and the modulation and coding scheme; and encode at least the portion of the block of information bits to obtain the encoded code word block; and a transceiver operable to transmit the subset of bits from the UE to the eNodeB.
• a baseband processor operable to: determine the matrix prototype and the code word sub-block size based on the size of the block of information bits and the modulation and coding scheme; and encode at least the portion of the block of information bits to obtain the encoded code word block; and a transceiver operable to transmit the subset of bits from the UE to the eNodeB.
• Example 3 includes the apparatus of any of Examples 1 to 2, wherein the matrix prototype corresponds to a defined code rate, wherein the defined code rate is a coding rate of 8/9.
• Example 4 includes the apparatus of any of Examples 1 to 3, wherein the modulation and coding scheme corresponds to a spectral efficiency of approximately 5.4 bits per symbol per Hertz.
• Example 5 includes the apparatus of any of Examples 1 to 4, wherein the code word sub-block size is 84 and the matrix prototype is:
• Example 6 includes the apparatus of any of Examples 1 to 5, wherein the code word sub-block size is 72 and the matrix prototype is:
• Example 7 includes the apparatus of any of Examples 1 to 6, wherein the code word sub-block size is 60 and the matrix prototype is:
• Example 8 includes the apparatus of any of Examples 1 to 7, wherein the code word sub-block size is 48 and the matrix prototype is:
• Example 9 includes the apparatus of any of Examples 1 to 8, wherein the code word sub-block size is 36 and the matrix prototype is:
• Example 10 includes the apparatus of any of Examples 1 to 9, wherein the code word sub-block size is 24 and the matrix prototype is:
• Example 11 includes the apparatus of any of Examples 1 to 10, wherein the code word sub-block size is 12 and the matrix prototype is:
• Example 12 includes an apparatus of a user equipment (UE) operable to decode information received from an eNodeB, the apparatus comprising one or more processors and memory configured to: identify, at the UE, a block of bits received from the eNodeB, wherein the block of bits is associated with a block size length and a modulation and coding scheme; determine, at the UE, a matrix prototype and a code word sub-block size based on the block size length and the modulation and coding scheme; and decode, at the UE, the block of bits received from the eNodeB to obtain a decoded block of information bits, wherein the decoded block of information bits is obtained based on the matrix prototype and the code word sub-block size.
• UE user equipment
• Example 13 includes the apparatus of Example 12, wherein the matrix prototype corresponds to a defined code rate, wherein the defined code rate is a coding rate of 8/9.
• Example 14 includes the apparatus of any of Examples 12 to 13, wherein the modulation and coding scheme corresponds to a spectral efficiency of approximately 5.4 bits per symbol per Hertz.
• Example 15 includes the apparatus of any of Examples 12 to 14, wherein the code word sub-block size is 84 and the matrix prototype is:
• Example 16 includes the apparatus of any of Examples 12 to 15, wherein the code word sub-block size is 72 and the matrix prototype is:
• Example 17 includes the apparatus of any of Examples 12 to 16, wherein the code word sub-block size is 60 and the matrix prototype is:
• Example 18 includes the apparatus of any of Examples 12 to 17, wherein the code word sub-block size is 48 and the matrix prototype is:
• Example 19 includes the apparatus of any of Examples 12 to 18, wherein the code word sub-block size is 36 and the matrix prototype is:
• Example 20 includes the apparatus of any of Examples 12 to 19, wherein the code word sub-block size is 24 and the matrix prototype is:
• Example 21 includes the apparatus of any of Examples 12 to 20, wherein the code word sub-block size is 12 and the matrix prototype is:
• Example 22 includes at least one machine readable storage medium having instructions embodied thereon for encoding and decoding information at an eNodeB, the instructions when executed perform the following: identifying, using one or more processors of the eNodeB, a block of information bits for transmission from the eNodeB to a user equipment (UE); determining, using the one or more processors of the eNodeB, a low density parity check (LDPC) matrix and a code word sub-block size based on a size of the block of information bits and a modulation and coding scheme; encoding, using the one or more processors of the eNodeB, at least a portion of the block of information bits to obtain an encoded code word block, wherein at least the portion of the block of information bits is encoded based on the LDPC matrix and the code word sub-block size; selecting, using the one or more processors of the eNodeB, a subset of bits from the encoded code word block; and formatting, using the one
• Example 23 includes the at least one machine readable storage medium of Example 22, further comprising instructions when executed perform the following: identifying a block of bits received from the UE, wherein the block of bits is associated with a second block size length and a second modulation and coding scheme; determining a second matrix prototype and a second code word sub-block size based on the second block size length and the second modulation and coding scheme; and decoding the block of bits to obtain a decoded block of information bits, wherein the decoded block of information bits is obtained based on the second matrix prototype and the second code word sub-block size.
• Example 24 includes the at least one machine readable storage medium of any of Examples 22-23, wherein: the matrix prototype corresponds to a coding rate of 8/9; and the modulation and coding scheme corresponds to a spectral efficiency of approximately 5.4 bits per symbol per Hertz.
• Example 25 includes the at least one machine readable storage medium of any of Examples 22-24, wherein:
• the code word sub-block size is 84 and the matrix prototype is:
• Example 26 includes an apparatus of a user equipment (UE) operable to encode information for transmission to an eNodeB, the apparatus comprising one or more processors and memory configured to: acquire, at the UE, a block of information bits; select, at the UE, a modulation and coding scheme; determine, at the UE, a matrix prototype and a code word sub-block size based on a size of the block of information bits and the modulation and coding scheme; encode, at the UE, at least a portion of the block of information bits to obtain an encoded code word block, wherein at least the portion of the block of information bits is encoded based on the matrix prototype and the code word sub-block size; select, at the UE, a subset of bits from the encoded code word block; and generate, at the UE, the subset of bits for transmission to an eNodeB.
• UE user equipment
• Example 27 includes the apparatus of Example 26, further comprising: a baseband processor operable to: determine the matrix prototype and the code word sub-block size based on the size of the block of information bits and the modulation and coding scheme; and encode at least the portion of the block of information bits to obtain the encoded code word block; and a transceiver operable to transmit the subset of bits from the UE to the eNodeB.
• a baseband processor operable to: determine the matrix prototype and the code word sub-block size based on the size of the block of information bits and the modulation and coding scheme; and encode at least the portion of the block of information bits to obtain the encoded code word block
• a transceiver operable to transmit the subset of bits from the UE to the eNodeB.
• Example 28 includes the apparatus of any of Examples 26 to 27, wherein the matrix prototype corresponds to a defined code rate, wherein the defined code rate is a coding rate of 8/9.
• Example 29 includes the apparatus of any of Examples 26 to 28, wherein the modulation and coding scheme corresponds to a spectral efficiency of approximately 5.4 bits per symbol per Hertz.
• Example 30 includes the apparatus of any of Examples 26 to 29, wherein:
• the code word sub-block size is 84 and the matrix prototype is:
• the code word sub-block size is 72 and the matrix prototype is:
• Example 31 includes an apparatus of a user equipment (UE) operable to decode information received from an eNodeB, the apparatus comprising one or more processors and memory configured to: identify, at the UE, a block of bits received from the eNodeB, wherein the block of bits is associated with a block size length and a modulation and coding scheme; determine, at the UE, a matrix prototype and a code word sub-block size based on the block size length and the modulation and coding scheme; and decode, at the UE, the block of bits received from the eNodeB to obtain a decoded block of information bits, wherein the decoded block of information bits is obtained based on the matrix prototype and the code word sub-block size.
• UE user equipment
• Example 32 includes the apparatus of Example 31, wherein the matrix prototype corresponds to a defined code rate, wherein the defined code rate is a coding rate of 8/9.
• Example 33 includes the apparatus of any of Examples 31 to 32, wherein the modulation and coding scheme corresponds to a spectral efficiency of approximately 5.4 bits per symbol per Hertz.
• Example 34 includes the apparatus of any of Examples 31 to 33, wherein:
• the code word sub-block size is 84 and the matrix prototype is:
• the code word sub-block size is 72 and the matrix prototype is:
• Example 35 includes at least one machine readable storage medium having instructions embodied thereon for encoding and decoding information at an eNodeB, the instructions when executed perform the following: identifying, using one or more processors of the eNodeB, a block of information bits for transmission from the eNodeB to a user equipment (UE); determining, using the one or more processors of the eNodeB, a low density parity check (LDPC) matrix and a code word sub-block size based on a size of the block of information bits and a modulation and coding scheme; encoding, using the one or more processors of the eNodeB, at least a portion of the block of information bits to obtain an encoded code word block, wherein at least the portion of the block of information bits is encoded based on the LDPC matrix and the code word sub-block size; selecting, using the one or more processors of the eNodeB, a subset of bits from the encoded code word block; and formatting, using the one
• Example 36 includes the at least one machine readable storage medium of Example 35, further comprising instructions when executed perform the following: identifying a block of bits received from the UE, wherein the block of bits is associated with a second block size length and a second modulation and coding scheme; determining a second matrix prototype and a second code word sub-block size based on the second block size length and the second modulation and coding scheme; and decoding the block of bits to obtain a decoded block of information bits, wherein the decoded block of information bits is obtained based on the second matrix prototype and the second code word sub-block size.
• Example 37 includes the at least one machine readable storage medium of any of Examples 35 to 36, wherein: the matrix prototype corresponds to a coding rate of 8/9; and the modulation and coding scheme corresponds to a spectral efficiency of approximately 5.4 bits per symbol per Hertz.
• Example 38 includes the at least one machine readable storage medium of any of Examples 35 to 37, wherein:
• the code word sub-block size is 84 and the matrix prototype is:
• Example 39 includes an eNodeB operable to encode and decode information, the eNodeB comprising: means for identifying a block of information bits for transmission from the eNodeB to a user equipment (UE); means for determining a low density parity check (LDPC) matrix and a code word sub-block size based on a size of the block of information bits and a modulation and coding scheme; means for encoding at least a portion of the block of information bits to obtain an encoded code word block, wherein at least the portion of the block of information bits is encoded based on the LDPC matrix and the code word sub-block size; means for selecting a subset of bits from the encoded code word block; and means for formatting the subset of bits for transmission to the UE.
• LDPC low density parity check
• Example 40 includes the eNodeB of Example 39, further comprising: means for identifying a block of bits received from the UE, wherein the block of bits is associated with a second block size length and a second modulation and coding scheme; means for determining a second matrix prototype and a second code word sub-block size based on the second block size length and the second modulation and coding scheme; and means for decoding the block of bits to obtain a decoded block of information bits, wherein the decoded block of information bits is obtained based on the second matrix prototype and the second code word sub-block size.
• Example 41 includes the eNodeB of any of Examples 39 to 40, wherein: the matrix prototype corresponds to a coding rate of 8/9; and the modulation and coding scheme corresponds to a spectral efficiency of approximately 5.4 bits per symbol per Hertz.
• Example 42 includes the eNodeB of any of Examples 39 to 41, wherein:
• the code word sub-block size is 84 and the matrix prototype is:
• Various techniques, or certain aspects or portions thereof, may take the form of program code (i.e., instructions) embodied in tangible media, such as floppy diskettes, compact disc-read-only memory (CD-ROMs), hard drives, non-transitory computer readable storage medium, or any other machine-readable storage medium wherein, when the program code is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the various techniques.
• a non-transitory computer readable storage medium can be a computer readable storage medium that does not include signal.
• the computing device may include a processor, a storage medium readable by the processor (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.
• the volatile and non-volatile memory and/or storage elements may be a random-access memory (RAM), erasable
• the node and wireless device may also include a transceiver module (i.e., transceiver), a counter module (i.e., counter), a processing module (i.e., processor), and/or a clock module (i.e., clock) or timer module (i.e., timer).
• transceiver module i.e., transceiver
• counter module i.e., counter
• processing module i.e., processor
• a clock module i.e., clock
• timer module i.e., timer
• selected components of the transceiver module can be located in a cloud radio access network (C-RAN).
• C-RAN cloud radio access network
• One or more programs that may implement or utilize the various techniques described herein may use an application programming interface (API), reusable controls, and the like.
• API application programming interface
• Such programs may be implemented in a high level procedural or object oriented programming language to communicate with a computer system.
• the program(s) may be implemented in assembly or machine language, if desired.
• the language may be a compiled or interpreted language, and combined with hardware implementations.
• circuitry may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable hardware components that provide the described functionality.
• ASIC Application Specific Integrated Circuit
• the circuitry may be implemented in, or functions associated with the circuitry may be implemented by, one or more software or firmware modules.
• circuitry may include logic, at least partially operable in hardware.
• modules may be implemented as a hardware circuit comprising custom very-large-scale integration (VLSI) circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components.
• VLSI very-large-scale integration
• a module may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices or the like.
• Modules may also be implemented in software for execution by various types of processors.
• An identified module of executable code may, for instance, comprise one or more physical or logical blocks of computer instructions, which may, for instance, be organized as an object, procedure, or function. Nevertheless, the executables of an identified module may not be physically located together, but may comprise disparate instructions stored in different locations which, when joined logically together, comprise the module and achieve the stated purpose for the module.
• a module of executable code may be a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, and across several memory devices.
• operational data may be identified and illustrated herein within modules, and may be embodied in any suitable form and organized within any suitable type of data structure. The operational data may be collected as a single data set, or may be distributed over different locations including over different storage devices, and may exist, at least partially, merely as electronic signals on a system or network.
• the modules may be passive or active, including agents operable to perform desired functions.

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• 2016
  • 2016-05-17 WO PCT/US2016/032931 patent/WO2017119922A1/en active Application Filing
  • 2016-05-17 CN CN201680071127.XA patent/CN108370284B/zh active Active
  • 2016-12-02 TW TW105139901A patent/TWI722063B/zh active
• 2019
  • 2019-01-15 HK HK19100633.2A patent/HK1258269A1/zh unknown

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