WO2017118060A1 - 指纹识别装置及其制作方法、阵列基板、显示装置 - Google Patents

指纹识别装置及其制作方法、阵列基板、显示装置 Download PDF

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Publication number
WO2017118060A1
WO2017118060A1 PCT/CN2016/097811 CN2016097811W WO2017118060A1 WO 2017118060 A1 WO2017118060 A1 WO 2017118060A1 CN 2016097811 W CN2016097811 W CN 2016097811W WO 2017118060 A1 WO2017118060 A1 WO 2017118060A1
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Prior art keywords
layer
electrode
transistor
doped semiconductor
fingerprint recognition
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PCT/CN2016/097811
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English (en)
French (fr)
Inventor
李昌峰
董学
陈小川
王海生
刘英明
杨盛际
丁小梁
赵卫杰
刘伟
王鹏鹏
王磊
卢鹏程
龙君
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US15/514,324 priority Critical patent/US10579852B2/en
Publication of WO2017118060A1 publication Critical patent/WO2017118060A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1318—Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/1382—Detecting the live character of the finger, i.e. distinguishing from a fake or cadaver finger
    • G06V40/1388—Detecting the live character of the finger, i.e. distinguishing from a fake or cadaver finger using image processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
    • H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PIN type
    • H01L31/1055—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PIN type the devices comprising amorphous materials of Group IV of the Periodic System
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14678—Contact-type imagers

Definitions

  • Embodiments of the present invention relate to a fingerprint recognition device, a method of fabricating the same, an array substrate, and a display device.
  • fingerprint identification technology Due to the uniqueness and invariance of human fingerprints, fingerprint identification technology has the characteristics of good security, high reliability and simple and convenient use, which makes fingerprint identification technology widely used in various fields to protect personal information security, especially mobile terminals. In areas such as mobile phones, laptops, tablet computers, digital cameras, etc., the demand for information security is more prominent. Fingerprint recognition is one of the commonly used functions of electronic devices. It is of great significance for enhancing the security of electronic devices and expanding their application range.
  • the optical fingerprinting device transmits light emitted from the light source 100 to the finger through the prism 101, and then passes through the prism and then enters the prism 101 again to reach the focusing lens 102, and is focused by the focusing lens 102 to reach the image processing.
  • the image processor 103 is provided with an image sensor, such as a CCD (Charge-Coupled Device) image sensor or a CMOS (Complementary Metal Oxide Semiconductor) image sensor. Since the angle of the reflected light of the valley line and the ridge line on the finger and the intensity of the light reflected back are different, the reflected light is projected on the image processor 103 to form a fingerprint image.
  • CCD Charge-Coupled Device
  • CMOS Complementary Metal Oxide Semiconductor
  • the prism 101, the focus lens 102, and the image processor 103 themselves occupy a large space; in addition, a certain distance between the imaging prism 101 and the focus lens 102 is required, and the focus lens 102 and image processing are required. A certain distance is also required between the devices 103.
  • An aspect of an embodiment of the present invention provides a fingerprint identification apparatus including a first gate line and a read signal line, wherein the first gate line and the read signal line cross define a plurality of fingerprint recognition units, and each fingerprint a photosensitive device and a first transistor are disposed in the identification unit;
  • the photosensitive device includes a first electrode a layer, and a first doped semiconductor layer, a second doped semiconductor layer, and a second electrode layer on the surface of the first electrode layer; an electric field is formed between the first electrode layer and the second electrode layer; Forming a PN junction between the first doped semiconductor layer and the second doped semiconductor layer; a gate of the first transistor is connected to the first gate line, and a first electrode of the first transistor is connected to the The signal line is read, and the second electrode of the first transistor is connected to the second electrode layer.
  • the photosensor further includes a depletion layer between the first doped semiconductor layer and the second doped semiconductor layer.
  • the depletion layer is of the same material as the active layer of the first transistor.
  • the first electrode layer is of the same material as the same layer of the gate of the first transistor.
  • the material constituting the second electrode layer includes a transparent conductive material.
  • it further includes an electrode signal line parallel to the first gate line, the electrode signal line being connected to the first electrode layer for supplying an electrical signal to the first electrode layer.
  • the first electrode layer has a thickness of 10 nm to 100 nm.
  • the first doped semiconductor layer or the second doped semiconductor layer has a thickness of 20 nm to 70 nm.
  • the depletion layer has a thickness of 500 nm to 1500 nm.
  • the second electrode layer has a thickness of 10 nm to 500 nm.
  • an array substrate comprising any of the fingerprint recognition devices as described above.
  • the array substrate includes a display area, and the fingerprint recognition device is disposed on the display area.
  • the display area includes a plurality of sub-pixels, and one fingerprint recognition unit is disposed in one of the sub-pixels.
  • the display area includes a first color sub-pixel, a second color sub-pixel, a third color sub-pixel, and a white sub-pixel constituting a pixel unit; the first color, the second color, and the third color constitute three a primary color; a fingerprint recognition unit is disposed in the white sub-pixel.
  • the array substrate includes a second gate line and a data line that are laterally intersected; the first gate line is parallel to the second gate line, and the read signal line is parallel to the data line.
  • the array substrate includes a peripheral area, and the fingerprint recognition device is located in the peripheral area.
  • a display device including any one of the above An array substrate.
  • Another aspect of the present invention provides a method for fabricating a fingerprint identification device, including: forming a gate of a first transistor, a first gate line, and a first electrode layer on a base substrate; a gate of one transistor, a surface of the first gate line and a substrate surface of the first electrode layer, forming a gate insulating layer of the first transistor; and forming a surface on a surface of the substrate on which the gate insulating layer is formed a doped semiconductor layer; an active layer of the first transistor formed on a surface of the substrate on which the first doped semiconductor layer is formed; and a read surface formed on a surface of the substrate on which the active layer of the first transistor is formed Taking a signal line, a first electrode and a second electrode of the first transistor; a first electrode of the first transistor is connected to the read signal line; and the read signal line is formed, the first Forming a second doped semiconductor layer on the substrate surface of the first electrode and the second electrode of one transistor; forming a passivation layer on the surface of
  • a depletion layer on the surface of the first doped semiconductor layer is formed while forming an active layer of the first transistor on a surface of the substrate on which the first doped semiconductor layer is formed.
  • FIG. 1 is a schematic structural view of a fingerprint identification device
  • FIG. 2 is a schematic structural diagram of a fingerprint identification apparatus according to an embodiment of the present invention.
  • Figure 3a is a side view of the photosensitive device of Figure 2;
  • 3b is a schematic view of a depletion region between the first doped semiconductor layer and the second doped semiconductor layer of FIG. 3a;
  • FIG. 4 is a schematic structural view showing a depletion layer provided in the photosensitive device shown in FIG. 3a;
  • Figure 5 is a cross-sectional view of the first transistor and photosensor of Figure 2;
  • FIG. 6 is a schematic diagram of area division of an array substrate according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural view showing the arrangement of the fingerprint recognition unit shown in FIG. 2 in the display area shown in FIG. 6;
  • FIG. 8 is a schematic diagram showing another structure of the fingerprint recognition unit shown in FIG. 2 in the display area shown in FIG. 6; FIG.
  • FIG. 9 is a flowchart of a method for fabricating a fingerprint identification device according to an embodiment of the present invention.
  • the embodiment of the invention provides a fingerprint identification device.
  • the fingerprint identification device includes a first gate line G1 and a read signal line RL.
  • the first gate line G1 and the read signal line RL cross define a plurality of fingerprint identification units 02, and each of the fingerprint recognition units 02 is provided with a photosensor 20 and a first transistor T1.
  • the photosensitive device 20, as shown in FIG. 3a may include a first electrode layer 201, and a first doped semiconductor layer 202, a second doped semiconductor layer 203, and a second electrode layer sequentially located on the surface of the first electrode layer 201. 204.
  • An electric field is formed between the first electrode layer 201 and the second electrode layer 204.
  • a PN junction is formed between the first doped semiconductor layer 202 and the second doped semiconductor layer 203.
  • the gate of the first transistor T1 is connected to the first gate line G1
  • the first electrode of the first transistor T1 is connected to the read signal line RL
  • the second electrode of the first transistor T1 is connected to the second electrode layer 204.
  • the fingerprint identification device may include N first gate lines G1 (G1_1, G1_2, G1_3, ..., G1_N, respectively) and M read signal lines RL (RL_1, RL_2, RL_3, ... RL_M, respectively).
  • N and M are positive integers greater than or equal to one.
  • the process of forming an electric field between the first electrode layer 201 and the second electrode layer 204 specifically applies different potentials on the first electrode layer 201 and the second electrode layer 204.
  • the first electrode layer 201 A fixed potential V0 can be provided.
  • the fingerprint identification device may further include an electrode signal line S parallel to the first gate line G1, and the electrode signal line S is connected to the first electrode layer 201 for the first electrode layer 201.
  • An electrical signal is provided, that is, the above fixed potential V0.
  • the first transistor T1 under the control of the first gate line G1, the first transistor T1 can be turned on, so that the read signal line RL is connected to the second electrode layer 204 through the first transistor T1, so that it can be read.
  • the signal line RL supplies an electrical signal to the second electrode layer 204. In this way, an electric field can be formed between the first electrode layer 201 and the second electrode layer 204.
  • forming a PN junction between the first doped semiconductor layer 202 and the second doped semiconductor layer 203 means that the interface between the first doped semiconductor layer 202 and the second doped semiconductor layer 203 has As shown in the drain region 03 of FIG. 3b, a PN junction of the semiconductor is formed in the depletion region 03.
  • the material constituting the first doped semiconductor layer 202 may include a P-type semiconductor material
  • the material constituting the second doped semiconductor layer 203 may include an N-type semiconductor material.
  • the first electrode layer 201 may apply a negative voltage
  • the second electrode layer 204 may apply a positive voltage.
  • the material constituting the first doped semiconductor layer 202 may include an N-type semiconductor material
  • the material constituting the second doped semiconductor layer 203 may include a P-type semiconductor material.
  • the first electrode layer 201 may apply a positive voltage
  • the second electrode layer 204 may apply a negative voltage.
  • the following description is performed by taking the first doped semiconductor layer 202 as a P-type semiconductor and the second doped semiconductor layer 203 as an N-type semiconductor.
  • the photosensitive device 20 operates on the principle that the P-type first doped semiconductor layer 202 and the N-type second doped semiconductor layer 203 have a semiconductor PN junction, and the photosensor 20 is in the light. Under excitation, a large number of hole-electron pairs are generated in the depletion region 03. Under the action of the electric field formed by the first electrode layer 201 and the second electrode layer 204, a part of the electrons move to an N-type conduction band having a lower energy level, that is, an N-type region composed of the second doped semiconductor layer 203, and a part thereof The holes move to a P-type valence band having a higher energy level, that is, a P-type region composed of the first doped semiconductor layer 202.
  • the negative charge of the N-type region increases, and the positive charge of the P-type region increases, thereby generating a current.
  • the skin on the surface of the finger is composed of the convex ridge line and the concave valley line
  • the light intensity reflected by the ridge line and the valley line is different, thereby exciting in the depletion region 03.
  • the number of hole-electron pairs is different and the current generated is different.
  • the current generated by the different fingerprint recognition unit 02 can be read through different read signal lines RL, and then the current is processed by the chip IC shown in FIG. 2, and finally, each fingerprint identification can be determined.
  • the fingerprint at the position corresponding to the unit 02 is a valley line or a ridge line, and the entire fingerprint pattern can be outlined.
  • an intrinsic semiconductor such as single crystal silicon can be used by an ion doping process.
  • Polycrystalline or amorphous silicon is doped with a trivalent impurity element such as boron ion or gallium ion, and then the above ions are activated to form a P-type semiconductor.
  • an N-type semiconductor can be formed by doping a pentavalent impurity element such as a phosphorus ion or an arsenic ion into the above-described intrinsic semiconductor by an ion doping process.
  • the following embodiments are described by taking boron ions in an intrinsic semiconductor to form a P-type semiconductor, and doping phosphorus ions to form an N-type semiconductor.
  • the first doped semiconductor layer 202 or the second doped semiconductor layer 203 may have a thickness of 20 nm to 70 nm.
  • the thickness of the first doped semiconductor layer 202 or the second doped semiconductor layer 203 is less than 20 nm, since the thickness of the thin film layer is too small, the precision of equipment preparation is high, which will result in an increase in manufacturing cost.
  • the thickness of the first doped semiconductor layer 202 or the second doped semiconductor layer 203 is greater than 70 nm, since the thickness of the thin film layer is too large, on the one hand, the ultrathin design of the photosensor 20 is disadvantageous; Making a thicker film layer increases the length of the manufacturing process, which reduces production efficiency.
  • the fingerprint identification device includes a first gate line and a read signal line, the first gate line and the read signal line intersecting to define a plurality of fingerprint recognition units, each of the fingerprint recognition units is provided with a photosensitive device and a a transistor.
  • the photosensitive device includes a first electrode layer, and a first doped semiconductor layer, a second doped semiconductor layer, and a second electrode layer sequentially located on the surface of the first electrode layer. An electric field is formed between the first electrode layer and the second electrode layer, and a PN junction is formed between the first doped semiconductor layer and the second doped semiconductor layer.
  • the gate of the first transistor is connected to the first gate line, the first electrode of the first transistor is connected to the read signal line, and the second electrode of the first transistor is connected to the second electrode layer.
  • the intersection of the first doped semiconductor layer and the second doped semiconductor layer has a depletion region, a semiconductor PN junction is formed in the depletion region, and the photosensor is excited by the light in the depletion region. A large number of hole-electron pairs are produced. Under the action of an electric field formed between the first electrode layer and the second electrode layer, holes and electrons respectively move toward a higher valence band and a lower energy band, thereby forming a current. At this time, when the user's finger presses the fingerprint recognition device, the intensity of the light reflected by the ridge line and the valley line of the finger is different, thereby exciting the magnitude of the current generated by the photosensitive device.
  • the first gate line can conduct the first transistor, so that the read signal line connected to the second electrode layer of the photosensor can collect the current to identify the ridge and valley lines of the finger.
  • the prism, CCD or CMOS is not used in the above fingerprint recognition unit, the thickness can be reduced.
  • the fingerprint identification device provided by the embodiment of the present invention does not need to be provided with a CCD or a CMOS, so that the production cost can be reduced.
  • the depletion region 03 is located at the interface of the first doped semiconductor layer 202 and the second doped semiconductor layer 203, the thickness of the depletion region 03 is thin, thereby reducing the excitation of the photosensor 20 in the light.
  • the stability of the current generated by the photosensor 20 is to be improved by the number of hole-electron pairs generated under the action.
  • the photosensor 20 may further include a depletion layer 205 between the first doped semiconductor layer 202 and the second doped semiconductor layer 203.
  • the thickness of the depletion region 03 can be increased by the depletion layer 205, so that the photosensor 20 can increase the number of hole-electron pairs of the depletion region 03 under the excitation of light to improve the photosensor 20 generation.
  • the stability of the current increases the photocurrent characteristics of the photosensor 20.
  • the material constituting the depletion layer 205 described above is an intrinsic semiconductor material, that is, an undoped pure semiconductor material such as single crystal silicon, polycrystalline silicon or amorphous silicon. Since the active layer 301 (shown in FIG. 5) of the first transistor T1 described above may be composed of single crystal silicon, polycrystalline silicon or amorphous silicon. Therefore, in order to simplify the fabrication process, the preparation of the depletion layer 205 described above may be completed while preparing the active layer 301 of the first transistor T1 described above. For example, the depletion layer 205 and the active layer 301 of the first transistor T1 may be of the same material.
  • the material of the one transistor T1 active layer 301 and the depletion layer 205 may be amorphous silicon (A-si) or polycrystalline silicon.
  • the temperature of the activation treatment is about 550 to 650 ° C.
  • the active layer 301 of the A-si TFT (English name: Thin Film Transistor, full name in Chinese: thin film transistor) is composed of amorphous silicon, and its preparation temperature is about 350 °C. Therefore, when the active layer 301 of the first transistor T1 is formed simultaneously with the depletion layer 205, since the formation of the depletion layer 205 is located behind the first doped semiconductor layer 202, the active layer 301 is in the first doped semiconductor. The preparation is performed after the layer 202 is formed, so that damage to the active layer 301 of the first transistor T1 caused by the high temperature at the time of ion activation in the first doped semiconductor layer 202 can be avoided.
  • the depletion layer 205 may have a thickness of 500 nm to 1500 nm.
  • the thickness of the depletion layer 205 is When the thickness is less than 500 nm, since the thickness of the film layer is too small, the precision of preparation of the device is high, which leads to an increase in manufacturing cost.
  • the thickness of the depletion layer 205 is greater than 1500 nm, since the thickness of the thin film layer is too large, on the one hand, it is disadvantageous to the ultra-thin design of the photosensor 20; on the other hand, making a thick thin film layer increases the manufacturing process. The length of time, which will reduce production efficiency.
  • the preparation of the photosensor 20 can be completed in the process of preparing the first transistor T1 described above.
  • the first electrode layer 201 may be of the same material as the gate 302 (shown in FIG. 5) of the first transistor T1.
  • metal molybdenum or molybdenum titanium alloy or the like can be used. In this way, the preparation of the first electrode layer 201 can be completed while preparing the gate electrode 302 by one patterning process.
  • the first electrode layer 201 may have a thickness of 10 nm to 100 nm.
  • the thickness of the first electrode layer 201 is less than 10 nm, since the thickness of the thin film layer is too small, the precision of preparation of the device is high, which will result in an increase in manufacturing cost.
  • the thickness of the first electrode layer 201 is greater than 100 nm, since the thickness of the thin film layer is too large, on the one hand, the ultra-thin design of the photosensor 20 is disadvantageous; on the other hand, the thicker thin film layer is added to increase the fabrication. The length of the process, which will reduce production efficiency.
  • the patterning process in the embodiment of the present invention may include a photolithography process, or may include a photolithography process and an etching step, or may further include printing, inkjet, and the like for forming a predetermined pattern;
  • the engraving process refers to a process of forming a pattern by using a photoresist, a mask, an exposure machine, or the like including a process of film formation, exposure, and development.
  • the corresponding patterning process can be selected in accordance with the structure formed in the embodiments of the present invention.
  • the one-time patterning process in the embodiment of the present invention is an example in which different exposure regions are formed by one mask exposure process, and then multiple etching, ashing, and the like removal processes are performed on different exposure regions to finally obtain an intended pattern. .
  • the material constituting the second electrode layer 204 may be a transparent conductive material.
  • the material constituting the second electrode layer 204 may be a transparent conductive material.
  • indium tin oxide, indium zinc oxide, zinc oxide, polyethylene dioxythiophene, carbon nanotubes, silver nanowires, and graphene may be a transparent conductive material.
  • the thickness of the second electrode layer 204 may be from 10 nm to 500 nm.
  • the thickness of the second electrode layer 204 is less than 10 nm, since the thickness of the thin film layer is too small, the precision of equipment preparation is high, which will result in an increase in manufacturing cost.
  • the thickness of the second electrode layer 204 is greater than At 500 nm, since the thickness of the film layer is too large, on the one hand, it is disadvantageous to the ultra-thin design of the photosensitive device 20; on the other hand, the production of a thick film layer increases the length of the manufacturing process, thereby reducing the production efficiency.
  • An embodiment of the present invention provides an array substrate, including any of the fingerprint recognition devices described above, having the same structure and advantageous effects as the fingerprint identification device provided by the foregoing embodiments. Since the foregoing embodiment has been described in detail for the structure and advantageous effects of the fingerprint recognition apparatus, details are not described herein again.
  • the array substrate can include a display area 40 and a peripheral area 50 located around the display area as shown in FIG.
  • the display area 40 is provided with a plurality of horizontally intersecting second gate lines G2 (G2_1, G2_2, G2_3, ...) and data lines D (D_1, D_2, D_3, ).
  • the display area 40 further includes a plurality of sub-pixels 01 defined by the above-described second gate line G2 and the data line D.
  • Each sub-pixel 01 is provided with a second transistor T2, the gate of the second transistor T2 is connected to the second gate line G2, the first electrode is connected to the data line D, and the other electrode is connected to the pixel in the sub-pixel 01.
  • the electrodes P X are connected.
  • the second transistor T2 can be controlled to be turned on by the second gate line G2, thereby transmitting the data voltage transmitted by the data line D to the pixel electrode P X through the second transistor T2 to charge the pixel electrode P X .
  • the plurality of sub-pixels may be the first color sub-pixel 110, the second color sub-pixel 111, or the third color sub-pixel 112, respectively, for monochromatic light constituting three primary colors.
  • the first color sub-pixel 110 is a red (R) sub-pixel
  • the second color sub-pixel 111 is a green (G) sub-pixel
  • the third color sub-pixel 112 is a blue (B) sub-pixel.
  • the first color sub-pixel 110, the second color sub-pixel 111, and the third color sub-pixel 112 may constitute one pixel unit.
  • the color of the first color sub-pixel 110, the second color sub-pixel 111, or the third color sub-pixel 112 is not limited, and may be, for example, cyan light, magenta light, or yellow light.
  • the array substrate provided with the fingerprint recognition device will be described in detail below by way of a specific example.
  • the fingerprint recognition device is provided in the display area 40.
  • a fingerprint recognition unit 02 as shown in FIG. 2 may be provided in each of the sub-pixels 01 as shown in FIG. 6.
  • the first transistor in the fingerprint identification unit 02 is T1 and photosensor 20 are disposed in one sub-pixel 01.
  • the second gate line G2 and the data line D can cross define the sub-pixel 01, and the first gate line G1 and the read signal line RL can define the fingerprint recognition unit 02. Therefore, in order to make the wiring structure on the entire array substrate tidy, for example, the first gate line G1 may be parallel to the second gate line G2, the read signal line RL may be parallel to the data line D.
  • the fingerprint recognition device described above is also disposed in the display area 40. Unlike the example 1, in the present example, the fingerprint recognition unit 02 is not provided in each of the sub-pixels 01.
  • the fingerprint recognition unit 02 may be disposed in one of a plurality of sub-pixels constituting the pixel unit.
  • the sub-pixels constituting the pixel unit include the first color sub-pixel 110, the second color sub-pixel 111, and the third color sub-pixel 112
  • the fingerprint recognition unit 02 may be disposed in the first color sub-pixel 110 and the second color.
  • the first color, the second color, and the third color constitute the three primary colors.
  • the pixel unit in the display area 40 includes a first color sub-pixel 110, a second color sub-pixel 111, a third color sub-pixel 112, and a white sub-pixel 113; in this case, for example, A fingerprint recognition unit 02 may be disposed in the white sub-pixel 113.
  • the white sub-pixel 113 is used to transmit a white light source provided by the backlight. Therefore, for a display device that can pass through the backlight without applying a voltage to the liquid crystal, the white sub-pixel 113 may not need to prepare a pixel electrode and The second transistor T2 to which the pixel electrode is connected. In this case, as shown in FIG. 8, the white sub-pixel 113 may be provided with only the first transistor T1 and the photosensor 20.
  • both Example 1 and Example 2 set the fingerprint recognition device to the display area.
  • some of the instructions displayed by display area 40 need to be fingerprinted before they can be triggered.
  • the fingerprint can be recognized when the user presses the virtual OK button displayed on the screen, thereby improving the security of the operation of the mobile terminal.
  • Example 2 With respect to Example 1, since it is only necessary to provide the fingerprint recognition unit 02 in the white sub-pixel 113, other sub-pixels such as the first color sub-pixel 110, the second color sub-pixel 111, and the third color sub-pixel are not The aperture ratio of the pixel 112 has an effect. Example 1 Compared with the example 2, since the fingerprint recognition unit 02 is provided in each sub-pixel, the fingerprint collection accuracy is higher. high.
  • the fingerprint recognition device can also be disposed in the peripheral region 50 as shown in FIG. 6, so that the aperture ratio of the display region 40 and the display effect are not affected.
  • the peripheral region 50 is used to provide a driving circuit, such as a gate driving circuit for progressively scanning the first gate line G1 and the second gate line G2, and a source driving for outputting a data signal to the data line D.
  • Embodiments of the present invention provide a display device including any of the array substrates described above.
  • the display device has the same structure and advantageous effects as the array substrate provided by the foregoing embodiments. Since the foregoing embodiment has been exemplified in detail for the structure and beneficial effects of the array substrate, details are not described herein again.
  • Embodiments of the present invention provide a method for fabricating a fingerprint identification device. As shown in FIG. 9, the method includes:
  • the above substrate may be a transparent glass substrate or a resin substrate.
  • a pattern of the gate electrode 302, the first gate line G1, and the first electrode layer 201 is formed by coating a gate metal layer on the above substrate substrate and then performing a patterning process.
  • the electrode signal line S may also be simultaneously formed in the process of performing the above-described step S101.
  • the first electrode layer 201 may have a thickness of 10 nm to 100 nm.
  • the first doped semiconductor layer 202 has a thickness of 20 nm to 70 nm.
  • an A-Si layer is coated on the surface of the substrate on which the gate insulating layer 303 is formed, and then a pattern of the undoped semiconductor layer is formed by one patterning process.
  • the above semiconductor layer is doped with boron ions by an ion doping process. Since the boron ion is a trivalent ion and forms a covalent bond with the silicon atom, one electron of the silicon atom is taken away, so that one hole of the silicon atom is formed, so that the doped A-si metal layer becomes a P-type semiconductor layer.
  • the doping ions such as boron ions are subjected to an activation treatment.
  • the temperature of the activation treatment is between 550 ° C and 650 ° C.
  • a layer of A-Si may be formed on the surface of the substrate on which the first doped semiconductor layer 202 is formed, and then a pattern of the active layer 301 may be formed by one constituent process. Since the active layer 301 of the TFT is formed after the step of the first doped semiconductor layer 202, the high temperature required for the activation of the ions in the above step S103 does not affect the active layer 301 of the first transistor T1.
  • the read signal line RL, the first electrode 304 and the second electrode 304' of the first transistor T1 are formed on the surface of the substrate on which the active layer 301 of the first transistor T1 is formed.
  • the first electrode 304 of the first transistor T1 is connected to the read signal line RL.
  • a source/drain metal layer may be formed on the surface of the substrate on which the active layer 301 is formed, and then the read signal line RL, the first electrode 304 and the second electrode 304' of the first transistor T1 are formed by one patterning process. pattern.
  • the first electrode of the transistor may be a source, and the second electrode may be a drain; or the first electrode may be a drain and the second electrode may be a source.
  • This embodiment of the present invention does not limit this.
  • the second doped semiconductor layer 203 has a thickness of 20 nm to 70 nm.
  • an A-Si layer is formed, and then an undoped semiconductor layer is formed by one forming process. picture of.
  • the above semiconductor layer is subjected to phosphorus ion doping by an ion doping process. Since the phosphorus ion is a pentavalent ion, when a covalent bond is formed with a silicon atom, one electron is added to the silicon atom, so that the semiconductor layer becomes an N-type semiconductor layer.
  • the pattern of the passivation layer 305 can be formed by a patterning process, and the via 306 described above can be formed.
  • the above steps may be performed after step S106, or may be performed after step S105 and before step S106.
  • the second electrode layer 204 is connected to the second electrode 304' of the first transistor T1 through the via 306.
  • the second electrode layer 204 has a thickness of 10 nm to 500 nm.
  • the pattern of the second electrode layer 204 may be formed on the surface of the substrate on which the second doped semiconductor layer 203 is formed by one patterning process.
  • the intersection of the first doped semiconductor layer and the second doped semiconductor layer has a depletion region, a semiconductor PN junction is formed in the depletion region, and the photosensor is excited by the light in the depletion region. A large number of hole-electron pairs are produced. Under the action of an electric field formed between the first electrode layer and the second electrode layer, holes and electrons respectively move toward a higher valence band and a lower energy band, thereby forming a current. At this time, when the user's finger presses the fingerprint recognition device, the intensity of the light reflected by the ridge line and the valley line of the finger is different, thereby exciting the magnitude of the current generated by the photosensitive device.
  • the first gate line can conduct the first transistor, so that the read signal line connected to the second electrode layer of the photosensor can collect the current to identify the ridge and valley lines of the finger. . Since the prism and the CCD are not used in the above fingerprint recognition unit, the thickness can be reduced.
  • the depletion region 03 is located at the interface of the first doped semiconductor layer 202 and the second doped semiconductor layer 203, the thickness of the depletion region 03 is thin, thereby reducing the excitation of the photosensor 20 in the light.
  • the stability of the current generated by the photosensor 20 is to be improved by the number of hole-electron pairs generated under the action.
  • the photosensor 20 may further include a depletion layer 205 between the first doped semiconductor layer 202 and the second doped semiconductor layer 203.
  • the thickness of the depletion region 03 can be increased by the depletion layer 205, so that the photosensor 20 can increase the number of hole-electron pairs of the depletion region 03 under the excitation of light to improve the photosensor 20 generation.
  • the stability of the current increases the photocurrent characteristics of the photosensor 20.
  • the depletion layer 205 on the surface of the first doped semiconductor layer 202 may be formed while performing the above step S104.
  • the depletion layer 205 may have a thickness of 500 nm to 1500 nm.

Abstract

一种指纹识别装置及其制作方法、阵列基板、显示装置。该指纹识别装置包括第一栅线（G1）和读取信号线（RL），所述第一栅线（G1）和所述读取信号线（RL）交叉界定多个指纹识别单元（02），每个指纹识别单元（02）中设置有光敏器件（20）和第一晶体管（T1）。所述光敏器件（20）包括第一电极层（201），以及依次位于所述第一电极层（201）表面第一掺杂半导体层（202）、第二掺杂半导体层（203）以及第二电极层（204）；所述第一电极层（201）与所述第二电极层（204）之间形成电场；所述第一掺杂半导体层（202）和所述第二掺杂半导体层（203）之间形成PN结。所述第一晶体管（T1）的栅极（302）连接所述第一栅线（G1），所述第一晶体管（T1）的第一电极（304）连接所述读取信号线（RL），所述第一晶体管（T1）的第二电极（304'）与所述第二电极层（204）相连接。能够解决现有的光学式指纹识别装置的厚度较大的问题。

Description

指纹识别装置及其制作方法、阵列基板、显示装置 技术领域
本发明的实施例涉及一种指纹识别装置及其制作方法、阵列基板、显示装置。
背景技术
随着现代社会的进步，个人身份识别以及个人信息安全的重要性逐步受到人们的关注。由于人体指纹具有唯一性和不变性，因此指纹识别技术具有安全性好，可靠性高，使用简单方便的特点，使得指纹识别技术被广泛应用于保护个人信息安全的各种领域，尤其是移动终端领域，例如手机、笔记本电脑、平板的电脑、数码相机等，对于信息安全性的需求更为突出。指纹识别功能是目前电子设备常用的功能之一，其对于增强电子设备的安全性，扩展其应用范围等均有重要意义。
光学式指纹识别装置如图1所示，光源100发出的光经棱镜101透射到手指上后，经手指反射后再次进入棱镜101传播后到达聚焦透镜102，并通过聚焦透镜102聚焦后到达图像处理器103上，图像处理器103上设置有图像传感器，例如CCD(英文全称：Charge-Coupled Device)图像传感器或CMOS(英文全称：Complementary Metal Oxide Semiconductor)图像传感器。由于手指上谷线和脊线反射光的角度及反射回去的光线强度不同，将反射光投射在图像处理器103上后，可形成指纹图像。
然而，在上述指纹识别装置中，棱镜101、聚焦透镜102、图像处理器103本身需占用较大空间；此外，成像棱镜101与聚焦透镜102之间需设置一定的距离，聚焦透镜102与图像处理器103之间也需设置一定的距离。
发明内容
本发明实施例的一方面，提供一种指纹识别装置，包括第一栅线和读取信号线，所述第一栅线和所述读取信号线交叉界定多个指纹识别单元，每个指纹识别单元中设置有光敏器件和第一晶体管；所述光敏器件包括第一电极 层，以及依次位于所述第一电极层表面第一掺杂半导体层、第二掺杂半导体层以及第二电极层；所述第一电极层与所述第二电极层之间形成电场；所述第一掺杂半导体层和所述第二掺杂半导体层之间形成PN结；所述第一晶体管的栅极连接所述第一栅线，所述第一晶体管的第一电极连接所述读取信号线，所述第一晶体管的第二电极与所述第二电极层相连接。
例如，所述光敏器件还包括位于所述第一掺杂半导体层与所述第二掺杂半导体层之间的耗尽层。
例如，所述耗尽层与所述第一晶体管的有源层同层同材料。
例如，所述第一电极层与所述第一晶体管的栅极的同层同材料。
例如，构成所述第二电极层的材料包括透明导电材料。
例如，还包括与所述第一栅线平行的电极信号线，所述电极信号线与所述第一电极层相连接，用于向所述第一电极层提供电信号。
例如，所述第一电极层的厚度为10nm-100nm。
例如，所述第一掺杂半导体层或所述第二掺杂半导体层的厚度为20nm-70nm。
例如，所述耗尽层的厚度为500nm-1500nm。
例如，所述第二电极层的厚度为10nm-500nm。
本发明实施例的另一方面，提供一种阵列基板，包括如上述所述的任意一种指纹识别装置。
例如，所述阵列基板包括显示区域，指纹识别装置设置于所述显示区域。
例如，所述显示区域包括多个亚像素，一个所述亚像素内设置有一个指纹识别单元。
例如，所述显示区域包括构成像素单元的第一颜色亚像素、第二颜色亚像素、第三颜色亚像素以及白色亚像素；所述第一颜色、第二颜色以及所述第三颜色构成三基色；所述白色亚像素内设置有指纹识别单元。
例如，所述阵列基板包括横纵交叉的第二栅线和数据线；第一栅线与所述第二栅线相平行，读取信号线与所述数据线相平行。
例如，所述阵列基板包括周边区域，所述指纹识别装置位于所述周边区域。
本发明实施例的又一方面，提供一种显示装置，包括如上所述的任意一 种阵列基板。
本发明实施例的另一方面，提供一种指纹识别装置的制作方法，包括：在衬底基板上形成第一晶体管的栅极、第一栅线以及第一电极层；在形成有所述第一晶体管的栅极、所述第一栅线以及所述第一电极层的基板表面，形成所述第一晶体管的栅极绝缘层；在形成有所述栅极绝缘层的基板表面，形成第一掺杂半导体层；在形成有所述第一掺杂半导体层的基板表面，形成所述第一晶体管的有源层；在形成有所述第一晶体管的有源层的基板表面，形成读取信号线、所述第一晶体管的第一电极和第二电极；所述第一晶体管的第一电极与所述读取信号线相连接；在形成有所述读取信号线、所述第一晶体管的第一电极和第二电极的基板表面，形成第二掺杂半导体层；在形成有所述第一晶体管的第一电极和第二电极的基板表面，形成钝化层，以及在所述钝化层表面对应所述第一晶体管第二电极的位置形成过孔；在形成所述第二掺杂半导体层的基板表面，形成第二电极层，所述第二电极层通过所述过孔与所述第一晶体管的第二电极相连接。
例如，在形成有所述第一掺杂半导体层的基板表面，形成所述第一晶体管的有源层的同时，形成位于所述第一掺杂半导体层表面的耗尽层。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一种指纹识别装置的结构示意图；
图2为本发明实施例提供的一种指纹识别装置的结构示意图；
图3a为图2中光敏器件的侧视图；
图3b为图3a中第一掺杂半导体层与第二掺杂半导体层之间的耗尽区的示意图；
图4为图3a所示的光敏器件中设置有耗尽层的结构示意图；
图5为图2中第一晶体管和光敏器件的截面图；
图6为本发明实施例提供的一种阵列基板的区域划分图；
图7为在图6所示的显示区域设置图2所示的指纹识别单元的一种结构示意图；
图8为在图6所示的显示区域设置图2所示的指纹识别单元的另一种结构示意图；
图9为本发明实施例提供的一种指纹识别装置的制作方法流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供一种指纹识别装置，如图2所示，该指纹识别装置包括第一栅线G1和读取信号线RL。该第一栅线G1和读取信号线RL交叉界定多个指纹识别单元02，每个指纹识别单元02中设置有光敏器件20、第一晶体管T1。
例如，该光敏器件20，如图3a所示，可以包括第一电极层201，以及依次位于第一电极层201表面第一掺杂半导体层202、第二掺杂半导体层203以及第二电极层204。第一电极层201与第二电极层204之间形成电场。第一掺杂半导体层202和第二掺杂半导体层203之间形成PN结。
例如，第一晶体管T1的栅极连接第一栅线G1，第一晶体管T1的第一电极连接读取信号线RL，第一晶体管T1的第二电极与第二电极层相连接204。
需要说明的是，上述指纹识别装置可以包括N条第一栅线G1(分别为G1_1、G1_2、G1_3……G1_N)和M条读取信号线RL(分别为RL_1、RL_2、RL_3……RL_M)，其中N和M为大于或等于1的正整数。
需要说明的是，第一电极层201与第二电极层204之间形成电场的过程具体为在第一电极层201和第二电极层204上施加不同的电位，此时，第一电极层201上可以提供固定电位V0。例如，如图3a所示，上述指纹识别装置还可以包括与第一栅线G1平行的电极信号线S，该电极信号线S与第一电极层201相连接，用于向第一电极层201提供电信号，即上述固定电位V0。
需要说明的是，在第一栅线G1的控制下，可以将第一晶体管T1导通，从而通过第一晶体管T1将读取信号线RL与第二电极层204相连接，从而可以通过读取信号线RL向第二电极层204提供电信号。这样一来，第一电极层201与第二电极层204之间可以形成电场。
需要说明的是，第一掺杂半导体层202和第二掺杂半导体层203之间形成PN结是指，在第一掺杂半导体层202和第二掺杂半导体层203之间的交界面具有如图3b所示的耗尽区03，该耗尽区03内形成有该半导体的PN结。为了形成上述PN结，构成上述第一掺杂半导体层202的材料可以包括P型半导体材料，构成上述第二掺杂半导体层203的材料可以包括N型半导体材料。在此情况下，第一电极层201可以施加负电压，第二电极层204可以施加正电压。
或者，构成上述第一掺杂半导体层202的材料可以包括N型半导体材料，构成上述第二掺杂半导体层203的材料可以包括P型半导体材料。第一电极层201可以施加正电压，第二电极层204可以施加负电压。
为了方便说明，以下描述均是以第一掺杂半导体层202为P型半导体且第二掺杂半导体层203为N型半导体为例进行。
在此情况下，上述光敏器件20的工作原理为，P型的第一掺杂半导体层202和N型的第二掺杂半导体层203之间具有半导体PN结，此时该光敏器件20在光线激发作用下，在耗尽区03会产生大量的空穴-电子对。在第一电极层201与第二电极层204形成的电场作用下，一部分电子会移动到能级较低的N型导带，即由第二掺杂半导体层203构成的N型区，而一部分空穴会移动到能级较高的P型价带，即由第一掺杂半导体层202构成的P型区。这样一来，N型区的负电荷增加，而P型区的正电荷增加，从而产生电流。基于此，由于人们手指表面的皮肤由凸出的脊线和凹陷的谷线构成，当手指按压上述光敏器件20时，脊线和谷线反射的光线强度不同，从而在上述耗尽区03激发出的空穴-电子对的数量不同，产生的电流不同。在此情况下，不同指纹识别单元02产生的电流可以通过不同的读取信号线RL进行读取，然后再通过图2所示的芯片IC对上述电流进行处理，最终便可以判断出各个指纹识别单元02对应的位置处的指纹是谷线或脊线，进而可以勾画出整个指纹图案。
需要说明的是，在第一掺杂半导体层202为P型半导体，而第二掺杂半导体层203为N型半导体的情况下，可以通过离子掺杂工艺，在本征半导体，例如单晶硅、多晶硅或者非晶硅中掺杂三价杂质元素，例如硼离子或镓离子，然后对上述离子进行活化处理，便可以形成P型半导体。此外，通过离子掺杂工艺，在上述本征半导体中掺杂五价杂质元素，例如磷离子或砷离子，便可以形成N型半导体。为了方便说明，以下实施例均是以在本征半导体中掺杂硼离子以形成P型半导体，掺杂磷离子以形成N型半导体为例进行的说明。
例如，第一掺杂半导体层202或第二掺杂半导体层203的厚度可以为20nm-70nm。当第一掺杂半导体层202或第二掺杂半导体层203的厚度小于20nm时，由于薄膜层的厚度太小，从而对设备制备精度的要求较高，这样将会导致制作成本的上升。此外，当第一掺杂半导体层202或第二掺杂半导体层203的厚度大于70nm时，由于薄膜层的厚度太大，一方面，会不利于光敏器件20的超薄化设计；另一方面，制作较厚的薄膜层会增加制作工序的时长，从而会降低生产效率。
根据本发明的实施例，指纹识别装置包括第一栅线和读取信号线，第一栅线和读取信号线交叉界定多个指纹识别单元，每个指纹识别单元中设置有光敏器件和第一晶体管。光敏器件包括第一电极层，以及依次位于第一电极层表面第一掺杂半导体层、第二掺杂半导体层以及第二电极层。第一电极层与第二电极层之间形成电场，第一掺杂半导体层和第二掺杂半导体层之间形成PN结。第一晶体管的栅极连接第一栅线，第一晶体管的第一电极连接读取信号线，第一晶体管的第二电极与第二电极层相连接。
由于第一掺杂半导体层和第二掺杂半导体层的交界面处具有耗尽区，该耗尽区内形成有半导体PN结，此时该光敏器件在光线激发作用下，在耗尽区会产生大量的空穴-电子对。在第一电极层与第二电极层之间形成的电场作用下，空穴和电子会分别向能级较高的价带和能级较低的导带移动，从而形成电流。此时当用户的手指按压该指纹识别装置时，手指上脊线和谷线反射的光线强度不同，从而激发光敏器件产生的电流大小不同。在此情况下，第一栅线可以将第一晶体管导通，从而使得与光敏器件的第二电极层相连接的读取信号线可以采集上述电流，以对手指的脊线和谷线进行识别。由于上述指纹识别单元中未使用棱镜、CCD或CMOS，从而可以减小厚度。此外，由 于本发明实施例提供的指纹识别装置无需设置CCD或CMOS，从而可以降低生产升本。
进一步的，由于上述耗尽区03位于第一掺杂半导体层202和第二掺杂半导体层203的交界面处，因此该耗尽区03的厚度较薄，从而降低了光敏器件20在光线激发作用下产生的空穴-电子对的数量，该光敏器件20产生的电流的稳定性有待提高。
为了解决上述问题，如图4所示，该所述光敏器件20还可以包括位于第一掺杂半导体层202与第二掺杂半导体层203之间的耗尽层205。这样一来，通过耗尽层205可以增加上述耗尽区03的厚度，从而使得光敏器件20在光线激发作用下，能够增加耗尽区03的空穴-电子对数量，以提高光敏器件20产生的电流的稳定性，从而提高该光敏器件20的光电流特性。
例如，构成上述耗尽层205的材料为本征半导体材料，即无掺杂的纯净半导体材料，例如单晶硅、多晶硅或非晶硅。由于上述第一晶体管T1的有源层301(如图5所示)可以由单晶硅、多晶硅或非晶硅构成。因此为了简化制作工艺，可以在制备上述第一晶体管T1有源层301的同时完成上述耗尽层205的制备。例如，耗尽层205与第一晶体管T1的有源层301可以同层同材料。
需要说明的是，由于非晶硅或多晶硅相对于单晶硅而言，更利于大面积制备，且成本较低，因此当上述指纹识别装置应用于尺寸较大的显示装置时，例如构成上述第一晶体管T1有源层301和耗尽层205的材料可以为非晶硅(A-si)或者多晶硅。
需要说明的是，由于在制备第一掺杂半导体层202的过程中，需要对掺杂的离子，例如硼离子进行活化处理，该活化处理的温度大约在550～650℃左右。A-si TFT(英文全称：Thin Film Transistor，中文全称：薄膜晶体管)中有源层301由非晶硅构成，其制备温度大约在350℃。因此当上述第一晶体管T1的有源层301与耗尽层205同时形成时，由于耗尽层205的形成位于第一掺杂半导体层202之后，从而使得有源层301在第一掺杂半导体层202形成之后才进行制备，因此可以避免制备第一掺杂半导体层202中离子活化时的高温对第一晶体管T1的有源层301造成的损坏。
例如，耗尽层205的厚度可以为500nm-1500nm。当耗尽层205的厚度 小于500nm时，由于薄膜层的厚度太小，从而对设备制备精度的要求较高，这样将会导致制作成本的上升。此外，当耗尽层205的厚度大于1500nm时，由于薄膜层的厚度太大，一方面，会不利于光敏器件20的超薄化设计；另一方面，制作较厚的薄膜层会增加制作工序的时长，从而会降低生产效率。
为了简化制作工艺可以在制备上述第一晶体管T1的过程中完成光敏器件20的制备。例如，第一电极层201可以与第一晶体管T1的栅极302(如图5所示)同层同材料。例如，可以采用金属钼，或者钼钛合金等。这样一来，可以通过一次构图工艺，在制备栅极302的同时，完成第一电极层201的制备。
例如，第一电极层201的厚度可以为10nm-100nm。当第一电极层201的厚度小于10nm时，由于薄膜层的厚度太小，从而对设备制备精度的要求较高，这样将会导致制作成本的上升。此外，当第一电极层201的厚度大于100nm时，由于薄膜层的厚度太大，一方面，会不利于光敏器件20的超薄化设计；另一方面，制作较厚的薄膜层会增加制作工序的时长，从而会降低生产效率。
需要说明的是，本发明实施例中的构图工艺，可包括光刻工艺，或，包括光刻工艺以及刻蚀步骤，或还可以包括打印、喷墨等其他用于形成预定图形的工艺；光刻工艺，是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本发明实施例中所形成的结构选择相应的构图工艺。
本发明实施例中的一次构图工艺，是以通过一次掩膜曝光工艺形成不同的曝光区域，然后对不同的曝光区域进行多次刻蚀、灰化等去除工艺最终得到预期图案为例进行的说明。
此外，为了提高手指反射的光线的输出率，使得更多的光线能够进入到光敏器件20中，以激发空穴-电子，例如构成第二电极层204的材料可以采用透明导电材料。例如，氧化铟锡、氧化铟锌、氧化锌、聚乙撑二氧噻吩、碳纳米管、银纳米线以及石墨烯等。
例如，第二电极层204的厚度为可以为10nm-500nm。当第二电极层204的厚度小于10nm时，由于薄膜层的厚度太小，从而对设备制备精度的要求较高，这样将会导致制作成本的上升。此外，当第二电极层204的厚度大于 500nm时，由于薄膜层的厚度太大，一方面，会不利于光敏器件20的超薄化设计；另一方面，制作较厚的薄膜层会增加制作工序的时长，从而会降低生产效率。
本发明实施例提供一种阵列基板，包括如上所述的任意一种指纹识别装置，具有与前述实施例提供的指纹识别装置相同的结构和有益效果。由于前述实施例已经对指纹识别装置的结构和有益效果进行详细的描述，此处不再赘述。
例如，阵列基板如图6所示可以包括显示区域40和位于显示区域周围的周边区域50。
例如，显示区域40上设置有多条横纵交叉的第二栅线G2(G2_1、G2_2、G2_3……)以及数据线D(D_1、D_2、D_3……)。
此外，该显示区域40还包括多个亚像素01，该亚像素01由上述第二栅线G2与数据线D交叉界定。每个亚像素01设置有第二晶体管T2，该第二晶体管T2的栅极与第二栅线G2相连接，第一电极与数据线D相连接，另一电极与该亚像素01中的像素电极PX相连接。通过第二栅线G2可以控制第二晶体管T2开启，从而将数据线D传输的数据电压通过第二晶体管T2传输给像素电极PX以使像素电极PX充电。
此外，上述多个亚像素可以为第一颜色亚像素110、第二颜色亚像素111或第三颜色亚像素112能够分别用于构成三基色的单色光。例如第一颜色亚像素110为红色(R)亚像素，第二颜色亚像素111为绿色(G)亚像素，第三颜色亚像素112为蓝色(B)亚像素。上述第一颜色亚像素110、第二颜色亚像素111以及第三颜色亚像素112可以构成一个像素单元。此外，本发明实施例对第一颜色亚像素110、第二颜色亚像素111或第三颜色亚像素112的颜色不做限定，例如可以为青色光、品红光以及黄光。
以下通过具体的示例，对设置有指纹识别装置的阵列基板进行详细的举例说明。
示例1
本示例1中，上述指纹识别装置设置于上述显示区域40。
例如，可以在如图6所示的每一个亚像素01内设置一个如图2所示的指纹识别单元02。具体的，如图7所示，将指纹识别单元02中的第一晶体管 T1和光敏器件20设置于一个亚像素01中。
这样一来，可以在显示区域40实现指纹识别。
此外，第二栅线G2和数据线D能够交叉界定亚像素01，而第一栅线G1和读取信号线RL能够界定指纹识别单元02。因此，为了使得整个阵列基板上布线结构整齐，例如，第一栅线G1可以与第二栅线G2相平行，读取信号线RL可以与数据线D相平行。
示例2
本示例中，上述指纹识别装置同样设置于显示区域40，与示例1不同的是，本示例中并不是每个亚像素01中均设置有上述指纹识别单元02。
例如，可以在构成像素单元的多个亚像素当中的一个亚像素中设置上述指纹识别单元02。例如，当构成像素单元的亚像素包括第一颜色亚像素110、第二颜色亚像素111、第三颜色亚像素112时，该指纹识别单元02可以设置于第一颜色亚像素110、第二颜色亚像素111或第三颜色亚像素112中。例如，上述第一颜色、第二颜色以及第三颜色构成三基色。
例如，如图8所示，该显示区域40中像素单元包括第一颜色亚像素110、第二颜色亚像素111、第三颜色亚像素112以及白色亚像素113；在此情形下，例如，该白色亚像素113内可以设置有指纹识别单元02。
例如，该白色亚像素113用于透过背光源提供的白色光源，因此对于无需对液晶施加电压就可以透过背光的显示装置而言，该白色亚像素113中可以无需制备像素电极和与该像素电极相连接的第二晶体管T2。在此情况下，该白色亚像素113内可以如图8所示，仅设置有第一晶体管T1和光敏器件20。
综上所述，示例1和示例2均是将指纹识别装置设置于显示区域。在此情形下，例如，显示区域40显示的某些指令需要通过指纹识别后才能够被触发。例如，银行交易信息需要点击确定按钮时，可以在用户按压屏幕上显示的虚拟确定按钮时对指纹进行识别，从而可以提高移动终端操作的安全性。
示例2相对于示例1而言，由于只需要在白色亚像素113中设置指纹识别单元02，因此不会对其它亚像素例如第一颜色亚像素110、第二颜色亚像素111以及第三颜色亚像素112的开口率造成影响。示例1相对于示例2而言，由于每个亚像素中均设置有上述指纹识别单元02，因此指纹采集精度较 高。
除此之外，指纹识别装置还可以设置于如图6所示的周边区域50，从而不会对显示区域40的开口率以及显示效果造成影响。例如，上述周边区域50用于设置驱动电路，例如用于对第一栅线G1、第二栅线G2进行逐行扫描的栅极驱动电路、用于对数据线D输出数据信号的源极驱动电路以及与图2所示的与读取信号线RL相连接的驱动IC等等驱动电路和元件。
本发明的实施例提供一种显示装置，包括如上所述的任意一种阵列基板。该显示装置具有与前述实施例提供的阵列基板相同的结构和有益效果。由于前述实施例已经对阵列基板的结构和有益效果进行了详细的举例说明，此处不再赘述。
本发明实施例提供一种指纹识别装置的制作方法。如图9所示，该方法包括：
S101、在衬底基板上形成如图5所示的第一晶体管T1的栅极302、如图3a所示的第一栅线G1以及第一电极层201。
例如，上述衬底基板可以为透明的玻璃基板或者树脂基板。通过在上述衬底基板上涂覆一层栅极金属层，然后再通过一次构图工艺形成上述栅极302、第一栅线G1以及第一电极层201的图案。
此外，当该指纹识别装置包括如图3a所示的电极信号线S时，该电极信号线S也可以在执行上述步骤S101的过程中同时形成。
例如，第一电极层201的厚度可以为10nm-100nm。
S102、在形成有第一晶体管T1的栅极302、第一栅线G1以及第一电极层201的基板表面，形成第一晶体管T1的栅极绝缘层303。
S103、在形成有栅极绝缘层303的基板表面，形成第一掺杂半导体层202。例如，第一掺杂半导体层202的厚度为20nm-70nm。
例如，在形成有栅极绝缘层303的基板表面涂覆A-si层，然后通过一次构图工艺形成未掺杂的半导体层的图案。接下来，通过离子掺杂工艺，对上述半导体层进行硼离子掺杂。由于硼离子为三价离子，与硅原子形成共价键时，会夺去硅原子的一个电子，使得硅原子多一个空穴，从而使得掺杂后的A-si金属层成为P型半导体层。接下来对诸如硼离子的掺杂离子进行活化处理。例如，活化处理的温度在550℃～650℃之间。
S104、在形成有第一掺杂半导体层202的基板表面，形成第一晶体管T1的有源层301。
例如，可以在形成有第一掺杂半导体层202的基板表面形成一层A-si层，然后通过一次构成工艺形成有源层301的图案。由于TFT的有源层301形成于第一掺杂半导体层202的步骤之后，因此上述步骤S103中对离子进行活化时需要的高温也不会对第一晶体管T1的有源层301造成影响。
S105、在形成有第一晶体管T1的有源层301的基板表面，形成读取信号线RL、第一晶体管T1的第一电极304和第二电极304’。例如，如图3a所示，第一晶体管T1的第一电极304与读取信号线RL相连接。
例如，可以在形成有有源层301的基板表面形成一层源漏极金属层，然后通过一次构图工艺形成读取信号线RL、第一晶体管T1的第一电极304和第二电极304’的图案。
需要说明的是，本发明实施例中晶体管的第一电极可以为源极，第二电极可以为漏极；或者，第一电极可以为漏极，第二电极可为源极。本发明实施例对此不做限定。
S106、在形成有读取信号线RL、第一晶体管T1的第一电极304和第二电极304’的基板表面，形成第二掺杂半导体层203。例如，第二掺杂半导体层203的厚度为20nm-70nm。
例如，在形成有读取信号线RL、第一晶体管T1的第一电极304和第二电极304’的基板表面，形成一层A-si层，然后通过一次构成工艺形成未掺杂的半导体层的图案。接下来，通过离子掺杂工艺对上述半导体层进行磷离子掺杂。由于磷离子为五价离子，因此与硅原子形成共价键时，会使得硅原子多出一个电子，从而使得该半导体层成为N型半导体层。
S107、在形成有第一晶体管T1的第一电极304和第二电极304’的基板表面，形成钝化层305，以及在钝化层305表面对应第一晶体管T1第二电极304’的位置形成过孔306。
例如，可以通过构图工艺形成钝化层305的图案，并形成上述过孔306。
例如，上述步骤可以在步骤S106之后进行，也可以在步骤S105之后且步骤S106之前进行。
S108、在形成第二掺杂半导体层203的基板表面，形成第二电极层204， 第二电极层204通过过孔306与第一晶体管T1的第二电极304’相连接。例如，第二电极层204的厚度为10nm-500nm。
例如，可以通过一次构图工艺在形成第二掺杂半导体层203的基板表面形成第二电极层204的图案。
由于第一掺杂半导体层和第二掺杂半导体层的交界面处具有耗尽区，该耗尽区内形成有半导体PN结，此时该光敏器件在光线激发作用下，在耗尽区会产生大量的空穴-电子对。在第一电极层与第二电极层之间形成的电场作用下，空穴和电子会分别向能级较高的价带和能级较低的导带移动，从而形成电流。此时当用户的手指按压该指纹识别装置时，手指上脊线和谷线反射的光线强度不同，从而激发光敏器件产生的电流大小不同。在此情况下，第一栅线可以将第一晶体管导通，从而使得与光敏器件的第二电极层相连接的读取信号线可以采集上述电流，以对手指的脊线和谷线进行识别。由于上述指纹识别单元中未使用棱镜和CCD，从而可以减小厚度。
进一步的，由于上述耗尽区03位于第一掺杂半导体层202和第二掺杂半导体层203的交界面处，因此该耗尽区03的厚度较薄，从而降低了光敏器件20在光线激发作用下产生的空穴-电子对的数量，该光敏器件20产生的电流的稳定性有待提高。
为了解决上述问题，如图4所示，该所述光敏器件20还可以包括位于第一掺杂半导体层202与第二掺杂半导体层203之间的耗尽层205。这样一来，通过耗尽层205可以增加上述耗尽区03的厚度，从而使得光敏器件20在光线激发作用下，能够增加耗尽区03的空穴-电子对数量，以提高光敏器件20产生的电流的稳定性，从而提高该光敏器件20的光电流特性。
例如，可以在进行上述步骤S104时，形成位于第一掺杂半导体层202表面的耗尽层205。例如，耗尽层205的厚度可以为500nm-1500nm。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。
本申请要求于2016年1月5日递交的第201610006717.6号中国专利申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一 部分。

Claims (19)

  1. 一种指纹识别装置，包括第一栅线和读取信号线，所述第一栅线和所述读取信号线交叉界定多个指纹识别单元，每个指纹识别单元中设置有光敏器件和第一晶体管；
    所述光敏器件包括第一电极层，以及依次位于所述第一电极层表面第一掺杂半导体层、第二掺杂半导体层以及第二电极层；所述第一电极层与所述第二电极层之间形成电场；所述第一掺杂半导体层和所述第二掺杂半导体层之间形成PN结；
    所述第一晶体管的栅极连接所述第一栅线，所述第一晶体管的第一电极连接所述读取信号线，所述第一晶体管的第二电极与所述第二电极层相连接。
  2. 根据权利要求1所述的指纹识别装置，其中，所述光敏器件还包括位于所述第一掺杂半导体层与所述第二掺杂半导体层之间的耗尽层。
  3. 根据权利要求2所述的指纹识别装置，其中，所述耗尽层与所述第一晶体管的有源层同层同材料。
  4. 根据权利要求1所述的指纹识别装置，其中，
    所述第一电极层与所述第一晶体管的栅极的同层同材料。
  5. 根据权利要求1所述的指纹识别装置，其中，
    构成所述第二电极层的材料包括透明导电材料。
  6. 根据权利要求1所述的指纹识别装置，其中，还包括与所述第一栅线平行的电极信号线，所述电极信号线与所述第一电极层相连接，用于向所述第一电极层提供电信号。
  7. 根据权利要求1所述的指纹识别装置，其中，所述第一电极层的厚度为10nm-100nm。
  8. 根据权利要求1所述的指纹识别装置，其中，所述第一掺杂半导体层或所述第二掺杂半导体层的厚度为20nm-70nm。
  9. 根据权利要求3所述的指纹识别装置，其中，所述耗尽层的厚度为500nm-1500nm。
  10. 根据权利要求1所述的指纹识别装置，其中，所述第二电极层的厚度为10nm-500nm。
  11. 一种阵列基板，包括如权利要求1-10任一项所述的指纹识别装置。
  12. 根据权利要求11所述的阵列基板，包括显示区域，指纹识别装置设置于所述显示区域。
  13. 根据权利要求12所述的阵列基板，其中，所述显示区域包括多个亚像素，一个所述亚像素内设置有一个指纹识别单元。
  14. 根据权利要求12所述的阵列基板，其中，所述显示区域包括构成像素单元的第一颜色亚像素、第二颜色亚像素、第三颜色亚像素以及白色亚像素；所述第一颜色、第二颜色以及所述第三颜色构成三基色；
    所述白色亚像素内设置有指纹识别单元。
  15. 根据权利要求12所述的阵列基板，包括横纵交叉的第二栅线和数据线；
    第一栅线与所述第二栅线相平行，读取信号线与所述数据线相平行。
  16. 根据权利要求11所述的阵列基板，还包括周边区域，所述指纹识别装置位于所述周边区域。
  17. 一种显示装置，包括如权利要求11-16任一项所述的阵列基板。
  18. 一种指纹识别装置的制作方法，包括：
    在衬底基板上形成第一晶体管的栅极、第一栅线以及第一电极层；
    在形成有所述第一晶体管的栅极、所述第一栅线以及所述第一电极层的基板表面，形成所述第一晶体管的栅极绝缘层；
    在形成有所述栅极绝缘层的基板表面，形成第一掺杂半导体层；
    在形成有所述第一掺杂半导体层的基板表面，形成所述第一晶体管的有源层；
    在形成有所述第一晶体管的有源层的基板表面，形成读取信号线、所述第一晶体管的第一电极和第二电极；所述第一晶体管的第一电极与所述读取信号线相连接；
    在形成有所述读取信号线、所述第一晶体管的第一电极和第二电极的基板表面，形成第二掺杂半导体层；
    在形成有所述第一晶体管的第一电极和第二电极的基板表面，形成钝化层，以及在所述钝化层表面对应所述第一晶体管第二电极的位置形成过孔；
    在形成所述第二掺杂半导体层的基板表面，形成第二电极层，所述第二 电极层通过所述过孔与所述第一晶体管的第二电极相连接。
  19. 根据权利要求18所述的指纹识别装置的制作方法，其中，在形成有所述第一掺杂半导体层的基板表面，形成所述第一晶体管的有源层的同时，形成位于所述第一掺杂半导体层表面的耗尽层。
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CN105095855A (zh) * 2015-06-26 2015-11-25 京东方科技集团股份有限公司 一种指纹识别器件、触控面板、输入设备及指纹识别方法
CN204808361U (zh) * 2015-07-29 2015-11-25 京东方科技集团股份有限公司 一种基板、指纹识别传感器、指纹识别装置
CN105550662A (zh) * 2016-01-05 2016-05-04 京东方科技集团股份有限公司 一种指纹识别装置及其制作方法、阵列基板、显示装置

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