WO2017118036A1 - 像素驱动电路及其驱动方法、显示装置 - Google Patents

像素驱动电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2017118036A1
WO2017118036A1 PCT/CN2016/096076 CN2016096076W WO2017118036A1 WO 2017118036 A1 WO2017118036 A1 WO 2017118036A1 CN 2016096076 W CN2016096076 W CN 2016096076W WO 2017118036 A1 WO2017118036 A1 WO 2017118036A1
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Prior art keywords
transistor
module
control signal
terminal
voltage
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PCT/CN2016/096076
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English (en)
French (fr)
Inventor
王光兴
张斌
董殿正
张强
张衎
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US15/507,904 priority Critical patent/US10140922B2/en
Publication of WO2017118036A1 publication Critical patent/WO2017118036A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0871—Several active elements per pixel in active matrix panels with level shifting
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present disclosure relates to a pixel driving circuit, a driving method thereof, and a display device.
  • OLED organic light emitting diode
  • the OLED can be divided into passive matrix driving OLED (PMOLED) and active matrix driving OLED (AMOLED) according to the driving method, because the AMOLED display has low manufacturing cost and high Responsive speed, power saving, DC drive for portable devices, large operating temperature range, etc. are expected to become the next generation of new flat panel displays to replace liquid crystal displays (LCDs).
  • PMOLED passive matrix driving OLED
  • AMOLED active matrix driving OLED
  • each OLED includes a plurality of Thin Film Transistor (TFT) switching circuits.
  • TFT Thin Film Transistor
  • Embodiments of the present disclosure provide a pixel driving circuit, a driving method thereof, and a display device. It is possible to improve the defect that the display display brightness is uneven due to the threshold voltage.
  • a pixel driving circuit includes an input module, a compensation module, a driving module, a lighting module, and a control signal input module; the input module is connected to the first gate signal end, the data voltage end, and The compensation module is configured to transmit a signal of the data voltage terminal to the compensation module under control of the first gate signal terminal; the compensation module is connected to a threshold voltage control terminal and the driving module, and is configured to: Performing compensation of a threshold voltage on the driving module under control of the input module and the threshold voltage control terminal; the lighting module is connected to the first voltage terminal and the driving module; and the driving module is connected to the first control signal End, configured to drive the light emitting module to emit light under the control of the first control signal end; the control signal input module is connected to the first control signal end, the second control signal end, the third control signal end, a second voltage terminal and a third voltage terminal for controlling under the control of the second control signal end and the third control signal end Said second signal transmitting terminal voltage or the third voltage terminal to
  • the input module includes a first transistor, a gate of the first transistor is connected to the first gate signal terminal, a first pole is connected to the data voltage terminal, and a second pole is connected to the compensation module. connection.
  • the compensation module includes a second transistor and a storage capacitor; a gate of the second transistor is connected to the threshold voltage control terminal, a first pole is connected to the other end of the storage capacitor, and the second pole is connected to the driving module. Connected.
  • the driving module includes a third transistor; a gate of the third transistor is connected to another end of the storage capacitor, a first pole is connected to the first control signal end, and a second pole is connected to the light emitting module .
  • the control signal input module includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; a gate of the fourth transistor is connected to the second control signal end, and the first pole is connected to the a second voltage end, the second pole is connected to the first control signal end; the gate of the fifth transistor is connected to the third control signal end, the first pole is connected to the second voltage end, the second pole Connected to the first control signal end; the gate of the sixth transistor is connected to the second control signal end, the first pole is connected to the first control signal end, and the second pole is connected to the seventh transistor The second pole is connected; the gate of the seventh transistor is connected to the third control signal end, and the first pole is connected to the third voltage end.
  • the input module further includes an eighth transistor; a gate of the eighth transistor is connected to the second gate signal terminal, a first pole is connected to the data voltage terminal, and a second pole is connected to the compensation module. .
  • a display device comprising any of the pixel driving circuits as described above.
  • the display device further includes a display panel having a plurality of gate lines and data lines crossing horizontally and vertically, the gate lines and the data lines intersecting to define a plurality of pixel units;
  • the control signal input module and the compensation module in the first pixel unit of the first column are shared with the control signal input module and the compensation module in the second pixel unit of the J+1th row and the 1st column; wherein J ⁇ 1, I ⁇ 2, J and I are positive integers.
  • the compensation module includes a first transistor and an eighth transistor
  • the first transistor is located in the first pixel unit
  • the eighth transistor is located in the second pixel unit.
  • a method for driving any one of the above pixel driving circuits comprising: transmitting, by a control signal input module, a signal of a third voltage terminal to a first control signal during a reset phase Ending, resetting the driving module; in the compensation phase, transmitting, by the control signal input module, a signal of the second voltage end to the first control signal end, turning on the driving module, and at the input module and the threshold Under the control of the voltage control terminal, the threshold voltage is compensated by the compensation module; in the writing phase, the signal of the second voltage terminal is transmitted by the control signal input module to the first control signal end, Turning on the driving module; and writing, by the input module and the threshold voltage control end, a signal input by the data voltage terminal to the driving module; in a lighting phase, the control signal input module Transmitting a signal of the two voltage terminals to the first control signal terminal, turning on the driving module; and at the input module and Under the control of the voltage control terminal of said threshold,
  • Embodiments of the present disclosure provide a pixel driving circuit, a driving method thereof, and a display device.
  • the pixel driving circuit includes an input module, a compensation module, a driving module, a lighting module, and a control signal input module.
  • the input module is connected to the first gate signal terminal, the data voltage terminal, and the compensation module, and is configured to control the data voltage terminal under the control of the first gate signal terminal
  • the signal is sent to the compensation module.
  • the compensation module is further connected to the threshold voltage control terminal and the driving module for performing compensation of the threshold voltage of the driving module under the control of the input module and the threshold voltage control terminal.
  • the light emitting module is connected to the first voltage end and the driving module, and the driving module is further connected to the first control signal end for driving the light emitting module to emit light under the control of the first control signal end.
  • the control signal input module is connected to the first control signal end, the second control signal end, the third control signal end, the second voltage end and the third voltage end for controlling under the second control signal end and the third control signal end, The signal of the second voltage terminal or the third voltage terminal is transmitted to the first control signal terminal.
  • the signal of the second voltage terminal or the third voltage terminal can be output to the first control signal terminal at different stages as needed to perform the driving module under the control of the first control signal terminal. Reset, or enable the drive module to drive the illumination module to illuminate. Since the compensation module can perform threshold voltage compensation on the driving module before the light emitting module emits light, the problem of uneven display brightness due to the drift of the threshold voltage can be avoided.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic view showing a specific structure of each module in FIG. 1;
  • FIG. 3 is a schematic diagram showing another specific structure of each module in FIG. 1;
  • FIG. 4 is a schematic view showing the arrangement of TFTs on a display panel using the pixel driving circuit of FIG. 3;
  • FIG. 5 is a timing chart of signals for controlling the pixel driving circuit shown in FIG. 2 or FIG. 3;
  • FIG. 6 is a timing diagram of the first gate signal terminal and the second gate signal terminal of FIG. 3;
  • FIG. 7 is a schematic view showing the arrangement of TFTs on a display panel provided with the pixel driving circuit shown in FIG. 3;
  • FIG. 8 is a flowchart of a driving method of a pixel driving circuit according to an embodiment of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present disclosure.
  • the pixel driving circuit may include an input module 60 , a compensation module 10 , a driving module 30 , a lighting module 20 , and a control signal input module 40 .
  • the input module 60 is connected to the first gate signal terminal Gn, the data voltage terminal Dm, and the compensation module 10 for transmitting the signal of the data voltage terminal Dm under the control of the first gate signal terminal Gn. To the compensation module 10.
  • the compensation module 10 is further connected to the threshold voltage control terminal Em and the driving module 30 for performing compensation of the threshold voltage of the driving module 30 under the control of the input module 60 and the threshold voltage control terminal Em.
  • the light emitting module 20 is connected to the first voltage terminal VSS and the driving module 30.
  • the driving module 30 is further connected to the first control signal terminal S1 for driving the light emitting module 20 to emit light under the control of the first control signal terminal S1.
  • the control signal input module 40 is connected to the first control signal terminal S1, the second control signal terminal S2, the third control signal terminal S3, the second voltage terminal VDD and the third voltage terminal VEE for the second control signal terminal S2 and the Under the control of the three control signal terminals S3, the signal of the second voltage terminal VDD or the third voltage terminal VEE is transmitted to the first control signal terminal S1.
  • the first voltage terminal VSS, the third voltage terminal VEE are input to the low level or the grounding process, and the second voltage terminal VDD is input to the high level as an example.
  • Embodiments of the present disclosure provide a pixel driving circuit including an input module, a compensation module, a driving module, a lighting module, and a control signal input module.
  • the input module is connected to the first gate signal terminal, the data voltage terminal, and the compensation module, and is configured to transmit the signal of the data voltage terminal to the compensation module under the control of the first gate signal terminal.
  • the compensation module is further connected to the threshold voltage control terminal and the driving module for performing compensation of the threshold voltage of the driving module under the control of the input module and the threshold voltage control terminal.
  • the light emitting module is connected to the first voltage end and the driving module, and the driving module is further connected to the first control signal end for controlling at the first control signal end
  • the lower illumination module is driven to emit light.
  • the control signal input module is connected to the first control signal end, the second control signal end, the third control signal end, the second voltage end and the third voltage end for controlling under the second control signal end and the third control signal end,
  • the signal of the second voltage terminal or the third voltage terminal is transmitted to the first control signal terminal.
  • the signal of the second voltage terminal or the third voltage terminal can be transmitted to the first control signal terminal at different stages as needed to perform the driving module under the control of the first control signal terminal. Reset, or enable the drive module to drive the illumination module to illuminate. Since the compensation module can perform threshold voltage compensation on the driving module before the light emitting module emits light, the problem of uneven display brightness due to the drift of the threshold voltage can be avoided.
  • FIG. 2 is a schematic view showing a specific structure of each module in FIG. 1.
  • the input module 60 can include a first transistor T1.
  • the gate of the first transistor T1 is connected to the first gate signal terminal Gn, the first pole is connected to the data voltage terminal Dm, and the second pole is connected to the compensation module 10.
  • the compensation module 10 can include a second transistor T2 and a storage capacitor C.
  • the gate of the second transistor T2 is connected to the threshold voltage control terminal Em, the first pole is connected to one end of the storage capacitor C (node a), and the second pole is connected to the driving module 30.
  • the structure of the input module 60 is as described above, its second pole is connected to the other end (node b) of the storage capacitor C.
  • the drive module 30 can include a third transistor T3.
  • the second pole of the second transistor T2 is connected to the second pole of the third transistor T3.
  • the gate of the third transistor T3 is connected to one end (node a) of the storage capacitor C, the first pole is connected to the first control signal terminal S1, and the second pole is connected to the light emitting module 20.
  • the light emitting module 20 includes an organic light emitting diode OLED.
  • the anode of the organic light emitting diode OLED is connected to the driving module 30, and the cathode is connected to the first voltage terminal VSS.
  • control signal input module 40 may include a fourth transistor T4 and a fifth transistor. T5, sixth transistor T6, and seventh transistor T7.
  • the gate of the fourth transistor T4 is connected to the second control signal terminal S2, the first pole is connected to the second voltage terminal VDD, and the second pole is connected to the first control signal terminal S1.
  • the gate of the fifth transistor T5 is connected to the third control signal terminal S3, the first pole is connected to the second voltage terminal VDD, and the second pole is connected to the first control signal terminal S1.
  • the gate of the sixth transistor T6 is connected to the second control signal terminal S2, the first electrode is connected to the first control signal terminal S1, and the second electrode is connected to the second electrode of the seventh transistor T7.
  • the gate of the seventh transistor T7 is connected to the third control signal terminal S3, and the first pole is connected to the third voltage terminal VEE.
  • the above pixel circuit may be disposed in each pixel unit of the display panel.
  • TFTs thin film transistors
  • Thin film transistors that are typically located in pixel cells of the same column can be connected to the same data line.
  • FIG. 3 shows another specific structural diagram of each module in FIG. 1.
  • 4 is a schematic view showing the arrangement of TFTs on a display panel employing the pixel driving circuit of FIG.
  • the TFTs on the display panel are arranged in a zigzag pattern. That is, the TFTs in the pixel unit of the same column are not connected to the same data line. Instead, any two sub-pixels located in two adjacent rows (L1 and L2) and located in adjacent two columns (H1 and H2) are connected to the same data line.
  • the first pixel unit 1 and the second pixel unit 2 wherein the TFT of the first pixel unit 1 and the TFT of the second pixel unit 2 are connected to the same data line.
  • the input module 60 may include an eighth transistor T8.
  • the first transistor T1 is located in the first pixel unit 1 and the eighth transistor T8 is located in the second pixel unit 2.
  • the gate of the eighth transistor T8 is connected to the second gate signal terminal G(n+1)
  • the first pole is connected to the data voltage terminal Dm
  • the second pole is connected to one end (node b) of the storage capacitor C.
  • the block 70 in FIG. 3 indicates an omission of the remaining power supply devices other than the first transistor T1 or the eighth transistor T8 in the above pixel driving circuit.
  • the first transistor T1 and the eighth transistor T8 share a data line Data for receiving the signal input from the data voltage terminal Dm.
  • First crystal The gate of the tube T1 is connected to the first gate line Gate1, and the first gate line Gate1 is for receiving a signal input by the first gate signal terminal Gn.
  • the second gate line Gate2 is for receiving a signal input by the second gate signal terminal G(n+1).
  • the first gate line Gate1 and the second gate line Gate2 are any two adjacent gate lines of all the gate lines on the display panel.
  • the first transistor T1 is turned on, and the input signal of the data signal terminal Dm can pass through the first transistor.
  • T1 is transmitted to the gate of the driving transistor (third transistor T3) located at the first pixel unit 1.
  • the eighth transistor T2 is turned on, and the signal input from the data signal terminal Dm can be transmitted to the driving transistor located in the second pixel unit 2 through the eighth transistor T8 (No. The gate of the three transistor T3).
  • the transistors provided in the embodiments of the present disclosure may all be N transistors or P-type transistors; or some of them are N-type transistors, and the other part is P-type transistors. This disclosure does not limit this.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 are P-type transistors
  • the sixth transistor T6 and the seventh transistor T7 are An explanation is given for an N-type transistor as an example.
  • the first pole of the transistor may be a source, and the second pole may be a drain; or the first pole may be a drain and the second pole may be a source. This disclosure does not limit this.
  • the above transistor may be an enhancement transistor or a depletion transistor. This disclosure does not limit this.
  • FIG. 5 shows a signal timing chart for controlling the pixel driving circuit shown in FIG. 2 or 3.
  • the driving process of the pixel driving circuit will be described in detail below with reference to the pixel driving circuit shown in FIG. 2 or FIG. 3 in conjunction with the timing chart of the control signal shown in FIG. 5.
  • the sixth transistor T6 and the seventh transistor T7 are turned on, and the fourth transistor T4 and the fifth transistor T5 are turned off.
  • the low level of the third voltage terminal VEE input passes through the seventh crystal
  • the body tube T7 and the sixth transistor T6 are transmitted to the first signal control terminal S1.
  • the first gate signal terminal Gn is input with a low level, the first transistor T1 is turned on, and the first data voltage Vdata input from the data voltage terminal Dm is transmitted to the one end (node b) of the storage capacitor C through the first transistor T1.
  • the threshold voltage control terminal Em inputs a low level to turn on the second transistor T2 such that the gate and the second electrode of the third transistor T3 as a driving transistor are turned on.
  • the first signal control terminal S1 inputs the voltage of the third voltage terminal VEE
  • Vth is the threshold voltage of the third transistor T3.
  • the voltage difference across the storage capacitor Vb-Va Vdata-VEE-Vth.
  • the first phase P1 is a reset phase
  • the third voltage terminal VEE is input with a low level, so that the gate of the driving transistor (the third transistor T3) can be reset to avoid the previous one.
  • the voltage remaining in the gate of the third transistor T3 of the frame picture affects the frame of the frame.
  • the fourth transistor T4 and the fifth transistor T5 are turned on, and the sixth transistor T6 and the seventh transistor T7 are turned off.
  • the high level of the second voltage terminal VDD input is transmitted to the first signal control terminal S1 through the fourth transistor T4 and the fifth transistor T5.
  • the first gate signal terminal Gn inputs a low level, and the first transistor T1 remains in an on state.
  • the first data voltage Vdata input from the data voltage terminal Dm is transmitted to the one end (node b) of the storage capacitor C through the first transistor T1.
  • the threshold voltage control terminal Em inputs a low level to turn on the second transistor T2 such that the gate and the second electrode of the third transistor T3 as a driving transistor are turned on.
  • the second phase P2 is a compensation phase of the threshold voltage for compensating for the threshold voltage of the third transistor T3.
  • the third control signal terminal S3 inputs a high level, so the fourth transistor T4 and the seventh transistor T7 are turned on, and the fifth transistor T5 and the sixth transistor T6 are turned on. It is in the cutoff state.
  • the high level input by the second voltage terminal VDD is transmitted to the first signal control terminal S1 through the fourth transistor T4.
  • the threshold voltage control terminal Em inputs a high level so that the second transistor T2 is in an off state.
  • the first gate signal terminal Gn is input with a low level, the first transistor T1 remains in an on state, and the second data voltage Vref input by the data voltage terminal Dm is transmitted to the one end (node b) of the storage capacitor C through the first transistor T1.
  • the voltage at one end of the storage capacitor C is changed from the first data voltage Vdata to the second data voltage Vref.
  • the voltage Va of the other end of the storage capacitor (node a) is Vref-Vdata+VDD+Vth.
  • the third phase P3 is a data writing phase for writing the second data voltage Vref to the gate of the third transistor T3.
  • the second control signal terminal S2 inputs a high level
  • the third control signal terminal S3 inputs a low level
  • the fifth transistor T5 and the sixth transistor T6 are turned on
  • the fourth transistor T4 and the seventh transistor T7 are turned on. It is in the cutoff state.
  • the high level of the second voltage terminal VDD input is transmitted to the first signal control terminal S1 through the fifth transistor T5.
  • the first gate signal terminal Gn inputs a high level, and the first transistor T1 is turned off.
  • the threshold voltage control terminal Em inputs a high level so that the second transistor T2 is in an off state. At this time, the current flowing through the third transistor T3 drives the light emitting device OLED to emit light. Therefore, the fourth phase P1 is the illuminating phase.
  • K is the current constant associated with the third transistor T3
  • Vgs is the voltage of the gate of the third transistor T3 with respect to the source stage, that is, the voltage of the node a relative to the node e at this time.
  • the Vths between different pixel units are not the same, and the Vth in the same pixel may drift over time, which will cause a difference in display brightness. Since this difference is related to the previously displayed image, it often appears as an afterimage phenomenon.
  • the current I flowing through the third transistor T3 is independent of the threshold voltage Vth of the third transistor M3. Therefore, it is possible to avoid the influence of the inconsistency or drift of the threshold voltage Vth of the third transistor T3 on the current flowing through the light emitting device, and the uniformity of the display brightness of the display device is remarkably improved.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 are P-type transistors
  • the sixth transistor is The description of the case where the T6 and the seventh transistor T7 are N-type transistors is taken as an example.
  • the control signal in FIG. 5 also needs to change accordingly.
  • the N-type transistor needs to be turned on, its gate can receive a high level
  • the P-type transistor needs to be turned on its gate can receive a low level.
  • the gate line on the display panel is generally in a progressive scan manner, that is, after the first gate signal terminal Gn inputs a gate driving signal to the first gate line Gate1 as shown in FIG. 4, the second gate signal terminal G(n+1) will input a gate drive signal to the second gate line Gate2 as shown in FIG.
  • FIG. 6 is a timing chart showing the gate lines of the first gate signal terminal Gn and the second gate signal terminal G(n+1) input in FIG.
  • the enable signal terminal OE is used to input an enable signal for controlling the first gate signal terminal Gn and the second gate signal terminal G(n+1). Since the first transistor T1 and the eighth transistor T8 are respectively located in two adjacent rows, the above-described driving process is only for the description of the first pixel unit 1 having the first transistor T1. The driving process of the second pixel unit 2 having the eighth transistor T8 is the same as described above, except that the turning-on and turning-off of the eighth transistor T8 are controlled by the second gate signal terminal G(n+1). Specific drive The process will not be repeated here.
  • the embodiment of the present disclosure further provides a display device including any of the pixel driving circuits as described above, having the same structure and advantageous effects as the pixel driving circuit provided in the foregoing embodiment. Since the foregoing embodiment has been described in detail for the structure and advantageous effects of the pixel driving circuit, details are not described herein again.
  • the display device provided by the embodiments of the present disclosure may be a display device having a current-driven light emitting device including an LED display or an OLED display.
  • a display panel is also included.
  • Fig. 7 is a view showing the arrangement of TFTs on the display panel provided with the pixel driving circuit shown in Fig. 3.
  • the display panel has a plurality of gate lines Gate and data lines Data which are vertically and horizontally intersected.
  • the gate line Gate and the data line Data cross define a plurality of pixel units.
  • control signal input module 40 and the compensation module 10 in the first pixel unit 1 of the Jth row and the first column are arranged in the second pixel unit 2 located in the J+1th row and the 1st column.
  • the control signal input module 40 and the compensation module 10 can be shared.
  • J ⁇ 1, I ⁇ 2, and J and I are positive integers.
  • the remaining modules can be shared with other pixel units, so that it is not necessary to provide the above-mentioned control signal input module 40 and the light emitting module in each pixel unit. 20, thereby increasing the aperture ratio of the pixel.
  • the compensation module 10 may include a first transistor T1 and an eighth transistor T8.
  • the first transistor T1 is located in the first pixel unit 1 and the eighth transistor T8 is located in the second pixel unit 2.
  • the first transistor T1 is turned on, and the input signal of the data signal terminal Dm can be transmitted through the first transistor T1.
  • the driving transistor third transistor T3 of the first pixel unit 1.
  • the eighth transistor T2 When the second gate signal terminal G(n+1) inputs a signal, the eighth transistor T2 is turned on, and the input signal of the data signal terminal Dm can be transmitted to the driving transistor located in the second pixel unit 2 through the eighth transistor T8 (No. The gate of the three transistor T3). Thereby, it is possible to drive the pixel unit to emit light when the TFT is arranged in a zigzag pattern.
  • the display panel may further include a gate for inputting a driving signal to the gate line Gate A pole driver 50, and a source driver 51 for inputting a data signal to the data line Date.
  • FIG. 8 shows a flowchart of a driving method for driving any of the above pixel driving circuits according to an embodiment of the present disclosure. As shown in FIG. 8, the driving method includes:
  • Step S101 In the reset phase, that is, the first phase P1 shown in FIG. 6, the control signal input die 40 inputs the signal of the third voltage terminal VEE to the first control signal terminal S1, and the driving module 30 performs resetting.
  • the second control signal terminal S2 and the third control signal terminal S3 are both input at a high level, the sixth transistor T6 and the seventh transistor T7 are turned on, and the fourth transistor T4 and the fifth transistor T5 are in an off state.
  • the low level input by the third voltage terminal VEE is transmitted to the first signal control terminal S1 through the seventh transistor T7 and the sixth transistor T6.
  • the first gate signal terminal Gn is input with a low level, the first transistor T1 is turned on, and the first data voltage Vdata input from the data voltage terminal Dm is transmitted to the one end (node b) of the storage capacitor C through the first transistor T1.
  • the threshold voltage control terminal Em inputs a low level to turn on the second transistor T2 such that the gate and the second electrode of the third transistor T3 as a driving transistor are turned on.
  • the first signal control terminal S1 inputs the voltage of the third voltage terminal VEE
  • Vth is the threshold voltage of the third transistor T3.
  • the voltage difference across the storage capacitor Vb-Va Vdata-VEE-Vth.
  • Step S102 in the compensation phase, that is, the second phase P2 shown in FIG. 6, the control signal input module 40 inputs the signal of the second voltage terminal VDD to the first control signal terminal S1, turns on the driving module 30; and at the input module Under the control of the threshold voltage control terminal Em and the threshold voltage control terminal Em, the compensation module 10 compensates the threshold voltage of the drive module 30.
  • the second control signal terminal S2 and the third control signal terminal S3 are both input with a low level, the fourth transistor T4 and the fifth transistor T5 are turned on, and the sixth transistor T6 and the seventh transistor T7 are in an off state.
  • the high level input by the second voltage terminal VDD is transmitted to the first signal control terminal S1 through the seventh transistor T7 and the sixth transistor T6.
  • the first gate signal terminal Gn inputs a low level, and the first transistor T1 remains in an on state.
  • the first data voltage Vdata input from the data voltage terminal Dm is transmitted to the one end (node b) of the storage capacitor C through the first transistor T1.
  • the threshold voltage control terminal Em inputs a low level,
  • the second transistor T2 is turned on, so that the gate and the second electrode of the third transistor T3 as a driving transistor are turned on.
  • the first signal control terminal S1 inputs the voltage of the second voltage terminal VDD
  • the gate voltage Va of the third transistor T3 and the voltage Vd of the second electrode are both VDD+Vth.
  • the voltage difference across the storage capacitor Vb-Va Vdata-VDD-Vth.
  • Step S103 in the writing phase, that is, the third phase P3 shown in FIG. 6, the control signal input module 40 inputs the signal of the second voltage terminal VDD to the first control signal terminal S1, turns on the driving module 30; Under the control of the module 60 and the threshold voltage control terminal Em, a signal input from the data voltage terminal Dm is written to the drive module 30.
  • the second control signal terminal S2 inputs a low level
  • the third control signal terminal S3 inputs a high level
  • the fourth transistor T4 and the seventh transistor T7 are turned on
  • the fifth transistor T5 and the sixth transistor T6 are turned off. status.
  • the high level input by the second voltage terminal VDD is transmitted to the first signal control terminal S1 through the fourth transistor T4.
  • the threshold voltage control terminal Em inputs a high level so that the second transistor T2 is in an off state.
  • the first gate signal terminal Gn is input with a low level, the first transistor T1 remains in an on state, and the second data voltage Vref input by the data voltage terminal Dm is transmitted to the one end (node b) of the storage capacitor C through the first transistor T1.
  • the voltage at one end of the storage capacitor C is changed from the first data voltage Vdata to the second data voltage Vref.
  • the voltage Va of the other end of the storage capacitor (node a) is Vref-Vdata+VDD+Vth.
  • Step S104 the lighting phase, that is, the fourth phase P4 shown in FIG. 6, the control signal input module 40 inputs the signal of the second voltage terminal VDD to the first control signal terminal S1, turns on the driving module 30; and at the input module 60 Under the control of the threshold voltage control terminal Em, the driving module 30 drives the light emitting module 20 to emit light.
  • the second control signal terminal S2 inputs a high level
  • the third control signal terminal S3 inputs a low level
  • the fifth transistor T5 and the sixth transistor T6 are turned on
  • the fourth transistor T4 and the seventh transistor T7 are turned off. status.
  • the high level of the second voltage terminal VDD input is transmitted to the first signal control terminal S1 through the fifth transistor T5.
  • the first gate signal terminal Gn inputs a high level, and the first transistor T1 is turned off.
  • the threshold voltage control terminal Em inputs a high level so that the second transistor T2 is in an off state. At this time, the current flowing through the third transistor T3 drives the light emitting device OLED to emit light. Therefore, the fourth phase P1 is the illuminating phase.
  • K is the current constant associated with the third transistor T3
  • Vgs is the voltage of the gate of the third transistor T3 with respect to the source stage, that is, the voltage of the node a relative to the node e at this time.
  • the Vths between different pixel units are not the same, and the Vth in the same pixel may drift over time, which will cause a difference in display brightness. Since this difference is related to the previously displayed image, it is often Presented as an afterimage phenomenon.
  • the current Id flowing through the third transistor T3 is independent of the threshold voltage Vth of the third transistor M3. Therefore, it is possible to avoid the influence of the inconsistency or drift of the threshold voltage Vth of the third transistor T3 on the current flowing through the light emitting device, and the uniformity of the display brightness of the display device is remarkably improved.
  • the foregoing program may be stored in a computer readable storage medium, and the program is executed when executed.
  • the foregoing steps include the steps of the foregoing method embodiments; and the foregoing storage medium includes: a medium that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

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Abstract

提供一种像素驱动电路及其驱动方法、显示装置。该像素驱动电路包括输入模块（60）、补偿模块（10）、驱动模块（30）、发光模块（20）以及控制信号输入模块（40）。输入模块（60）用于在第一栅极信号端的控制下，将数据电压端的信号传送至补偿模块（10）。补偿模块（10）用于在输入模块（60）以及阈值电压控制端的控制下，对驱动模块（30）进行阈值电压的补偿；驱动模块（30）用于在第一控制信号端的控制下驱动发光模块（20）进行发光；控制信号输入模块（40）用于在第二控制信号端和第三控制信号端的控制下，将第二电压端或第三电压端的信号传送至第一控制信号端，用于驱动像素单元发光。能够改善由于阈值电压引起的显示器显示亮度不均匀的不良现象。

Description

像素驱动电路及其驱动方法、显示装置 技术领域
本公开涉及一种像素驱动电路及其驱动方法、显示装置。
背景技术
随着显示技术的急速进步，作为显示装置核心的半导体元件技术也随之得到了飞跃性的进步。对于现有的显示装置而言，有机发光二极管(Organic Light Emitting Diode，OLED)作为一种电流型发光器件，因其所具有的自发光、快速响应、宽视角和可制作在柔性衬底上等特点而越来越多地被应用于高性能显示领域当中。
OLED按驱动方式可分为无源矩阵驱动有机发光二极管(Passive Matrix Driving OLED，PMOLED)和有源矩阵驱动有机发光二极管(Active Matrix Driving OLED，AMOLED)两种，由于AMOLED显示器具有低制造成本、高应答速度、省电、可用于便携式设备的直流驱动、工作温度范围大等等优点而可望成为取代液晶显示器(liquid crystal display，LCD)的下一代新型平面显示器。
在现有的AMOLED显示面板中，每个OLED均包括多个薄膜晶体管(Thin Film Transistor，TFT)开关电路。然而由于生产工艺和多晶硅的特性，导致在大面积玻璃基板上制作的TFT开关电路时，常常在诸如阈值电压Vth、迁移率等电学参数上出现波动，从而使得流经AMOLED显示面板中OLED器件的电流不仅会随着TFT长时间导通所产生的导通电压应力的变化而改变，而且其还会随着TFT的阈值电压Vth漂移而有所不同。如此一来，将会影响到显示器的亮度均匀性与亮度恒定性。从而降低显示器的画面品质和质量。
发明内容
本公开的实施例提供一种像素驱动电路及其驱动方法、显示装置， 能够改善由于阈值电压引起的显示器显示亮度不均匀的不良现象。
在本公开实施例的一方面，提供一种像素驱动电路，包括输入模块、补偿模块、驱动模块、发光模块以及控制信号输入模块；所述输入模块连接第一栅极信号端、数据电压端以及所述补偿模块，用于在所述第一栅极信号端的控制下，将所述数据电压端的信号传送至所述补偿模块；所述补偿模块连接阈值电压控制端以及所述驱动模块，用于在所述输入模块、所述阈值电压控制端的控制下，对所述驱动模块进行阈值电压的补偿；所述发光模块连接第一电压端和所述驱动模块；所述驱动模块连接第一控制信号端，用于在所述第一控制信号端的控制下驱动所述发光模块进行发光；所述控制信号输入模块连接所述第一控制信号端、第二控制信号端、第三控制信号端、第二电压端以及第三电压端，用于在所述第二控制信号端和所述第三控制信号端的控制下，将所述第二电压端或所述第三电压端的信号传送至所述第一控制信号端。
可选择地，所述输入模块包括第一晶体管，所述第一晶体管的栅极连接所述第一栅极信号端、第一极连接所述数据电压端，第二极与所述补偿模块相连接。
可选择地，所述补偿模块包括第二晶体管以及存储电容；所述第二晶体管的栅极连接所述阈值电压控制端，第一极连接所述存储电容的另一端，第二极与驱动模块相连接。
可选择地，所述驱动模块包括第三晶体管；所述第三晶体管的栅极连接所述存储电容的另一端，第一极连接所述第一控制信号端，第二极连接所述发光模块。
可选择地，所述控制信号输入模块包括第四晶体管、第五晶体管、第六晶体管以及第七晶体管；所述第四晶体管的栅极连接所述第二控制信号端，第一极连接所述第二电压端，第二极与所述第一控制信号端相连接；所述第五晶体管的栅极连接所述第三控制信号端，第一极连接所述第二电压端，第二极与所述第一控制信号端相连接；所述第六晶体管的栅极连接所述第二控制信号端，第一极连接所述第一控制信号端，第二极与所述第七晶体管的第二极相连接；所述第七晶体管的栅极连接所述第三控制信号端，第一极与所述第三电压端相连接。
可选择地，所述输入模块还包括第八晶体管；所述第八晶体管的栅极连接第二栅极信号端，第一极连接所述数据电压端，第二极与所述补偿模块相连接。
在本公开实施例的另一方面，提供一种显示装置，包括如上所述的任意一种像素驱动电路。
可选择地，所述显示装置还包括显示面板，所述显示面板具有横纵交叉的多条栅线和数据线，所述栅线和所述数据线交叉界定多个像素单元；位于第J行、第I列的第一像素单元中的控制信号输入模块和补偿模块，与位于第J+1行、第I-1列的第二像素单元中的控制信号输入模块和补偿模块共用；其中，J≥1，I≥2，J、I均为正整数。
可选择地，当所述补偿模块包括第一晶体管和第八晶体管时，所述第一晶体管位于所述第一像素单元，所述第八晶体管位于所述第二像素单元。
在本公开实施例的又一方面，提供一种用于驱动上述任意一种像素驱动电路的方法，包括：在重置阶段，由控制信号输入模块将第三电压端的信号传送至第一控制信号端，对驱动模块进行重置；在补偿阶段，由所述控制信号输入模块将第二电压端的信号传送至所述第一控制信号端，开启所述驱动模块，并且在输入模块以及所述阈值电压控制端的控制下，由所述补偿模块对所述驱动模块进行阈值电压的补偿；在写入阶段，由所述控制信号输入模块将第二电压端的信号传送至所述第一控制信号端，开启所述驱动模块；并且在所述输入模块以及所述阈值电压控制端的控制下，将所述数据电压端输入的信号写入所述驱动模块；发光阶段，由所述控制信号输入模块将第二电压端的信号传送至所述第一控制信号端，开启所述驱动模块；并且在所述输入模块以及所述阈值电压控制端的控制下，由所述驱动模块驱动发光模块进行发光。
本公开实施例提供一种像素驱动电路及其驱动方法、显示装置。其中，该像素驱动电路包括输入模块、补偿模块、驱动模块、发光模块以及控制信号输入模块。可替换地，输入模块连接第一栅极信号端、数据电压端以及补偿模块，用于在第一栅极信号端的控制下，将数据电压端 的信号传送至补偿模块。而补偿模块还连接阈值电压控制端以及驱动模块，用于在输入模块、阈值电压控制端的控制下，对驱动模块进行阈值电压的补偿。发光模块连接第一电压端和驱动模块，该驱动模块还连接第一控制信号端，用于在第一控制信号端的控制下驱动发光模块进行发光。控制信号输入模块连接第一控制信号端、第二控制信号端、第三控制信号端、第二电压端以及第三电压端，用于在第二控制信号端和第三控制信号端的控制下，将第二电压端或第三电压端的信号传送至第一控制信号端。
这样一来，通过采用控制信号输入模块，能够在不同阶段根据需要将第二电压端或第三电压端的信号输出至第一控制信号端，以在该第一控制信号端的控制下对驱动模块进行重置，或者使得驱动模块能够驱动发光模块发光。由于在发光模块发光前，补偿模块可以对驱动模块进行阈值电压补偿，因此能够避免由于阈值电压的漂移造成显示亮度不均的问题。
附图说明
图1为本公开实施例提供的一种像素驱动电路的结构示意图；
图2为图1中各个模块的一种具体结构示意图；
图3为图1中各个模块的另一种具体结构示意图；
图4为采用图3中的像素驱动电路的显示面板上TFT的排布示意图；
图5为用于控制图2或图3所示的像素驱动电路的信号时序图；
图6为图3中第一栅极信号端和第二栅极信号端的时序示意图；
图7为设置有图3所示的像素驱动电路的显示面板上TFT的排布示意图；
图8为本公开实施例提供的一种像素驱动电路的驱动方法流程图。
具体实施方式
下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。
图1示出本公开实施例提供一种像素驱动电路的结构示意图。如图1所示，该像素驱动电路可以包括输入模块60、补偿模块10、驱动模块30、发光模块20以及控制信号输入模块40。
在该像素驱动电路中，输入模块60连接第一栅极信号端Gn、数据电压端Dm以及补偿模块10，用于在第一栅极信号端Gn的控制下，将数据电压端Dm的信号传送至补偿模块10。
除了与输入模块60连接外，补偿模块10还连接阈值电压控制端Em以及驱动模块30，用于在上述输入模块60、阈值电压控制端Em的控制下，对驱动模块30进行阈值电压的补偿。
发光模块20连接第一电压端VSS和驱动模块30。在此情况下，驱动模块30还连接第一控制信号端S1，用于在第一控制信号端S1的控制下驱动发光模块20进行发光。
控制信号输入模块40连接第一控制信号端S1、第二控制信号端S2、第三控制信号端S3、第二电压端VDD以及第三电压端VEE，用于在第二控制信号端S2和第三控制信号端S3的控制下，将第二电压端VDD或第三电压端VEE的信号传送至第一控制信号端S1。
需要说明的是，本公开实施例中，是以使第一电压端VSS、第三电压端VEE输入低电平或接地处理，第二电压端VDD输入高电平为例进行的说明。
本公开实施例提供一种像素驱动电路，包括输入模块、补偿模块、驱动模块、发光模块以及控制信号输入模块。可替换地，输入模块连接第一栅极信号端、数据电压端以及补偿模块，用于在第一栅极信号端的控制下，将数据电压端的信号传送至补偿模块。而补偿模块还连接阈值电压控制端以及驱动模块，用于在输入模块、阈值电压控制端的控制下，对驱动模块进行阈值电压的补偿。发光模块连接第一电压端和驱动模块，该驱动模块还连接第一控制信号端，用于在第一控制信号端的控制 下驱动发光模块进行发光。控制信号输入模块连接第一控制信号端、第二控制信号端、第三控制信号端、第二电压端以及第三电压端，用于在第二控制信号端和第三控制信号端的控制下，将第二电压端或第三电压端的信号传送至第一控制信号端。
这样一来，通过采用控制信号输入模块，能够在不同阶段根据需要将第二电压端或第三电压端的信号传送至第一控制信号端，以在该第一控制信号端的控制下对驱动模块进行重置，或者使得驱动模块能够驱动发光模块发光。由于在发光模块发光前，补偿模块可以对驱动模块进行阈值电压补偿，因此能够避免由于阈值电压的漂移造成显示亮度不均的问题。
以下结合附图对像素电路中各个模块的具体结构进行详细的描述。
图2示出图1中各个模块的一种具体结构示意图。如图2所示，输入模块60可以包括第一晶体管T1。第一晶体管T1的栅极连接第一栅极信号端Gn、第一极连接数据电压端Dm，第二极与补偿模块10相连接。
补偿模块10可以包括第二晶体管T2以及存储电容C。第二晶体管T2的栅极连接阈值电压控制端Em，第一极连接存储电容C的一端(节点a)，第二极与驱动模块30相连接。当输入模块60的结构如上所述时，其第二极与存储电容C的另一端(节点b)相连接。
驱动模块30可以包括第三晶体管T3。在此情况下，当补偿模块10的结构如上所述时，上述第二晶体管T2的第二极与该第三晶体管T3的第二极相连接。
第三晶体管T3的栅极连接存储电容C的一端(节点a)，第一极连接第一控制信号端S1，第二极连接发光模块20。其中，该发光模块20包括有机发光二极管OLED，该有机发光二极管OLED的阳极与驱动模块30相连接，阴极连接第一电压端VSS。当驱动模块30的结构如上所述时，上述有机发光二极管OLED的阳极与第二晶体管T3的第二极相连接。
此外，控制信号输入模块40可以包括第四晶体管T4、第五晶体管 T5、第六晶体管T6以及第七晶体管T7。
其中，第四晶体管T4的栅极连接第二控制信号端S2，第一极连接第二电压端VDD，第二极与第一控制信号端S1相连接。
第五晶体管T5的栅极连接第三控制信号端S3，第一极连接第二电压端VDD，第二极与第一控制信号端S1相连接。
第六晶体管T6的栅极连接第二控制信号端S2，第一极连接第一控制信号端S1，第二极与第七晶体管T7的第二极相连接。
第七晶体管T7的栅极连接第三控制信号端S3，第一极与第三电压端VEE相连接。
上述像素电路可以设置于显示面板的每个像素单元中。显示面板上的薄膜晶体管(TFT)的排布方式有多种。通常位于同一列的像素单元中的薄膜晶体管可以连接同一条数据线。
图3示出图1中各个模块的另一种具体结构示意图。图4示出采用图3中的像素驱动电路的显示面板上TFT的排布示意图。
如图4所示，显示面板上的TFT呈Z字型排布。即，位于同一列的像素单元中的TFT并未连接同一条数据线。而是位于相邻两行(L1和L2)且位于相邻两列(H1和H2)的任意两个亚像素连接同一条数据线。例如，第一像素单元①和第二像素单元②，其中第一像素单元①的TFT和第二像素单元②的TFT与同一条数据线相连接。
在上述情况下，为了实现像素驱动单元的驱动，如图3所示，输入模块60可以包括第八晶体管T8。其中，第一晶体管T1位于第一像素单元①，第八晶体管T8位于第二像素单元②。此外，该第八晶体管T8的栅极连接第二栅极信号端G(n+1)，第一极连接数据电压端Dm，第二极与存储电容C的一端(节点b)相连接。需要说明的是，图3中的方框70表示上述像素驱动电路中除了第一晶体管T1或第八晶体管T8以外的其余电源器件的省略示意。
可替换地，第一晶体管T1和第八晶体管T8公用一条数据线Data，该数据线Data用于接收上述数据电压端Dm输入的信号。而第一晶体 管T1的栅极连接第一栅线Gate1，该第一栅线Gate1用于接收所述第一栅极信号端Gn输入的信号。第二栅线Gate2用于接收第二栅极信号端G(n+1)输入的信号。上述第一栅线Gate1与第二栅线Gate2为显示面板上所有栅线中任意相邻的两条栅线。
在此情况下，在栅线逐行扫描的过程中，当第一栅极信号端G(n)输入信号时，第一晶体管T1导通，数据信号端Dm的输入的信号可以通过第一晶体管T1传送至位于第一像素单元①的驱动晶体管(第三晶体管T3)的栅极。当第二栅极信号端G(n+1)输入信号时，第八晶体管T2导通，数据信号端Dm输入的信号可以通过第八晶体管T8传送至位于第二像素单元②的驱动晶体管(第三晶体管T3)的栅极。从而能够实现对于TFT呈Z字型排布时，驱动像素单元发光。
需要说明的是，本公开实施例提供的晶体管可以均为N晶体管，也可以均为P型晶体管；或者一部分为N型晶体管，另一部分为P型晶体管。本公开对此不做限定。本发以下实施例是以第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5以及第八晶体管T8为P型晶体管，第六晶体管T6和第七晶体管T7为N型晶体管为例进行的说明。
在此基础上，上述晶体管的第一极可以为源极，第二极可以为漏极；或者，第一极可以为漏极，第二极为源极。本公开对此不做限定。
此外，上述晶体管可以为增强型晶体管，也可以为耗尽型晶体管。本公开对此不做限定。
图5示出用于控制图2或图3所示的像素驱动电路的信号时序图。以下针对图2或图3所示的像素驱动电路，结合图5所示的控制信号时序图，对该像素驱动电路的驱动过程进行详细的说明。
如图5所示，在第一阶段P1中，Gn＝0，S1＝0，S2＝1，S3＝1，Dm＝Vdata，Em＝0。其中，“1”表示高电平，“0”表示低电平。
在此情况下，由于第二控制信号端S2和第三控制信号端S3均输入的高电平，第六晶体管T6和第七晶体管T7导通，第四晶体管T4和第五晶体管T5处于截止状态。第三电压端VEE输入的低电平通过第七晶 体管T7和第六晶体管T6传送至第一信号控制端S1。
第一栅极信号端Gn输入低电平，第一晶体管T1导通，将数据电压端Dm输入的第一数据电压Vdata通过第一晶体管T1传送至存储电容C的一端(节点b)。阈值电压控制端Em输入低电平，将第二晶体管T2导通，使得作为驱动晶体管的第三晶体管T3的栅极和第二极导通。在此情况下，由于第一信号控制端S1输入第三电压端VEE的电压，因此第三晶体管T3的栅极电压Vg＝Va和第二极的电压Vd均为VEE+Vth。其中Vth为第三晶体管T3的阈值电压。此时，存储电容两端的压差Vb-Va＝Vdata-VEE-Vth。
综上所述，上述第一阶段P1为重置阶段，上述第三电压端VEE输入的是低电平，因此能够使得作为驱动晶体管(第三晶体管T3)的栅极得到重置，避免上一帧画面残留于第三晶体管T3栅极的电压对本帧画面造成影响。
如图5所示，在第二阶段P2中，Gn＝0，S1＝1，S2＝0，S3＝0，Dm＝Vdata，Em＝0。
在此情况下，由于第二控制信号端S2和第三控制信号端S3均输入的低电平，第四晶体管T4和第五晶体管T5导通，第六晶体管T6和第七晶体管T7处于截止状态。第二电压端VDD输入的高电平通过第四晶体管T4和第五晶体管T5传送至第一信号控制端S1。
第一栅极信号端Gn输入低电平，第一晶体管T1仍然保持导通状态。数据电压端Dm输入的第一数据电压Vdata通过第一晶体管T1传送至存储电容C的一端(节点b)。阈值电压控制端Em输入低电平，将第二晶体管T2导通，使得作为驱动晶体管的第三晶体管T3的栅极和第二极导通。在此情况下，由于第一信号控制端S1输入第二电压端VDD的电压，因此第三晶体管T3的栅极电压Va和第二极的电压Vd均为VDD+Vth。此时，存储电容两端的压差Vb-Va＝Vdata-VDD-Vth。
综上所述，上述第二阶段P2为阈值电压的补偿阶段，用于对第三晶体管T3的阈值电压进行补偿。
如图5所示，在第三阶段P3中，Gn＝0，S1＝1，S2＝0，S3＝1，Dm＝Vref， Em＝1。
在此情况下，由于第二控制信号端S2输入低电平，第三控制信号端S3输入高电平，因此第四晶体管T4、第七晶体管T7导通，第五晶体管T5和第六晶体管T6处于截止状态。第二电压端VDD输入的高电平通过第四晶体管T4传送至第一信号控制端S1。
在该阶段中，阈值电压控制端Em输入高电平，使得第二晶体管T2处于截止状态。第一栅极信号端Gn输入低电平，第一晶体管T1仍然保持导通状态，数据电压端Dm输入的第二数据电压Vref通过第一晶体管T1传送至存储电容C的一端(节点b)，使得存储电容C的一端的电压由第一数据电压Vdata变为第二数据电压Vref。此时，在存储电容的自举作用下，该存储电容另一端(节点a)的电压Va为Vref-Vdata+VDD+Vth。在此情况下，第三晶体管T3的栅极电压Vg＝Va＝Vref-Vdata+VDD+Vth。由于第一信号控制端S1输入第二电压端VDD的电压，因此第三晶体管T3的第一极(节点e)的电压Vs＝VDD。
综上所述，上述第三阶段P3为数据写入阶段，用于将第二数据电压Vref写入第三晶体管T3的栅极。
如图5所示，在第四阶段P4中，Gn＝1，S1＝1，S2＝1，S3＝0，Dm＝Vdata，Em＝1。
在此情况下，由于第二控制信号端S2输入高电平，第三控制信号端S3输入低电平，因此第五晶体管T5和第六晶体管T6导通，第四晶体管T4、第七晶体管T7处于截止状态。第二电压端VDD输入的高电平通过第五晶体管T5传送至第一信号控制端S1。
第一栅极信号端Gn输入高电平，第一晶体管T1截止。阈值电压控制端Em输入高电平，使得第二晶体管T2处于截止状态。这时流过第三晶体管T3的电流驱动发光器件OLED进行发光。因此第四阶段P1为发光阶段。
此外，在上述发光阶段第三晶体管M3处于饱和区，由于第三晶体管T3的栅极电压Vg＝Vref-Vdata+VDD+Vth，源极电压Vs＝VDD，因此可以根据饱和区TFT的电流特性，得出流经第三晶体管M3的电流为：
I＝1/2×K×(Vgs-Vth)2
＝1/2×K×{Vref-Vdata+VDD+Vth-VDD-Vth}2
＝1/2×K×(Vref-Vdata)2
其中，K为关联于第三晶体管T3的电流常数；Vgs为第三晶体管T3的栅极相对于源级的电压，即此时节点a相对于节点e的电压。
现有技术中，不同像素单元之间的Vth不尽相同，且同一像素中的Vth还有可能随时间发生漂移，这将造成显示亮度差异。由于这种差异与之前显示的图像有关，因此常呈现为残影现象。然而，由上述公式可以看出，本公开实施例提供的像素驱动电路中，流经第三晶体管T3的电流I与第三晶体管M3的阈值电压Vth无关。因此可以避免由于第三晶体管T3的阈值电压Vth的不一致或漂移对流过发光器件的电流所造成的影响，显著改善了显示装置显示亮度的均匀性。
需要说明的是，第一、由于上述过程是以第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5以及第八晶体管T8为P型晶体管，第六晶体管T6和第七晶体管T7为N型晶体管为例进行的说明。当上述晶体管的类型发生变化时，图5中的控制信号也需要发生相应的变化。N型晶体管需要导通时，其栅极能够接收到高电平，而P型晶体管需要导通时，其栅极能够接收到低电平。
第二、显示面板上的栅线一般采用逐行扫描的方式，即第一栅极信号端Gn向如图4所示的第一栅线Gate1输入栅极驱动信号后，第二栅极信号端G(n+1)才会向如图4所示的第二栅线Gate2输入栅极驱动信号。
图6示出图3中第一栅极信号端Gn和第二栅极信号端G(n+1)输入的栅线的时序信号示意图。如图6所示，使能信号端OE用于输入控制第一栅极信号端Gn和第二栅极信号端G(n+1)的使能信号。由于上述第一晶体管T1和第八晶体管T8分别位于相邻的两行，因此上述驱动过程只针对具有第一晶体管T1的第一像素单元①进行的说明。而具有第八晶体管T8的第二像素单元②的驱动过程同上所述，区别在于由第二栅极信号端G(n+1)控制第八晶体管T8的导通和截止。具体驱 动过程此处不再赘述。
本公开实施例还提供一种显示装置，包括如上所述的任意一种像素驱动电路，具有与前述实施例提供的像素驱动电路相同的结构和有益效果。由于前述实施例已经对像素驱动电路的结构和有益效果进行了详细的描述，此处不再赘述。
本公开实施例所提供的显示装置可以是包括LED显示器或OLED显示器在内的具有电流驱动发光器件的显示装置。
在此基础上，还包括显示面板。图7示出设置有图3所示的像素驱动电路的显示面板上TFT的排布示意图。如图7所示，该显示面板具有横纵交叉的多条栅线Gate和数据线Data。栅线Gate和数据线Data交叉界定多个像素单元。
图7中，位于第J行、第I列的第一像素单元①中的控制信号输入模块40和补偿模块10，与位于第J+1行、第I-1列的第二像素单元②中的控制信号输入模块40和补偿模块10可以被共用。其中，J≥1，I≥2，J、I均为正整数。这样一来，上述像素驱动电路中，除了输入模块60和发光模块20以外，其余的模块均可以与其它像素单元共用，因此无需在每一个像素单元中均设置上述控制信号输入模块40和发光模块20，从而可以提高像素的开口率。
当上述显示面板上的TFT为Z字型排布时，补偿模块10可以包括第一晶体管T1和第八晶体管T8。在此情况下，如图4所示，第一晶体管T1位于上述第一像素单元①，第八晶体管T8位于上述第二像素单元②。这样一来，在栅线逐行扫描的过程中，当第一栅极信号端G(n)输入信号时，第一晶体管T1导通，数据信号端Dm的输入信号可以通过第一晶体管T1传送至位于第一像素单元①的驱动晶体管(第三晶体管T3)的栅极。当第二栅极信号端G(n+1)输入信号时，第八晶体管T2导通，数据信号端Dm的输入信号可以通过第八晶体管T8传送至位于第二像素单元②的驱动晶体管(第三晶体管T3)的栅极。从而能够实现对于TFT呈Z字型排布时，驱动像素单元发光。
此外，该显示面板还可以包括用于向栅线Gate输入驱动信号的栅 极驱动器50，以及用于向数据线Date输入数据信号的源极驱动器51。
图8示出本公开实施例提供一种用于驱动上述任意一种像素驱动电路的驱动方法流程图。如图8所示，该驱动方法包括：
步骤S101、在重置阶段，即如图6所示的第一阶段P1，控制信号输入模40将第三电压端VEE的信号输入至第一控制信号端S1，驱动模块30进行重置。
可替换地，第二控制信号端S2和第三控制信号端S3均输入的高电平，第六晶体管T6和第七晶体管T7导通，第四晶体管T4和第五晶体管T5处于截止状态。第三电压端VEE输入的低电平通过第七晶体管T7和第六晶体管T6传送至第一信号控制端S1。
第一栅极信号端Gn输入低电平，第一晶体管T1导通，将数据电压端Dm输入的第一数据电压Vdata通过第一晶体管T1传送至存储电容C的一端(节点b)。阈值电压控制端Em输入低电平，将第二晶体管T2导通，使得作为驱动晶体管的第三晶体管T3的栅极和第二极导通。在此情况下，由于第一信号控制端S1输入第三电压端VEE的电压，因此第三晶体管T3的栅极电压Vg＝Va和第二极的电压Vd均为VEE+Vth。其中Vth为第三晶体管T3的阈值电压。此时，存储电容两端的压差Vb-Va＝Vdata-VEE-Vth。
步骤S102、在补偿阶段，即如图6所示的第二阶段P2，控制信号输入模块40将第二电压端VDD的信号输入至第一控制信号端S1，开启驱动模块30；并且在输入模块60以及阈值电压控制端Em的控制下，补偿模块10对驱动模块30进行阈值电压的补偿。
可替换地，第二控制信号端S2和第三控制信号端S3均输入的低电平，第四晶体管T4和第五晶体管T5导通，第六晶体管T6和第七晶体管T7处于截止状态。第二电压端VDD输入的高电平通过第七晶体管T7和第六晶体管T6传送至第一信号控制端S1。
第一栅极信号端Gn输入低电平，第一晶体管T1仍然保持导通状态。数据电压端Dm输入的第一数据电压Vdata通过第一晶体管T1传送至存储电容C的一端(节点b)。阈值电压控制端Em输入低电平， 将第二晶体管T2导通，使得作为驱动晶体管的第三晶体管T3的栅极和第二极导通。在此情况下，由于第一信号控制端S1输入第二电压端VDD的电压，因此第三晶体管T3的栅极电压Va和第二极的电压Vd均为VDD+Vth。此时，存储电容两端的压差Vb-Va＝Vdata-VDD-Vth。
步骤S103、在写入阶段，即如图6所示的第三阶段P3，控制信号输入模块40将第二电压端VDD的信号输入至第一控制信号端S1，开启驱动模块30；并且在输入模块60以及阈值电压控制端Em的控制下，将数据电压端Dm输入的信号写入驱动模块30。
可替换地，第二控制信号端S2输入低电平，第三控制信号端S3输入高电平，因此第四晶体管T4、第七晶体管T7导通，第五晶体管T5和第六晶体管T6处于截止状态。第二电压端VDD输入的高电平通过第四晶体管T4传送至第一信号控制端S1。
阈值电压控制端Em输入高电平，使得第二晶体管T2处于截止状态。第一栅极信号端Gn输入低电平，第一晶体管T1仍然保持导通状态，数据电压端Dm输入的第二数据电压Vref通过第一晶体管T1传送至存储电容C的一端(节点b)，使得存储电容C的一端的电压由第一数据电压Vdata变为第二数据电压Vref。此时，在存储电容的自举作用下，该存储电容另一端(节点a)的电压Va为Vref-Vdata+VDD+Vth。在此情况下，第三晶体管T3的栅极电压Vg＝Va＝Vref-Vdata+VDD+Vth。由于第一信号控制端S1输入第二电压端VDD的电压，因此第三晶体管T3的第一极(节点e)的电压Vs＝VDD。
步骤S104、发光阶段，即如图6所示的第四阶段P4，控制信号输入模块40将第二电压端VDD的信号输入至第一控制信号端S1，开启驱动模块30；并且在输入模块60以及阈值电压控制端Em的控制下，驱动模块30驱动发光模块20进行发光。
可替换地，第二控制信号端S2输入高电平，第三控制信号端S3输入低电平，因此第五晶体管T5和第六晶体管T6导通，第四晶体管T4、第七晶体管T7处于截止状态。第二电压端VDD输入的高电平通过第五晶体管T5传送至第一信号控制端S1。
第一栅极信号端Gn输入高电平，第一晶体管T1截止。阈值电压控制端Em输入高电平，使得第二晶体管T2处于截止状态。这时流过第三晶体管T3的电流驱动发光器件OLED进行发光。因此第四阶段P1为发光阶段。
此外，在上述发光阶段第三晶体管M3处于饱和区，由于第三晶体管T3的栅极电压Vg＝Vref-Vdata+VDD+Vth，源极电压Vs＝VDD，因此可以根据饱和区TFT的电流特性，得出流经第三晶体管M3的电流为：
Id＝1/2×K×(Vgs-Vth)2
＝1/2×K×{Vref-Vdata+VDD+Vth-VDD-Vth}2
＝1/2×K×(Vref-Vdata)2
其中，K为关联于第三晶体管T3的电流常数；Vgs为第三晶体管T3的栅极相对于源级的电压，即此时节点a相对于节点e的电压。
现有技术中，不同像素单元之间的Vth不尽相同，且同一像素中的Vth还有可能随时间发生漂移，这将造成显示亮度差异，由于这种差异与之前显示的图像有关，因此常呈现为残影现象。然而，由上述公式可以看出，本公开实施例提供的像素驱动电路中，流经第三晶体管T3的电流Id与第三晶体管M3的阈值电压Vth无关。因此可以避免由于第三晶体管T3的阈值电压Vth的不一致或漂移对流过发光器件的电流所造成的影响，显著改善了显示装置显示亮度的均匀性。
本领域普通技术人员可以理解：实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成，前述的程序可以存储于一计算机可读取存储介质中，该程序在执行时，执行包括上述方法实施例的步骤；而前述的存储介质包括：ROM、RAM、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本公开的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。
本申请要求于2016年1月4日递交的中国专利申请第201610004492.0号 的优先权，在此全文引用该中国专利申请公开的内容作为本申请的一部分。

Claims (10)

  1. 一种像素驱动电路，包括输入模块、补偿模块、驱动模块、发光模块以及控制信号输入模块；
    所述输入模块连接第一栅极信号端、数据电压端以及所述补偿模块，用于在所述第一栅极信号端的控制下，将所述数据电压端的信号传送至所述补偿模块；
    所述补偿模块连接阈值电压控制端以及所述驱动模块，用于在所述输入模块、所述阈值电压控制端的控制下，对所述驱动模块进行阈值电压的补偿；
    所述发光模块连接第一电压端和所述驱动模块；
    所述驱动模块连接第一控制信号端，用于在所述第一控制信号端的控制下驱动所述发光模块进行发光；
    所述控制信号输入模块连接所述第一控制信号端、第二控制信号端、第三控制信号端、第二电压端以及第三电压端，用于在所述第二控制信号端和所述第三控制信号端的控制下，将所述第二电压端或所述第三电压端的信号传送至所述第一控制信号端。
  2. 根据权利要求1所述的像素驱动电路，其中，所述输入模块包括第一晶体管，所述第一晶体管的栅极连接所述第一栅极信号端、第一极连接所述数据电压端，第二极与所述补偿模块相连接。
  3. 根据权利要求1所述的像素驱动电路，其中，所述补偿模块包括第二晶体管以及存储电容；
    所述第二晶体管的栅极连接所述阈值电压控制端，第一极连接所述存储电容的另一端，第二极与驱动模块相连接。
  4. 根据权利要求1所述的像素驱动电路，其中，所述驱动模块包括第三晶体管；
    所述第三晶体管的栅极连接所述存储电容的另一端，第一极连接所述第一控制信号端，第二极连接所述发光模块。
  5. 根据权利要求1所述的像素驱动电路，其中，所述控制信号输入模块包括第四晶体管、第五晶体管、第六晶体管以及第七晶体管；
    所述第四晶体管的栅极连接所述第二控制信号端，第一极连接所述 第二电压端，第二极与所述第一控制信号端相连接；
    所述第五晶体管的栅极连接所述第三控制信号端，第一极连接所述第二电压端，第二极与所述第一控制信号端相连接；
    所述第六晶体管的栅极连接所述第二控制信号端，第一极连接所述第一控制信号端，第二极与所述第七晶体管的第二极相连接；
    所述第七晶体管的栅极连接所述第三控制信号端，第一极与所述第三电压端相连接。
  6. 根据权利要求2所述的像素驱动电路，其中，所述输入模块还包括第八晶体管；
    所述第八晶体管的栅极连接第二栅极信号端，第一极连接所述数据电压端，第二极与所述补偿模块相连接。
  7. 一种显示装置，包括如权利要求1-6任一项所述的像素驱动电路。
  8. 根据权利要求7所述的显示装置，其中，还包括显示面板，所述显示面板具有横纵交叉的多条栅线和数据线，所述栅线和所述数据线交叉界定多个像素单元；
    位于第J行、第I列的第一像素单元中的控制信号输入模块和补偿模块，与位于第J+1行、第I-1列的第二像素单元中的控制信号输入模块和补偿模块共用；
    其中，J≥1，I≥2，J、I均为正整数。
  9. 根据权利要求8所述的显示装置，其中，当所述补偿模块包括第一晶体管和第八晶体管时，
    所述第一晶体管位于所述第一像素单元中，所述第八晶体管位于所述第二像素单元中。
  10. 一种用于驱动如权利要求1-6任一项所述的像素驱动电路的方法，包括：
    在重置阶段，由控制信号输入模块将第三电压端的信号传送至第一控制信号端，对驱动模块进行重置；
    在补偿阶段，由所述控制信号输入模块将第二电压端的信号传送至所述第一控制信号端，开启所述驱动模块，并且在输入模块以及阈值电压控制端的控制下，由所述补偿模块对所述驱动模块进行阈值电压的补 偿；
    在写入阶段，由所述控制信号输入模块将第二电压端的信号传送至所述第一控制信号端，开启所述驱动模块；并且在所述输入模块以及所述阈值电压控制端的控制下，将所述数据电压端输入的信号写入所述驱动模块；
    发光阶段，由所述控制信号输入模块将第二电压端的信号传送至所述第一控制信号端，开启所述驱动模块；并且在所述输入模块以及所述阈值电压控制端的控制下，由所述驱动模块驱动发光模块进行发光。
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Families Citing this family (5)

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Publication number Priority date Publication date Assignee Title
CN105427808B (zh) * 2016-01-04 2018-04-10 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法、显示装置
CN106057130B (zh) * 2016-08-18 2018-09-21 上海天马有机发光显示技术有限公司 一种显示面板和显示面板的补偿方法
CN107967894B (zh) * 2018-01-25 2019-11-01 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板及显示装置
CN110738964A (zh) * 2019-10-29 2020-01-31 京东方科技集团股份有限公司 像素电路及显示装置
CN111583864B (zh) * 2020-06-11 2021-09-03 京东方科技集团股份有限公司 显示驱动电路及其驱动方法、显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130057595A (ko) * 2011-11-24 2013-06-03 엘지디스플레이 주식회사 유기발광 다이오드 표시장치 및 그 구동방법
CN103700338A (zh) * 2012-09-27 2014-04-02 乐金显示有限公司 像素电路及其驱动方法及采用该电路的有机发光显示装置
CN104077999A (zh) * 2013-03-28 2014-10-01 群创光电股份有限公司 像素电路及其驱动方法与显示面板
US20140320544A1 (en) * 2013-04-24 2014-10-30 Samsung Display Co., Ltd. Organic light emitting diode display
CN104821150A (zh) * 2015-04-24 2015-08-05 北京大学深圳研究生院 像素电路及其驱动方法和显示装置
CN105427808A (zh) * 2016-01-04 2016-03-23 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法、显示装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105609051B (zh) * 2016-01-05 2018-05-01 京东方科技集团股份有限公司 一种像素电路、显示面板及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130057595A (ko) * 2011-11-24 2013-06-03 엘지디스플레이 주식회사 유기발광 다이오드 표시장치 및 그 구동방법
CN103700338A (zh) * 2012-09-27 2014-04-02 乐金显示有限公司 像素电路及其驱动方法及采用该电路的有机发光显示装置
CN104077999A (zh) * 2013-03-28 2014-10-01 群创光电股份有限公司 像素电路及其驱动方法与显示面板
US20140320544A1 (en) * 2013-04-24 2014-10-30 Samsung Display Co., Ltd. Organic light emitting diode display
CN104821150A (zh) * 2015-04-24 2015-08-05 北京大学深圳研究生院 像素电路及其驱动方法和显示装置
CN105427808A (zh) * 2016-01-04 2016-03-23 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法、显示装置

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