WO2017117850A1 - 阵列基板、液晶显示面板及液晶显示装置 - Google Patents

阵列基板、液晶显示面板及液晶显示装置 Download PDF

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Publication number
WO2017117850A1
WO2017117850A1 PCT/CN2016/074526 CN2016074526W WO2017117850A1 WO 2017117850 A1 WO2017117850 A1 WO 2017117850A1 CN 2016074526 W CN2016074526 W CN 2016074526W WO 2017117850 A1 WO2017117850 A1 WO 2017117850A1
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Prior art keywords
pixel
sub
pixel region
array substrate
electrode
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PCT/CN2016/074526
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English (en)
French (fr)
Inventor
郝思坤
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to GB1805415.5A priority Critical patent/GB2557159B/en
Priority to KR1020187013706A priority patent/KR102043578B1/ko
Priority to JP2018528952A priority patent/JP6632169B2/ja
Priority to DE112016004400.3T priority patent/DE112016004400B4/de
Priority to US15/023,378 priority patent/US9971212B2/en
Publication of WO2017117850A1 publication Critical patent/WO2017117850A1/zh
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134336—Matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/52—RGB geometrical arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2203/00—Function characteristic
    • G02F2203/01—Function characteristic transmissive

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to an array substrate and a liquid crystal display panel and a liquid crystal display device having the array substrate.
  • the array substrate which is an important component of the LCD, mainly includes a plurality of pixel regions arranged in a matrix, and each pixel The area includes a plurality of sub-pixel areas.
  • a common electrode via is provided in each sub-pixel region, so that the common electrode receives the scan voltage through the via.
  • the presence of a large number of common electrode vias occupies more sub-pixel regions, which undoubtedly reduces the area of the display region, thereby reducing the pixel aperture ratio, resulting in a decrease in the light transmittance of the pixel.
  • the present invention provides an array substrate, a liquid crystal display panel, and a liquid crystal display device, which can increase the pixel aperture ratio and improve the light transmittance of the pixel.
  • An array substrate provided by the present invention includes: a plurality of scan lines and a plurality of data lines, the intersection defines a plurality of first sub-pixel regions and a plurality of second sub-pixel regions; and the first pixel electrode is located in the first sub-pixel region a second pixel electrode located in the second sub-pixel region; a common electrode between the adjacent two first pixel electrodes, and between the adjacent first pixel electrode and the second pixel electrode; the first via Between the first sub-pixel region and the second sub-pixel region, the first via hole is used to realize electrical connection between the first pixel electrode and the data line, and electrical connection between the second pixel electrode and the data line; Two vias are located in the second sub-pixel region such that the common electrode receives the voltage through the second via.
  • the area of the first pixel electrode is larger than the area of the second pixel electrode.
  • one pixel area of the array substrate includes two first sub-pixel areas and one second sub-pixel area, and the second sub-pixel area is one of R, G, B sub-pixel areas, in each pixel area, common
  • the electrode receives a voltage through a second via in the second sub-pixel region.
  • one pixel area of the array substrate includes three first sub-pixel areas and one second sub-pixel area, and the second sub-pixel area is one of R, G, B, W sub-pixel areas, in each pixel area.
  • the common electrode receives the voltage through the second via in the second sub-pixel region.
  • the array substrate includes a plurality of scan lines arranged in a row direction, each of the first sub-pixel regions is connected to one scan line, and each second sub-pixel region is connected to a scan line, the nth row and the n+1th row.
  • the first sub-pixel region and the second sub-pixel region between the scan lines are electrically connected to the n-th row scan line, and n is a positive integer.
  • the common electrode and the first pixel electrode and the second pixel electrode are formed by the same mask process.
  • the common electrode is disposed overlapping with the corresponding data line, and the common electrode includes a conductive metal layer that is opaque.
  • the first via and the second via are located on opposite sides of the scan line, and the first via is located between the scan line and the first pixel electrode, and between the scan line and the second pixel electrode.
  • the present invention provides a liquid crystal display panel comprising an array substrate, the array substrate comprising: a plurality of scan lines and a plurality of data lines, the intersection defines a plurality of first sub-pixel regions and a plurality of second sub-pixel regions; the first pixel electrode Located in the first sub-pixel region; the second pixel electrode is located in the second sub-pixel region; the common electrode is located between the adjacent two first pixel electrodes, and the adjacent first pixel electrode and second pixel electrode a first via hole located in the first sub-pixel region and the second sub-pixel region, the first via hole for achieving electrical connection between the first pixel electrode and the data line, and the second pixel electrode and the data line An electrical connection between the second vias is located in the second sub-pixel region such that the common electrode receives the voltage through the second via.
  • the area of the first pixel electrode is larger than the area of the second pixel electrode.
  • one pixel area of the array substrate includes two first sub-pixel areas and one second sub-pixel area, and the second sub-pixel area is one of R, G, B sub-pixel areas, in each pixel area, common
  • the electrode receives a voltage through a second via in the second sub-pixel region.
  • one pixel area of the array substrate includes three first sub-pixel areas and one second sub-pixel area, and the second sub-pixel area is one of R, G, B, W sub-pixel areas, in each pixel area.
  • the common electrode receives the voltage through the second via in the second sub-pixel region.
  • the array substrate includes a plurality of scan lines arranged in a row direction, each of the first sub-pixel regions is connected to one scan line, and each second sub-pixel region is connected to a scan line, the nth row and the n+1th row.
  • the first sub-pixel area and the second sub-pixel area and the nth line scan between the scan lines Wire drawing electrical connection, n is a positive integer.
  • the common electrode and the first pixel electrode and the second pixel electrode are formed by the same mask process.
  • the common electrode is disposed overlapping with the corresponding data line, and the common electrode includes a conductive metal layer that is opaque.
  • the first via and the second via are located on opposite sides of the scan line, and the first via is located between the scan line and the first pixel electrode, and between the scan line and the second pixel electrode.
  • a liquid crystal display device includes a liquid crystal display panel and a backlight module for providing backlighting to the liquid crystal display panel.
  • the liquid crystal display panel includes an array substrate, and the array substrate includes: a plurality of scan lines and a plurality of data lines, and the cross definition a plurality of first sub-pixel regions and a plurality of second sub-pixel regions; a first pixel electrode located in the first sub-pixel region; a second pixel electrode located in the second sub-pixel region; and a common electrode located adjacent to the two Between the first pixel electrodes and between the adjacent first pixel electrodes and the second pixel electrodes; the first via holes are located in the first sub-pixel region and the second sub-pixel region, and the first via holes are used to implement the first An electrical connection between the pixel electrode and the data line, and an electrical connection between the second pixel electrode and the data line; and a second via located in the second sub-pixel region such that the common electrode receives the voltage through the second via.
  • a plurality of sub-pixels located in the same pixel region share a via hole, so that the common electrode receives the scan voltage, thereby increasing the pixel aperture ratio and improving the pixel light. Transmittance.
  • FIG. 1 is a cross-sectional view of a liquid crystal display panel according to an embodiment of the present invention.
  • FIG. 2 is a partial schematic view showing a pixel structure of an embodiment of the liquid crystal display panel of FIG. 1;
  • FIG. 3 is a schematic structural view of a pixel area shown in FIG. 2;
  • FIG. 4 is a schematic view showing the formation of a first pixel region according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of forming a second pixel region according to an embodiment of the invention.
  • Fig. 6 is a cross-sectional view showing the structure of a liquid crystal display device according to an embodiment of the present invention.
  • the liquid crystal display panel 10 of the present embodiment includes a color filter substrate (Color Filter Substrate, CF substrate, also referred to as a color filter substrate) 11 and an array substrate (Thin Film Transistor).
  • CF substrate Color Filter Substrate
  • an array substrate Thin Film Transistor
  • a TFT substrate also referred to as a thin film transistor substrate or an Array substrate 12
  • a liquid crystal (liquid crystal molecule) 13 filled between the two substrates, the liquid crystal 13 being located in a liquid crystal cell in which the array substrate 11 and the color filter substrate 12 are stacked.
  • the array substrate 12 includes a plurality of data lines D arranged in the column direction, a plurality of scanning lines G arranged in the row direction, and a plurality of sub-pixel regions P defined by the intersection of the plurality of scanning lines G and the plurality of data lines D.
  • Each sub-pixel region P is connected to a corresponding one of the data lines D and one of the scan lines G, and each of the scan lines G is connected to the gate driver 21 to supply a scan voltage to each of the sub-pixel regions P, and each of the data lines D is connected to the source.
  • the driver 22 supplies a gray scale voltage to each of the sub-pixel regions P.
  • the S-IPS Super In-Plane Switching
  • the electrodes are chevron electrodes or " ⁇ " shaped electrodes, and correspondingly, the data lines D are not straight lines arranged in the column direction.
  • the sub-pixel region P of the present embodiment includes a first sub-pixel region P 1 and a second sub-pixel region P 2 .
  • the second sub-pixel region P 2 corresponds to B ( a blue, blue) sub-pixel region
  • the first sub-pixel region P 1 corresponding to an R (Red, red) sub-pixel region and a G (Green) sub-pixel region
  • a second sub-pixel region P 2 and adjacent The two first sub-pixel regions P 1 form one pixel region of the array substrate 12. Since the structure of a plurality of pixel regions arranged in a matrix is completely the same, a description will be given below by taking a pixel region located in the nth row shown in FIG. 3 as a representative, and n is a positive integer.
  • the array substrate 12 includes a common electrode 31, a first through hole 32, the first pixel electrode 133, and a first sub-pixel region P of the second via hole 34 is, in the second sub-pixel region P in the second pixel 2 Electrode 35.
  • the common electrode 31 is located between the adjacent two first pixel electrodes 34 and between the adjacent first pixel electrode 34 and the second pixel electrode 35; the first via 32 is located in the first sub-pixel region P 1 and In the second sub-pixel region P 2 , the first via 32 in the first sub-pixel region P 1 is specifically located between the scan line G n and the first pixel electrode 34 , and the first via 32 is a pixel electrode via ( The pixel via) is used to realize the electrical connection between the first pixel electrode 34 and the corresponding data line D.
  • the first via 32 in the second sub-pixel region P 2 is specifically located on the scan line G n and the second pixel electrode 35.
  • the second via 33 is located in the second sub-pixel region P 2 and is located on the scan line G n with the first via 32
  • the second via 33 is a common electrode via for causing the common electrode 31 to receive a voltage through the second via 33, which may be a scan voltage. Since the second via hole 33 is disposed only in the second sub-pixel region P 2 and is not disposed in the first sub-pixel region P 1 , the area of the first pixel electrode 34 is larger than the area of the second pixel electrode 35 .
  • the common electrode located in the second sub-pixel region P 2 receives the voltage through the second via 33, and the common electrode 31 located in the first sub-pixel region P 1 may pass through the peripheral trace and be located in the second sub-pixel region P 2 .
  • the internal common electrode 31 is electrically connected.
  • the outer traces + 1 may be set to overlap the scanning line or scanning line G n G n.
  • the R sub-pixel and the G sub-pixel do not include the common electrode via (the second via 33), the area of the first pixel electrode 34 becomes larger than that of the prior art, and the aperture ratio of the pixel Increase, light transmission increases.
  • the reason why the second via hole 33 is disposed in the B sub-pixel in this embodiment is that the B sub-pixel allows blue light to pass through, and the blue light contributes less to the display brightness of the liquid crystal display panel 10 than the red light and the green light, even if The area of the second pixel electrode 35 is small, and the influence on the light transmittance of the entire pixel is also small.
  • the second via 33 in the R sub-pixel region or the G sub-pixel region, that is, the second sub-pixel region P 2 is an R sub-pixel region or a G sub-pixel region.
  • one pixel region of the array substrate 12 includes three first sub-pixel regions P 1 and one second sub-pixel region P 2 , and the second sub-pixel region P 2 is One of the R, G, B, W (White, white) sub-pixel regions, for example, also a B sub-pixel region, in each pixel region, the common electrode 31 passes through the second sub-pixel region P 2 Hole 33 receives the voltage.
  • FIG. 4 is a schematic diagram showing the formation of a first pixel region in accordance with an embodiment of the present invention. 4, the first sub-pixel region P of the present embodiment comprises a forming step:
  • first metal layer 41 having a predetermined pattern for forming the scan line G, the gate g of the TFT (Thin Film Transistor) of the array substrate 12, corresponding to the first via 32 Metal layers, as well as other metal traces;
  • an active semiconductor layer (AS) 42 of the TFT on the first metal layer 41, the active semiconductor layer 42 being located above the gate g;
  • the first pixel electrode 34 and the common electrode 31 are formed on the flat passivation layer on which the first via 32 is opened.
  • the common electrode 31 and the first pixel electrode 34 are formed by the same mask process, that is, the common electrode 31 is a transparent conductive layer, and the material thereof may be ITO.
  • FIG. 5 is a schematic diagram showing the formation of a first pixel region according to an embodiment of the invention. As shown in FIG. 5, the forming step of the second sub-pixel region P 2 of the embodiment includes:
  • first metal layer 51 having a predetermined pattern for forming the scan line G, the gate g of the TFT, the metal layer corresponding to the first via 32, and the metal corresponding to the second via 33 Layers, and other metal traces;
  • An active semiconductor layer 52 is formed on the first metal layer 51, which is located above the gate g;
  • the flat passivation layer not only has a first via 32, but also a second via 33;
  • the second pixel electrode 35 and the common electrode 31 are formed on the flat passivation layer on which the first via 32 and the second via 33 are opened.
  • the common electrode 31 and the second pixel electrode 35 are formed by the same mask process, that is, the common electrode 31 is a transparent conductive layer, and the material thereof includes but is not limited to ITO.
  • the common electrode 31 is formed by a separate mask process or other manner. Since the common electrode 31 is disposed to overlap with the corresponding data line D, the common electrode 31 may also be an opaque conductive metal layer.
  • the first sub-pixel region P 1 and the second sub-pixel region P 2 are not separately formed.
  • the first metal layers 41 , 51 may be formed by the same mask process; the active semiconductor layer 42, 52 may be formed by the same process; the second metal layers 43, 53 may be formed by the same mask process; the flat passivation layer may be formed by the same process; the second via 33 and all of the first vias 32 may also be formed by the same process;
  • the common electrode 31 and the first pixel electrode 34 and the second pixel electrode 35 can be formed by the same mask process.
  • the embodiment of the present invention further provides a liquid crystal display device 60 as shown in FIG. 6 .
  • the liquid crystal display device 60 includes the liquid crystal display panel 10 and a backlight module 61 that supplies light to the liquid crystal display panel 10 . Since the liquid crystal display device 60 also has the above-described design of the array substrate 12, it also has the same advantageous effects.

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  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
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Abstract

一种阵列基板（12）、液晶显示面板（10）及液晶显示装置（60），设计位于同一像素区域（P）内的多个子像素（34,35）共用一个过孔（33），以使公共电极（31）接收电压，从而能够增加像素开口率，提升像素的光透过率。

Description

阵列基板、液晶显示面板及液晶显示装置 【技术领域】
本发明涉及液晶显示技术领域，具体而言涉及一种阵列基板以及具有该阵列基板的液晶显示面板和液晶显示装置。
【背景技术】
随着电子技术的不断发展，LCD(Liquid Crystal Display，液晶显示器)已广泛应用于各个显示领域，其中，作为LCD重要组件的阵列基板主要包括多个呈矩阵排布的像素区域，且每一像素区域包括多个子像素区域。在当前的像素结构中，每一子像素区域内均设置有一个公共电极过孔(com via)，使得公共电极通过该过孔接收扫描电压。然而，大量公共电极过孔的存在占据了较多的子像素区域，这无疑会减少显示区域的面积，从而降低像素开口率，造成像素的光透过率下降。
【发明内容】
鉴于此，本发明提供一种阵列基板、液晶显示面板及液晶显示装置，能够增加像素开口率，提升像素的光透过率。
本发明提供的一种阵列基板，包括：多条扫描线和多条数据线，交叉限定多个第一子像素区域和多个第二子像素区域；第一像素电极，位于第一子像素区域内；第二像素电极，位于第二子像素区域内；公共电极，位于相邻两个第一像素电极之间，以及相邻的第一像素电极和第二像素电极之间；第一过孔，位于第一子像素区域和第二子像素区域内，第一过孔用于实现第一像素电极和数据线之间的电连接，以及第二像素电极和数据线之间的电连接；第二过孔，位于第二子像素区域内，使得公共电极通过第二过孔接收电压。
其中，第一像素电极的面积大于第二像素电极的面积。
其中，阵列基板的一个像素区域包括两个第一子像素区域和一个第二子像素区域，第二子像素区域为R、G、B子像素区域中的一个，在每一像素区域内，公共电极通过第二子像素区域内的第二过孔接收电压。
其中，阵列基板的一个像素区域包括三个第一子像素区域和一个第二子像素区域，第二子像素区域为R、G、B、W子像素区域中的一个，在每一像素区域内，公共电极通过第二子像素区域内的第二过孔接收电压。
其中，阵列基板包括沿行方向排列的多条扫描线，每一第一子像素区域对应连接一条扫描线，每一第二子像素区域对应连接一条扫描线，第n行和第n+1行扫描线之间的第一子像素区域和第二子像素区域与第n行扫描线电连接，n为正整数。
其中，公共电极和第一像素电极、第二像素电极由同一光罩制程形成。
其中，公共电极与对应的数据线重叠设置，公共电极包括不透光的导电金属层。
其中，第一过孔和第二过孔位于扫描线的两侧，第一过孔位于扫描线和第一像素电极之间，以及扫描线和第二像素电极之间。
本发明提供的一种液晶显示面板，包括阵列基板，阵列基板包括：多条扫描线和多条数据线，交叉限定多个第一子像素区域和多个第二子像素区域；第一像素电极，位于第一子像素区域内；第二像素电极，位于第二子像素区域内；公共电极，位于相邻两个第一像素电极之间，以及相邻的第一像素电极和第二像素电极之间；第一过孔，位于第一子像素区域和第二子像素区域内，第一过孔用于实现第一像素电极和数据线之间的电连接，以及第二像素电极和数据线之间的电连接；第二过孔，位于第二子像素区域内，使得公共电极通过第二过孔接收电压。
其中，第一像素电极的面积大于第二像素电极的面积。
其中，阵列基板的一个像素区域包括两个第一子像素区域和一个第二子像素区域，第二子像素区域为R、G、B子像素区域中的一个，在每一像素区域内，公共电极通过第二子像素区域内的第二过孔接收电压。
其中，阵列基板的一个像素区域包括三个第一子像素区域和一个第二子像素区域，第二子像素区域为R、G、B、W子像素区域中的一个，在每一像素区域内，公共电极通过第二子像素区域内的第二过孔接收电压。
其中，阵列基板包括沿行方向排列的多条扫描线，每一第一子像素区域对应连接一条扫描线，每一第二子像素区域对应连接一条扫描线，第n行和第n+1行扫描线之间的第一子像素区域和第二子像素区域与第n行扫 描线电连接，n为正整数。
其中，公共电极和第一像素电极、第二像素电极由同一光罩制程形成。
其中，公共电极与对应的数据线重叠设置，公共电极包括不透光的导电金属层。
其中，第一过孔和第二过孔位于扫描线的两侧，第一过孔位于扫描线和第一像素电极之间，以及扫描线和第二像素电极之间。
本发明提供的一种液晶显示装置，包括液晶显示面板以及为液晶显示面板提供背光的背光模组，液晶显示面板包括阵列基板，该阵列基板包括：多条扫描线和多条数据线，交叉限定多个第一子像素区域和多个第二子像素区域；第一像素电极，位于第一子像素区域内；第二像素电极，位于第二子像素区域内；公共电极，位于相邻两个第一像素电极之间，以及相邻的第一像素电极和第二像素电极之间；第一过孔，位于第一子像素区域和第二子像素区域内，第一过孔用于实现第一像素电极和数据线之间的电连接，以及第二像素电极和数据线之间的电连接；第二过孔，位于第二子像素区域内，使得公共电极通过第二过孔接收电压。
本发明实施例的阵列基板、液晶显示面板及液晶显示装置，设计位于同一像素区域内的多个子像素共用一个过孔，以使公共电极接收扫描电压，从而能够增加像素开口率，提升像素的光透过率。
【附图说明】
图1是本发明一实施例的液晶显示面板的剖视图；
图2是图1所示液晶显示面板一实施例的像素结构的局部示意图；
图3是图2所示一个像素区域的结构示意图；
图4是本发明一实施例的第一像素区域的形成示意图；
图5是本发明一实施例的第二像素区域的形成示意图；
图6是本发明一实施例的液晶显示装置的结构剖视图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明所提供的示例性的实施例的技术方案进行清楚、完整地描述。
图1是本发明一实施例的液晶显示面板的结构剖视图，图2是图1所示液晶显示面板一实施例的像素结构的局部示意图。请参阅图1和图2所示，本实施例的液晶显示面板10包括相对间隔设置的彩膜基板(Color Filter Substrate，CF基板，又称彩色滤光片基板)11和阵列基板(Thin Film Transistor Substrate，TFT基板，又称薄膜晶体管基板或Array基板)12以及填充于两基板之间的液晶(液晶分子)13，液晶13位于阵列基板11和彩膜基板12叠加形成的液晶盒内。
阵列基板12包括沿列方向设置的多条数据线D、沿行方向设置的多条扫描线G，及由多条扫描线G和多条数据线D交叉限定的多个子像素区域P。每一子像素区域P连接对应的一条数据线D和一条扫描线G，各条扫描线G连接于栅极驱动器21以对各子像素区域P提供扫描电压，各条数据线D连接于源极驱动器22以对各子像素区域P提供灰阶电压。其中，鉴于液晶显示面板10采用S-IPS(Super In-Plane Switching，横向电场效应显示)技术，本实施例的阵列基板12采用畴结构的像素结构设计，位于各子像素区域P内的子像素电极呈人字形电极或“＜”形电极，对应地，数据线D并非沿列方向设置的直线。
本实施例的子像素区域P包括第一子像素区域P1和第二子像素区域P2，以包括RGB三子像素的液晶显示面板10为例，第二子像素区域P2对应为B(Blue，蓝色)子像素区域，第一子像素区域P1对应为R(Red，红色)子像素区域和G(Green，绿色)子像素区域，且一个第二子像素区域P2和相邻的两个第一子像素区域P1形成阵列基板12的一个像素区域。鉴于呈矩阵排布的多个像素区域的结构完全相同，下文以图3所示的位于第n行的一个像素区域为代表进行描述，n为正整数。
参阅图3所示，位于第n行和第n+1行之间的两个第一子像素区域P1和一个第二子像素区域P2均与第n行扫描线Gn连接。阵列基板12包括公共电极31、第一过孔32、第二过孔33、以及位于第一子像素区域P1内的第一像素电极34、位于第二子像素区域P2内的第二像素电极35。其中，公共电极31位于相邻两个第一像素电极34之间，以及相邻的第一像素电极34和第二像素电极35之间；第一过孔32位于第一子像素区域P1和第二子像素区域P2内，第一子像素区域P1内的第一过孔32具体位于扫描线Gn和 第一像素电极34之间，该第一过孔32为像素电极过孔(pixel via)用于实现第一像素电极34和对应的数据线D之间的电连接，第二子像素区域P2内的第一过孔32具体位于扫描线Gn和第二像素电极35之间，用于实现第二像素电极35和对应的数据线D之间的电连接；第二过孔33位于第二子像素区域P2内，并和第一过孔32位于扫描线Gn的两侧，该第二过孔33为公共电极过孔用于使得公共电极31通过第二过孔33接收电压，该电压可以为扫描电压。由于第二过孔33仅设置于第二子像素区域P2内，而未设置于第一子像素区域P1内，因此第一像素电极34的面积大于第二像素电极35的面积。
其中，位于第二子像素区域P2内的公共电极通过第二过孔33接收电压，位于第一子像素区域P1内的公共电极31可以通过外围走线与位于第二子像素区域P2内的公共电极31电连接。优选地，该外围走线可以与扫描线Gn或者扫描线Gn+1重叠设置。
由上述可知，位于同一像素区域内的多个子像素(子像素电极)共用一个过孔以使公共电极31通过该过孔接收电压，与现有技术相比，减少了过孔的数量，从而能够增加像素开口率，提升像素的光透过率。
在上述像素结构设计中，R子像素和G子像素由于不包含公共电极过孔(第二过孔33)，相比较于现有技术，第一像素电极34的面积变大，像素的开口率增加，光透过率增加。并且本实施例将第二过孔33设置于B子像素内的原因在于：B子像素允许蓝色光透过，蓝色光对液晶显示面板10的显示亮度的贡献小于红光和绿光，即使其第二像素电极35的面积变小，对整个像素的光透过率的影响也小。
当然，其他实施例可将第二过孔33设置于R子像素区域或G子像素区域内，即第二子像素区域P2为R子像素区域或G子像素区域。
另外，对于包括RGBW四子像素的液晶显示面板10，其阵列基板12的一个像素区域包括三个第一子像素区域P1和一个第二子像素区域P2，第二子像素区域P2为R、G、B、W(White，白色)子像素区域中的一个，例如也为B子像素区域，在每一像素区域内，公共电极31通过第二子像素区域P2内的第二过孔33接收电压。
图4是本发明一实施例的第一像素区域的形成示意图。如图4所示， 本实施例的第一子像素区域P1的形成步骤包括：
形成具有预定图案的第一金属层41，该第一金属层41用于形成扫描线G、阵列基板12的TFT(Thin Film Transistor，薄膜晶体管)的栅极g、对应于第一过孔32的金属层、以及其他金属走线；
在第一金属层41上形成TFT的有源半导体层(Active Semiconductor Layer，AS)42，该有源半导体层42位于栅极g的上方；
在有源半导体层42上形成具有预定图案的第二金属层43，该第二金属层43用于形成数据线D以及TFT的源极s和漏极d；
在第二金属层43上形成平坦钝化层，其开设有第一过孔32；
在开设有第一过孔32的平坦钝化层上形成第一像素电极34和公共电极31。其中，优选公共电极31和第一像素电极34由同一光罩制程形成，即该公共电极31为透明导电层，其材质可以为ITO。
图5是本发明一实施例的第一像素区域的形成示意图。如图5所示，本实施例的第二子像素区域P2的形成步骤包括：
形成具有预定图案的第一金属层51，该第一金属层51用于形成扫描线G、TFT的栅极g、对应于第一过孔32的金属层、对应于第二过孔33的金属层、以及其他金属走线；
在第一金属层51上形成有源半导体层52，其位于栅极g的上方；
在有源半导体层52上形成具有预定图案的第二金属层53，该第二金属层53用于形成数据线D以及TFT的源极s和漏极d；
在第二金属层53上形成平坦钝化层，该平坦钝化层不仅开设有第一过孔32，而且还设有第二过孔33；
在开设有第一过孔32和第二过孔33的平坦钝化层上形成第二像素电极35和公共电极31。其中，优选公共电极31和第二像素电极35由同一光罩制程形成，即该公共电极31为透明导电层，其材质包括但不限于ITO。当然，其他实施例可以设置公共电极31由单独的光罩制程或其他方式形成，鉴于公共电极31与对应的数据线D重叠设置，因此公共电极31还可以为不透光的导电金属层。
在实际应用场景中，第一子像素区域P1和第二子像素区域P2并非单独形成，结合图4和图5，第一金属层41、51可由同一光罩制程形成；有源 半导体层42、52可由同一制程形成；第二金属层43、53可由同一光罩制程形成；平坦钝化层可由同一制程形成；第二过孔33和所有第一过孔32也可以由同一制程形成；公共电极31和第一像素电极34、第二像素电极35同样可以由同一光罩制程形成。
本发明实施例还提供一种如图6所示的液晶显示装置60，该液晶显示装置60包括上述液晶显示面板10以及为液晶显示面板10提供光线的背光模组61。由于该液晶显示装置60也具有阵列基板12的上述设计，因此亦具有相同的有益效果。
应理解，以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (17)

  1. 一种阵列基板，其中，所述阵列基板包括：
    多条扫描线和多条数据线，所述多条扫描线和所述多条数据线交叉限定多个第一子像素区域和多个第二子像素区域；
    第一像素电极，位于所述第一子像素区域内；
    第二像素电极，位于所述第二子像素区域内；
    公共电极，位于相邻两个所述第一像素电极之间，以及相邻的第一像素电极和第二像素电极之间；
    第一过孔，位于所述第一子像素区域和所述第二子像素区域内，所述第一过孔用于实现所述第一像素电极和所述数据线之间的电连接，以及所述第二像素电极和所述数据线之间的电连接；
    第二过孔，位于所述第二子像素区域内，使得所述公共电极通过所述第二过孔接收电压。
  2. 根据权利要求1所述的阵列基板，其中，所述第一像素电极的面积大于所述第二像素电极的面积。
  3. 根据权利要求1所述的阵列基板，其中，所述阵列基板的一个像素区域包括两个所述第一子像素区域和一个所述第二子像素区域，所述第二子像素区域为R、G、B子像素区域中的一个，在每一所述像素区域内，所述公共电极通过所述第二子像素区域内的第二过孔接收所述电压。
  4. 根据权利要求1所述的阵列基板，其中，所述阵列基板的一个像素区域包括三个所述第一子像素区域和一个所述第二子像素区域，所述第二子像素区域为R、G、B、W子像素区域中的一个，在每一所述像素区域内，所述公共电极通过所述第二子像素区域内的第二过孔接收所述电压。
  5. 根据权利要求1所述的阵列基板，其中，所述阵列基板包括沿行方向排列的所述多条扫描线，每一所述第一子像素区域对应连接一条所述扫描线，每一所述第二子像素区域对应连接一条所述扫描线，第n行和第n+1行所述扫描线之间的所述第一子像素区域和所述第二子像素区域与第n行所述扫描线电连接，其中所述n为正整数。
  6. 根据权利要求5所述的阵列基板，其中，所述公共电极和所述第一 像素电极、所述第二像素电极由同一光罩制程形成。
  7. 根据权利要求5所述的阵列基板，其中，所述公共电极与对应的数据线重叠设置，所述公共电极包括不透光的导电金属层。
  8. 根据权利要求1所述的阵列基板，其中，所述第一过孔和所述第二过孔位于所述扫描线的两侧，所述第一过孔位于所述扫描线和所述第一像素电极之间，以及所述扫描线和所述第二像素电极之间。
  9. 一种液晶显示面板，其中，所述液晶显示面板包括阵列基板，所述阵列基板包括：
    多条扫描线和多条数据线，所述多条扫描线和所述多条数据线交叉限定多个第一子像素区域和多个第二子像素区域；
    第一像素电极，位于所述第一子像素区域内；
    第二像素电极，位于所述第二子像素区域内；
    公共电极，位于相邻两个所述第一像素电极之间，以及相邻的第一像素电极和第二像素电极之间；
    第一过孔，位于所述第一子像素区域和所述第二子像素区域内，所述第一过孔用于实现所述第一像素电极和所述数据线之间的电连接，以及所述第二像素电极和所述数据线之间的电连接；
    第二过孔，位于所述第二子像素区域内，使得所述公共电极通过所述第二过孔接收电压。
  10. 根据权利要求9所述的液晶显示面板，其中，所述第一像素电极的面积大于所述第二像素电极的面积。
  11. 根据权利要求9所述的液晶显示面板，其中，所述阵列基板的一个像素区域包括两个所述第一子像素区域和一个所述第二子像素区域，所述第二子像素区域为R、G、B子像素区域中的一个，在每一所述像素区域内，所述公共电极通过所述第二子像素区域内的第二过孔接收所述电压。
  12. 根据权利要求9所述的液晶显示面板，其中，所述阵列基板的一个像素区域包括三个所述第一子像素区域和一个所述第二子像素区域，所述第二子像素区域为R、G、B、W子像素区域中的一个，在每一所述像素区域内，所述公共电极通过所述第二子像素区域内的第二过孔接收所述电压。
  13. 根据权利要求9所述的液晶显示面板，其中，所述阵列基板包括沿 行方向排列的所述多条扫描线，每一所述第一子像素区域对应连接一条所述扫描线，每一所述第二子像素区域对应连接一条所述扫描线，第n行和第n+1行所述扫描线之间的所述第一子像素区域和所述第二子像素区域与第n行所述扫描线电连接，其中所述n为正整数。
  14. 根据权利要求13所述的液晶显示面板，其中，所述公共电极和所述第一像素电极、所述第二像素电极由同一光罩制程形成。
  15. 根据权利要求13所述的液晶显示面板，其中，所述公共电极与对应的数据线重叠设置，所述公共电极包括不透光的导电金属层。
  16. 根据权利要求9所述的液晶显示面板，其中，所述第一过孔和所述第二过孔位于所述扫描线的两侧，所述第一过孔位于所述扫描线和所述第一像素电极之间，以及所述扫描线和所述第二像素电极之间。
  17. 一种液晶显示装置，其中，包括液晶显示面板以及为所述液晶显示面板提供背光的背光模组，所述液晶显示面板包括阵列基板，所述阵列基板包括：
    多条扫描线和多条数据线，所述多条扫描线和所述多条数据线交叉限定多个第一子像素区域和多个第二子像素区域；
    第一像素电极，位于所述第一子像素区域内；
    第二像素电极，位于所述第二子像素区域内；
    公共电极，位于相邻两个所述第一像素电极之间，以及相邻的第一像素电极和第二像素电极之间；
    第一过孔，位于所述第一子像素区域和所述第二子像素区域内，所述第一过孔用于实现所述第一像素电极和所述数据线之间的电连接，以及所述第二像素电极和所述数据线之间的电连接；
    第二过孔，位于所述第二子像素区域内，使得所述公共电极通过所述第二过孔接收电压。
PCT/CN2016/074526 2016-01-06 2016-02-25 阵列基板、液晶显示面板及液晶显示装置 Ceased WO2017117850A1 (zh)

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