WO2017109642A1 - Film d'oxyde métallique et dispositif à semi-conducteurs - Google Patents

Film d'oxyde métallique et dispositif à semi-conducteurs Download PDF

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WO2017109642A1
WO2017109642A1 PCT/IB2016/057594 IB2016057594W WO2017109642A1 WO 2017109642 A1 WO2017109642 A1 WO 2017109642A1 IB 2016057594 W IB2016057594 W IB 2016057594W WO 2017109642 A1 WO2017109642 A1 WO 2017109642A1
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film
transistor
oxide semiconductor
insulating film
metal oxide
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PCT/IB2016/057594
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English (en)
Japanese (ja)
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太田将志
津吹将志
野中裕介
石原典隆
山内諒
肥塚純一
島行徳
生内俊光
保坂泰靖
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株式会社半導体エネルギー研究所
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02554—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • One embodiment of the present invention relates to a metal oxide film and a manufacturing method thereof.
  • One embodiment of the present invention relates to a semiconductor device including a metal oxide film.
  • a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics
  • a transistor, a semiconductor circuit, and the like are one embodiment of a semiconductor device.
  • An arithmetic device, a storage device, an imaging device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, and the like) and an electronic device may include a semiconductor device.
  • Oxide semiconductors are attracting attention as semiconductor materials applicable to transistors.
  • a plurality of oxide semiconductor layers are stacked, and among the plurality of oxide semiconductor layers, the composition of the oxide semiconductor layer serving as a channel includes indium and gallium, and the composition of indium is gallium.
  • a semiconductor device is disclosed in which the field effect mobility (which may be simply referred to as mobility or ⁇ FE) is increased by making the composition larger than the above composition.
  • Non-Patent Document 1 an oxide semiconductor including indium, gallium, and zinc is In 1-x Ga 1 + x O 3 (ZnO) m (x is a number satisfying ⁇ 1 ⁇ x ⁇ 1, m is It is disclosed to have a homologous phase represented by a natural number).
  • An object of one embodiment of the present invention is to provide a metal oxide film including a crystal part. Another object is to provide a metal oxide film with high stability in physical properties. Another object is to provide a metal oxide film with improved electrical characteristics. Another object is to provide a metal oxide film that can increase field-effect mobility. Another object is to provide a highly reliable semiconductor device to which a metal oxide film is applied.
  • Another object of one embodiment of the present invention is to provide a metal oxide film that can be formed at a low temperature and has high physical stability. Another object is to provide a highly reliable semiconductor device that can be formed at low temperature.
  • Another object of one embodiment of the present invention is to provide a flexible device to which a metal oxide film is applied.
  • One embodiment of the present invention is a metal oxide film containing indium, M (M is Al, Ga, Y, or Sn), and zinc. Further, in X-ray diffraction in a direction perpendicular to the film surface, there is a region where a peak of diffraction intensity due to the crystal structure is observed. Further, in the electron beam diffraction in the direction perpendicular to the cross section where the thickness was reduced to 10 nm or more and 50 nm or less and the probe diameter was 50 nm or more, two ring-shaped diffraction patterns and two positions overlapping with the ring-shaped diffraction pattern were obtained.
  • the two first spots are observed symmetrically with respect to the center, and the points of the highest brightness of the first spot, the first straight line passing through the center, and the normal direction of the film surface It is preferable to have a region where the angle between them is 0 degree or more and 10 degrees or less.
  • the luminance of the ring-shaped diffraction pattern at the intersection of the second straight line orthogonal to the first straight line and the ring-shaped diffraction pattern is greater than the luminance of the first spot. It is preferable to have a small region.
  • the first spot has a region in which the luminance of the first spot is greater than 1 and less than 10 times the luminance of the ring-shaped diffraction pattern at the intersection of the second straight line and the ring-shaped diffraction pattern. It is preferable.
  • the area ratio of the portion excluding the portion where the crystal portion where the angle between the c-axis direction and the film surface direction is 10 degrees or less exists is 25% or more and 100 It is preferred to have a region that is less than.
  • the first image obtained by fast Fourier transform of the cross-sectional TEM image was subjected to mask processing that leaves a range showing periodicity, and the second image obtained by inverse Fourier transform remained from the original image. It is preferable to have a region where the ratio of the area after subtracting the image is 25% or more and less than 100.
  • the first spot has a shape spreading in the circumferential direction, and includes two straight lines passing through each of the two ends in the circumferential direction of the first spot and the center of the electron diffraction pattern.
  • the angle is preferably within 45 degrees.
  • Another embodiment of the present invention is a semiconductor device including a semiconductor layer, a gate insulating layer, and a gate, and the semiconductor layer includes the metal oxide film.
  • a metal oxide film including a crystal part can be provided.
  • a metal oxide film with high physical properties can be provided.
  • a highly reliable semiconductor device to which a metal oxide film is applied can be provided.
  • a metal oxide film that can be formed at a low temperature and has high physical stability can be provided.
  • a highly reliable semiconductor device that can be formed at low temperature can be provided.
  • a metal oxide film is applied to provide a flexible device.
  • the XRD measurement result of a metal oxide The XRD measurement result of a metal oxide.
  • Cross-sectional observation image of metal oxide Electron diffraction pattern of metal oxide. Electron diffraction pattern of metal oxide. Electron diffraction pattern of metal oxide. Electron diffraction pattern of metal oxide. Electron diffraction pattern of metal oxide and luminance profile. Relative luminance estimated from electron diffraction pattern of metal oxide. Electron diffraction pattern of metal oxide.
  • Cross-sectional observation image of metal oxide and cross-sectional observation image after image analysis. Transistor electrical characteristics. 6A and 6B illustrate a range of the atomic ratio of an oxide semiconductor film.
  • FIG. 6 illustrates a crystal of InMZnO 4 .
  • FIG. 6A and 6B illustrate energy bands in a transistor in which an oxide semiconductor film is used for a channel region.
  • 8A and 8B are a top view and cross-sectional views illustrating a semiconductor device.
  • 8A and 8B are a top view and cross-sectional views illustrating a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device.
  • 8A and 8B are a top view and cross-sectional views illustrating a semiconductor device.
  • 8A and 8B are a top view and cross-sectional views illustrating a semiconductor device.
  • 8A and 8B are a top view and cross-sectional views illustrating a semiconductor device.
  • 8A and 8B are a top view and cross-sectional views illustrating a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device.
  • FIG. 8A and 8B are a top view and cross-sectional views illustrating a semiconductor device.
  • FIG. 14 is a top view illustrating one embodiment of a display device.
  • FIG. 14 is a cross-sectional view illustrating one embodiment of a display device.
  • FIG. 14 is a cross-sectional view illustrating one embodiment of a display device.
  • FIG. 14 is a cross-sectional view illustrating one embodiment of a display device.
  • FIG. 14 is a cross-sectional view illustrating one embodiment of a display device.
  • 10A and 10B are a block diagram and a circuit diagram illustrating a display device.
  • 6A and 6B are a circuit diagram and a timing chart for illustrating one embodiment of the present invention.
  • 5A and 5B are a graph and a circuit diagram for illustrating one embodiment of the present invention.
  • 6A and 6B are a circuit diagram and a timing chart for illustrating one embodiment of the present invention.
  • 6A and 6B are a circuit diagram and a timing chart for illustrating one embodiment of the present invention.
  • 4A and 4B are a block diagram, a circuit diagram, and a waveform diagram for illustrating one embodiment of the present invention.
  • 6A and 6B are a circuit diagram and a timing chart for illustrating one embodiment of the present invention.
  • FIG. 10 is a circuit diagram illustrating one embodiment of the present invention.
  • FIG. 10 is a circuit diagram illustrating one embodiment of the present invention.
  • the figure explaining a display module. 10A and 10B each illustrate an electronic device.
  • 10A and 10B each illustrate an electronic device.
  • FIG. 14 is a perspective view illustrating a display device
  • a transistor is a kind of semiconductor element, and can realize amplification of current and voltage, switching operation for controlling conduction or non-conduction, and the like.
  • the transistors in this specification include an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT: Thin Film Transistor).
  • source and drain may be interchanged when transistors having different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.
  • One embodiment of the present invention is a metal oxide film including two kinds of crystal parts.
  • One of the crystal parts (also referred to as a first crystal part) is a crystal part having orientation in a film thickness direction (also referred to as a film surface direction, a film formation surface, or a direction perpendicular to the film surface). is there.
  • Another of the crystal parts (also referred to as a second crystal part) is a crystal part that is oriented in various directions without having a specific orientation.
  • the metal oxide film of one embodiment of the present invention includes such a mixture of two kinds of crystal parts.
  • the metal oxide film of one embodiment of the present invention can be expressed without distinction. That is, the metal oxide film of one embodiment of the present invention includes a plurality of crystal parts, and of these, a crystal part having orientation in a direction perpendicular to the surface of the film is more than a crystal part oriented in another direction. It can be paraphrased as a film that exists in large numbers.
  • a specific crystal plane has orientation with respect to the thickness direction of the film. Therefore, when X-ray diffraction (XRD) measurement in a direction substantially perpendicular to the top surface of the metal oxide film including the first crystal part is performed, a predetermined diffraction angle (2 ⁇ ) A diffraction peak derived from the first crystal part is confirmed. Note that the height (intensity) of the diffraction peak increases as the proportion of the first crystal portion included in the film increases, and can be an index for estimating the crystallinity of the film.
  • XRD X-ray diffraction
  • the metal oxide film of one embodiment of the present invention is subjected to electron beam diffraction measurement in a direction perpendicular to the cross section of the film, an electron beam diffraction pattern caused by the first crystal part and a second crystal part are formed. A diffraction pattern in which the resulting electron beam diffraction pattern is mixed is obtained.
  • a clear spot derived from crystallinity is confirmed.
  • the spot has orientation with respect to the thickness direction of the film.
  • the second crystal part is a crystal part existing in the film so as to be randomly oriented in all directions. Therefore, different images are confirmed as follows depending on the diameter of the electron beam (probe diameter) used for electron beam diffraction, that is, the area of the region to be observed.
  • the limited-field electron beam diffraction is one of electron beam diffractions, in which an irradiation region is narrowed and a parallel region is irradiated with a parallel electron beam.
  • Nanobeam electron diffraction also called Nano Beam Electron Diffraction
  • the electron beam diameter probe diameter
  • the ⁇ direction A plurality of spots distributed in the circumferential direction (also referred to as the ⁇ direction) are confirmed at the position of the ring-shaped pattern seen in the limited-field electron diffraction pattern. That is, it can be confirmed that the ring-shaped pattern seen in the limited-field electron diffraction pattern is formed by the aggregate of the spots.
  • Nanobeam electron diffraction is one type of convergent electron beam diffraction among electron beam diffractions, and converges an electron beam and irradiates a sample.
  • the first spot derived from the first crystal portion and the ring-shaped pattern derived from the second crystal portion are mixed in the limited-field electron diffraction pattern of the cross section. Confirmed diffraction pattern. Further, the metal oxide film has a plurality of second spots that are derived from the first spot derived from the first crystal part and the second crystal part and scattered along the circumferential direction in the nanobeam electron diffraction pattern of the cross section. A diffraction pattern with mixed spots is confirmed.
  • the first spot and the ring are positioned so as to overlap in the radial direction.
  • the first spot and the second spot are positioned so as to overlap in the radial direction.
  • the first spot derived from the first crystal part is a diffraction spot derived from a crystal plane perpendicular to the c-axis of the crystal.
  • the crystal structure has two-fold symmetry in the direction perpendicular to the c-axis, two first spots are observed symmetrically with respect to the center of the electron beam diffraction pattern.
  • other spots derived from the crystal plane perpendicular to the c-axis and diffraction spots derived from crystal planes other than the crystal plane perpendicular to the c-axis are observed. Sometimes it is done.
  • the plurality of second spots constituting the ring are diffracted from crystal planes perpendicular to the c-axis of crystal parts oriented in different directions. Can be understood as a spot.
  • the first ring and the second ring from the inside may be observed.
  • the first spot derived from the first crystal portion is positioned so as to overlap with the ring (first ring) positioned inside.
  • another spot derived from the first crystal part may be observed at a position overlapping the second ring.
  • the presence ratio of the first crystal part having orientation in the metal oxide film is high, a pattern with higher anisotropy is dominant in the obtained electron beam diffraction pattern.
  • the luminance of the first ring and the second ring is relatively lower than the luminance of the first spot derived from the first crystal part.
  • a different spot (third spot) derived from the first crystal part may be observed at a position overlapping the second ring located outside.
  • the third spot and the second ring overlap in the radial direction, it can be inferred that they originate from diffraction from the same crystal plane.
  • the brightness (diffraction intensity) of the second spot caused by the second crystal part in the nanobeam electron diffraction pattern is smaller than the brightness of the first spot caused by the first crystal part.
  • This difference in luminance increases as the proportion of the first crystal portion in the metal oxide film increases, and it becomes an index for estimating the crystallinity of the metal oxide film.
  • the brightness of the first spot is greater than 1 time and 10 times or less than the brightness of the second spot.
  • the metal oxide film of one embodiment of the present invention is an oxide film containing indium, M (M is Al, Ga, Y, or Sn), and zinc.
  • M is Al, Ga, Y, or Sn
  • Such an oxide film has a feature of taking a crystal structure having a layered structure along the c-axis. Further, such an oxide film has a characteristic of having semiconductor characteristics.
  • the metal oxide film of one embodiment of the present invention can be applied to a semiconductor in which a channel of a transistor is formed.
  • a transistor to which a metal oxide film in which a first crystal part having orientation and a second crystal part having no orientation are mixed is composed of only the second crystal part having no orientation. Compared with a transistor to which a metal oxide film is applied, the electrical characteristics can be increased and the channel length can be easily reduced.
  • a transistor using a metal oxide film in which a first crystal part having orientation and a second crystal part not having orientation are mixed has a very high proportion of the first crystal part having orientation.
  • a transistor to which a high (eg, greater than 75%) metal oxide film is applied field effect mobility can be increased particularly under a low gate voltage. Therefore, there are features such that the drive voltage of the device can be lowered and high-frequency driving is facilitated.
  • the metal oxide film of one embodiment of the present invention includes indium (In), M (M is Al, Ga, Y, or Sn), and zinc (Zn).
  • M is preferably gallium (Ga).
  • the metal oxide film contains In, for example, carrier mobility (electron mobility) increases. Further, when the metal oxide film contains Ga, for example, the energy gap (Eg) of the metal oxide film is increased. Note that Ga is an element having a high binding energy with oxygen, and has a higher binding energy with oxygen than In. In addition, when the metal oxide film contains Zn, the metal oxide film is easily crystallized.
  • the metal oxide film of one embodiment of the present invention preferably has a crystal structure exhibiting a single phase, particularly a homologous phase.
  • the metal oxide film has a composition of In 1 + x M 1-x O 3 (ZnO) y (x is a number satisfying 0 ⁇ x ⁇ 0.5, and y is near 1).
  • the carrier mobility (electron mobility) of the metal oxide film can be increased.
  • the metal oxide film of one embodiment of the present invention has a structure of In 1 + x M 1-x O 3 (ZnO) y (x represents a number satisfying 0 ⁇ x ⁇ 0.5, and y represents 1 vicinity).
  • a metal oxide film having such a composition can have both high carrier mobility and high film stability.
  • composition of the metal oxide film is not limited to this, and may be any composition that can take a layered crystal structure.
  • the vicinity may be within a range of plus or minus 1 and more preferably within a plus or minus 0.5 with respect to the atomic ratio of a certain metal atom.
  • Ga is 1 to 3 (1 ⁇ Ga ⁇ 3) and Zn is 2 or more 4 or less (2 ⁇ Zn ⁇ 4)
  • Ga is 1.5 or more and 2.5 or less (1.5 ⁇ Ga ⁇ 2.5)
  • Zn is 2 or more and 4 or less (2 ⁇ Zn ⁇ 4) If it is.
  • Sample 1 is a sample in which a metal oxide film including indium, gallium, and zinc having a thickness of about 100 nm is formed over a glass substrate.
  • the substrate is heated to 130 ° C.
  • argon gas with a flow rate of 180 sccm and oxygen gas with a flow rate of 20 sccm are introduced into the chamber of the sputtering apparatus, the pressure is 0.6 Pa, indium, and gallium.
  • the above gas flow ratio may be described as an oxygen flow ratio from the ratio of the oxygen flow rate to the total gas flow rate. At this time, the oxygen flow ratio in the production conditions of the sample 1 is 10%.
  • Sample 2 is a sample in which a metal oxide film having a thickness of about 100 nm is formed on a glass substrate.
  • the metal oxide film of Sample 2 was formed under the same conditions as Sample 1 except that the substrate was heated to 170 ° C. and conditions other than the substrate temperature.
  • the oxygen flow rate ratio under the production conditions of Sample 2 is 10%.
  • Sample 3 is a sample in which a metal oxide film having a thickness of about 100 nm is formed on a glass substrate.
  • the substrate is heated to 170 ° C.
  • argon gas having a flow rate of 140 sccm and oxygen gas having a flow rate of 60 sccm are introduced into the chamber of the sputtering apparatus. Formed under the same conditions.
  • the oxygen flow rate ratio under the production conditions of Sample 3 is 30%.
  • Sample 4 is a sample in which a metal oxide having a thickness of about 100 nm is formed on a glass substrate.
  • the oxygen flow rate ratio under the production conditions of Sample 4 is 33%.
  • FIGS. 1A, 1B, and 1C show the results of XRD measurement performed on samples 1 to 3.
  • measurement was performed using a powder method (also referred to as a ⁇ -2 ⁇ method) which is a kind of out-of-plane method.
  • the ⁇ -2 ⁇ method is a method of measuring the X-ray diffraction intensity by changing the incident angle of the X-ray and setting the angle of the detector provided facing the X-ray source to be the same as the incident angle.
  • GIXRD Grazing-Incidence XRD
  • Method also referred to as a thin film method or a Seemann-Bohlin method
  • the horizontal axis represents the angle 2 ⁇
  • the vertical axis represents the diffraction intensity in arbitrary units.
  • any sample includes a crystal part in which the c-axis is oriented in the film thickness direction (hereinafter also referred to as an oriented crystal part or a first crystal part). I can confirm that. In addition, it can be seen from the comparison of the strength that the proportion of crystal parts having orientation is higher in the order of Sample 3, Sample 2, and Sample 1.
  • the electron beam diffraction pattern of each sample is shown.
  • the electron beam diffraction pattern shown here is obtained by adjusting the contrast so that the diffraction pattern becomes clear.
  • the luminance analysis of the diffraction pattern shown below not adjusted image data but not adjusted image data shown in the figure is used.
  • the thickness of the sample used for electron beam diffraction will be described.
  • the sample is too thin, for example, when the thickness is 5 nm or less, only information on a very fine region can be obtained.
  • the electron beam diffraction pattern may be a pattern similar to that of a single crystal. If the purpose is not to analyze an extremely fine region, the thickness of the sample is preferably 10 nm to 100 nm, typically 10 nm to 50 nm.
  • FIG. 3A and 3B show the electron diffraction patterns of Sample 1.
  • FIG. 3A and 3B are electron beam diffraction patterns when the beam diameter is 100 nm and 1 nm, respectively.
  • the brightest bright spot at the center is due to the incident electron beam, and is the center (also referred to as a direct spot) of the electron diffraction pattern.
  • FIG. 3A two ring-shaped diffraction patterns having different radii can be confirmed.
  • the first ring and the second ring are referred to from the smaller diameter. It can be confirmed that the brightness of the first ring is higher than that of the second ring. Further, two spots (first spots) indicated by arrows are confirmed at positions overlapping the first ring.
  • the radial distance from the center of the first ring and the two first spots substantially coincides with the radial distance from the center of the diffraction spot on the (009) plane in the structural model of single crystal InGaZnO 4. .
  • crystal parts having no orientation or second crystal parts Since a ring-shaped diffraction pattern is observed, in the metal oxide film, crystal parts that are oriented in all directions (hereinafter also referred to as crystal parts having no orientation or second crystal parts). ) Can be confirmed.
  • the two first spots are symmetrically arranged with respect to the center point of the electron beam diffraction pattern and have the same luminance, so that the crystal part derived from the first spot has twofold symmetry. It is inferred. Further, as described above, since the two first spots are diffraction spots by a crystal plane perpendicular to the c-axis, the direction of a straight line (a straight line indicated by a broken line) connecting the two first spots and the center is the crystal. This coincides with the direction of the c-axis of the part. In FIG. 3A, since the vertical direction is the film thickness direction, it can be seen that there is a crystal part in which the c-axis is oriented in the film thickness direction in the metal oxide film.
  • FIG. 3 (B) a plurality of circumferentially distributed spots (second spots) can be confirmed at the position of the first ring seen in FIG. 3 (A). Furthermore, two first spots can also be confirmed.
  • FIG. 3 (B) when the diameter of the incident electron beam is extremely small, a plurality of second spots distributed in a circumferential shape are seen, so that the metal oxide film is extremely small. Further, it can be seen that a plurality of crystal parts having plane orientations oriented in all directions are mixed.
  • the first ring seen in FIG. 3A is the result of averaging the brightness by connecting a plurality of diffraction spots from this fine crystal part by widening the observation region. Can understand.
  • the metal oxide film of Sample 1 is a film in which crystal parts having orientation and crystal parts having no orientation are mixed.
  • the crystal part having orientation is high in the crystal part existing in the film. I can confirm that.
  • FIGS. 4A and 4B show the electron diffraction pattern of the sample 2
  • FIGS. 4C and 4D show the electron diffraction pattern of the sample 3, respectively.
  • 4A and 4C each show a beam diameter of 100 nm
  • FIGS. 4B and 4D each show a beam diameter of 1 nm.
  • the third spot has a luminance that cannot be distinguished from the second ring.
  • the two third spots are positioned in a direction rotated 90 degrees with respect to the first spot.
  • This third spot is a diffraction spot derived from a plane other than the crystal plane perpendicular to the c-axis.
  • the sample 3 is a film having a higher proportion of crystal parts having orientation, that is, higher crystallinity, as the diffraction spots other than the first spot are clearly observed.
  • FIG. 5 shows an electron diffraction pattern measured on the sample 4 under the condition that the beam diameter is 100 nm.
  • sample 4 Although the first ring was seen, the first spot seen in samples 1 to 3 was not observed. From this, sample 4 has a plurality of crystal parts derived from the first ring, and the ratio of crystal parts having orientation is equal to the ratio of crystal parts oriented in other directions. It is suggested that
  • FIG. 6A shows an enlarged view of FIG.
  • the first spot is 30 degrees, 90 degrees around the center of the electron diffraction pattern at a position overlapping the first ring in the radial direction
  • a diffraction spot is not observed at a position rotated by 120 degrees (a region surrounded by a broken line in FIG. 6A). That is, the luminance that appears in this region is scattered from electrons diffracted from a crystal part other than the crystal part having orientation in the metal oxide film, or from a region other than the crystal part in the film or a region such as a substrate. It is thought to be derived from electrons.
  • the latter scattered electrons are considered to be observed at the same intensity at positions where the radius is equal, and can be ignored here. Therefore, for example, the difference between the brightness of the first spot and the brightness at a position rotated by 90 degrees is an important parameter for knowing the existence ratio of crystal parts having orientation.
  • the difference between the luminance of the first spot and the luminance of the position rotated by a predetermined angle from here can be obtained by normalizing with the luminance of the direct spot appearing at the center position of the electron beam diffraction pattern. This also allows a relative comparison between the samples.
  • FIG. 7 (A1) shows an electron beam diffraction pattern (same as FIG. 3 (A)) in the sample 1
  • FIG. 7 (A2) shows A ⁇ passing through the first spot and the direct spot in the figure.
  • the normalized luminance profile with respect to the radial position along each line of A ′ and BB ′ orthogonal thereto is shown.
  • two peaks are observed across the peak of the direct spot. Further, there is a clear difference between the two peak luminances between A-A 'and B-B'.
  • FIGS. 7C1 and 7C2 are profiles of an electron beam diffraction pattern and a normalized luminance in the sample 3, respectively.
  • the difference between the peak luminance of the first spot and the peak luminance at the position rotated by 90 degrees is larger than that of the sample 1. Further, it can be seen that the difference is larger in the sample 3 than in the sample 2.
  • FIG. 7 (D1) and FIG. 7 (D2) are an electron beam diffraction pattern and a normalized luminance profile in the sample 4, respectively.
  • sample 4 it can be seen that the profiles are almost the same in the two directions. That is, it can be confirmed that the sample 4 contains few crystal parts having orientation, and contains a plurality of crystal parts whose crystal planes face in various directions.
  • the first ring appears as a set of discrete bright spots in the electron diffraction pattern.
  • the ring brightness may not be accurately determined.
  • a rectangular region having a specific width and having a long side direction coincident with the radial direction is a rectangle in the rectangular width direction (FIG. 6B).
  • the luminance at a predetermined position may be calculated from the luminance profile in the radial direction using the luminance value averaged in the short side direction).
  • a higher-accuracy comparison can be performed by subtracting the luminance component caused by inelastic scattering or the like from the sample as the background.
  • the background luminance may be calculated by linear approximation. For example, a straight line can be drawn along the skirts on both sides of the target peak, and a region located on the lower luminance side than the straight line can be subtracted as the background.
  • the luminance of the first spot and the luminance of the position rotated by 90 degrees from the position of the first spot were calculated from the data obtained by subtracting the background by the method described above. Then, a value obtained by dividing the luminance of the first spot by the luminance at the position rotated 90 degrees from the first spot was obtained as the relative luminance R.
  • FIG. 8 shows the result of estimating the relative luminance R from the electron beam diffraction pattern measured for each of the samples 1 to 4 under the condition that the beam diameter is 100 nm.
  • the luminance difference is not confirmed at the two positions, and the relative luminance R is 1.
  • the relative luminance increases in the order of sample 1, sample 2, and sample 3.
  • the relative luminance R is more than 1 time and 10 times or less, preferably more than 1.2 times and 8 times or less, more preferably It is preferable to use a metal oxide film that is larger than 1.5 times and smaller than 6 times, more preferably larger than 1.5 times and smaller than 4 times.
  • the fluctuation in the orientation direction can be evaluated as follows.
  • the electron diffraction pattern for the cross section of the metal oxide film is measured at a plurality of locations, and for each of the obtained images, a straight line passing through the center of the electron beam diffraction pattern and the first spot, and the film of the metal oxide film By measuring the inclination with respect to the thickness direction, it is possible to estimate the variation in the orientation direction of the crystal part existing in each region.
  • an electron beam diffraction pattern was acquired as a moving image while scanning the electron beam in a direction parallel to the film surface direction under the condition that the beam diameter of the electron beam was 1 nm. The scan was performed at a distance of about 250 nm for 100 seconds.
  • FIG. 9 shows a part of electron beam diffraction patterns of the captured moving images of Sample 1, Sample 2, and Sample 3.
  • FIG. 9 shows nine electron beam diffraction patterns, each interval being about 10 seconds.
  • FIG. 9 a straight line passing through the first spot and the center of the electron diffraction pattern is indicated by a broken line. As shown in FIG. 9, it is confirmed that the orientation direction of the crystal part varies depending on the region to be observed.
  • FIG. 10 shows a distribution diagram of the orientation direction estimated from each electron diffraction pattern shown in FIG.
  • the horizontal axis is the distance when the imaging start position is the origin, and the vertical axis is the orientation direction angle at each position when the average value of the orientation direction measured at each position is 0 degree.
  • the clockwise direction is shown as positive.
  • FIG. 10 there is almost no difference in the variation in the orientation direction between the samples, and any sample is within a range of less than 10 degrees.
  • the orientation direction of the crystal part in the metal oxide film can be estimated by the spread of the spot in the circumferential direction in the electron beam diffraction pattern measured under the condition that the beam diameter of the electron beam is increased.
  • an electron beam diffraction pattern in which information on crystal parts existing in the measurement range is averaged can be obtained. Therefore, the spread of the spot in the circumferential direction becomes wider as the variation in the orientation direction of the crystal part becomes larger.
  • the luminance distribution in the circumferential direction is a distribution reflecting the existence ratio of the crystal parts oriented in a specific direction.
  • the first spot is not a perfect point (or circle) shape, but has a shape close to an elliptical shape extending in the circumferential direction.
  • the angle between two straight lines connecting each of the two end portions in the circumferential direction of the spot and the center point of the electron beam diffraction pattern represents variation in the orientation direction of the crystal portion.
  • the position of 1 ⁇ or 2 ⁇ may be set as the end with respect to the brightest point of the first spot.
  • the difference in luminance between the first ring and the first spot is small, it may be estimated based on a luminance distribution obtained by subtracting the luminance of the first ring from the luminance of the first spot. In this method, depending on the measurement conditions of the electron beam diffraction pattern, the spread of the spot increases as the luminance increases, and it may be estimated to be larger than the actual orientation variation.
  • the central angle of both ends of the first spot centered on the center of the electron beam diffraction pattern is 0 degree or more and 45 degrees or less, preferably 0 degree or more and 40 degrees or less, more preferably 0 degree or more and 35 degrees or less, Preferably it is 0 degree or more and 30 degrees or less.
  • the existence ratio of the crystal part in the metal oxide film can be estimated by analyzing the cross-sectional observation image.
  • a two-dimensional fast Fourier transform FFT: Fast Fourier Transform
  • FFT Fast Fourier Transform
  • the obtained FFT image is subjected to a mask process that leaves a range having periodicity and removes the rest.
  • the masked FFT image is then subjected to a two-dimensional inverse Fourier transform (IFFT: Inverse Fast Fourier Transform) to obtain an FFT filtered image.
  • IFFT Inverse Fast Fourier Transform
  • the existence ratio of the crystal part can be estimated from the ratio of the area of the remaining image. Further, by subtracting the remaining area from the area of the region used for image processing (also referred to as the area of the original image), it is possible to estimate the existence ratio of the part other than the crystal part.
  • FIGS. 11A and 11B show cross-sectional TEM observation images of Sample 3 and Sample 1 before image processing
  • FIGS. 11C and 11D show images obtained after image processing, respectively.
  • a white area in the metal oxide film corresponds to an area including a crystal part.
  • the ratio of the area excluding the region including the crystal part in the sample 3 was about 21.0%. Further, the ratio of the area excluding the region including the crystal part having orientation in the sample 1 estimated from FIG. 11D was about 39.8%.
  • the metal oxide film is a film having extremely high crystallinity, and electrical characteristics. Is preferable because of its high stability. Further, when the proportion of the portion excluding the crystal part in the metal oxide film is 25% or more and less than 100%, preferably 25% or more and 90% or less, more preferably 25% or more and 80% or less, the metal oxide In the film, crystal parts having orientation and crystal parts having no orientation are mixed, and both stability of electric characteristics and high mobility can be achieved.
  • the atomic void region is a region in which a plurality of crystal parts having irregular surface orientations and extremely fine and different sizes are mixed. Presence of the crystal part is such that no spot is observed in an electron diffraction pattern having a large beam diameter (probe diameter) (for example, 25 nm ⁇ or more, or 50 nm ⁇ or more), and the beam diameter is extremely small (for example, 0.3 nm or more and 10 nm ⁇ ). It can be understood from the fact that it is finally observed as a spot in the electron diffraction pattern, and the crystal part is extremely fine.
  • beam diameter beam diameter
  • a titanium film with a thickness of 10 nm and a copper film with a thickness of 100 nm were formed on a glass substrate using a sputtering apparatus. Subsequently, the conductive film was processed by a photolithography method.
  • insulating films were formed on the substrate and the conductive film.
  • the insulating film was continuously formed in a vacuum using a plasma enhanced chemical vapor deposition (PECVD) apparatus.
  • PECVD plasma enhanced chemical vapor deposition
  • a silicon nitride film with a thickness of 50 nm, a silicon nitride film with a thickness of 300 nm, a silicon nitride film with a thickness of 50 nm, and a silicon oxynitride film with a thickness of 50 nm were used from the bottom.
  • an oxide semiconductor film was formed over the insulating film, and the semiconductor layer was formed by processing the oxide semiconductor film into an island shape.
  • the oxide semiconductor film 108 an oxide semiconductor film with a thickness of 40 nm was formed.
  • the metal oxide film used for the oxide semiconductor film has the same conditions as in sample 1. That is, a metal having indium, gallium, and zinc at a substrate temperature of 130 ° C., an argon gas with a flow rate of 180 sccm and an oxygen gas with a flow rate of 20 sccm are introduced into the chamber of the sputtering apparatus, the pressure is 0.6 Pa.
  • the oxygen flow rate ratio is 10%.
  • the thickness was about 40 nm.
  • the metal oxide film used for the oxide semiconductor film has the same conditions as Sample 3. That is, a metal having indium, gallium, and zinc at a substrate temperature of 170 ° C., an argon gas having a flow rate of 140 sccm and an oxygen gas having a flow rate of 60 sccm are introduced into the chamber of the sputtering apparatus, the pressure is 0.6 Pa.
  • the oxygen flow rate ratio is 30%.
  • the thickness was about 40 nm.
  • an insulating film was formed over the insulating film and the oxide semiconductor layer.
  • a 150 nm thick silicon oxynitride film was formed using a PECVD apparatus.
  • heat treatment was performed.
  • heat treatment was performed at 350 ° C. for 1 hour in a mixed gas atmosphere of nitrogen and oxygen.
  • an opening was formed in a desired region of the insulating film.
  • a dry etching method was used as a method for forming the opening.
  • an oxide semiconductor film having a thickness of 100 nm was formed over the insulating film so as to cover the opening, and the oxide semiconductor film was processed into an island shape, whereby a conductive film was formed.
  • the insulating film in contact with the lower side of the conductive film was processed to form the insulating film.
  • an oxide semiconductor film having a thickness of 100 nm was formed. Note that the oxide semiconductor film has a two-layer structure.
  • the substrate temperature was 170 ° C.
  • an oxygen gas with a flow rate of 200 sccm was introduced into the chamber of the sputtering apparatus, the pressure was 0.6 Pa, indium, gallium,
  • the film thickness becomes 10 nm. Formed.
  • the substrate temperature was set to 170 ° C.
  • argon gas having a flow rate of 180 sccm and oxygen gas having a flow rate of 20 sccm were introduced into the chamber of the sputtering apparatus, and the pressure was set to 0.6 Pa.
  • the film thickness was 90 nm.
  • plasma treatment was performed on the oxide semiconductor film, the insulating film, and the conductive film.
  • the plasma treatment was performed using a PECVD apparatus at a substrate temperature of 220 ° C. in a mixed gas atmosphere of argon gas and nitrogen gas.
  • an insulating film was formed over the oxide semiconductor film, the insulating film, and the conductive film.
  • a silicon nitride film with a thickness of 100 nm and a silicon oxynitride film with a thickness of 300 nm were stacked using a PECVD apparatus.
  • a mask was formed on the formed insulating film, and an opening was formed in the insulating film using the mask.
  • a conductive film was formed so as to fill the opening, and the conductive film was processed into an island shape, thereby forming a conductive film to be a source electrode and a drain electrode.
  • a titanium film with a thickness of 10 nm and a copper film with a thickness of 100 nm were formed using a sputtering apparatus, respectively.
  • an insulating film was formed over the insulating film and the conductive film.
  • an acrylic photosensitive resin having a thickness of 1.5 ⁇ m was used.
  • measurement conditions for the Id-Vg characteristics of the transistor include a voltage applied to a conductive film functioning as a first gate electrode (hereinafter also referred to as a gate voltage (Vg)) and a conductive function functioning as a second gate electrode.
  • a voltage (also referred to as Vbg) applied to the film was applied from ⁇ 15V to + 20V in steps of 0.25V.
  • a voltage applied to the conductive film functioning as the source electrode hereinafter also referred to as source voltage (Vs)
  • source voltage (Vs)) is 0 V (comm)
  • drain voltage (Vd) also referred to as drain voltage (Vd)
  • drain voltage (Vd) also referred to as 0.1V and 20V.
  • FIGS. 12A and 12B show the Id-Vg characteristic results of Sample A1 and Sample A2, respectively.
  • the first vertical axis represents Id (A)
  • the second vertical axis represents field effect mobility ( ⁇ FE (cm 2 / Vs))
  • the horizontal axis represents Vg (V).
  • Id-Vg characteristic results of a total of five transistors are shown in an overlapping manner.
  • a transistor in which a metal oxide film including a crystal part with orientation and a crystal part without orientation, which is one embodiment of the present invention, is used for a semiconductor layer in which a channel is formed has high field-effect mobility. It was confirmed that the degree was shown. In particular, it was confirmed that a high field-effect mobility and a high drain current were exhibited under conditions where the gate voltage was low.
  • the metal oxide film of one embodiment of the present invention can be formed by a sputtering method in a state where the substrate is heated in an atmosphere containing oxygen.
  • the substrate temperature during film formation is 80 ° C. or higher and 150 ° C. or lower, preferably 100 ° C. or higher and 150 ° C. or lower, typically 130 ° C. By increasing the temperature of the substrate, more crystal parts having orientation can be formed.
  • the flow rate ratio of oxygen during film formation is 1% to less than 33%, preferably 5% to 30%, more preferably 5% to 20%, and even more preferably 5% to 15%. % Or less, typically 10%.
  • oxygen partial pressure oxygen partial pressure
  • a metal oxide film in which a crystal part having orientation and a crystal part having no orientation are mixed can be obtained. Obtainable. Further, by optimizing the substrate temperature and the oxygen flow rate within the above-described ranges, it is possible to control the existence ratio of the crystal part having orientation and the crystal part not having orientation.
  • An oxide target that can be used for forming a metal oxide film is not limited to an In—Ga—Zn-based oxide, and includes, for example, an In—M—Zn-based oxide (M is Al, Ga, Y). Or Sn) can be applied.
  • a metal oxide film including a crystal part which is a metal oxide film
  • a sputtering target including a polycrystalline oxide having a plurality of crystal grains a sputtering target not including a polycrystalline oxide is used. Compared with the case where it had, the metal oxide film which has crystallinity is easy to be obtained.
  • the sputtering target has a plurality of crystal grains and the crystal grains have a layered structure, and there is an interface that is easily cleaved, the ions are allowed to collide with the sputtering target.
  • the crystal grains may be cleaved to obtain flat or pellet-like sputtered particles. It is considered that the obtained flat or pellet-like sputtered particles are deposited on a substrate to form a metal oxide film containing nanocrystals. In addition, it is considered that by heating the substrate, bonding or rearrangement of the nanocrystals progresses on the substrate surface, so that a metal oxide film including a crystal part having orientation is easily formed.
  • a sputtering method is particularly preferable because the crystallinity can be easily controlled.
  • a pulse laser deposition (PLD) method for example, a pulse laser deposition (PLD) method, a plasma chemical vapor deposition (PECVD) method, a thermal CVD (Chemical Vapor Deposition) method, an ALD (Atomic Layer Deposition) method, a vacuum evaporation method, or the like is used.
  • PLD pulse laser deposition
  • PECVD plasma chemical vapor deposition
  • thermal CVD Thermal CVD
  • ALD Atomic Layer Deposition
  • a vacuum evaporation method or the like.
  • An example of the thermal CVD method is a MOCVD (Metal Organic Chemical Vapor Deposition) method.
  • the metal oxide film of one embodiment of the present invention can be applied to a semiconductor device such as a transistor.
  • a metal oxide film having semiconductor characteristics hereinafter referred to as an oxide semiconductor film
  • composition First, the composition of the oxide semiconductor film is described.
  • the oxide semiconductor film includes indium (In), M (M represents Al, Ga, Y, or Sn), and Zn (zinc).
  • the element M is aluminum, gallium, yttrium, or tin, but as elements applicable to the element M, in addition to the above, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, Cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be used. Further, as the element M, a plurality of the aforementioned elements may be combined.
  • FIGS. 13A, 13B, and 13C a preferable range of the atomic ratio of indium, element M, and zinc included in the oxide semiconductor film of one embodiment of the present invention is described with reference to FIGS.
  • the atomic ratio of oxygen is not described.
  • the terms of the atomic ratio of indium, element M, and zinc included in the oxide semiconductor film are [In], [M], and [Zn].
  • 13A and 13B illustrate an example of a preferable range of the atomic ratio of indium, element M, and zinc included in the oxide semiconductor film of one embodiment of the present invention.
  • FIG. 14 shows a crystal structure of InMZnO 4 when observed from a direction parallel to the b-axis.
  • a metal element in a layer containing M, Zn, and oxygen (hereinafter, (M, Zn) layer) illustrated in FIG. 14 represents the element M or zinc.
  • the ratio of the element M and zinc shall be equal.
  • the element M and zinc can be substituted and the arrangement is irregular.
  • InMZnO 4 has a layered crystal structure (also referred to as a layered structure). As shown in FIG. 14, a layer containing indium and oxygen (hereinafter referred to as an In layer) contains 1 element M, zinc, and oxygen. The (M, Zn) layer having 2 is 2.
  • indium and element M can be substituted for each other. Therefore, the element M in the (M, Zn) layer can be replaced with indium and expressed as an (In, M, Zn) layer. In that case, a layered structure in which the In layer is 1 and the (In, M, Zn) layer is 2 is employed.
  • the number of (M, Zn) layers is non-integer with respect to one In layer
  • the number of (M, Zn) layers is integer with respect to one In layer.
  • a film having an atomic ratio that deviates from the atomic ratio of the target is formed.
  • [Zn] of the film may be smaller than [Zn] of the target.
  • a plurality of phases may coexist in the oxide semiconductor film (two-phase coexistence, three-phase coexistence, etc.).
  • a grain boundary also referred to as a grain boundary
  • a grain boundary may be formed between different crystal structures.
  • the oxide semiconductor of one embodiment of the present invention have an atomic ratio shown in a region A in FIG. 13A in which a carrier mobility is high and a layered structure with few grain boundaries is likely to be formed.
  • An oxide semiconductor film having an atomic ratio represented by the region B is an excellent oxide semiconductor film that has particularly high crystallinity and high carrier mobility.
  • the conditions under which the oxide semiconductor film forms a layered structure are not uniquely determined by the atomic ratio. Depending on the atomic ratio, there is a difference in difficulty for forming a layered structure. On the other hand, even if the atomic ratio is the same, there may be a layered structure or a layered structure depending on the formation conditions. Therefore, the illustrated region is a region that exhibits an atomic ratio in which the oxide semiconductor film has a layered structure, and the boundaries between the regions A to C are not strict.
  • an oxide semiconductor film for a transistor for example, carrier scattering at a crystal grain boundary can be reduced as compared with a transistor using polycrystalline silicon for a channel region.
  • a transistor can be realized.
  • a highly reliable transistor can be realized.
  • the oxide semiconductor film of one embodiment of the present invention is a film in which a crystal part having orientation and a crystal part not having orientation are mixed. By using such an oxide semiconductor film having crystallinity, a transistor having both high field-effect mobility and high reliability can be realized.
  • oxygen vacancies (Vo) in the oxide semiconductor film As a factor that affects the carrier density of the oxide semiconductor film, oxygen vacancies (Vo) in the oxide semiconductor film, impurities in the oxide semiconductor film, and the like can be given.
  • the density of defect states increases when hydrogen is bonded to the oxygen vacancies (this state is also referred to as VoH).
  • the carrier density of the oxide semiconductor film can be controlled by controlling the density of defect states in the oxide semiconductor film.
  • the object is to suppress a negative shift in the threshold voltage of the transistor or to reduce the off-state current of the transistor, it is preferable to reduce the carrier density of the oxide semiconductor film.
  • the impurity concentration in the oxide semiconductor film may be decreased and the defect level density may be decreased.
  • a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic.
  • the carrier density of the high-purity intrinsic oxide semiconductor film is less than 8 ⁇ 10 15 cm ⁇ 3 , preferably less than 1 ⁇ 10 11 cm ⁇ 3 , more preferably less than 1 ⁇ 10 10 cm ⁇ 3 , and 1 ⁇ What is necessary is just to set it as 10 ⁇ -9 > cm ⁇ -3 > or more.
  • the carrier density of an oxide semiconductor film it is preferable to increase the carrier density of an oxide semiconductor film.
  • the impurity concentration of the oxide semiconductor film may be slightly increased or the defect state density of the oxide semiconductor film may be slightly increased.
  • the band gap of the oxide semiconductor film is preferably made smaller.
  • an oxide semiconductor film with a slightly high impurity concentration or a slightly high defect state density within a range where the on / off ratio of the Id-Vg characteristics of the transistor can be obtained can be regarded as substantially intrinsic.
  • the oxide semiconductor film with the increased carrier density is slightly n-type. Therefore, an oxide semiconductor film with an increased carrier density may be referred to as “Slightly-n”.
  • the carrier density of the substantially intrinsic oxide semiconductor film is preferably 1 ⁇ 10 5 cm ⁇ 3 or more and less than 1 ⁇ 10 18 cm ⁇ 3 , preferably 1 ⁇ 10 7 cm ⁇ 3 or more and 1 ⁇ 10 17 cm ⁇ 3 or less. More preferably, it is 1 ⁇ 10 9 cm ⁇ 3 or more and 5 ⁇ 10 16 cm ⁇ 3 or less, more preferably 1 ⁇ 10 10 cm ⁇ 3 or more and 1 ⁇ 10 16 cm ⁇ 3 or less, and further preferably 1 ⁇ 10 11 cm ⁇ 3. More preferably, it is 1 ⁇ 10 15 cm ⁇ 3 or less.
  • FIG. 15 illustrates an energy band in a transistor in which an oxide semiconductor film is used for a channel region.
  • FIG. 15 illustrates an example of the energy band of the gate electrode, the gate insulating film, the oxide semiconductor film, and the source or drain electrode in contact with the oxide semiconductor film.
  • a silicon oxide film is used as the gate insulating film and an In—Ga—Zn oxide is used as the oxide semiconductor film.
  • the transition level ( ⁇ f) of defects that can be formed in the silicon oxide film is formed at a position about 3.1 eV away from the lower end of the conduction band of the gate insulating film, and the gate voltage (Vg) is 30V.
  • the Fermi level (Ef) of the silicon oxide film at the interface between the oxide semiconductor film and the silicon oxide film is formed at a position about 3.6 eV away from the lower end of the conduction band of the gate insulating film. Note that the Fermi level of the silicon oxide film varies depending on the gate voltage.
  • the Fermi level (Ef) of the silicon oxide film at the interface between the oxide semiconductor film and the silicon oxide film is lowered.
  • white circles in FIG. 15 represent electrons (carriers), and X in FIG. 15 represents a defect level in the silicon oxide film.
  • the depth at which the Fermi level at the interface between the gate insulating film and the oxide semiconductor film is formed may be different.
  • the lower end of the conduction band of the gate insulating film is relatively high in the vicinity of the interface between the gate insulating film and the oxide semiconductor film.
  • a defect level (X in FIG. 15) that can be formed in the gate insulating film is also relatively high, an energy difference between the Fermi level of the gate insulating film and the Fermi level of the oxide semiconductor film is increased. growing. As the energy difference increases, the charge trapped in the gate insulating film decreases. For example, the change in the charge state of the defect level that can be formed in the above-described silicon oxide film is reduced, and variation in the threshold voltage of the transistor due to gate bias thermal (also referred to as GBT) stress can be reduced. .
  • the charge trapped in the defect level of the oxide semiconductor film takes a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor film with a high defect level density may have unstable electrical characteristics.
  • Impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.
  • the concentration of silicon or carbon in the oxide semiconductor film and the concentration of silicon or carbon in the vicinity of the interface with the oxide semiconductor film are obtained. 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the concentration of alkali metal or alkaline earth metal in the oxide semiconductor film obtained by SIMS is set to 1 ⁇ 10 18 atoms / cm 3 or lower, preferably 2 ⁇ 10 16 atoms / cm 3 or lower.
  • the nitrogen in the oxide semiconductor film is preferably reduced as much as possible.
  • the nitrogen concentration in the oxide semiconductor film is less than 5 ⁇ 10 19 atoms / cm 3 in SIMS, preferably 5 ⁇ . 10 18 atoms / cm 3 or less, more preferably 1 ⁇ 10 18 atoms / cm 3 or less, and even more preferably 5 ⁇ 10 17 atoms / cm 3 or less.
  • hydrogen contained in the oxide semiconductor film reacts with oxygen bonded to a metal atom to become water, so that an oxygen vacancy may be formed in some cases.
  • oxygen vacancy may be formed in some cases.
  • electrons serving as carriers may be generated.
  • a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor including an oxide semiconductor film containing hydrogen is likely to be normally on. For this reason, it is preferable that hydrogen in the oxide semiconductor film be reduced as much as possible.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , more preferably 5 ⁇ 10 18 atoms / cm 3. Less than cm 3 , more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • the oxide semiconductor film preferably has an energy gap of 2 eV or more, or 2.5 eV or more.
  • the thickness of the oxide semiconductor film is 3 nm to 200 nm, preferably 3 nm to 100 nm, more preferably 3 nm to 60 nm.
  • the oxide semiconductor film is an In-M-Zn oxide
  • FIG. 16A is a top view of the transistor 100
  • FIG. 16B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 16A
  • FIG. 16C is FIG. It is sectional drawing between dashed-dotted lines Y1-Y2.
  • components such as the insulating film 110 are omitted for clarity.
  • some components may be omitted in the following drawings as in FIG. 16A.
  • alternate long and short dash line X1-X2 direction may be referred to as a channel length (L) direction
  • the alternate long and short dash line Y1-Y2 direction may be referred to as a channel width (W) direction.
  • 16A, 16B, and 16C includes an insulating film 104 over a substrate 102, an oxide semiconductor film 108 over the insulating film 104, an insulating film 110 over the oxide semiconductor film 108, The conductive film 112 over the insulating film 110, the insulating film 104, the oxide semiconductor film 108, and the insulating film 116 over the conductive film 112 are included.
  • the oxide semiconductor film 108 includes a channel region 108 i overlapping with the conductive film 112, a source region 108 s in contact with the insulating film 116, and a drain region 108 d in contact with the insulating film 116.
  • the insulating film 116 has nitrogen or hydrogen.
  • nitrogen or hydrogen in the insulating film 116 is added to the source region 108s and the drain region 108d.
  • the carrier density is increased by adding nitrogen or hydrogen.
  • the transistor 100 includes an insulating film 118 over the insulating film 116, a conductive film 120a electrically connected to the source region 108s through the opening 141a provided in the insulating films 116 and 118, and the insulating film 116. , 118 may be provided, and the conductive film 120b electrically connected to the drain region 108d through the opening 141b provided in the opening 118b.
  • the insulating film 104 is a first insulating film
  • the insulating film 110 is a second insulating film
  • the insulating film 116 is a third insulating film
  • the insulating film 118 is a fourth insulating film.
  • the conductive film 112 functions as a gate electrode
  • the conductive film 120a functions as a source electrode
  • the conductive film 120b functions as a drain electrode.
  • the insulating film 110 functions as a gate insulating film.
  • the insulating film 110 has an excess oxygen region.
  • excess oxygen can be supplied to the channel region 108 i included in the oxide semiconductor film 108. Accordingly, oxygen vacancies that can be formed in the channel region 108i can be filled with excess oxygen, so that a highly reliable semiconductor device can be provided.
  • excess oxygen may be supplied to the insulating film 104 formed below the oxide semiconductor film 108.
  • excess oxygen contained in the insulating film 104 can be supplied also to the source region 108s and the drain region 108d included in the oxide semiconductor film 108.
  • the resistance of the source region 108s and the drain region 108d may increase.
  • the insulating film 110 formed over the oxide semiconductor film 108 has excess oxygen, it is possible to selectively supply excess oxygen only to the channel region 108i.
  • the carrier density in the source region 108s and the drain region 108d is selectively increased, so that the source region 108s and the drain region 108d It can suppress that resistance becomes high.
  • the source region 108s and the drain region 108d included in the oxide semiconductor film 108 preferably each include an element that forms oxygen vacancies or an element that combines with oxygen vacancies.
  • an element that forms oxygen vacancies or an element that combines with oxygen vacancies typically, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, a rare gas, or the like can be given.
  • rare gas elements include helium, neon, argon, krypton, and xenon.
  • the oxygen vacancies diffuse into the source region 108 s and the drain region 108 d.
  • the element that forms oxygen vacancies is added to the source region 108s and the drain region 108d by impurity addition treatment.
  • the bond between the metal element and oxygen in the oxide semiconductor film is cut, and oxygen vacancies are formed.
  • oxygen bonded to the metal element in the oxide semiconductor film is bonded to the impurity element, so that oxygen is released from the metal element and oxygen vacancies are formed. The As a result, the carrier density in the oxide semiconductor film is increased and the conductivity is increased.
  • FIGS. 16A, 16B, and 16C Details of the components of the semiconductor device shown in FIGS. 16A, 16B, and 16C will be described.
  • a material having heat resistance high enough to withstand heat treatment in a manufacturing process can be used.
  • alkali-free glass soda-lime glass, alkali glass, crystal glass, quartz, sapphire, or the like can be used.
  • an inorganic insulating film may be used. Examples of the inorganic insulating film include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film.
  • the non-alkali glass may have a thickness of 0.2 mm to 0.7 mm, for example.
  • the above-described thickness may be obtained by polishing alkali-free glass.
  • the sixth generation (1500 mm ⁇ 1850 mm), the seventh generation (1870 mm ⁇ 2200 mm), the eighth generation (2200 mm ⁇ 2400 mm), the ninth generation (2400 mm ⁇ 2800 mm), the tenth generation (2950 mm ⁇ 3400 mm)
  • a glass substrate having a large area such as) can be used.
  • a large display device can be manufactured.
  • a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like may be used.
  • an inorganic material such as a metal may be used as the substrate 102.
  • inorganic materials such as metals include stainless steel and aluminum.
  • an organic material such as resin, resin film, or plastic may be used as the substrate 102.
  • the resin film include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, polyurethane, acrylic resin, epoxy resin, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES). Or a resin having a siloxane bond.
  • a composite material in which an inorganic material and an organic material are combined may be used as the substrate 102.
  • a composite material a material obtained by bonding a metal plate or a thin glass plate and a resin film, a fibrous metal, a particulate metal, a fibrous glass, or a particulate glass is dispersed in a resin film Or a material obtained by dispersing a fibrous resin or a particulate resin in an inorganic material.
  • the substrate 102 may be any substrate as long as it can support at least a film or a layer formed thereon or below, and may be any one or more of an insulating film, a semiconductor film, and a conductive film.
  • the insulating film 104 can be formed using a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like as appropriate.
  • a sputtering method for example, an oxide insulating film or a nitride insulating film can be formed as a single layer or a stacked layer.
  • at least a region in contact with the oxide semiconductor film 108 in the insulating film 104 is preferably formed using an oxide insulating film.
  • oxygen contained in the insulating film 104 can be transferred to the oxide semiconductor film 108 by heat treatment.
  • the thickness of the insulating film 104 can be 50 nm or more, 100 nm or more and 3000 nm or less, or 200 nm or more and 1000 nm or less.
  • the insulating film 104 for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga—Zn oxide, or the like may be used, and the insulating film 104 can be provided as a single layer or a stacked layer.
  • a stacked structure of a silicon nitride film and a silicon oxynitride film is used as the insulating film 104.
  • oxygen can be efficiently introduced into the oxide semiconductor film 108 by using the insulating film 104 as a stacked structure and using a silicon nitride film on the lower layer side and a silicon oxynitride film on the upper layer side.
  • oxide semiconductor film As the oxide semiconductor film 108, the metal oxide film described in Embodiment 1 can be used.
  • the oxide semiconductor film 108 is preferably formed by a sputtering method because the film density can be increased.
  • a rare gas typically argon
  • oxygen or a mixed gas of a rare gas and oxygen is used as the sputtering gas as appropriate.
  • oxygen gas or argon gas used as a sputtering gas has a dew point of ⁇ 60 ° C. or lower, preferably ⁇ 100 ° C. or lower, so that moisture or the like is taken into the oxide semiconductor film 108 by using a highly purified gas. It can be prevented as much as possible.
  • an adsorption-type vacuum exhaust pump such as a cryopump is used to remove as much impurities as possible from the oxide semiconductor film 108 in the chamber of the sputtering apparatus. Is preferably exhausted to a high vacuum (from about 5 ⁇ 10 ⁇ 7 Pa to about 1 ⁇ 10 ⁇ 4 Pa).
  • the partial pressure of gas molecules corresponding to H 2 O in the chamber is 1 ⁇ 10 ⁇ 4 Pa or less, preferably 5 ⁇ 10 ⁇ 5. It is preferable to set it to Pa or less.
  • the insulating film 110 functions as a gate insulating film of the transistor 100.
  • the insulating film 110 has a function of supplying oxygen to the oxide semiconductor film 108, particularly the channel region 108i.
  • the insulating film 110 can be formed using a single layer or a stacked layer of an oxide insulating film or a nitride insulating film.
  • a region in the insulating film 110 which is in contact with the oxide semiconductor film 108 is preferably formed using at least the oxide insulating film.
  • the insulating film 110 for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like may be used.
  • the thickness of the insulating film 110 can be 5 nm to 400 nm, 5 nm to 300 nm, or 10 nm to 250 nm.
  • the insulating film 110 preferably has few defects. Typically, it is preferable that the number of signals observed by an electron spin resonance (ESR) be small.
  • the signal described above includes the E ′ center where the g value is observed at 2.001.
  • the E ′ center is caused by silicon dangling bonds.
  • As the insulating film 110 a silicon oxide film or a silicon oxynitride film whose spin density due to the E ′ center is 3 ⁇ 10 17 spins / cm 3 or less, preferably 5 ⁇ 10 6 spins / cm 3 or less is used. Good.
  • a signal due to nitrogen dioxide (NO 2 ) may be observed in addition to the above signal.
  • the signal is split into three signals by N nuclear spins, each having a g value of 2.037 or more and 2.039 or less (referred to as the first signal), and a g value of 2.001 or more and 2.003.
  • the g value is observed below (referred to as the second signal) and from 1.964 to 1.966 (referred to as the third signal).
  • the insulating film 110 an insulating film whose spin density due to nitrogen dioxide (NO 2 ) is 1 ⁇ 10 17 spins / cm 3 or more and less than 1 ⁇ 10 18 spins / cm 3 is preferably used.
  • NO 2 nitrogen dioxide
  • nitrogen oxide (NO x ) containing nitrogen dioxide (NO 2 ) forms a level in the insulating film 110.
  • the level is located in the energy gap of the oxide semiconductor film 108. Therefore, when nitrogen oxide (NOx) diffuses to the interface between the insulating film 110 and the oxide semiconductor film 108, the level may trap electrons on the insulating film 110 side. As a result, trapped electrons remain in the vicinity of the interface between the insulating film 110 and the oxide semiconductor film 108, so that the threshold voltage of the transistor is shifted in the positive direction. Therefore, when the insulating film 110 is a film with a low content of nitrogen oxides, the threshold voltage shift of the transistor can be reduced.
  • a silicon oxynitride film can be used as the insulating film that emits less nitrogen oxide (NO x ).
  • the silicon oxynitride film is a film in which the amount of ammonia released is larger than the amount of nitrogen oxide (NO x ) released in a temperature programmed desorption gas analysis (TDS).
  • TDS temperature programmed desorption gas analysis
  • the discharge amount is 1 ⁇ 10 18 / cm 3 or more and 5 ⁇ 10 19 / cm 3 or less. Note that the amount of ammonia released is the total amount when the temperature of the heat treatment in TDS is in the range of 50 ° C. to 650 ° C. or 50 ° C. to 550 ° C.
  • nitrogen oxide (NO x ) reacts with ammonia and oxygen in the heat treatment, nitrogen oxide (NO x ) is reduced by using an insulating film that releases a large amount of ammonia.
  • the nitrogen concentration in the film is preferably 6 ⁇ 10 20 atoms / cm 3 or less.
  • hafnium silicate HfSiO x
  • hafnium silicate added with nitrogen HfSi x O y N z
  • hafnium aluminate added with nitrogen HfAl x O y N z
  • hafnium oxide or the like
  • High-k materials may be used. By using the high-k material, gate leakage of the transistor can be reduced.
  • the insulating film 116 includes nitrogen or hydrogen.
  • the insulating film 116 may contain fluorine.
  • An example of the insulating film 116 is a nitride insulating film.
  • the nitride insulating film can be formed using silicon nitride, silicon nitride oxide, silicon oxynitride, silicon nitride fluoride, silicon fluoronitride, or the like.
  • the concentration of hydrogen contained in the insulating film 116 is preferably 1 ⁇ 10 22 atoms / cm 3 or more.
  • the insulating film 116 is in contact with the source region 108s and the drain region 108d of the oxide semiconductor film 108. Therefore, the impurity (nitrogen or hydrogen) concentration in the source region 108s and the drain region 108d in contact with the insulating film 116 is increased, and the carrier density of the source region 108s and the drain region 108d can be increased.
  • an oxide insulating film can be used.
  • a stacked film of an oxide insulating film and a nitride insulating film can be used.
  • the insulating film 118 for example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, gallium oxide, Ga—Zn oxide, or the like may be used.
  • the insulating film 118 is preferably a film that functions as a barrier film of hydrogen, water, etc. from the outside.
  • the thickness of the insulating film 118 can be greater than or equal to 30 nm and less than or equal to 500 nm, or greater than or equal to 100 nm and less than or equal to 400 nm.
  • the conductive films 112, 120a, and 120b can be formed by a sputtering method, a vacuum evaporation method, a pulse laser deposition (PLD) method, a thermal CVD method, or the like.
  • a conductive metal film, a conductive film having a function of reflecting visible light, or a conductive film having a function of transmitting visible light may be used.
  • a material containing a metal element selected from aluminum, gold, platinum, silver, copper, chromium, tantalum, titanium, molybdenum, tungsten, nickel, iron, cobalt, palladium, or manganese is used. It can. Alternatively, an alloy containing the above metal element may be used.
  • the conductive metal film described above includes a two-layer structure in which a copper film is stacked on a titanium film, a two-layer structure in which a copper film is stacked on a titanium nitride film, and a copper film on a tantalum nitride film.
  • a two-layer structure to be laminated, a three-layer structure in which a copper film is laminated on a titanium film, and a titanium film is further formed thereon may be used.
  • examples of the conductive film containing a copper element include an alloy film containing copper and manganese. The alloy film is preferable because it can be processed by a wet etching method.
  • a tantalum nitride film is preferably used as the conductive films 112, 120a, and 120b.
  • the tantalum nitride film has conductivity and high barrier properties against copper or hydrogen.
  • the tantalum nitride film can be most preferably used as a metal film in contact with the oxide semiconductor film 108 or a metal film in the vicinity of the oxide semiconductor film 108 because it emits less hydrogen from itself.
  • a conductive polymer or a conductive polymer may be used as the conductive film having the above-described conductivity.
  • the conductive film having a function of reflecting visible light a material containing a metal element selected from gold, silver, copper, or palladium can be used.
  • a conductive film containing a silver element because the reflectance in visible light can be increased.
  • a material containing an element selected from indium, tin, zinc, gallium, or silicon can be used as the conductive film having a function of transmitting visible light.
  • a material containing an element selected from indium, tin, zinc, gallium, or silicon can be used.
  • a film containing graphene or graphite may be used as the conductive film having a function of transmitting visible light.
  • a film containing graphene a film containing graphene can be formed by forming a film containing graphene oxide and reducing the film containing graphene oxide. Examples of the reduction method include a method of applying heat and a method of using a reducing agent.
  • the conductive films 112, 120a, and 120b can be formed by an electroless plating method.
  • a material that can be formed by the electroless plating method for example, any one or more selected from Cu, Ni, Al, Au, Sn, Co, Ag, and Pd can be used.
  • the use of Cu or Ag is preferable because the resistance of the conductive film can be lowered.
  • a diffusion prevention film may be formed under the conductive film so that constituent elements of the conductive film do not diffuse outside.
  • a seed layer capable of growing a conductive film may be formed between the diffusion prevention film and the conductive film.
  • the diffusion preventing film can be formed using, for example, a sputtering method.
  • a tantalum nitride film or a titanium nitride film can be used.
  • the seed layer can be formed by an electroless plating method.
  • a material similar to the material of the conductive film that can be formed by an electroless plating method can be used.
  • an oxide semiconductor typified by an In—Ga—Zn oxide may be used as the conductive film 112.
  • the oxide semiconductor has high carrier density when nitrogen or hydrogen is supplied from the insulating film 116.
  • the oxide semiconductor functions as an oxide conductor (OC: Oxide Conductor). Therefore, the oxide semiconductor can be used as a gate electrode.
  • examples of the conductive film 112 include a single layer structure of an oxide conductor (OC), a single layer structure of a metal film, or a stacked structure of an oxide conductor (OC) and a metal film.
  • the conductive film 112 is formed below the conductive film 112 in the case where a single-layer structure of a light-blocking metal film or a stacked structure of an oxide conductor (OC) and a light-blocking metal film is used. This is preferable because the channel region 108i can be shielded from light.
  • the metal film is formed over the oxide semiconductor or the oxide conductor (OC).
  • the constituent elements in the metal film diffuse to the oxide semiconductor or oxide conductor (OC) side and the resistance is reduced. The resistance is reduced by damage (for example, sputtering damage) or oxygen in the oxide semiconductor or the oxide conductor (OC) is diffused in the metal film, so that oxygen deficiency is formed and the resistance is reduced.
  • the thickness of the conductive films 112, 120a, and 120b can be 30 nm to 500 nm, or 100 nm to 400 nm.
  • FIG. 17A is a top view of the transistor 100A
  • FIG. 17B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 17A
  • FIG. 17C is FIG. It is sectional drawing between dashed-dotted lines Y1-Y2.
  • a transistor 100A illustrated in FIGS. 17A to 17C includes a conductive film 106 over a substrate 102, an insulating film 104 over the conductive film 106, an oxide semiconductor film 108 over the insulating film 104, and an oxide.
  • the insulating film 110 over the semiconductor film 108, the conductive film 112 over the insulating film 110, the insulating film 104, the oxide semiconductor film 108, and the insulating film 116 over the conductive film 112 are included.
  • the oxide semiconductor film 108 includes a channel region 108 i overlapping with the conductive film 112, a source region 108 s in contact with the insulating film 116, and a drain region 108 d in contact with the insulating film 116.
  • the transistor 100A includes a conductive film 106 and an opening 143 in addition to the structure of the transistor 100 described above.
  • the opening 143 is provided in the insulating films 104 and 110.
  • the conductive film 106 is electrically connected to the conductive film 112 through the opening 143. Therefore, the same potential is applied to the conductive film 106 and the conductive film 112. Note that different potentials may be applied to the conductive film 106 and the conductive film 112 without providing the opening 143.
  • the conductive film 106 may be used as a light-blocking film without providing the opening 143. For example, when the conductive film 106 is formed using a light-blocking material, light from below irradiated to the channel region 108 i can be suppressed.
  • the conductive film 106 functions as a first gate electrode (also referred to as a bottom gate electrode), and the conductive film 112 is also referred to as a second gate electrode (also referred to as a top gate electrode). ).
  • the insulating film 104 has a function as a first gate insulating film, and the insulating film 110 has a function as a second gate insulating film.
  • the conductive film 106 As the conductive film 106, the same material as the conductive films 112, 120a, and 120b described above can be used. In particular, the conductive film 106 is preferably formed using a material containing copper because the resistance can be lowered.
  • the conductive film 106 has a stacked structure in which a copper film is provided over a titanium nitride film, a tantalum nitride film, or a tungsten film, and the conductive films 120a and 120b are provided with a copper film over the titanium nitride film, the tantalum nitride film, or the tungsten film. A laminated structure is preferable.
  • the transistor 100A for one or both of the pixel transistor and the driving transistor of the display device, parasitic capacitance generated between the conductive film 106 and the conductive film 120a, and the conductive film 106 and the conductive film 120b The parasitic capacitance generated between them can be reduced. Therefore, the conductive film 106, the conductive film 120a, and the conductive film 120b are used not only as the first gate electrode, the source electrode, and the drain electrode of the transistor 100A, but also for power supply wiring and signal supply of the display device. It can also be used for wiring or wiring for connection.
  • the transistor 100A illustrated in FIGS. 17A to 17C has a structure including conductive films functioning as gate electrodes above and below the oxide semiconductor film 108.
  • the semiconductor device of one embodiment of the present invention may include a plurality of gate electrodes.
  • the oxide semiconductor film 108 is opposite to the conductive film 106 functioning as the first gate electrode and the conductive film 112 functioning as the second gate electrode, respectively. And is sandwiched between conductive films functioning as two gate electrodes.
  • the length of the conductive film 112 in the channel width direction is longer than the length of the oxide semiconductor film 108 in the channel width direction, and the entire length of the oxide semiconductor film 108 in the channel width direction is conductive with the insulating film 110 interposed therebetween.
  • the film 112 is covered. Further, since the conductive film 112 and the conductive film 106 are connected to each other in the insulating film 104 and the opening 143 provided in the insulating film 110, one of the side surfaces in the channel width direction of the oxide semiconductor film 108 is the insulating film 110. Is opposed to the conductive film 112.
  • the conductive film 106 and the conductive film 112 are connected to each other through the insulating film 104 and the opening 143 provided in the insulating film 110, and the insulating film 104 and the insulating film 110 are interposed between them.
  • the oxide semiconductor film 108 is surrounded by the structure.
  • the oxide semiconductor film 108 included in the transistor 100A is electrically connected to the conductive film 106 functioning as the first gate electrode and the conductive film 112 functioning as the second gate electrode. Can be surrounded.
  • a device structure of a transistor that electrically surrounds the oxide semiconductor film 108 in which a channel region is formed by an electric field of the first gate electrode and the second gate electrode is a surround channel (S-channel) structure. Can be called.
  • the transistor 100A Since the transistor 100A has an S-channel structure, an electric field for inducing a channel by the conductive film 106 or the conductive film 112 can be effectively applied to the oxide semiconductor film 108; thus, the current driving capability of the transistor 100A Thus, high on-current characteristics can be obtained. Further, since the on-state current can be increased, the transistor 100A can be miniaturized. In addition, since the transistor 100A has a structure surrounded by the conductive film 106 and the conductive film 112, the mechanical strength of the transistor 100A can be increased.
  • an opening different from the opening 143 may be formed on the side where the opening 143 of the oxide semiconductor film 108 is not formed in the channel width direction of the transistor 100A.
  • the signal A is supplied to one gate electrode and the fixed potential is supplied to the other gate electrode.
  • Vb may be given.
  • the signal A may be given to one gate electrode, and the signal B may be given to the other gate electrode.
  • One gate electrode may be given a fixed potential Va, and the other gate electrode may be given a fixed potential Vb.
  • the signal A is a signal for controlling, for example, a conduction state or a non-conduction state.
  • the signal A may be a digital signal that takes two kinds of potentials, that is, the potential V1 or the potential V2 (V1> V2).
  • the potential V1 can be a high power supply potential and the potential V2 can be a low power supply potential.
  • the signal A may be an analog signal.
  • the fixed potential Vb is a potential for controlling the threshold voltage VthA of the transistor, for example.
  • the fixed potential Vb may be the potential V1 or the potential V2. In this case, it is preferable that a potential generating circuit for generating the fixed potential Vb does not need to be provided separately.
  • the fixed potential Vb may be a potential different from the potential V1 or the potential V2.
  • the threshold voltage VthA can be increased by lowering the fixed potential Vb. As a result, the drain current when the gate-source voltage Vgs is 0 V can be reduced, and the leakage current of a circuit including a transistor can be reduced in some cases.
  • the fixed potential Vb may be set lower than the low power supply potential.
  • the threshold voltage VthA can be lowered by increasing the fixed potential Vb.
  • the drain current when the gate-source voltage Vgs is at a high power supply potential can be improved, and the operation speed of a circuit including a transistor can be improved in some cases.
  • the fixed potential Vb may be higher than the low power supply potential.
  • the signal B is a signal for controlling a conduction state or a non-conduction state, for example.
  • the signal B may be a digital signal that takes two kinds of potentials, that is, the potential V3 or the potential V4 (V3> V4).
  • the potential V3 can be a high power supply potential and the potential V4 can be a low power supply potential.
  • the signal B may be an analog signal.
  • the signal B may be a signal having the same digital value as the signal A.
  • the on-state current of the transistor can be improved and the operation speed of the circuit including the transistor can be improved in some cases.
  • the potential V1 and the potential V2 in the signal A may be different from the potential V3 and the potential V4 in the signal B.
  • the potential amplitude (V3 to V4) of the signal B is It may be larger than the potential amplitude (V1-V2). By doing so, the influence of the signal A and the influence of the signal B on the conduction state or non-conduction state of the transistor may be approximately the same.
  • the signal B may be a signal having a digital value different from that of the signal A.
  • the transistor can be controlled separately by the signal A and the signal B, and a higher function may be realized.
  • the transistor is an n-channel transistor
  • the transistor A is in a conductive state only when the signal A is the potential V1 and the signal B is the potential V3, or the signal A is the potential V2 and the signal B is In the case where a non-conducting state is obtained only when the potential is V4, functions such as a NAND circuit and a NOR circuit may be realized with one transistor.
  • the signal B may be a signal for controlling the threshold voltage VthA.
  • the signal B may be a signal having a different potential between a period in which a circuit including a transistor is operating and a period in which the circuit is not operating.
  • the signal B may be a signal having a different potential according to the operation mode of the circuit. In this case, the potential of the signal B may not be switched as frequently as the signal A.
  • the signal B is an analog signal having the same potential as the signal A, an analog signal obtained by multiplying the potential of the signal A by a constant, or the potential of the signal A is added or subtracted by a constant.
  • An analog signal or the like may be used.
  • the on-state current of the transistor can be improved and the operation speed of the circuit including the transistor can be improved in some cases.
  • the signal B may be an analog signal different from the signal A. In this case, the transistor can be controlled separately by the signal A and the signal B, and a higher function may be realized.
  • the signal A may be a digital signal and the signal B may be an analog signal.
  • the signal A may be an analog signal and the signal B may be a digital signal.
  • the transistor When a fixed potential is applied to both gate electrodes of a transistor, the transistor may function as an element equivalent to a resistance element.
  • the effective resistance of the transistor can be decreased (increased) by increasing (decreasing) the fixed potential Va or the fixed potential Vb in some cases.
  • an effective resistance lower (higher) than that obtained by a transistor having only one gate may be obtained.
  • FIGS. 18A and 18B are cross-sectional views of the transistor 100B.
  • a top view of the transistor 100B is similar to that of the transistor 100A illustrated in FIG. 17A; therefore, description thereof is omitted here.
  • 18A and 18B includes the insulating film 122 over the conductive films 120a and 120b and the insulating film 118.
  • the transistor 100B illustrated in FIGS. Other configurations are similar to those of the transistor 100A, and have the same effects.
  • the insulating film 122 has a function of flattening unevenness caused by a transistor or the like.
  • the insulating film 122 only needs to be insulative and is formed using an inorganic material or an organic material.
  • the inorganic material include a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, and an aluminum nitride film.
  • photosensitive resin materials such as an acrylic resin or a polyimide resin, are mentioned, for example.
  • FIGS. 19A and 19B are cross-sectional views of the transistor 100C
  • FIGS. 20A and 20B are cross-sectional views of the transistor 100D
  • FIGS. 21A and 21B are cross-sectional views of the transistor 100E.
  • FIG. Note that top views of the transistor 100C, the transistor 100D, and the transistor 100E are the same as those of the transistor 100A illustrated in FIG. 17A, and thus description thereof is omitted here.
  • 19A and 19B is different from the transistor 100A in the stacked structure of the conductive film 112, the shape of the conductive film 112, and the shape of the insulating film 110.
  • the conductive film 112 of the transistor 100C includes a conductive film 112_1 over the insulating film 110 and a conductive film 112_2 over the conductive film 112_1.
  • excess oxide can be added to the insulating film 110 by using an oxide conductive film as the conductive film 112_1.
  • the oxide conductive film can be formed in an atmosphere containing oxygen gas by a sputtering method.
  • an oxide having indium and tin an oxide having tungsten and indium, an oxide having tungsten, indium, and zinc, an oxide having titanium and indium
  • examples thereof include an oxide having titanium, indium, and tin, an oxide having indium and zinc, an oxide having silicon, indium, and tin, and an oxide having indium, gallium, and zinc.
  • the conductive film 112_2 and the conductive film 106 are connected to each other in the opening 143.
  • the opening 143 is formed, after the conductive film to be the conductive film 112_1 is formed, the opening 143 is formed, whereby the shape illustrated in FIG. 19B can be obtained.
  • the connection resistance between the conductive film 112 and the conductive film 106 can be reduced by connecting the conductive film 112_2 and the conductive film 106.
  • the conductive film 112 and the insulating film 110 of the transistor 100C are tapered. More specifically, the lower end portion of the conductive film 112 is formed outside the upper end portion of the conductive film 112. The lower end portion of the insulating film 110 is formed outside the upper end portion of the insulating film 110. Further, the lower end portion of the conductive film 112 is formed at substantially the same position as the upper end portion of the insulating film 110.
  • the conductive film 112 and the insulating film 110 of the transistor 100C have a tapered shape because the coverage of the insulating film 116 can be increased as compared with the case where the conductive film 112 and the insulating film 110 of the transistor 100A are rectangular. is there.
  • 20A and 20B is different from the transistor 100A in the stacked structure of the conductive film 112, the shape of the conductive film 112, and the shape of the insulating film 110.
  • the conductive film 112 of the transistor 100D includes a conductive film 112_1 over the insulating film 110 and a conductive film 112_2 over the conductive film 112_1.
  • the lower end portion of the conductive film 112_1 is formed outside the upper end portion of the conductive film 112_2.
  • the conductive film 112_1, the conductive film 112_2, and the insulating film 110 are processed with the same mask, the conductive film 112_2 is processed with a wet etching method, and the conductive film 112_1 and the insulating film 110 are processed with a dry etching method.
  • the above structure can be obtained.
  • the region 108f may be formed in the oxide semiconductor film 108 in some cases.
  • the region 108f is formed between the channel region 108i and the source region 108s, and between the channel region 108i and the drain region 108d.
  • the region 108f functions as either a high resistance region or a low resistance region.
  • the high resistance region is a region which has a resistance equivalent to that of the channel region 108 i and does not overlap with the conductive film 112 functioning as a gate electrode.
  • the region 108f functions as a so-called offset region.
  • the region 108f may be 1 ⁇ m or less in the channel length (L) direction in order to suppress a decrease in on-state current of the transistor 100D.
  • the low resistance region is a region having a resistance lower than that of the channel region 108i and higher than that of the source region 108s and the drain region 108d.
  • the region 108f functions as a so-called LDD (Lightly Doped Drain) region.
  • LDD Lightly Doped Drain
  • the region 108f is an LDD region
  • one or more of nitrogen, hydrogen, and fluorine is supplied from the insulating film 116 to the region 108f, or the conductive film 112_1 is used with the insulating film 110 and the conductive film 112_1 as a mask.
  • the impurity can be formed by being added to the oxide semiconductor film 108 through the conductive film 112_1 and the insulating film 110.
  • the conductive film 112_2 and the conductive film 106 are connected to each other in the opening 143.
  • 21A and 21B is different from the transistor 100A in the stacked structure of the conductive film 112, the shape of the conductive film 112, and the shape of the insulating film 110.
  • the conductive film 112 of the transistor 100E includes a conductive film 112_1 over the insulating film 110 and a conductive film 112_2 over the conductive film 112_1.
  • the lower end portion of the conductive film 112_1 is formed outside the lower end portion of the conductive film 112_2.
  • the lower end portion of the insulating film 110 is formed outside the lower end portion of the conductive film 112_1.
  • the conductive film 112_1, the conductive film 112_, and the insulating film 110 are processed using the same mask
  • the conductive film 112_2 and the conductive film 112_1 are processed using a wet etching method
  • the insulating film 110 is processed using a dry etching method.
  • the transistor 100E may have a region 108f formed in the oxide semiconductor film 108.
  • the region 108f is formed between the channel region 108i and the source region 108s, and between the channel region 108i and the drain region 108d.
  • the conductive film 112_2 and the conductive film 106 are connected to each other in the opening 143.
  • FIGS. 22A and 22B are cross-sectional views of the transistor 100F
  • FIGS. 23A and 23B are cross-sectional views of the transistor 100G
  • FIGS. 24A and 24B are cross-sectional views of the transistor 100H
  • 25A and 25B are cross-sectional views of the transistor 100J
  • FIGS. 26A and 26B are cross-sectional views of the transistor 100K. Note that the top view of the transistor 100F, the transistor 100G, the transistor 100H, the transistor 100J, and the transistor 100K is similar to the transistor 100A illustrated in FIG. 17A; therefore, description thereof is omitted here.
  • the transistor 100F, the transistor 100G, the transistor 100H, the transistor 100J, and the transistor 100K are different from each other in the structure of the transistor 100A and the oxide semiconductor film 108 described above.
  • Other configurations are similar to those of the transistor 100A described above, and have the same effects.
  • 22A and 22B includes an oxide semiconductor film 108_1 over the insulating film 104, an oxide semiconductor film 108_2 over the oxide semiconductor film 108_1, and an oxide semiconductor.
  • the channel region 108i, the source region 108s, and the drain region 108d each have a three-layer structure of the oxide semiconductor film 108_1, the oxide semiconductor film 108_2, and the oxide semiconductor film 108_3.
  • the oxide semiconductor film 108 included in the transistor 100G includes an oxide semiconductor film 108_2 over the insulating film 104 and an oxide semiconductor film 108_3 over the oxide semiconductor film 108_2.
  • the channel region 108i, the source region 108s, and the drain region 108d each have a two-layer structure of an oxide semiconductor film 108_2 and an oxide semiconductor film 108_3.
  • the oxide semiconductor film 108 included in the transistor 100H includes an oxide semiconductor film 108_1 over the insulating film 104 and an oxide semiconductor film 108_2 over the oxide semiconductor film 108_1.
  • the channel region 108i, the source region 108s, and the drain region 108d each have a two-layer structure of the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2.
  • An oxide semiconductor film 108 included in the transistor 100J illustrated in FIGS. 25A and 25B includes an oxide semiconductor film 108_1 over the insulating film 104, an oxide semiconductor film 108_2 over the oxide semiconductor film 108_1, and an oxide semiconductor.
  • the channel region 108i has a three-layer structure of the oxide semiconductor film 108_1, the oxide semiconductor film 108_2, and the oxide semiconductor film 108_3.
  • the source region 108s and the drain region 108d each have an oxide semiconductor film.
  • the oxide semiconductor film 108 included in the transistor 100K illustrated in FIGS. 26A and 26B includes an oxide semiconductor film 108_2 over the insulating film 104 and an oxide semiconductor film 108_3 over the oxide semiconductor film 108_2.
  • the channel region 108i has a two-layer structure of an oxide semiconductor film 108_2 and an oxide semiconductor film 108_3, and the source region 108s and the drain region 108d have a single layer structure of the oxide semiconductor film 108_2, respectively. is there. Note that in the cross section of the transistor 100K in the channel width (W) direction, the oxide semiconductor film 108_3 covers the side surface of the oxide semiconductor film 108_2.
  • the channel region 108i in the channel width (W) direction or in the vicinity thereof defects (for example, oxygen vacancies) are likely to be formed due to damage in processing, or contamination due to adhesion of impurities. Therefore, even when the channel region 108i is substantially intrinsic, application of stress such as an electric field activates the side surface of the channel region 108i in the channel width (W) direction or the vicinity thereof, thereby reducing low resistance (n Type) area.
  • stress such as an electric field activates the side surface of the channel region 108i in the channel width (W) direction or the vicinity thereof, thereby reducing low resistance (n Type) area.
  • the side surface in the channel width (W) direction of the channel region 108i or the vicinity thereof is an n-type region, a parasitic channel may be formed because the n-type region serves as a carrier path.
  • the channel region 108i has a stacked structure, and the side surface in the channel width (W) direction of the channel region 108i is covered with one layer of the stacked structure.
  • defects on the side surface of the channel region 108i or the vicinity thereof can be suppressed, or adhesion of impurities to the side surface of the channel region 108i or the vicinity thereof can be reduced.
  • FIG. 27A illustrates an example of a band structure in a film thickness direction of a stacked structure including the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3, and the insulating film 110.
  • FIG. 27B illustrates an example of a band structure in the film thickness direction of a stacked structure including the insulating film 104, the oxide semiconductor films 108_2 and 108_3, and the insulating film 110.
  • FIG. 27C illustrates an example of a band structure in the film thickness direction of a stacked structure including the insulating film 104, the oxide semiconductor films 108_1 and 108_2, and the insulating film 110.
  • the band structure indicates the energy level (Ec) of the lower end of the conduction band of the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3, and the insulating film 110 for easy understanding.
  • FIG. 10 is a band diagram of a structure using an oxide semiconductor film.
  • FIG. 10 is a band diagram of a structure using an oxide semiconductor film formed using an oxide semiconductor film.
  • the energy level at the lower end of the conduction band changes gently.
  • the energy level at the lower end of the conduction band in the oxide semiconductor films 108_1 and 108_2 changes gently. In other words, it can be said that it is continuously changed or continuously joined.
  • a trap center or a recombination center is formed at the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2 or the interface between the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3. It is assumed that there is no impurity that forms such a defect level.
  • each film is continuously formed without being exposed to the air using a multi-chamber film formation apparatus (sputtering apparatus) including a load lock chamber. It is necessary to laminate them.
  • sputtering apparatus sputtering apparatus
  • the oxide semiconductor film 108_2 becomes a well, and a channel region is formed in the oxide semiconductor film 108_2 in the transistor including the above stacked structure.
  • the trap level can be further away from the oxide semiconductor film 108_2.
  • the defect level may be farther from the vacuum level than the energy level (Ec) at the lower end of the conduction band of the oxide semiconductor film 108_2 functioning as a channel region, and electrons are likely to accumulate in the defect level. . Accumulation of electrons at the defect level results in a negative fixed charge, and the threshold voltage of the transistor shifts in the positive direction. Therefore, it is preferable that the defect level be closer to the vacuum level than the energy level (Ec) at the lower end of the conduction band of the oxide semiconductor film 108_2. Thus, electrons are less likely to accumulate at the defect level, the on-state current of the transistor can be increased, and field effect mobility can be increased.
  • the oxide semiconductor films 108_1 and 108_3 each have an energy level at the lower end of the conduction band that is closer to the vacuum level than the oxide semiconductor film 108_2. Typically, the energy level at the lower end of the conduction band of the oxide semiconductor film 108_2. And the energy level at the lower end of the conduction band of the oxide semiconductor films 108_1 and 108_3 is 0.15 eV or more, 0.5 eV or more, 2 eV or less, or 1 eV or less.
  • the difference between the electron affinity of the oxide semiconductor films 108_1 and 108_3 and the electron affinity of the oxide semiconductor film 108_2 is 0.15 eV or more, 0.5 eV or more, 2 eV or less, or 1 eV or less.
  • the oxide semiconductor film 108_2 becomes a main current path.
  • the oxide semiconductor film 108_2 functions as a channel region
  • the oxide semiconductor films 108_1 and 108_3 function as oxide insulating films.
  • the oxide semiconductor films 108_1 and 108_3 are preferably formed using one or more metal elements included in the oxide semiconductor film 108_2 in which a channel region is formed.
  • the oxide semiconductor films 108_1 and 108_3 are formed using a material with sufficiently low conductivity in order to prevent the oxide semiconductor films 108_1 and 108_3 from functioning as part of the channel region. Therefore, the oxide semiconductor films 108_1 and 108_3 can also be referred to as oxide insulating films because of their physical properties and / or functions.
  • the electron affinity difference between the vacuum level and the energy level at the bottom of the conduction band
  • the energy level at the bottom of the conduction band is an oxide.
  • a material having a difference (band offset) from the lower energy level of the conduction band of the semiconductor film 108_2 is used.
  • the energy level at the lower end of the conduction band of the oxide semiconductor films 108_1 and 108_3 is determined so that the conduction level of the oxide semiconductor film 108_2 is reduced. It is preferable to use a material closer to the vacuum level than the energy level at the lower end of the band.
  • the difference between the energy level at the bottom of the conduction band of the oxide semiconductor film 108_2 and the energy level at the bottom of the conduction bands of the oxide semiconductor films 108_1 and 108_3 is 0.2 eV or more, preferably 0.5 eV or more. It is preferable.
  • the oxide semiconductor films 108_1 and 108_3 do not include a spinel crystal structure.
  • the constituent elements of the conductive films 120a and 120b enter the oxide semiconductor film 108_2 at the interface between the spinel crystal structure and another region. May diffuse.
  • the oxide semiconductor films 108_1 and 108_3 be a CAAC-OS to be described later because the blocking properties of constituent elements of the conductive films 120a and 120b, for example, a copper element are increased.
  • the configuration using the film is exemplified, the configuration is not limited thereto.
  • the oxide semiconductor films 108_1 and 108_3 are preferable because the difference from the energy level at the lower end of the conduction band can be 0.6 eV or more.
  • FIG. 28A is a top view of the transistor 300A
  • FIG. 28B corresponds to a cross-sectional view of a cross section taken along dashed-dotted line X1-X2 in FIG. 28A.
  • some components such as an insulating film functioning as a gate insulating film
  • the direction of the alternate long and short dash line X1-X2 may be referred to as a channel length direction, and the direction of the alternate long and short dash line Y1-Y2 may be referred to as a channel width direction. Note that in the top view of the transistor, some components may be omitted in the following drawings as in FIG. 28A.
  • a transistor 300A illustrated in FIG. 28 includes a conductive film 304 over a substrate 302, an insulating film 306 over the substrate 302 and the conductive film 304, an insulating film 307 over the insulating film 306, and an oxide semiconductor film 308 over the insulating film 307.
  • a conductive film 312 a over the oxide semiconductor film 308 and a conductive film 312 b over the oxide semiconductor film 308.
  • insulating films 314 and 316 and an insulating film 318 are provided over the transistor 300A, more specifically, over the conductive films 312a and 312b and the oxide semiconductor film 308.
  • the insulating films 306 and 307 function as gate insulating films of the transistor 300A, and the insulating films 314, 316, and 318 function as protective insulating films of the transistor 300A.
  • the conductive film 304 functions as a gate electrode
  • the conductive film 312a functions as a source electrode
  • the conductive film 312b functions as a drain electrode.
  • the insulating films 306 and 307 may be referred to as a first insulating film, the insulating films 314 and 316 as a second insulating film, and the insulating film 318 as a third insulating film, respectively. is there.
  • the transistor 300A shown in FIG. 28 has a channel etch type transistor structure.
  • the oxide semiconductor film of one embodiment of the present invention can be favorably used for a channel-etched transistor.
  • FIG. 29A is a top view of the transistor 300B, and FIG. 29B corresponds to a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 29A. Corresponds to a cross-sectional view of a cut surface taken along the alternate long and short dash line Y1-Y2 shown in FIG.
  • a transistor 300B illustrated in FIG. 29 includes a conductive film 304 over a substrate 302, an insulating film 306 over the substrate 302 and the conductive film 304, an insulating film 307 over the insulating film 306, and an oxide semiconductor film 308 over the insulating film 307. And the insulating film 314 over the oxide semiconductor film 308, the insulating film 316 over the insulating film 314, and the oxide semiconductor film 308 through the openings 341a provided in the insulating film 314 and the insulating film 316. And a conductive film 312b which is electrically connected to the oxide semiconductor film 308 through an opening 341b provided in the insulating film 314 and the insulating film 316. An insulating film 318 is provided over the transistor 300B, more specifically, over the conductive films 312a and 312b and the insulating film 316.
  • the insulating films 306 and 307 function as gate insulating films of the transistor 300B, and the insulating films 314 and 316 have functions as protective insulating films of the oxide semiconductor film 308.
  • the film 318 functions as a protective insulating film of the transistor 300B.
  • the conductive film 304 functions as a gate electrode
  • the conductive film 312a functions as a source electrode
  • the conductive film 312b functions as a drain electrode.
  • the transistor 300B shown in FIGS. 29A, 29B, and 29C has a channel protection type structure.
  • the oxide semiconductor film of one embodiment of the present invention can be favorably used for a channel protection transistor.
  • FIG. 30A is a top view of the transistor 300C
  • FIG. 30B corresponds to a cross-sectional view of a cross section taken along dashed-dotted line X1-X2 in FIG. 30A.
  • FIG. 31A is a top view of the transistor 300D
  • FIG. 31B corresponds to a cross-sectional view of a cross section taken along dashed-dotted line X1-X2 in FIG.
  • a transistor 300D illustrated in FIG. 31 includes a conductive film 304 over a substrate 302, an insulating film 306 over the substrate 302 and the conductive film 304, an insulating film 307 over the insulating film 306, and an oxide semiconductor film 308 over the insulating film 307.
  • An insulating film 316, an insulating film 318 over the insulating film 316, and conductive films 320a and 320b over the insulating film 318 are included.
  • the insulating films 306 and 307 function as a first gate insulating film of the transistor 300D
  • the insulating films 314, 316, and 318 function as a second gate insulating film of the transistor 300D.
  • the conductive film 304 has a function as a first gate electrode
  • the conductive film 320a has a function as a second gate electrode
  • the conductive film 320b is a pixel used for a display device. It has a function as an electrode.
  • the conductive film 312a functions as a source electrode
  • the conductive film 312b functions as a drain electrode.
  • the conductive film 320a is connected to the conductive film 304 in openings 342b and 342c provided in the insulating films 306, 307, 314, 316, and 318. Therefore, the same potential is applied to the conductive film 320a and the conductive film 304.
  • the opening portions 342b and 342c are provided and the conductive film 320a and the conductive film 304 are connected to each other, but the invention is not limited thereto.
  • a structure in which only one of the opening 342b and the opening 342c is formed and the conductive film 320a and the conductive film 304 are connected, or the conductive film 320a without the opening 342b and the opening 342c is provided.
  • the conductive film 304 may not be connected. Note that in the case where the conductive film 320a and the conductive film 304 are not connected to each other, different potentials can be applied to the conductive film 320a and the conductive film 304, respectively.
  • the conductive film 320b is connected to the conductive film 312b through the opening 342a provided in the insulating films 314, 316, and 318.
  • transistor 300D has the S-channel structure described above.
  • the oxide semiconductor film 308 included in the transistor 300A illustrated in FIGS. 28A, 28B, and 28C may have a stacked structure. Examples of such cases are shown in FIGS. 32A and 32B and FIGS. 33A and 33B.
  • FIGS. 33A and 33B are cross-sectional views of the transistor 300E
  • FIGS. 33A and 33B are cross-sectional views of the transistor 300F. Note that top views of the transistors 300E and 300F are similar to those of the transistor 300A illustrated in FIG.
  • the oxide semiconductor film 308 included in the transistor 300E includes an oxide semiconductor film 308_1, an oxide semiconductor film 308_2, and an oxide semiconductor film 308_3.
  • the oxide semiconductor film 308 included in the transistor 300F illustrated in FIGS. 33A and 33B includes an oxide semiconductor film 308_2 and an oxide semiconductor film 308_3.
  • the conductive film 304, the insulating film 306, the insulating film 307, the oxide semiconductor film 308, the oxide semiconductor film 308_1, the oxide semiconductor film 308_2, the oxide semiconductor film 308_3, the conductive films 312a and 312b, the insulating film 314, and the insulating film 316, the insulating film 318, and the conductive films 320a and 320b include the conductive film 106, the insulating film 116, the insulating film 114, the oxide semiconductor film 108, the oxide semiconductor film 108_1, the oxide semiconductor film 108_2, and the like described above, respectively.
  • a material similar to that of the oxide semiconductor film 108_3, the conductive films 120a and 120b, the insulating film 104, the insulating film 118, the insulating film 116, and the conductive film 112 can be used.
  • FIG. 34A is a top view of the transistor 300G
  • FIG. 34B corresponds to a cross-sectional view of a cross section taken along dashed-dotted line X1-X2 in FIG. 34A.
  • the upper insulating film 316, the conductive film 320a over the insulating film 316, and the conductive film 320b over the insulating film 316 are included.
  • the insulating film 306 and the insulating film 307 have an opening 351, and a conductive film 312c that is electrically connected to the conductive film 304 through the opening 351 is formed over the insulating film 306 and the insulating film 307. Is done.
  • the insulating film 314 and the insulating film 316 include an opening 352a reaching the conductive film 312b and an opening 352b reaching the conductive film 312c.
  • the oxide semiconductor film 308 includes an oxide semiconductor film 308_2 on the conductive film 304 side and an oxide semiconductor film 308_3 over the oxide semiconductor film 308_2.
  • an insulating film 318 is provided over the transistor 300G.
  • the insulating film 318 is formed so as to cover the insulating film 316, the conductive film 320a, and the conductive film 320b.
  • the insulating films 306 and 307 have a function as a first gate insulating film of the transistor 300G, and the insulating films 314 and 316 have a function as a second gate insulating film of the transistor 300G.
  • the insulating film 318 functions as a protective insulating film of the transistor 300G.
  • the conductive film 304 functions as a first gate electrode
  • the conductive film 320a functions as a second gate electrode
  • the conductive film 320b is a pixel used for a display device. It has a function as an electrode.
  • the conductive film 312a functions as a source electrode
  • the conductive film 312b functions as a drain electrode.
  • the conductive film 312c functions as a connection electrode.
  • transistor 300G has the S-channel structure described above.
  • the structures of the transistors 300A to 300G may be used in any combination.
  • FIG. 35 is a top view showing an example of the display device.
  • a display device 700 illustrated in FIG. 35 includes a pixel portion 702 provided over a first substrate 701, a source driver circuit portion 704 and a gate driver circuit portion 706 provided over the first substrate 701, a pixel portion 702,
  • the sealant 712 is disposed so as to surround the source driver circuit portion 704 and the gate driver circuit portion 706, and the second substrate 705 is provided so as to face the first substrate 701.
  • the first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are sealed with the first substrate 701, the sealant 712, and the second substrate 705.
  • a display element is provided between the first substrate 701 and the second substrate 705.
  • the display device 700 includes a pixel portion 702, a source driver circuit portion 704, a gate driver circuit portion 706, and a gate driver circuit portion in a region different from the region surrounded by the sealant 712 over the first substrate 701. 706 and an FPC terminal portion 708 (FPC: Flexible printed circuit) electrically connected to each other.
  • FPC Flexible printed circuit
  • an FPC 716 is connected to the FPC terminal portion 708, and various signals are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 by the FPC 716.
  • a signal line 710 is connected to each of the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708.
  • Various signals and the like supplied by the FPC 716 are supplied to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708 through the signal line 710.
  • a plurality of gate driver circuit portions 706 may be provided in the display device 700.
  • the display device 700 an example in which the source driver circuit portion 704 and the gate driver circuit portion 706 are formed over the same first substrate 701 as the pixel portion 702 is shown; however, the display device 700 is not limited to this structure.
  • only the gate driver circuit portion 706 may be formed on the first substrate 701, or only the source driver circuit portion 704 may be formed on the first substrate 701.
  • a substrate on which a source driver circuit, a gate driver circuit, or the like is formed eg, a driver circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film
  • a connection method of a separately formed drive circuit board is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or the like can be used.
  • the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 included in the display device 700 include a plurality of transistors.
  • the display device 700 can have various elements.
  • the element include, for example, an electroluminescence (EL) element (an EL element including an organic substance and an inorganic substance, an organic EL element, an inorganic EL element, an LED, and the like), a light-emitting transistor element (a transistor that emits light in response to current), an electron Emission element, liquid crystal element, electronic ink element, electrophoretic element, electrowetting element, plasma display panel (PDP), MEMS (micro electro mechanical system) display (for example, grating light valve (GLV), digital micromirror Devices (DMD), digital micro shutter (DMS) elements, interferometric modulation (IMOD) elements, etc.), piezoelectric ceramic displays, and the like.
  • EL electroluminescence
  • a light-emitting transistor element a transistor that emits light in response to current
  • an electron Emission element for example, grating light valve (GLV), digital micromirror Devices (DMD), digital micro shutter (DMS) elements,
  • An example of a display device using an EL element is an EL display.
  • a display device using an electron-emitting device there is a field emission display (FED), a SED type flat display (SED: Surface-conduction Electron-emitter Display), or the like.
  • FED field emission display
  • SED SED type flat display
  • a display device using a liquid crystal element there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like.
  • An example of a display device using an electronic ink element or an electrophoretic element is electronic paper.
  • part or all of the pixel electrode may have a function as a reflective electrode.
  • part or all of the pixel electrode may have aluminum, silver, or the like.
  • a memory circuit such as an SRAM can be provided under the reflective electrode. Thereby, power consumption can be further reduced.
  • the color elements controlled by the pixels when performing color display are not limited to three colors of RGB (R represents red, G represents green, and B represents blue).
  • RGB red
  • G represents green
  • B represents blue
  • it may be composed of four pixels: an R pixel, a G pixel, a B pixel, and a W (white) pixel.
  • one color element may be configured by two colors of RGB, and two different colors may be selected and configured depending on the color element.
  • one or more colors such as yellow, cyan, and magenta may be added to RGB.
  • the size of the display area may be different for each dot of the color element.
  • the disclosed invention is not limited to a display device for color display, and can be applied to a display device for monochrome display.
  • a colored layer (also referred to as a color filter) may be used in order to display white light (W) in a backlight (an organic EL element, an inorganic EL element, an LED, a fluorescent lamp, or the like) and display a full color display device.
  • a backlight an organic EL element, an inorganic EL element, an LED, a fluorescent lamp, or the like
  • red (R), green (G), blue (B), yellow (Y), and the like can be used in appropriate combination for the colored layer.
  • the colored layer the color reproducibility can be increased as compared with the case where the colored layer is not used.
  • white light in a region having no colored layer may be directly used for display by arranging a region having a colored layer and a region having no colored layer.
  • a decrease in luminance due to the colored layer can be reduced during bright display, and power consumption can be reduced by about 20% to 30%.
  • a self-luminous element such as an organic EL element or an inorganic EL element
  • R, G, B, Y, and W may be emitted from elements having respective emission colors.
  • power consumption may be further reduced as compared with the case where a colored layer is used.
  • colorization method in addition to a method (color filter method) in which part of the light emission from the white light emission described above is converted into red, green, and blue through a color filter, red, green, and blue light emission is performed.
  • a method of using each (three-color method) or a method of converting a part of light emission from blue light emission into red or green (color conversion method, quantum dot method) may be applied.
  • FIGS. 36 and FIG. 37 are cross-sectional views taken along one-dot chain line QR shown in FIG. 35, in which a liquid crystal element is used as a display element.
  • FIG. 38 is a cross-sectional view taken along one-dot chain line QR shown in FIG. 35 and has a configuration using an EL element as a display element.
  • a display device 700 illustrated in FIGS. 36 to 38 includes a lead wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. Further, the lead wiring portion 711 includes a signal line 710. In addition, the pixel portion 702 includes a transistor 750 and a capacitor 790. In addition, the source driver circuit portion 704 includes a transistor 752.
  • the transistor 750 and the transistor 752 have the same structure as the transistor 100B described above. Note that as the structures of the transistor 750 and the transistor 752, other transistors described in the above embodiment may be used.
  • the transistor used in this embodiment includes an oxide semiconductor film which is highly purified and suppresses formation of oxygen vacancies.
  • the transistor can have low off-state current. Therefore, the holding time of an electric signal such as an image signal can be increased, and the writing interval can be set longer in the power-on state. Therefore, since the frequency of the refresh operation can be reduced, there is an effect of suppressing power consumption.
  • the transistor used in this embodiment can be driven at high speed because relatively high field-effect mobility can be obtained.
  • the switching transistor in the pixel portion and the driver transistor used in the driver circuit portion can be formed over the same substrate. That is, since it is not necessary to use a semiconductor device formed of a silicon wafer or the like as a separate drive circuit, the number of parts of the semiconductor device can be reduced.
  • a high-quality image can be provided by using a transistor that can be driven at high speed.
  • the capacitor 790 includes a lower electrode formed through a step of processing the same conductive film as the conductive film that functions as the first gate electrode included in the transistor 750, and a conductive function that functions as a source electrode and a drain electrode included in the transistor 750. And an upper electrode formed through a process of processing the same conductive film as the film. Further, between the lower electrode and the upper electrode, an insulating film formed through a process of forming the same insulating film as the first gate insulating film of the transistor 750 and protection of the transistor 750 An insulating film formed through a step of forming the same insulating film as the insulating film functioning as the insulating film is provided. That is, the capacitor 790 has a stacked structure in which an insulating film functioning as a dielectric film is sandwiched between a pair of electrodes.
  • a planarization insulating film 770 is provided over the transistor 750, the transistor 752, and the capacitor 790.
  • the pixel portion 702 and the source driver circuit portion 704 may use different transistors. Specifically, a top-gate transistor is used for the pixel portion 702 and a bottom-gate transistor is used for the source driver circuit portion 704, or a bottom-gate transistor is used for the pixel portion 702, and the source driver circuit portion 704 is used. In addition, a configuration using a top gate type transistor can be given. Note that the source driver circuit portion 704 may be replaced with a gate driver circuit portion.
  • the signal line 710 is formed through the same process as the conductive film functioning as the source electrode and the drain electrode of the transistors 750 and 752. For example, when a material containing a copper element is used as the signal line 710, signal delay due to wiring resistance is small and display on a large screen is possible.
  • the FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 716.
  • the connection electrode 760 is formed through the same process as the conductive film functioning as the source and drain electrodes of the transistors 750 and 752.
  • the connection electrode 760 is electrically connected to a terminal included in the FPC 716 through an anisotropic conductive film 780.
  • first substrate 701 and the second substrate 705 for example, glass substrates can be used.
  • a flexible substrate may be used as the first substrate 701 and the second substrate 705.
  • the flexible substrate include a plastic substrate.
  • a structure body 778 is provided between the first substrate 701 and the second substrate 705.
  • the structure body 778 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Note that a spherical spacer may be used as the structure body 778.
  • a light shielding film 738 functioning as a black matrix, a colored film 736 functioning as a color filter, and an insulating film 734 in contact with the light shielding film 738 and the colored film 736 are provided.
  • a display device 700 illustrated in FIG. 36 includes a liquid crystal element 775.
  • the liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776.
  • the conductive film 774 is provided on the second substrate 705 side and functions as a counter electrode.
  • a display device 700 illustrated in FIG. 36 can display an image by controlling transmission and non-transmission of light by changing the alignment state of the liquid crystal layer 776 depending on voltages applied to the conductive films 772 and 774.
  • the conductive film 772 is electrically connected to a conductive film functioning as a source electrode and a drain electrode of the transistor 750.
  • the conductive film 772 is formed over the planarization insulating film 770 and functions as one electrode of the pixel electrode or the display element.
  • a conductive film that is transparent to visible light or a conductive film that is reflective to visible light can be used.
  • a material containing one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used.
  • a material containing aluminum or silver is preferably used.
  • the display device 700 is a reflective liquid crystal display device. In the case where a conductive film that transmits visible light is used for the conductive film 772, the display device 700 is a transmissive liquid crystal display device.
  • the driving method of the liquid crystal element can be changed by changing the structure over the conductive film 772.
  • FIG. A display device 700 illustrated in FIG. 37 is an example of a configuration using a horizontal electric field method (eg, an FFS mode) as a driving method of a liquid crystal element.
  • the insulating film 773 is provided over the conductive film 772, and the conductive film 774 is provided over the insulating film 773.
  • the conductive film 774 functions as a common electrode (also referred to as a common electrode), and the alignment of the liquid crystal layer 776 is generated by an electric field generated between the conductive film 772 and the conductive film 774 through the insulating film 773. The state can be controlled.
  • an alignment film may be provided on one or both of the conductive film 772 and the conductive film 774 on the side in contact with the liquid crystal layer 776.
  • an optical member optical substrate
  • a polarizing member such as a polarizing member, a retardation member, or an antireflection member
  • circularly polarized light using a polarizing substrate and a retardation substrate may be used.
  • a backlight, a sidelight, or the like may be used as the light source.
  • thermotropic liquid crystal When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like depending on conditions.
  • a liquid crystal exhibiting a blue phase without using an alignment film may be used.
  • the blue phase is one of the liquid crystal phases.
  • the temperature of the cholesteric liquid crystal is increased, the blue phase appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with several percent by weight or more of a chiral agent is used for the liquid crystal layer in order to improve the temperature range.
  • a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed and is optically isotropic, so that alignment treatment is unnecessary.
  • a liquid crystal material exhibiting a blue phase has a small viewing angle dependency.
  • a liquid crystal element when used as a display element, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axial Symmetrical Aligned MicroOcell) mode.
  • a Compensated Birefringence mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (Antiferroelectric Liquid Crystal) mode, and the like can be used.
  • a normally black liquid crystal display device such as a transmissive liquid crystal display device employing a vertical alignment (VA) mode may be used.
  • VA vertical alignment
  • the vertical alignment mode There are several examples of the vertical alignment mode. For example, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV mode, and the like can be used.
  • a display device 700 illustrated in FIG. 38 includes a light-emitting element 782.
  • the light-emitting element 782 includes a conductive film 772, an EL layer 786, and a conductive film 788.
  • the display device 700 illustrated in FIG. 38 can display an image when the EL layer 786 included in the light-emitting element 782 emits light.
  • the EL layer 786 includes an organic compound or an inorganic compound such as a quantum dot.
  • Examples of materials that can be used for the organic compound include fluorescent materials and phosphorescent materials.
  • Examples of materials that can be used for the quantum dots include colloidal quantum dot materials, alloy type quantum dot materials, core / shell type quantum dot materials, and core type quantum dot materials.
  • a material including an element group of Group 12 and Group 16, Group 13 and Group 15, or Group 14 and Group 16 may be used.
  • a quantum dot material having an element such as aluminum (Al) may be used.
  • the organic compound and inorganic compound for example, a deposition method (including a vacuum deposition method), a droplet discharge method (also referred to as an inkjet method), a coating method, a gravure printing method, or the like is used. be able to.
  • the EL layer 786 may include a low molecular material, a medium molecular material (including an oligomer and a dendrimer), or a high molecular material.
  • FIGS. FIG. 39A to FIG. 39D are cross-sectional views illustrating a method for manufacturing the EL layer 786.
  • a conductive film 772 is formed over the planarization insulating film 770, and an insulating film 730 is formed so as to cover part of the conductive film 772 (see FIG. 39A).
  • a droplet 784 is discharged from a droplet discharge device 783 to an exposed portion of the conductive film 772 which is an opening of the insulating film 730, so that a layer 785 containing a composition is formed.
  • the droplet 784 is a composition including a solvent and is attached to the conductive film 772 (see FIG. 39B).
  • step of discharging the droplet 784 may be performed under reduced pressure.
  • an EL layer 786 is formed by removing the solvent from the layer 785 containing the composition and solidifying the layer (see FIG. 39C).
  • a conductive film 788 is formed over the EL layer 786, so that the light-emitting element 782 is formed (see FIG. 39D).
  • the composition can be selectively discharged, so that material loss can be reduced.
  • the process can be simplified and cost reduction can be achieved.
  • the droplet discharge method described above is a general term for a device having means for discharging droplets such as a nozzle having a composition discharge port or a head having one or a plurality of nozzles.
  • FIG. 40 is a conceptual diagram for explaining the droplet discharge device 1400.
  • the droplet discharge device 1400 has droplet discharge means 1403.
  • the droplet discharge unit 1403 includes a head 1405 and a head 1412.
  • the head 1405 and the head 1412 are connected to the control means 1407, and can be drawn in a pre-programmed pattern by being controlled by the computer 1410.
  • the drawing timing may be performed with reference to the marker 1411 formed on the substrate 1402, for example.
  • the reference point may be determined based on the outer edge of the substrate 1402.
  • the marker 1411 is detected by the image pickup means 1404, the digital signal converted by the image processing means 1409 is recognized by the computer 1410, a control signal is generated and sent to the control means 1407.
  • an image sensor using a charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS) can be used as the imaging means 1404.
  • Information on the pattern to be formed on the substrate 1402 is stored in the storage medium 1408. Based on this information, a control signal is sent to the control means 1407, and the individual heads 1405 of the droplet discharge means 1403 are sent.
  • the heads 1412 can be individually controlled.
  • the material to be discharged is supplied from the material supply source 1413 and the material supply source 1414 to the head 1405 and the head 1412 through piping.
  • the interior of the head 1405 has a structure having a space filled with a liquid material as indicated by a dotted line 1406 and a nozzle that is a discharge port.
  • the head 1412 has the same internal structure as the head 1405.
  • the nozzles of the head 1405 and the head 1412 are provided in different sizes, different materials can be drawn simultaneously with different widths.
  • a single head can discharge and draw multiple types of light emitting materials, and when drawing over a wide area, the same material can be simultaneously discharged and drawn from multiple nozzles to improve throughput. it can.
  • the head 1405 and the head 1412 can freely scan on the substrate in the directions of arrows X, Y, and Z shown in FIG. Can be drawn on a single substrate.
  • the step of discharging the composition may be performed under reduced pressure.
  • the substrate may be heated at the time of discharge.
  • steps of drying and baking are performed.
  • the drying and firing steps are both heat treatment steps, but their purpose, temperature and time are different.
  • the drying process and the firing process are performed under normal pressure or reduced pressure by laser light irradiation, rapid thermal annealing, a heating furnace, or the like. Note that the timing of performing this heat treatment and the number of heat treatments are not particularly limited. In order to satisfactorily perform the drying and firing steps, the temperature at that time depends on the material of the substrate and the properties of the composition.
  • the EL layer 786 can be manufactured using a droplet discharge device.
  • an insulating film 730 is provided over the planarization insulating film 770 and the conductive film 772.
  • the insulating film 730 covers part of the conductive film 772.
  • the light-emitting element 782 has a top emission structure. Therefore, the conductive film 788 has a light-transmitting property and transmits light emitted from the EL layer 786.
  • the top emission structure is illustrated, but is not limited thereto. For example, a bottom emission structure in which light is emitted to the conductive film 772 side or a dual emission structure in which light is emitted to both the conductive film 772 and the conductive film 788 can be used.
  • a coloring film 736 is provided at a position overlapping with the light emitting element 782, and a light shielding film 738 is provided at a position overlapping with the insulating film 730, the lead wiring portion 711, and the source driver circuit portion 704. Further, the coloring film 736 and the light shielding film 738 are covered with an insulating film 734. A space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. Note that in the display device 700 illustrated in FIG. 38, the structure in which the colored film 736 is provided is illustrated, but the present invention is not limited to this. For example, in the case where the EL layer 786 is formed by separate coating, the coloring film 736 may not be provided.
  • an input / output device may be provided in the display device 700 illustrated in FIGS.
  • Examples of the input / output device include a touch panel.
  • FIG. 37 shows a configuration in which the touch panel 791 is provided in the display device 700 shown in FIG. 37
  • FIG. 42 shows a configuration in which the touch panel 791 is provided in the display device 700 shown in FIG.
  • FIG. 41 is a cross-sectional view of a configuration in which the touch panel 791 is provided on the display device 700 shown in FIG. 37
  • FIG. 42 is a cross-sectional view of a configuration in which the touch panel 791 is provided on the display device 700 shown in FIG.
  • a touch panel 791 shown in FIGS. 41 and 42 is a so-called in-cell type touch panel provided between the substrate 705 and the colored film 736.
  • the touch panel 791 may be formed on the substrate 705 side before the light shielding film 738 and the coloring film 736 are formed.
  • the touch panel 791 includes a light-blocking film 738, an insulating film 792, an electrode 793, an electrode 794, an insulating film 795, an electrode 796, and an insulating film 797.
  • a change in mutual capacitance between the electrode 793 and the electrode 794 can be detected when a detection target such as a finger or a stylus comes close.
  • the intersection of the electrode 793 and the electrode 794 is clearly shown.
  • the electrode 796 is electrically connected to two electrodes 793 sandwiching the electrode 794 through an opening provided in the insulating film 795.
  • 41 and FIG. 42 exemplify the configuration in which the region where the electrode 796 is provided is provided in the pixel portion 702, but the present invention is not limited to this.
  • the region may be formed in the source driver circuit portion 704.
  • the electrode 793 and the electrode 794 are provided in a region overlapping with the light shielding film 738. As shown in FIG. 41, the electrode 793 is preferably provided so as not to overlap with the light-emitting element 782. As shown in FIG. 42, the electrode 793 is preferably provided so as not to overlap with the liquid crystal element 775. In other words, the electrode 793 has an opening in a region overlapping with the light-emitting element 782 and the liquid crystal element 775. That is, the electrode 793 has a mesh shape. With such a structure, the electrode 793 can be configured not to block light emitted from the light-emitting element 782. Alternatively, the electrode 793 can have a structure that does not block light transmitted through the liquid crystal element 775. Therefore, since the reduction in luminance due to the arrangement of the touch panel 791 is extremely small, a display device with high visibility and low power consumption can be realized. Note that the electrode 794 may have a similar structure.
  • a metal material with low visible light transmittance can be used for the electrode 793 and the electrode 794.
  • a metal material with low visible light transmittance can be used for the electrode 793 and the electrode 794.
  • the resistance of the electrode 793 and the electrode 794 can be reduced as compared with an electrode using an oxide material having a high visible light transmittance, and the sensor sensitivity of the touch panel can be improved.
  • conductive nanowires may be used for the electrodes 793, 794, and 796.
  • the nanowire may have an average diameter of 1 nm to 100 nm, preferably 5 nm to 50 nm, more preferably 5 nm to 25 nm.
  • metal nanowires such as Ag nanowire, Cu nanowire, or Al nanowire, or a carbon nanotube etc. may be used.
  • the light transmittance in visible light can be 89% or more
  • the sheet resistance value can be 40 ⁇ / ⁇ or more and 100 ⁇ / ⁇ or less.
  • 41 and 42 illustrate the configuration of the in-cell type touch panel, but the present invention is not limited to this.
  • a so-called on-cell touch panel formed over the display device 700 or a so-called out-cell touch panel used by being attached to the display device 700 may be used.
  • the display device of one embodiment of the present invention can be used in combination with various forms of touch panels.
  • a display device illustrated in FIG. 43A includes a region having a pixel of a display element (hereinafter referred to as a pixel portion 502) and a circuit portion (hereinafter referred to as a pixel portion 502) which is disposed outside the pixel portion 502 and has a circuit for driving the pixel. , A driver circuit portion 504), a circuit having a function of protecting an element (hereinafter referred to as a protection circuit 506), and a terminal portion 507. Note that the protection circuit 506 may be omitted.
  • part or all of the drive circuit portion 504 is formed on the same substrate as the pixel portion 502. Thereby, the number of parts and the number of terminals can be reduced.
  • part or all of the driver circuit portion 504 is formed by COG or TAB (Tape Automated Bonding). Can be implemented.
  • the pixel portion 502 includes a circuit (hereinafter referred to as a pixel circuit 501) for driving a plurality of display elements arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more).
  • the driver circuit portion 504 outputs a signal for selecting a pixel (scanning signal) (hereinafter referred to as a gate driver 504a) and a circuit for supplying a signal (data signal) for driving a display element of the pixel (a data signal).
  • a drive circuit such as a source driver 504b).
  • the gate driver 504a has a shift register and the like.
  • the gate driver 504a receives a signal for driving the shift register via the terminal portion 507, and outputs a signal.
  • the gate driver 504a receives a start pulse signal, a clock signal, and the like and outputs a pulse signal.
  • the gate driver 504a has a function of controlling the potential of a wiring to which a scan signal is supplied (hereinafter referred to as scan lines GL_1 to GL_X).
  • scan lines GL_1 to GL_X a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a.
  • the gate driver 504a has a function of supplying an initialization signal.
  • the present invention is not limited to this, and the gate driver 504a can supply another signal.
  • the source driver 504b has a shift register and the like. In addition to a signal for driving the shift register, the source driver 504b receives a signal (image signal) as a source of a data signal through the terminal portion 507.
  • the source driver 504b has a function of generating a data signal to be written in the pixel circuit 501 based on the image signal.
  • the source driver 504b has a function of controlling output of a data signal in accordance with a pulse signal obtained by inputting a start pulse, a clock signal, or the like.
  • the source driver 504b has a function of controlling the potential of a wiring to which a data signal is supplied (hereinafter referred to as data lines DL_1 to DL_Y).
  • the source driver 504b has a function of supplying an initialization signal.
  • the present invention is not limited to this, and the source driver 504b can supply another signal.
  • the source driver 504b is configured using a plurality of analog switches, for example.
  • the source driver 504b can output a signal obtained by time-dividing the image signal as a data signal by sequentially turning on the plurality of analog switches. Further, the source driver 504b may be configured using a shift register or the like.
  • Each of the plurality of pixel circuits 501 receives a pulse signal through one of the plurality of scanning lines GL to which the scanning signal is applied, and receives the data signal through one of the plurality of data lines DL to which the data signal is applied. Entered.
  • writing and holding of data signals are controlled by the gate driver 504a.
  • the pixel circuit 501 in the m-th row and the n-th column receives a pulse signal from the gate driver 504a through the scanning line GL_m (m is a natural number equal to or less than X), and the data line DL_n (n Is a natural number less than or equal to Y), a data signal is input from the source driver 504b.
  • the protection circuit 43A is connected to, for example, the scanning line GL that is a wiring between the gate driver 504a and the pixel circuit 501.
  • the protection circuit 506 illustrated in FIG. the protection circuit 506 is connected to a data line DL that is a wiring between the source driver 504 b and the pixel circuit 501.
  • the protection circuit 506 can be connected to a wiring between the gate driver 504 a and the terminal portion 507.
  • the protection circuit 506 can be connected to a wiring between the source driver 504 b and the terminal portion 507.
  • the terminal portion 507 is a portion where a terminal for inputting a power supply, a control signal, and an image signal from an external circuit to the display device is provided.
  • the protection circuit 506 is a circuit that brings the wiring and another wiring into a conductive state when a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected.
  • the configuration of the protection circuit 506 is not limited thereto, and for example, a configuration in which the protection circuit 506 is connected to the gate driver 504a or a configuration in which the protection circuit 506 is connected to the source driver 504b may be employed. Alternatively, the protection circuit 506 may be connected to the terminal portion 507.
  • FIG. 43A illustrates an example in which the driver circuit portion 504 is formed using the gate driver 504a and the source driver 504b; however, the present invention is not limited to this structure.
  • the gate driver 504a may be formed, and a substrate on which a separately prepared source driver circuit is formed (for example, a driver circuit substrate formed using a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted.
  • the plurality of pixel circuits 501 illustrated in FIG. 43A can have a structure illustrated in FIG. 43B, for example.
  • 43B includes a liquid crystal element 570, a transistor 550, and a capacitor 560.
  • One potential of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specification of the pixel circuit 501.
  • the alignment state of the liquid crystal element 570 is set by written data. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Further, a different potential may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 in each row.
  • a driving method of a display device including the liquid crystal element 570, a TN mode, an STN mode, a VA mode, an ASM (axially aligned micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, and an FLC (Frequential) mode.
  • AFLC Anti Ferroelectric Liquid Crystal
  • MVA mode MVA mode
  • PVA Powerned Vertical Alignment
  • IPS mode Packed Vertical Alignment
  • FFS mode Transverse Bend Alignment
  • TBA Transverse Bend Alignment
  • ECB Electrode Controlled Birefringence
  • PDLC Polymer Dispersed Liquid Crystal
  • PNLC Polymer Network Liquid mode
  • the present invention is not limited to this, and various liquid crystal elements and driving methods thereof can be used.
  • one of the source electrode and the drain electrode of the transistor 550 is electrically connected to the data line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570.
  • the In addition, the gate electrode of the transistor 550 is electrically connected to the scan line GL_m.
  • the transistor 550 has a function of controlling data writing of the data signal by being turned on or off.
  • One of the pair of electrodes of the capacitor 560 is electrically connected to a wiring to which a potential is supplied (hereinafter, potential supply line VL), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570.
  • potential supply line VL a wiring to which a potential is supplied
  • the capacitor 560 functions as a storage capacitor for storing written data.
  • the pixel circuits 501 in each row are sequentially selected by the gate driver 504a illustrated in FIG. Write data.
  • the pixel circuit 501 in which data is written is in a holding state when the transistor 550 is turned off. By sequentially performing this for each row, an image can be displayed.
  • the plurality of pixel circuits 501 illustrated in FIG. 43A can have a structure illustrated in FIG. 43C, for example.
  • the pixel circuit 501 illustrated in FIG. 43C includes transistors 552 and 554, a capacitor 562, and a light-emitting element 572.
  • the transistor described in any of the above embodiments can be applied to one or both of the transistor 552 and the transistor 554.
  • One of the source electrode and the drain electrode of the transistor 552 is electrically connected to a wiring to which a data signal is supplied (hereinafter referred to as a signal line DL_n). Further, the gate electrode of the transistor 552 is electrically connected to a wiring to which a gate signal is supplied (hereinafter referred to as a scanning line GL_m).
  • the transistor 552 has a function of controlling data writing of the data signal by being turned on or off.
  • One of the pair of electrodes of the capacitor 562 is electrically connected to a wiring to which a potential is applied (hereinafter referred to as a potential supply line VL_a), and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 552. Is done.
  • the capacitor element 562 functions as a storage capacitor for storing written data.
  • One of the source electrode and the drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. Further, the gate electrode of the transistor 554 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.
  • One of an anode and a cathode of the light-emitting element 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554.
  • the light-emitting element 572 for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used.
  • the light-emitting element 572 is not limited thereto, and an inorganic EL element made of an inorganic material may be used.
  • one of the potential supply line VL_a and the potential supply line VL_b is supplied with the high power supply potential VDD, and the other is supplied with the low power supply potential VSS.
  • the pixel circuits 501 in each row are sequentially selected by the gate driver 504a illustrated in FIG. Write.
  • the pixel circuit 501 in which data is written is in a holding state when the transistor 552 is turned off. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled in accordance with the potential of the written data signal, and the light-emitting element 572 emits light with luminance corresponding to the amount of flowing current. By sequentially performing this for each row, an image can be displayed.
  • FIG. 44A is a circuit diagram of an inverter that can be applied to a shift register, a buffer, or the like included in a driver circuit.
  • the inverter 800 outputs a signal obtained by inverting the logic of the signal applied to the input terminal IN to the output terminal OUT.
  • the inverter 800 includes a plurality of OS transistors.
  • the signal SBG is a signal that can switch the electrical characteristics of the OS transistor.
  • FIG. 44B is an example of the inverter 800.
  • the inverter 800 includes an OS transistor 810 and an OS transistor 820. Since the inverter 800 can be manufactured using only an n-channel transistor, it can be manufactured at a lower cost than a case where an inverter (CMOS inverter) is manufactured using a CMOS (Complementary Metal Oxide Semiconductor).
  • CMOS inverter Complementary Metal Oxide Semiconductor
  • the inverter 800 having an OS transistor can also be arranged on a CMOS composed of Si transistors. Since the inverter 800 can be arranged so as to overlap with a CMOS circuit, an increase in circuit area corresponding to the addition of the inverter 800 can be suppressed.
  • the OS transistors 810 and 820 include a first gate that functions as a front gate, a second gate that functions as a back gate, a first terminal that functions as one of a source and a drain, and a second gate that functions as the other of a source and a drain. Terminal.
  • the first gate of the OS transistor 810 is connected to the second terminal.
  • a second gate of the OS transistor 810 is connected to a wiring for supplying the signal SBG .
  • a first terminal of the OS transistor 810 is connected to a wiring that supplies the voltage VDD.
  • the second terminal of the OS transistor 810 is connected to the output terminal OUT.
  • the first gate of the OS transistor 820 is connected to the input terminal IN.
  • a second gate of the OS transistor 820 is connected to the input terminal IN.
  • the first terminal of the OS transistor 820 is connected to the output terminal OUT.
  • a second terminal of the OS transistor 820 is connected to a wiring that supplies the voltage VSS.
  • FIG. 44C is a timing chart for explaining the operation of the inverter 800.
  • the timing chart in FIG. 44C shows changes in the signal waveform of the input terminal IN, the signal waveform of the output terminal OUT, the signal waveform of the signal SBG, and the threshold voltage of the OS transistor 810.
  • the threshold voltage of the OS transistor 810 can be controlled.
  • Signal S BG has a voltage V BG_B for shifted in the positive voltage V BG_A, the threshold voltage for negative shift the threshold voltage.
  • FIG. 45A shows an Id-Vg curve which is one of the electrical characteristics of the transistor.
  • the above-described electrical characteristics of the OS transistor 810 can be shifted to a curve represented by a broken line 840 in FIG. 45A by increasing the voltage of the second gate as the voltage V BG_A .
  • the above-described electrical characteristics of the OS transistor 810 can be shifted to a curve represented by a solid line 841 in FIG. 45A by reducing the voltage of the second gate as the voltage V BG_B .
  • OS transistor 810 by switching the signal S BG and so the voltage V BG_A or voltage V BG_B, can be shifted in the positive or negative shift of the threshold voltage.
  • the OS transistor 810 can be in a state in which current does not easily flow.
  • FIG. 45B visualizes this state.
  • FIG. 45C visualizes this state. As shown in FIG. 45 (C), it can be larger than at least the current I B of the current I A flowing at this time. Therefore, when the signal supplied to the input terminal IN is at a low level and the OS transistor 820 is in an off state (OFF), the voltage of the output terminal OUT can be rapidly increased. As shown in FIG. 45C, since the current flowing through the OS transistor 810 can easily flow, the signal waveform 832 at the output terminal in the timing chart shown in FIG. Can do.
  • the control of the threshold voltage of the OS transistor 810 by the signal S BG previously the state of the OS transistor 820 is switched, i.e. it is preferably performed before a time T1 and T2.
  • the threshold voltage V TH_A is changed from the threshold voltage V TH_A to the threshold voltage V TH_B before the time T1 when the signal applied to the input terminal IN switches to the high level. It is preferable to switch the threshold voltage.
  • the OS transistor 810 is switched from the threshold voltage V TH_B to the threshold voltage V TH_A before the time T2 when the signal applied to the input terminal IN is switched to the low level. It is preferable to switch the threshold voltage.
  • the voltage for controlling the threshold voltage may be held in the second gate of the OS transistor 810 in a floating state.
  • An example of a circuit configuration that can realize this configuration is illustrated in FIG.
  • 46A includes an OS transistor 850 in addition to the circuit configuration illustrated in FIG.
  • the first terminal of the OS transistor 850 is connected to the second gate of the OS transistor 810.
  • the second terminal of the OS transistor 850 is connected to a wiring for applying the voltage V BG_B (or voltage V BG_A ).
  • the first gate of the OS transistor 850 is connected to a wiring for providing signal S F.
  • a second gate of the OS transistor 850 is connected to a wiring that supplies the voltage V BG_B (or the voltage V BG_A ).
  • FIG. 46A The operation in FIG. 46A will be described with reference to the timing chart in FIG.
  • the voltage for controlling the threshold voltage of the OS transistor 810 is applied to the second gate of the OS transistor 810 before the time T3 when the signal applied to the input terminal IN switches to the high level.
  • the OS transistor 850 is turned on the signal S F to the high level, providing a voltage V BG_B for controlling a threshold voltage in the node N BG.
  • FIGS. 44B and 46A a configuration in which the voltage applied to the second gate of the OS transistor 810 is given by external control is shown, but another configuration may be used.
  • a voltage for controlling the threshold voltage may be generated based on a signal supplied to the input terminal IN and supplied to the second gate of the OS transistor 810.
  • FIG. 47A illustrates an example of a circuit configuration that can realize this configuration.
  • a CMOS inverter 860 is provided between the input terminal IN and the second gate of the OS transistor 810.
  • the input terminal of the CMOS inverter 860 is connected to the input terminal IN.
  • the output terminal of the CMOS inverter 860 is connected to the second gate of the OS transistor 810.
  • FIG. 47A The operation in FIG. 47A will be described with reference to the timing chart in FIG.
  • the timing chart in FIG. 47B shows changes in the signal waveform of the input terminal IN, the signal waveform of the output terminal OUT, the output waveform IN_B of the CMOS inverter 860, and the threshold voltage of the OS transistor 810.
  • the output waveform IN_B which is a signal obtained by inverting the logic of the signal applied to the input terminal IN, can be a signal for controlling the threshold voltage of the OS transistor 810. Therefore, as described with reference to FIGS. 45A to 45C, the threshold voltage of the OS transistor 810 can be controlled. For example, at time T4 in FIG. 47B, the signal applied to the input terminal IN is at a high level and the OS transistor 820 is turned on. At this time, the output waveform IN_B is at a low level. Therefore, the OS transistor 810 can be set in a state in which current does not easily flow, and the voltage increase at the output terminal OUT can be sharply decreased.
  • the signal applied to the input terminal IN is at a low level, so that the OS transistor 820 is turned off.
  • the output waveform IN_B is at a high level. Therefore, the OS transistor 810 can be in a state in which current easily flows, and the voltage of the output terminal OUT can be rapidly increased.
  • the voltage of the back gate in the inverter having the OS transistor is switched in accordance with the signal logic of the input terminal IN.
  • the threshold voltage of the OS transistor can be controlled.
  • the voltage of the output terminal OUT can be changed abruptly.
  • the through current between the wirings supplying the power supply voltage can be reduced. Therefore, low power consumption can be achieved.
  • FIG. 48A is a block diagram of the semiconductor device 900.
  • the semiconductor device 900 includes a power supply circuit 901, a circuit 902, a voltage generation circuit 903, a circuit 904, a voltage generation circuit 905, and a circuit 906.
  • the power supply circuit 901 is a circuit that generates a reference voltage V ORG .
  • the voltage V ORG may be a plurality of voltages instead of a single voltage.
  • the voltage V ORG can be generated based on the voltage V 0 given from the outside of the semiconductor device 900.
  • the semiconductor device 900 can generate the voltage V ORG based on a single power supply voltage given from the outside. Therefore, the semiconductor device 900 can operate without applying a plurality of power supply voltages from the outside.
  • the circuits 902, 904, and 906 are circuits that operate with different power supply voltages.
  • the power supply voltage of the circuit 902 is a voltage applied based on the voltage V ORG and the voltage V SS (V ORG > V SS ).
  • the power supply voltage of the circuit 904 is a voltage applied based on the voltage V POG and the voltage V SS (V POG > V ORG ).
  • the power supply voltage of the circuit 906 is a voltage applied based on the voltage V ORG , the voltage V SS, and the voltage V NEG (V ORG > V SS > V NEG ). Note that if the voltage VSS is equal to the ground potential (GND), the types of voltages generated by the power supply circuit 901 can be reduced.
  • GND ground potential
  • the voltage generation circuit 903 is a circuit that generates the voltage V POG .
  • the voltage generation circuit 903 can generate the voltage V POG based on the voltage V ORG supplied from the power supply circuit 901. Therefore, the semiconductor device 900 including the circuit 904 can operate based on a single power supply voltage supplied from the outside.
  • the voltage generation circuit 905 is a circuit that generates a voltage V NEG .
  • the voltage generation circuit 905 can generate the voltage V NEG based on the voltage V ORG supplied from the power supply circuit 901. Therefore, the semiconductor device 900 including the circuit 906 can operate based on a single power supply voltage given from the outside.
  • FIG. 48B illustrates an example of a circuit 904 that operates at the voltage V POG
  • FIG. 48C illustrates an example of a waveform of a signal for operating the circuit 904.
  • the transistor 911 is illustrated.
  • Signal applied to the gate of the transistor 911 is generated, for example, based on the voltage V POG and voltage V SS.
  • the signal is a voltage V SS during operation of the conductive state of transistor 911 voltage V POG, during operation of the non-conductive state.
  • the voltage V POG is larger than the voltage V ORG as illustrated in FIG. Therefore, the transistor 911 can be more reliably connected between the source (S) and the drain (D).
  • the circuit 904 can be a circuit in which malfunctions are reduced.
  • FIG. 48D illustrates an example of a circuit 906 that operates at the voltage V NEG
  • FIG. 48E illustrates an example of a waveform of a signal for operating the circuit 906.
  • FIG. 48D illustrates a transistor 912 having a back gate.
  • Signal applied to the gate of the transistor 912 for example, generated based on the voltage V ORG and the voltage V SS.
  • the signal voltage V ORG during operation of the conductive state of transistor 912 is generated based on the voltage V SS during operation of a non-conductive state.
  • a signal given to the back gate of the transistor 912 is generated based on the voltage V NEG .
  • the voltage V NEG is smaller than the voltage V SS (GND) as illustrated in FIG. Therefore, the threshold voltage of the transistor 912 can be controlled to shift positively. Therefore, the transistor 912 can be more reliably turned off, and the current flowing between the source (S) and the drain (D) can be reduced.
  • the circuit 906 can be a circuit in which malfunctions are reduced and power consumption is reduced.
  • the voltage V NEG may be directly applied to the back gate of the transistor 912.
  • a signal to be supplied to the gate of the transistor 912 may be generated based on the voltage V ORG and the voltage V NEG and the signal may be supplied to the back gate of the transistor 912.
  • 49 (A) and 49 (B) show modified examples of FIGS. 48 (D) and 48 (E).
  • a transistor 922 whose conduction state can be controlled by the control circuit 921 is illustrated between the voltage generation circuit 905 and the circuit 906.
  • the transistor 922 is an n-channel OS transistor.
  • Control signal S BG control circuit 921 is output a signal for controlling the conduction state of the transistor 922.
  • transistors 912A and 912B included in the circuit 906 are OS transistors which are the same as the transistor 922.
  • control signal S BG is transistor 922 in a conducting state at the high level, the node N BG becomes voltage V NEG. Thereafter, when the control signal SBG is at a low level, the node NBG becomes electrically floating. Since the transistor 922 is an OS transistor, the off-state current is small. Therefore, even if the node NBG is electrically floating, the voltage V NEG once applied can be held.
  • FIG. 50A illustrates an example of a circuit configuration which can be applied to the voltage generation circuit 903 described above.
  • a voltage generation circuit 903 illustrated in FIG. 50A is a five-stage charge pump including diodes D1 to D5, capacitors C1 to C5, and an inverter INV.
  • the clock signal CLK is supplied to the capacitors C1 to C5 directly or via the inverter INV.
  • the power supply voltage of the inverter INV is a voltage applied based on the voltage V ORG and the voltage V SS
  • the voltage V POG boosted to a positive voltage five times the voltage V ORG is given by applying the clock signal CLK.
  • the forward voltage of the diodes D1 to D5 is 0V. Further, by changing the number of stages of the charge pump, it is possible to obtain a desired voltage V POG.
  • FIG. 50B illustrates an example of a circuit configuration which can be applied to the voltage generation circuit 905 described above.
  • a voltage generation circuit 905 illustrated in FIG. 50B is a four-stage charge pump including diodes D1 to D5, capacitors C1 to C5, and an inverter INV.
  • the clock signal CLK is supplied to the capacitors C1 to C5 directly or via the inverter INV.
  • the power supply voltage of the inverter INV is a voltage applied based on the voltage V ORG and the voltage V SS , by supplying the clock signal CLK, the ground, that is, the negative voltage that is four times the voltage V ORG from the voltage V SS is obtained.
  • the stepped down voltage V NEG can be obtained.
  • the forward voltage of the diodes D1 to D5 is 0V. Further, the desired voltage V NEG can be obtained by changing the number of stages of the charge pump.
  • circuit configuration of the voltage generation circuit 903 described above is not limited to the configuration of the circuit diagram illustrated in FIG.
  • modification examples of the voltage generation circuit 903 are illustrated in FIGS.
  • a modification example of the voltage generation circuit 903 includes changing the voltage applied to each wiring or changing the arrangement of elements in the voltage generation circuits 903A to 903C illustrated in FIGS. It is feasible.
  • a voltage generation circuit 903A illustrated in FIG. 51A includes transistors M1 to M10, capacitors C11 to C14, and an inverter INV1.
  • the clock signal CLK is supplied directly to the gates of the transistors M1 to M10 or via the inverter INV1.
  • By providing the clock signal CLK it is possible to obtain a voltage V POG that is boosted to a positive voltage that is four times the voltage V ORG .
  • a desired voltage V POG can be obtained by changing the number of stages.
  • the voltage generation circuit 903A illustrated in FIG. 51A can reduce off-state current by using the transistors M1 to M10 as OS transistors, and can suppress leakage of charges held in the capacitors C11 to C14. Therefore, the voltage V ORG can be efficiently boosted from the voltage V POG .
  • a voltage generation circuit 903B illustrated in FIG. 51B includes transistors M11 to M14, capacitors C15 and C16, and an inverter INV2.
  • the clock signal CLK is supplied directly to the gates of the transistors M11 to M14 or via the inverter INV2. By providing the clock signal CLK, it is possible to obtain a voltage V POG that is boosted to a positive voltage that is twice the voltage V ORG .
  • the voltage generation circuit 903B illustrated in FIG. 51B can reduce off-state current by using the transistors M11 to M14 as OS transistors, and can suppress leakage of charges held in the capacitors C15 and C16. Therefore, the voltage V ORG can be efficiently boosted from the voltage V POG .
  • a voltage generation circuit 903C illustrated in FIG. 51C includes an inductor Ind1, a transistor M15, a diode D6, and a capacitor C17.
  • the conduction state of the transistor M15 is controlled by the control signal EN.
  • a voltage V POG obtained by boosting the voltage V ORG can be obtained by the control signal EN. Since the voltage generation circuit 903C illustrated in FIG. 51C uses the inductor Ind1 to increase the voltage, the voltage generation circuit 903C can increase the voltage with high conversion efficiency.
  • a voltage necessary for a circuit included in the semiconductor device can be generated internally. Therefore, the semiconductor device can reduce the number of power supply voltages given from the outside.
  • a display module 7000 shown in FIG. 52 includes a touch panel 7004 connected to the FPC 7003, a display panel 7006 connected to the FPC 7005, a backlight 7007, a frame 7009, a printed circuit board 7010, a battery, between an upper cover 7001 and a lower cover 7002. 7011.
  • the semiconductor device of one embodiment of the present invention can be used for the display panel 7006, for example.
  • the shape and dimensions of the upper cover 7001 and the lower cover 7002 can be changed as appropriate in accordance with the sizes of the touch panel 7004 and the display panel 7006.
  • a resistive film type or capacitive type touch panel can be used by being superimposed on the display panel 7006.
  • the counter substrate (sealing substrate) of the display panel 7006 can have a touch panel function.
  • an optical sensor can be provided in each pixel of the display panel 7006 to form an optical touch panel.
  • the backlight 7007 has a light source 7008.
  • FIG. 52 illustrates the configuration in which the light source 7008 is provided over the backlight 7007, the present invention is not limited to this.
  • the light source 7008 may be disposed at the end of the backlight 7007 and a light diffusing plate may be used.
  • the backlight 7007 may not be provided.
  • the frame 7009 has a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed circuit board 7010 in addition to the protective function of the display panel 7006.
  • the frame 7009 may have a function as a heat sink.
  • the printed circuit board 7010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal.
  • the power source for supplying power to the power supply circuit may be an external commercial power source or a power source using a battery 7011 provided separately.
  • the battery 7011 can be omitted when a commercial power source is used.
  • the display module 7000 may be additionally provided with a member such as a polarizing plate, a phase difference plate, and a prism sheet.
  • FIGS. 53A to 53E illustrate examples of electronic devices.
  • FIG. 53 (A) is a diagram showing the appearance of the camera 8000 with the viewfinder 8100 attached.
  • the camera 8000 includes a housing 8001, a display portion 8002, operation buttons 8003, a shutter button 8004, and the like.
  • the camera 8000 is attached with a detachable lens 8006.
  • the camera 8000 is configured such that the lens 8006 can be removed from the housing 8001 and replaced, but the lens 8006 and the housing may be integrated.
  • the camera 8000 can take an image by pressing a shutter button 8004.
  • the display portion 8002 has a function as a touch panel and can capture an image by touching the display portion 8002.
  • the housing 8001 of the camera 8000 has a mount having electrodes, and can be connected to a stroboscope or the like in addition to the finder 8100.
  • the finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.
  • the housing 8101 has a mount that engages with the mount of the camera 8000, and the finder 8100 can be attached to the camera 8000.
  • the mount includes an electrode, and an image received from the camera 8000 via the electrode can be displayed on the display portion 8102.
  • the button 8103 has a function as a power button.
  • a button 8103 can be used to switch display on the display portion 8102 on and off.
  • the display device of one embodiment of the present invention can be applied to the display portion 8002 of the camera 8000 and the display portion 8102 of the finder 8100.
  • the camera 8000 and the viewfinder 8100 are separate electronic devices and can be attached to and detached from each other.
  • a finder including a display device is incorporated in the housing 8001 of the camera 8000. Also good.
  • FIG. 53 (B) is a diagram showing the appearance of the head mounted display 8200.
  • the head mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, a cable 8205, and the like.
  • a battery 8206 is built in the mounting portion 8201.
  • the cable 8205 supplies power from the battery 8206 to the main body 8203.
  • the main body 8203 includes a wireless receiver and the like, and can display video information such as received image data on the display portion 8204.
  • the mounting portion 8201 may be provided with a plurality of electrodes at positions where the user touches the mounting portion 8201.
  • the main body 8203 may have a function of recognizing the user's viewpoint by detecting a current flowing through the electrode in accordance with the movement of the user's eyeball. Moreover, you may have a function which monitors a user's pulse by detecting the electric current which flows into the said electrode.
  • the mounting portion 8201 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display portion 8204. Further, the movement of the user's head or the like may be detected, and the video displayed on the display unit 8204 may be changed in accordance with the movement.
  • the display device of one embodiment of the present invention can be applied to the display portion 8204.
  • FIG. 53C, 53D, and 53E are views showing the appearance of the head mounted display 8300.
  • FIG. The head mounted display 8300 includes a housing 8301, a display portion 8302, a band-shaped fixture 8304, and a pair of lenses 8305.
  • the user can visually recognize the display on the display portion 8302 through the lens 8305.
  • the display portion 8302 is preferably arranged curved. By arranging the display portion 8302 to be curved, the user can feel a high sense of realism.
  • a structure in which one display portion 8302 is provided is described in this embodiment mode, the present invention is not limited thereto, and for example, a structure in which two display portions 8302 are provided may be employed. In this case, if one display unit is arranged in one eye of the user, three-dimensional display using parallax or the like can be performed.
  • the display device of one embodiment of the present invention can be applied to the display portion 8302. Since the display device including the semiconductor device of one embodiment of the present invention has extremely high definition, the pixel is not visually recognized by the user even when the display device is enlarged using the lens 8305 as illustrated in FIG. More realistic video can be displayed.
  • FIGS. 54A to 54G examples of electronic devices that are different from the electronic devices illustrated in FIGS. 53A to 53E are illustrated in FIGS. 54A to 54G.
  • 54A to 54G includes a housing 9000, a display portion 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (force , Displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration , Including a function of measuring odor or infrared light), a microphone 9008, and the like.
  • the electronic devices illustrated in FIGS. 54A to 54G have various functions. For example, a function for displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function for displaying a calendar, date or time, a function for controlling processing by various software (programs), Wireless communication function, function for connecting to various computer networks using the wireless communication function, function for transmitting or receiving various data using the wireless communication function, and reading and displaying the program or data recorded on the recording medium It can have a function of displaying on the section. Note that the functions of the electronic devices illustrated in FIGS. 54A to 54G are not limited to these, and can have various functions. Although not illustrated in FIGS.
  • the electronic device may have a plurality of display portions.
  • the electronic device is equipped with a camera, etc., to capture still images, to capture moving images, to store captured images on a recording medium (externally or built into the camera), and to display captured images on the display unit And the like.
  • FIGS. 54A to 54G Details of the electronic devices shown in FIGS. 54A to 54G will be described below.
  • FIG. 54A is a perspective view showing the television device 9100.
  • the television device 9100 can incorporate the display portion 9001 with a large screen, for example, a display portion 9001 with a size of 50 inches or more, or 100 inches or more.
  • FIG. 54B is a perspective view showing the portable information terminal 9101.
  • the portable information terminal 9101 has one or a plurality of functions selected from, for example, a telephone, a notebook, an information browsing device, or the like. Specifically, it can be used as a smartphone.
  • the portable information terminal 9101 may include a speaker 9003, a connection terminal 9006, a sensor 9007, and the like.
  • the portable information terminal 9101 can display characters and image information on the plurality of surfaces.
  • three operation buttons 9050 also referred to as operation icons or simply icons
  • information 9051 indicated by a broken-line rectangle can be displayed on another surface of the display portion 9001.
  • a display that notifies an incoming call such as an e-mail, SNS (social networking service) or a telephone, a title such as an e-mail or SNS, a sender name such as an e-mail or SNS, a date, a time , Battery level, antenna reception strength and so on.
  • an operation button 9050 or the like may be displayed instead of the information 9051 at a position where the information 9051 is displayed.
  • FIG. 54C is a perspective view showing the portable information terminal 9102.
  • the portable information terminal 9102 has a function of displaying information on three or more surfaces of the display portion 9001.
  • information 9052, information 9053, and information 9054 are displayed on different planes.
  • the user of the portable information terminal 9102 can check the display (information 9053 here) in a state where the portable information terminal 9102 is stored in the chest pocket of clothes. Specifically, the telephone number or name of the caller of the incoming call is displayed at a position where it can be observed from above portable information terminal 9102. The user can check the display and determine whether to receive a call without taking out the portable information terminal 9102 from the pocket.
  • FIG. 54D is a perspective view showing a wristwatch-type portable information terminal 9200.
  • the portable information terminal 9200 can execute various applications such as a mobile phone, electronic mail, text browsing and creation, music playback, Internet communication, and computer games.
  • the display portion 9001 is provided with a curved display surface, and can perform display along the curved display surface.
  • the portable information terminal 9200 can execute short-range wireless communication with a communication standard. For example, it is possible to talk hands-free by communicating with a headset capable of wireless communication.
  • the portable information terminal 9200 includes a connection terminal 9006 and can directly exchange data with other information terminals via a connector. Charging can also be performed through the connection terminal 9006. Note that the charging operation may be performed by wireless power feeding without using the connection terminal 9006.
  • FIG. 54E, 54F, and 54G are perspective views showing a foldable portable information terminal 9201.
  • FIG. FIG. 54E is a perspective view of a state in which the portable information terminal 9201 is expanded
  • FIG. 54F is a state in the middle of changing from one of the expanded state or the folded state of the portable information terminal 9201 to the other.
  • FIG. 54G is a perspective view of the portable information terminal 9201 folded.
  • the portable information terminal 9201 is excellent in portability in the folded state, and in the expanded state, the portable information terminal 9201 is excellent in display listability due to a seamless wide display area.
  • a display portion 9001 included in the portable information terminal 9201 is supported by three housings 9000 connected by a hinge 9055.
  • the portable information terminal 9201 By bending between the two housings 9000 via the hinge 9055, the portable information terminal 9201 can be reversibly deformed from the expanded state to the folded state.
  • the portable information terminal 9201 can be bent with a curvature radius of 1 mm to 150 mm.
  • FIGS. 53A to 53E and the electronic device different from the electronic devices illustrated in FIGS. 54A to 54G are illustrated in FIGS.
  • Shown in 55A and 55B are perspective views of a display device having a plurality of display panels.
  • FIG. 55A is a perspective view of a form in which a plurality of display panels are wound
  • FIG. 55B is a perspective view of a state in which the plurality of display panels are developed.
  • 55A and 55B includes a plurality of display panels 9501, a shaft portion 9511, and a bearing portion 9512.
  • the plurality of display panels 9501 each include a display region 9502 and a region 9503 having a light-transmitting property.
  • the plurality of display panels 9501 have flexibility. Further, two adjacent display panels 9501 are provided so that a part of them overlap each other. For example, a light-transmitting region 9503 of two adjacent display panels 9501 can be overlapped. By using a plurality of display panels 9501, a large-screen display device can be obtained. In addition, since the display panel 9501 can be taken up depending on the use state, a display device with excellent versatility can be obtained.
  • FIGS. 55A and 55B illustrate a state in which the display area 9502 is separated by the adjacent display panel 9501, but is not limited to this.
  • the display area 9502 of the adjacent display panel 9501 is displayed.
  • the display area 9502 may be a continuous display area by overlapping them with no gap.
  • the electronic device described in this embodiment has a display portion for displaying some information. Note that the semiconductor device of one embodiment of the present invention can also be applied to an electronic device that does not include a display portion.

Abstract

L'invention concerne un film d'oxyde métallique comprenant une partie cristalline, un film d'oxyde métallique présentant une grande stabilité de propriétés, un film d'oxyde métallique possédant des caractéristiques électriques améliorées, un film d'oxyde métallique permettant d'améliorer la mobilité d'effet de champ, et un dispositif à semi-conducteurs hautement fiable sur lequel le film d'oxyde métallique est appliqué. Dans une analyse de diffraction des rayons X d'un film d'oxyde métallique de la présente invention, ladite diffraction des rayons X étant dans la direction perpendiculaire à une surface du film, on observe un pic d'intensité de diffraction dû à une structure cristalline, et dans une analyse de diffraction d'un faisceau d'électrons avec un diamètre de sonde supérieur ou égal à 50 nm, on observe une figure de diffraction de forme annulaire et deux premières taches à des positions chevauchant la figure de diffraction de forme annulaire, et dans une analyse de diffraction d'un faisceau d'électrons avec un diamètre de sonde de 0,3 à 5 nm, on observe une première tache et une pluralité de secondes taches réparties dans la direction circonférentielle.
PCT/IB2016/057594 2015-12-24 2016-12-14 Film d'oxyde métallique et dispositif à semi-conducteurs WO2017109642A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014143404A (ja) * 2012-12-25 2014-08-07 Semiconductor Energy Lab Co Ltd 抵抗素子、表示装置、及び電子機器
JP2015046594A (ja) * 2013-08-02 2015-03-12 株式会社半導体エネルギー研究所 酸化物半導体膜および半導体装置
JP2015109427A (ja) * 2013-10-22 2015-06-11 株式会社半導体エネルギー研究所 酸化物半導体膜の作製方法
JP2015128163A (ja) * 2012-12-28 2015-07-09 株式会社半導体エネルギー研究所 半導体装置
US20150310906A1 (en) * 2014-04-25 2015-10-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, electronic component, and electronic device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014143404A (ja) * 2012-12-25 2014-08-07 Semiconductor Energy Lab Co Ltd 抵抗素子、表示装置、及び電子機器
JP2015128163A (ja) * 2012-12-28 2015-07-09 株式会社半導体エネルギー研究所 半導体装置
JP2015046594A (ja) * 2013-08-02 2015-03-12 株式会社半導体エネルギー研究所 酸化物半導体膜および半導体装置
JP2015109427A (ja) * 2013-10-22 2015-06-11 株式会社半導体エネルギー研究所 酸化物半導体膜の作製方法
US20150310906A1 (en) * 2014-04-25 2015-10-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, electronic component, and electronic device

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