WO2017109642A1 - Metal oxide film and semiconductor device - Google Patents

Metal oxide film and semiconductor device Download PDF

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Publication number
WO2017109642A1
WO2017109642A1 PCT/IB2016/057594 IB2016057594W WO2017109642A1 WO 2017109642 A1 WO2017109642 A1 WO 2017109642A1 IB 2016057594 W IB2016057594 W IB 2016057594W WO 2017109642 A1 WO2017109642 A1 WO 2017109642A1
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Prior art keywords
film
transistor
oxide semiconductor
insulating film
metal oxide
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PCT/IB2016/057594
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French (fr)
Japanese (ja)
Inventor
太田将志
津吹将志
野中裕介
石原典隆
山内諒
肥塚純一
島行徳
生内俊光
保坂泰靖
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株式会社半導体エネルギー研究所
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Publication of WO2017109642A1 publication Critical patent/WO2017109642A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02554—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • One embodiment of the present invention relates to a metal oxide film and a manufacturing method thereof.
  • One embodiment of the present invention relates to a semiconductor device including a metal oxide film.
  • a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics
  • a transistor, a semiconductor circuit, and the like are one embodiment of a semiconductor device.
  • An arithmetic device, a storage device, an imaging device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, and the like) and an electronic device may include a semiconductor device.
  • Oxide semiconductors are attracting attention as semiconductor materials applicable to transistors.
  • a plurality of oxide semiconductor layers are stacked, and among the plurality of oxide semiconductor layers, the composition of the oxide semiconductor layer serving as a channel includes indium and gallium, and the composition of indium is gallium.
  • a semiconductor device is disclosed in which the field effect mobility (which may be simply referred to as mobility or ⁇ FE) is increased by making the composition larger than the above composition.
  • Non-Patent Document 1 an oxide semiconductor including indium, gallium, and zinc is In 1-x Ga 1 + x O 3 (ZnO) m (x is a number satisfying ⁇ 1 ⁇ x ⁇ 1, m is It is disclosed to have a homologous phase represented by a natural number).
  • An object of one embodiment of the present invention is to provide a metal oxide film including a crystal part. Another object is to provide a metal oxide film with high stability in physical properties. Another object is to provide a metal oxide film with improved electrical characteristics. Another object is to provide a metal oxide film that can increase field-effect mobility. Another object is to provide a highly reliable semiconductor device to which a metal oxide film is applied.
  • Another object of one embodiment of the present invention is to provide a metal oxide film that can be formed at a low temperature and has high physical stability. Another object is to provide a highly reliable semiconductor device that can be formed at low temperature.
  • Another object of one embodiment of the present invention is to provide a flexible device to which a metal oxide film is applied.
  • One embodiment of the present invention is a metal oxide film containing indium, M (M is Al, Ga, Y, or Sn), and zinc. Further, in X-ray diffraction in a direction perpendicular to the film surface, there is a region where a peak of diffraction intensity due to the crystal structure is observed. Further, in the electron beam diffraction in the direction perpendicular to the cross section where the thickness was reduced to 10 nm or more and 50 nm or less and the probe diameter was 50 nm or more, two ring-shaped diffraction patterns and two positions overlapping with the ring-shaped diffraction pattern were obtained.
  • the two first spots are observed symmetrically with respect to the center, and the points of the highest brightness of the first spot, the first straight line passing through the center, and the normal direction of the film surface It is preferable to have a region where the angle between them is 0 degree or more and 10 degrees or less.
  • the luminance of the ring-shaped diffraction pattern at the intersection of the second straight line orthogonal to the first straight line and the ring-shaped diffraction pattern is greater than the luminance of the first spot. It is preferable to have a small region.
  • the first spot has a region in which the luminance of the first spot is greater than 1 and less than 10 times the luminance of the ring-shaped diffraction pattern at the intersection of the second straight line and the ring-shaped diffraction pattern. It is preferable.
  • the area ratio of the portion excluding the portion where the crystal portion where the angle between the c-axis direction and the film surface direction is 10 degrees or less exists is 25% or more and 100 It is preferred to have a region that is less than.
  • the first image obtained by fast Fourier transform of the cross-sectional TEM image was subjected to mask processing that leaves a range showing periodicity, and the second image obtained by inverse Fourier transform remained from the original image. It is preferable to have a region where the ratio of the area after subtracting the image is 25% or more and less than 100.
  • the first spot has a shape spreading in the circumferential direction, and includes two straight lines passing through each of the two ends in the circumferential direction of the first spot and the center of the electron diffraction pattern.
  • the angle is preferably within 45 degrees.
  • Another embodiment of the present invention is a semiconductor device including a semiconductor layer, a gate insulating layer, and a gate, and the semiconductor layer includes the metal oxide film.
  • a metal oxide film including a crystal part can be provided.
  • a metal oxide film with high physical properties can be provided.
  • a highly reliable semiconductor device to which a metal oxide film is applied can be provided.
  • a metal oxide film that can be formed at a low temperature and has high physical stability can be provided.
  • a highly reliable semiconductor device that can be formed at low temperature can be provided.
  • a metal oxide film is applied to provide a flexible device.
  • the XRD measurement result of a metal oxide The XRD measurement result of a metal oxide.
  • Cross-sectional observation image of metal oxide Electron diffraction pattern of metal oxide. Electron diffraction pattern of metal oxide. Electron diffraction pattern of metal oxide. Electron diffraction pattern of metal oxide. Electron diffraction pattern of metal oxide and luminance profile. Relative luminance estimated from electron diffraction pattern of metal oxide. Electron diffraction pattern of metal oxide.
  • Cross-sectional observation image of metal oxide and cross-sectional observation image after image analysis. Transistor electrical characteristics. 6A and 6B illustrate a range of the atomic ratio of an oxide semiconductor film.
  • FIG. 6 illustrates a crystal of InMZnO 4 .
  • FIG. 6A and 6B illustrate energy bands in a transistor in which an oxide semiconductor film is used for a channel region.
  • 8A and 8B are a top view and cross-sectional views illustrating a semiconductor device.
  • 8A and 8B are a top view and cross-sectional views illustrating a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device.
  • 8A and 8B are a top view and cross-sectional views illustrating a semiconductor device.
  • 8A and 8B are a top view and cross-sectional views illustrating a semiconductor device.
  • 8A and 8B are a top view and cross-sectional views illustrating a semiconductor device.
  • 8A and 8B are a top view and cross-sectional views illustrating a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device.
  • FIG. 10 is a cross-sectional view illustrating a semiconductor device.
  • FIG. 8A and 8B are a top view and cross-sectional views illustrating a semiconductor device.
  • FIG. 14 is a top view illustrating one embodiment of a display device.
  • FIG. 14 is a cross-sectional view illustrating one embodiment of a display device.
  • FIG. 14 is a cross-sectional view illustrating one embodiment of a display device.
  • FIG. 14 is a cross-sectional view illustrating one embodiment of a display device.
  • FIG. 14 is a cross-sectional view illustrating one embodiment of a display device.
  • 10A and 10B are a block diagram and a circuit diagram illustrating a display device.
  • 6A and 6B are a circuit diagram and a timing chart for illustrating one embodiment of the present invention.
  • 5A and 5B are a graph and a circuit diagram for illustrating one embodiment of the present invention.
  • 6A and 6B are a circuit diagram and a timing chart for illustrating one embodiment of the present invention.
  • 6A and 6B are a circuit diagram and a timing chart for illustrating one embodiment of the present invention.
  • 4A and 4B are a block diagram, a circuit diagram, and a waveform diagram for illustrating one embodiment of the present invention.
  • 6A and 6B are a circuit diagram and a timing chart for illustrating one embodiment of the present invention.
  • FIG. 10 is a circuit diagram illustrating one embodiment of the present invention.
  • FIG. 10 is a circuit diagram illustrating one embodiment of the present invention.
  • the figure explaining a display module. 10A and 10B each illustrate an electronic device.
  • 10A and 10B each illustrate an electronic device.
  • FIG. 14 is a perspective view illustrating a display device
  • a transistor is a kind of semiconductor element, and can realize amplification of current and voltage, switching operation for controlling conduction or non-conduction, and the like.
  • the transistors in this specification include an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT: Thin Film Transistor).
  • source and drain may be interchanged when transistors having different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.
  • One embodiment of the present invention is a metal oxide film including two kinds of crystal parts.
  • One of the crystal parts (also referred to as a first crystal part) is a crystal part having orientation in a film thickness direction (also referred to as a film surface direction, a film formation surface, or a direction perpendicular to the film surface). is there.
  • Another of the crystal parts (also referred to as a second crystal part) is a crystal part that is oriented in various directions without having a specific orientation.
  • the metal oxide film of one embodiment of the present invention includes such a mixture of two kinds of crystal parts.
  • the metal oxide film of one embodiment of the present invention can be expressed without distinction. That is, the metal oxide film of one embodiment of the present invention includes a plurality of crystal parts, and of these, a crystal part having orientation in a direction perpendicular to the surface of the film is more than a crystal part oriented in another direction. It can be paraphrased as a film that exists in large numbers.
  • a specific crystal plane has orientation with respect to the thickness direction of the film. Therefore, when X-ray diffraction (XRD) measurement in a direction substantially perpendicular to the top surface of the metal oxide film including the first crystal part is performed, a predetermined diffraction angle (2 ⁇ ) A diffraction peak derived from the first crystal part is confirmed. Note that the height (intensity) of the diffraction peak increases as the proportion of the first crystal portion included in the film increases, and can be an index for estimating the crystallinity of the film.
  • XRD X-ray diffraction
  • the metal oxide film of one embodiment of the present invention is subjected to electron beam diffraction measurement in a direction perpendicular to the cross section of the film, an electron beam diffraction pattern caused by the first crystal part and a second crystal part are formed. A diffraction pattern in which the resulting electron beam diffraction pattern is mixed is obtained.
  • a clear spot derived from crystallinity is confirmed.
  • the spot has orientation with respect to the thickness direction of the film.
  • the second crystal part is a crystal part existing in the film so as to be randomly oriented in all directions. Therefore, different images are confirmed as follows depending on the diameter of the electron beam (probe diameter) used for electron beam diffraction, that is, the area of the region to be observed.
  • the limited-field electron beam diffraction is one of electron beam diffractions, in which an irradiation region is narrowed and a parallel region is irradiated with a parallel electron beam.
  • Nanobeam electron diffraction also called Nano Beam Electron Diffraction
  • the electron beam diameter probe diameter
  • the ⁇ direction A plurality of spots distributed in the circumferential direction (also referred to as the ⁇ direction) are confirmed at the position of the ring-shaped pattern seen in the limited-field electron diffraction pattern. That is, it can be confirmed that the ring-shaped pattern seen in the limited-field electron diffraction pattern is formed by the aggregate of the spots.
  • Nanobeam electron diffraction is one type of convergent electron beam diffraction among electron beam diffractions, and converges an electron beam and irradiates a sample.
  • the first spot derived from the first crystal portion and the ring-shaped pattern derived from the second crystal portion are mixed in the limited-field electron diffraction pattern of the cross section. Confirmed diffraction pattern. Further, the metal oxide film has a plurality of second spots that are derived from the first spot derived from the first crystal part and the second crystal part and scattered along the circumferential direction in the nanobeam electron diffraction pattern of the cross section. A diffraction pattern with mixed spots is confirmed.
  • the first spot and the ring are positioned so as to overlap in the radial direction.
  • the first spot and the second spot are positioned so as to overlap in the radial direction.
  • the first spot derived from the first crystal part is a diffraction spot derived from a crystal plane perpendicular to the c-axis of the crystal.
  • the crystal structure has two-fold symmetry in the direction perpendicular to the c-axis, two first spots are observed symmetrically with respect to the center of the electron beam diffraction pattern.
  • other spots derived from the crystal plane perpendicular to the c-axis and diffraction spots derived from crystal planes other than the crystal plane perpendicular to the c-axis are observed. Sometimes it is done.
  • the plurality of second spots constituting the ring are diffracted from crystal planes perpendicular to the c-axis of crystal parts oriented in different directions. Can be understood as a spot.
  • the first ring and the second ring from the inside may be observed.
  • the first spot derived from the first crystal portion is positioned so as to overlap with the ring (first ring) positioned inside.
  • another spot derived from the first crystal part may be observed at a position overlapping the second ring.
  • the presence ratio of the first crystal part having orientation in the metal oxide film is high, a pattern with higher anisotropy is dominant in the obtained electron beam diffraction pattern.
  • the luminance of the first ring and the second ring is relatively lower than the luminance of the first spot derived from the first crystal part.
  • a different spot (third spot) derived from the first crystal part may be observed at a position overlapping the second ring located outside.
  • the third spot and the second ring overlap in the radial direction, it can be inferred that they originate from diffraction from the same crystal plane.
  • the brightness (diffraction intensity) of the second spot caused by the second crystal part in the nanobeam electron diffraction pattern is smaller than the brightness of the first spot caused by the first crystal part.
  • This difference in luminance increases as the proportion of the first crystal portion in the metal oxide film increases, and it becomes an index for estimating the crystallinity of the metal oxide film.
  • the brightness of the first spot is greater than 1 time and 10 times or less than the brightness of the second spot.
  • the metal oxide film of one embodiment of the present invention is an oxide film containing indium, M (M is Al, Ga, Y, or Sn), and zinc.
  • M is Al, Ga, Y, or Sn
  • Such an oxide film has a feature of taking a crystal structure having a layered structure along the c-axis. Further, such an oxide film has a characteristic of having semiconductor characteristics.
  • the metal oxide film of one embodiment of the present invention can be applied to a semiconductor in which a channel of a transistor is formed.
  • a transistor to which a metal oxide film in which a first crystal part having orientation and a second crystal part having no orientation are mixed is composed of only the second crystal part having no orientation. Compared with a transistor to which a metal oxide film is applied, the electrical characteristics can be increased and the channel length can be easily reduced.
  • a transistor using a metal oxide film in which a first crystal part having orientation and a second crystal part not having orientation are mixed has a very high proportion of the first crystal part having orientation.
  • a transistor to which a high (eg, greater than 75%) metal oxide film is applied field effect mobility can be increased particularly under a low gate voltage. Therefore, there are features such that the drive voltage of the device can be lowered and high-frequency driving is facilitated.
  • the metal oxide film of one embodiment of the present invention includes indium (In), M (M is Al, Ga, Y, or Sn), and zinc (Zn).
  • M is preferably gallium (Ga).
  • the metal oxide film contains In, for example, carrier mobility (electron mobility) increases. Further, when the metal oxide film contains Ga, for example, the energy gap (Eg) of the metal oxide film is increased. Note that Ga is an element having a high binding energy with oxygen, and has a higher binding energy with oxygen than In. In addition, when the metal oxide film contains Zn, the metal oxide film is easily crystallized.
  • the metal oxide film of one embodiment of the present invention preferably has a crystal structure exhibiting a single phase, particularly a homologous phase.
  • the metal oxide film has a composition of In 1 + x M 1-x O 3 (ZnO) y (x is a number satisfying 0 ⁇ x ⁇ 0.5, and y is near 1).
  • the carrier mobility (electron mobility) of the metal oxide film can be increased.
  • the metal oxide film of one embodiment of the present invention has a structure of In 1 + x M 1-x O 3 (ZnO) y (x represents a number satisfying 0 ⁇ x ⁇ 0.5, and y represents 1 vicinity).
  • a metal oxide film having such a composition can have both high carrier mobility and high film stability.
  • composition of the metal oxide film is not limited to this, and may be any composition that can take a layered crystal structure.
  • the vicinity may be within a range of plus or minus 1 and more preferably within a plus or minus 0.5 with respect to the atomic ratio of a certain metal atom.
  • Ga is 1 to 3 (1 ⁇ Ga ⁇ 3) and Zn is 2 or more 4 or less (2 ⁇ Zn ⁇ 4)
  • Ga is 1.5 or more and 2.5 or less (1.5 ⁇ Ga ⁇ 2.5)
  • Zn is 2 or more and 4 or less (2 ⁇ Zn ⁇ 4) If it is.
  • Sample 1 is a sample in which a metal oxide film including indium, gallium, and zinc having a thickness of about 100 nm is formed over a glass substrate.
  • the substrate is heated to 130 ° C.
  • argon gas with a flow rate of 180 sccm and oxygen gas with a flow rate of 20 sccm are introduced into the chamber of the sputtering apparatus, the pressure is 0.6 Pa, indium, and gallium.
  • the above gas flow ratio may be described as an oxygen flow ratio from the ratio of the oxygen flow rate to the total gas flow rate. At this time, the oxygen flow ratio in the production conditions of the sample 1 is 10%.
  • Sample 2 is a sample in which a metal oxide film having a thickness of about 100 nm is formed on a glass substrate.
  • the metal oxide film of Sample 2 was formed under the same conditions as Sample 1 except that the substrate was heated to 170 ° C. and conditions other than the substrate temperature.
  • the oxygen flow rate ratio under the production conditions of Sample 2 is 10%.
  • Sample 3 is a sample in which a metal oxide film having a thickness of about 100 nm is formed on a glass substrate.
  • the substrate is heated to 170 ° C.
  • argon gas having a flow rate of 140 sccm and oxygen gas having a flow rate of 60 sccm are introduced into the chamber of the sputtering apparatus. Formed under the same conditions.
  • the oxygen flow rate ratio under the production conditions of Sample 3 is 30%.
  • Sample 4 is a sample in which a metal oxide having a thickness of about 100 nm is formed on a glass substrate.
  • the oxygen flow rate ratio under the production conditions of Sample 4 is 33%.
  • FIGS. 1A, 1B, and 1C show the results of XRD measurement performed on samples 1 to 3.
  • measurement was performed using a powder method (also referred to as a ⁇ -2 ⁇ method) which is a kind of out-of-plane method.
  • the ⁇ -2 ⁇ method is a method of measuring the X-ray diffraction intensity by changing the incident angle of the X-ray and setting the angle of the detector provided facing the X-ray source to be the same as the incident angle.
  • GIXRD Grazing-Incidence XRD
  • Method also referred to as a thin film method or a Seemann-Bohlin method
  • the horizontal axis represents the angle 2 ⁇
  • the vertical axis represents the diffraction intensity in arbitrary units.
  • any sample includes a crystal part in which the c-axis is oriented in the film thickness direction (hereinafter also referred to as an oriented crystal part or a first crystal part). I can confirm that. In addition, it can be seen from the comparison of the strength that the proportion of crystal parts having orientation is higher in the order of Sample 3, Sample 2, and Sample 1.
  • the electron beam diffraction pattern of each sample is shown.
  • the electron beam diffraction pattern shown here is obtained by adjusting the contrast so that the diffraction pattern becomes clear.
  • the luminance analysis of the diffraction pattern shown below not adjusted image data but not adjusted image data shown in the figure is used.
  • the thickness of the sample used for electron beam diffraction will be described.
  • the sample is too thin, for example, when the thickness is 5 nm or less, only information on a very fine region can be obtained.
  • the electron beam diffraction pattern may be a pattern similar to that of a single crystal. If the purpose is not to analyze an extremely fine region, the thickness of the sample is preferably 10 nm to 100 nm, typically 10 nm to 50 nm.
  • FIG. 3A and 3B show the electron diffraction patterns of Sample 1.
  • FIG. 3A and 3B are electron beam diffraction patterns when the beam diameter is 100 nm and 1 nm, respectively.
  • the brightest bright spot at the center is due to the incident electron beam, and is the center (also referred to as a direct spot) of the electron diffraction pattern.
  • FIG. 3A two ring-shaped diffraction patterns having different radii can be confirmed.
  • the first ring and the second ring are referred to from the smaller diameter. It can be confirmed that the brightness of the first ring is higher than that of the second ring. Further, two spots (first spots) indicated by arrows are confirmed at positions overlapping the first ring.
  • the radial distance from the center of the first ring and the two first spots substantially coincides with the radial distance from the center of the diffraction spot on the (009) plane in the structural model of single crystal InGaZnO 4. .
  • crystal parts having no orientation or second crystal parts Since a ring-shaped diffraction pattern is observed, in the metal oxide film, crystal parts that are oriented in all directions (hereinafter also referred to as crystal parts having no orientation or second crystal parts). ) Can be confirmed.
  • the two first spots are symmetrically arranged with respect to the center point of the electron beam diffraction pattern and have the same luminance, so that the crystal part derived from the first spot has twofold symmetry. It is inferred. Further, as described above, since the two first spots are diffraction spots by a crystal plane perpendicular to the c-axis, the direction of a straight line (a straight line indicated by a broken line) connecting the two first spots and the center is the crystal. This coincides with the direction of the c-axis of the part. In FIG. 3A, since the vertical direction is the film thickness direction, it can be seen that there is a crystal part in which the c-axis is oriented in the film thickness direction in the metal oxide film.
  • FIG. 3 (B) a plurality of circumferentially distributed spots (second spots) can be confirmed at the position of the first ring seen in FIG. 3 (A). Furthermore, two first spots can also be confirmed.
  • FIG. 3 (B) when the diameter of the incident electron beam is extremely small, a plurality of second spots distributed in a circumferential shape are seen, so that the metal oxide film is extremely small. Further, it can be seen that a plurality of crystal parts having plane orientations oriented in all directions are mixed.
  • the first ring seen in FIG. 3A is the result of averaging the brightness by connecting a plurality of diffraction spots from this fine crystal part by widening the observation region. Can understand.
  • the metal oxide film of Sample 1 is a film in which crystal parts having orientation and crystal parts having no orientation are mixed.
  • the crystal part having orientation is high in the crystal part existing in the film. I can confirm that.
  • FIGS. 4A and 4B show the electron diffraction pattern of the sample 2
  • FIGS. 4C and 4D show the electron diffraction pattern of the sample 3, respectively.
  • 4A and 4C each show a beam diameter of 100 nm
  • FIGS. 4B and 4D each show a beam diameter of 1 nm.
  • the third spot has a luminance that cannot be distinguished from the second ring.
  • the two third spots are positioned in a direction rotated 90 degrees with respect to the first spot.
  • This third spot is a diffraction spot derived from a plane other than the crystal plane perpendicular to the c-axis.
  • the sample 3 is a film having a higher proportion of crystal parts having orientation, that is, higher crystallinity, as the diffraction spots other than the first spot are clearly observed.
  • FIG. 5 shows an electron diffraction pattern measured on the sample 4 under the condition that the beam diameter is 100 nm.
  • sample 4 Although the first ring was seen, the first spot seen in samples 1 to 3 was not observed. From this, sample 4 has a plurality of crystal parts derived from the first ring, and the ratio of crystal parts having orientation is equal to the ratio of crystal parts oriented in other directions. It is suggested that
  • FIG. 6A shows an enlarged view of FIG.
  • the first spot is 30 degrees, 90 degrees around the center of the electron diffraction pattern at a position overlapping the first ring in the radial direction
  • a diffraction spot is not observed at a position rotated by 120 degrees (a region surrounded by a broken line in FIG. 6A). That is, the luminance that appears in this region is scattered from electrons diffracted from a crystal part other than the crystal part having orientation in the metal oxide film, or from a region other than the crystal part in the film or a region such as a substrate. It is thought to be derived from electrons.
  • the latter scattered electrons are considered to be observed at the same intensity at positions where the radius is equal, and can be ignored here. Therefore, for example, the difference between the brightness of the first spot and the brightness at a position rotated by 90 degrees is an important parameter for knowing the existence ratio of crystal parts having orientation.
  • the difference between the luminance of the first spot and the luminance of the position rotated by a predetermined angle from here can be obtained by normalizing with the luminance of the direct spot appearing at the center position of the electron beam diffraction pattern. This also allows a relative comparison between the samples.
  • FIG. 7 (A1) shows an electron beam diffraction pattern (same as FIG. 3 (A)) in the sample 1
  • FIG. 7 (A2) shows A ⁇ passing through the first spot and the direct spot in the figure.
  • the normalized luminance profile with respect to the radial position along each line of A ′ and BB ′ orthogonal thereto is shown.
  • two peaks are observed across the peak of the direct spot. Further, there is a clear difference between the two peak luminances between A-A 'and B-B'.
  • FIGS. 7C1 and 7C2 are profiles of an electron beam diffraction pattern and a normalized luminance in the sample 3, respectively.
  • the difference between the peak luminance of the first spot and the peak luminance at the position rotated by 90 degrees is larger than that of the sample 1. Further, it can be seen that the difference is larger in the sample 3 than in the sample 2.
  • FIG. 7 (D1) and FIG. 7 (D2) are an electron beam diffraction pattern and a normalized luminance profile in the sample 4, respectively.
  • sample 4 it can be seen that the profiles are almost the same in the two directions. That is, it can be confirmed that the sample 4 contains few crystal parts having orientation, and contains a plurality of crystal parts whose crystal planes face in various directions.
  • the first ring appears as a set of discrete bright spots in the electron diffraction pattern.
  • the ring brightness may not be accurately determined.
  • a rectangular region having a specific width and having a long side direction coincident with the radial direction is a rectangle in the rectangular width direction (FIG. 6B).
  • the luminance at a predetermined position may be calculated from the luminance profile in the radial direction using the luminance value averaged in the short side direction).
  • a higher-accuracy comparison can be performed by subtracting the luminance component caused by inelastic scattering or the like from the sample as the background.
  • the background luminance may be calculated by linear approximation. For example, a straight line can be drawn along the skirts on both sides of the target peak, and a region located on the lower luminance side than the straight line can be subtracted as the background.
  • the luminance of the first spot and the luminance of the position rotated by 90 degrees from the position of the first spot were calculated from the data obtained by subtracting the background by the method described above. Then, a value obtained by dividing the luminance of the first spot by the luminance at the position rotated 90 degrees from the first spot was obtained as the relative luminance R.
  • FIG. 8 shows the result of estimating the relative luminance R from the electron beam diffraction pattern measured for each of the samples 1 to 4 under the condition that the beam diameter is 100 nm.
  • the luminance difference is not confirmed at the two positions, and the relative luminance R is 1.
  • the relative luminance increases in the order of sample 1, sample 2, and sample 3.
  • the relative luminance R is more than 1 time and 10 times or less, preferably more than 1.2 times and 8 times or less, more preferably It is preferable to use a metal oxide film that is larger than 1.5 times and smaller than 6 times, more preferably larger than 1.5 times and smaller than 4 times.
  • the fluctuation in the orientation direction can be evaluated as follows.
  • the electron diffraction pattern for the cross section of the metal oxide film is measured at a plurality of locations, and for each of the obtained images, a straight line passing through the center of the electron beam diffraction pattern and the first spot, and the film of the metal oxide film By measuring the inclination with respect to the thickness direction, it is possible to estimate the variation in the orientation direction of the crystal part existing in each region.
  • an electron beam diffraction pattern was acquired as a moving image while scanning the electron beam in a direction parallel to the film surface direction under the condition that the beam diameter of the electron beam was 1 nm. The scan was performed at a distance of about 250 nm for 100 seconds.
  • FIG. 9 shows a part of electron beam diffraction patterns of the captured moving images of Sample 1, Sample 2, and Sample 3.
  • FIG. 9 shows nine electron beam diffraction patterns, each interval being about 10 seconds.
  • FIG. 9 a straight line passing through the first spot and the center of the electron diffraction pattern is indicated by a broken line. As shown in FIG. 9, it is confirmed that the orientation direction of the crystal part varies depending on the region to be observed.
  • FIG. 10 shows a distribution diagram of the orientation direction estimated from each electron diffraction pattern shown in FIG.
  • the horizontal axis is the distance when the imaging start position is the origin, and the vertical axis is the orientation direction angle at each position when the average value of the orientation direction measured at each position is 0 degree.
  • the clockwise direction is shown as positive.
  • FIG. 10 there is almost no difference in the variation in the orientation direction between the samples, and any sample is within a range of less than 10 degrees.
  • the orientation direction of the crystal part in the metal oxide film can be estimated by the spread of the spot in the circumferential direction in the electron beam diffraction pattern measured under the condition that the beam diameter of the electron beam is increased.
  • an electron beam diffraction pattern in which information on crystal parts existing in the measurement range is averaged can be obtained. Therefore, the spread of the spot in the circumferential direction becomes wider as the variation in the orientation direction of the crystal part becomes larger.
  • the luminance distribution in the circumferential direction is a distribution reflecting the existence ratio of the crystal parts oriented in a specific direction.
  • the first spot is not a perfect point (or circle) shape, but has a shape close to an elliptical shape extending in the circumferential direction.
  • the angle between two straight lines connecting each of the two end portions in the circumferential direction of the spot and the center point of the electron beam diffraction pattern represents variation in the orientation direction of the crystal portion.
  • the position of 1 ⁇ or 2 ⁇ may be set as the end with respect to the brightest point of the first spot.
  • the difference in luminance between the first ring and the first spot is small, it may be estimated based on a luminance distribution obtained by subtracting the luminance of the first ring from the luminance of the first spot. In this method, depending on the measurement conditions of the electron beam diffraction pattern, the spread of the spot increases as the luminance increases, and it may be estimated to be larger than the actual orientation variation.
  • the central angle of both ends of the first spot centered on the center of the electron beam diffraction pattern is 0 degree or more and 45 degrees or less, preferably 0 degree or more and 40 degrees or less, more preferably 0 degree or more and 35 degrees or less, Preferably it is 0 degree or more and 30 degrees or less.
  • the existence ratio of the crystal part in the metal oxide film can be estimated by analyzing the cross-sectional observation image.
  • a two-dimensional fast Fourier transform FFT: Fast Fourier Transform
  • FFT Fast Fourier Transform
  • the obtained FFT image is subjected to a mask process that leaves a range having periodicity and removes the rest.
  • the masked FFT image is then subjected to a two-dimensional inverse Fourier transform (IFFT: Inverse Fast Fourier Transform) to obtain an FFT filtered image.
  • IFFT Inverse Fast Fourier Transform
  • the existence ratio of the crystal part can be estimated from the ratio of the area of the remaining image. Further, by subtracting the remaining area from the area of the region used for image processing (also referred to as the area of the original image), it is possible to estimate the existence ratio of the part other than the crystal part.
  • FIGS. 11A and 11B show cross-sectional TEM observation images of Sample 3 and Sample 1 before image processing
  • FIGS. 11C and 11D show images obtained after image processing, respectively.
  • a white area in the metal oxide film corresponds to an area including a crystal part.
  • the ratio of the area excluding the region including the crystal part in the sample 3 was about 21.0%. Further, the ratio of the area excluding the region including the crystal part having orientation in the sample 1 estimated from FIG. 11D was about 39.8%.
  • the metal oxide film is a film having extremely high crystallinity, and electrical characteristics. Is preferable because of its high stability. Further, when the proportion of the portion excluding the crystal part in the metal oxide film is 25% or more and less than 100%, preferably 25% or more and 90% or less, more preferably 25% or more and 80% or less, the metal oxide In the film, crystal parts having orientation and crystal parts having no orientation are mixed, and both stability of electric characteristics and high mobility can be achieved.
  • the atomic void region is a region in which a plurality of crystal parts having irregular surface orientations and extremely fine and different sizes are mixed. Presence of the crystal part is such that no spot is observed in an electron diffraction pattern having a large beam diameter (probe diameter) (for example, 25 nm ⁇ or more, or 50 nm ⁇ or more), and the beam diameter is extremely small (for example, 0.3 nm or more and 10 nm ⁇ ). It can be understood from the fact that it is finally observed as a spot in the electron diffraction pattern, and the crystal part is extremely fine.
  • beam diameter beam diameter
  • a titanium film with a thickness of 10 nm and a copper film with a thickness of 100 nm were formed on a glass substrate using a sputtering apparatus. Subsequently, the conductive film was processed by a photolithography method.
  • insulating films were formed on the substrate and the conductive film.
  • the insulating film was continuously formed in a vacuum using a plasma enhanced chemical vapor deposition (PECVD) apparatus.
  • PECVD plasma enhanced chemical vapor deposition
  • a silicon nitride film with a thickness of 50 nm, a silicon nitride film with a thickness of 300 nm, a silicon nitride film with a thickness of 50 nm, and a silicon oxynitride film with a thickness of 50 nm were used from the bottom.
  • an oxide semiconductor film was formed over the insulating film, and the semiconductor layer was formed by processing the oxide semiconductor film into an island shape.
  • the oxide semiconductor film 108 an oxide semiconductor film with a thickness of 40 nm was formed.
  • the metal oxide film used for the oxide semiconductor film has the same conditions as in sample 1. That is, a metal having indium, gallium, and zinc at a substrate temperature of 130 ° C., an argon gas with a flow rate of 180 sccm and an oxygen gas with a flow rate of 20 sccm are introduced into the chamber of the sputtering apparatus, the pressure is 0.6 Pa.
  • the oxygen flow rate ratio is 10%.
  • the thickness was about 40 nm.
  • the metal oxide film used for the oxide semiconductor film has the same conditions as Sample 3. That is, a metal having indium, gallium, and zinc at a substrate temperature of 170 ° C., an argon gas having a flow rate of 140 sccm and an oxygen gas having a flow rate of 60 sccm are introduced into the chamber of the sputtering apparatus, the pressure is 0.6 Pa.
  • the oxygen flow rate ratio is 30%.
  • the thickness was about 40 nm.
  • an insulating film was formed over the insulating film and the oxide semiconductor layer.
  • a 150 nm thick silicon oxynitride film was formed using a PECVD apparatus.
  • heat treatment was performed.
  • heat treatment was performed at 350 ° C. for 1 hour in a mixed gas atmosphere of nitrogen and oxygen.
  • an opening was formed in a desired region of the insulating film.
  • a dry etching method was used as a method for forming the opening.
  • an oxide semiconductor film having a thickness of 100 nm was formed over the insulating film so as to cover the opening, and the oxide semiconductor film was processed into an island shape, whereby a conductive film was formed.
  • the insulating film in contact with the lower side of the conductive film was processed to form the insulating film.
  • an oxide semiconductor film having a thickness of 100 nm was formed. Note that the oxide semiconductor film has a two-layer structure.
  • the substrate temperature was 170 ° C.
  • an oxygen gas with a flow rate of 200 sccm was introduced into the chamber of the sputtering apparatus, the pressure was 0.6 Pa, indium, gallium,
  • the film thickness becomes 10 nm. Formed.
  • the substrate temperature was set to 170 ° C.
  • argon gas having a flow rate of 180 sccm and oxygen gas having a flow rate of 20 sccm were introduced into the chamber of the sputtering apparatus, and the pressure was set to 0.6 Pa.
  • the film thickness was 90 nm.
  • plasma treatment was performed on the oxide semiconductor film, the insulating film, and the conductive film.
  • the plasma treatment was performed using a PECVD apparatus at a substrate temperature of 220 ° C. in a mixed gas atmosphere of argon gas and nitrogen gas.
  • an insulating film was formed over the oxide semiconductor film, the insulating film, and the conductive film.
  • a silicon nitride film with a thickness of 100 nm and a silicon oxynitride film with a thickness of 300 nm were stacked using a PECVD apparatus.
  • a mask was formed on the formed insulating film, and an opening was formed in the insulating film using the mask.
  • a conductive film was formed so as to fill the opening, and the conductive film was processed into an island shape, thereby forming a conductive film to be a source electrode and a drain electrode.
  • a titanium film with a thickness of 10 nm and a copper film with a thickness of 100 nm were formed using a sputtering apparatus, respectively.
  • an insulating film was formed over the insulating film and the conductive film.
  • an acrylic photosensitive resin having a thickness of 1.5 ⁇ m was used.
  • measurement conditions for the Id-Vg characteristics of the transistor include a voltage applied to a conductive film functioning as a first gate electrode (hereinafter also referred to as a gate voltage (Vg)) and a conductive function functioning as a second gate electrode.
  • a voltage (also referred to as Vbg) applied to the film was applied from ⁇ 15V to + 20V in steps of 0.25V.
  • a voltage applied to the conductive film functioning as the source electrode hereinafter also referred to as source voltage (Vs)
  • source voltage (Vs)) is 0 V (comm)
  • drain voltage (Vd) also referred to as drain voltage (Vd)
  • drain voltage (Vd) also referred to as 0.1V and 20V.
  • FIGS. 12A and 12B show the Id-Vg characteristic results of Sample A1 and Sample A2, respectively.
  • the first vertical axis represents Id (A)
  • the second vertical axis represents field effect mobility ( ⁇ FE (cm 2 / Vs))
  • the horizontal axis represents Vg (V).
  • Id-Vg characteristic results of a total of five transistors are shown in an overlapping manner.
  • a transistor in which a metal oxide film including a crystal part with orientation and a crystal part without orientation, which is one embodiment of the present invention, is used for a semiconductor layer in which a channel is formed has high field-effect mobility. It was confirmed that the degree was shown. In particular, it was confirmed that a high field-effect mobility and a high drain current were exhibited under conditions where the gate voltage was low.
  • the metal oxide film of one embodiment of the present invention can be formed by a sputtering method in a state where the substrate is heated in an atmosphere containing oxygen.
  • the substrate temperature during film formation is 80 ° C. or higher and 150 ° C. or lower, preferably 100 ° C. or higher and 150 ° C. or lower, typically 130 ° C. By increasing the temperature of the substrate, more crystal parts having orientation can be formed.
  • the flow rate ratio of oxygen during film formation is 1% to less than 33%, preferably 5% to 30%, more preferably 5% to 20%, and even more preferably 5% to 15%. % Or less, typically 10%.
  • oxygen partial pressure oxygen partial pressure
  • a metal oxide film in which a crystal part having orientation and a crystal part having no orientation are mixed can be obtained. Obtainable. Further, by optimizing the substrate temperature and the oxygen flow rate within the above-described ranges, it is possible to control the existence ratio of the crystal part having orientation and the crystal part not having orientation.
  • An oxide target that can be used for forming a metal oxide film is not limited to an In—Ga—Zn-based oxide, and includes, for example, an In—M—Zn-based oxide (M is Al, Ga, Y). Or Sn) can be applied.
  • a metal oxide film including a crystal part which is a metal oxide film
  • a sputtering target including a polycrystalline oxide having a plurality of crystal grains a sputtering target not including a polycrystalline oxide is used. Compared with the case where it had, the metal oxide film which has crystallinity is easy to be obtained.
  • the sputtering target has a plurality of crystal grains and the crystal grains have a layered structure, and there is an interface that is easily cleaved, the ions are allowed to collide with the sputtering target.
  • the crystal grains may be cleaved to obtain flat or pellet-like sputtered particles. It is considered that the obtained flat or pellet-like sputtered particles are deposited on a substrate to form a metal oxide film containing nanocrystals. In addition, it is considered that by heating the substrate, bonding or rearrangement of the nanocrystals progresses on the substrate surface, so that a metal oxide film including a crystal part having orientation is easily formed.
  • a sputtering method is particularly preferable because the crystallinity can be easily controlled.
  • a pulse laser deposition (PLD) method for example, a pulse laser deposition (PLD) method, a plasma chemical vapor deposition (PECVD) method, a thermal CVD (Chemical Vapor Deposition) method, an ALD (Atomic Layer Deposition) method, a vacuum evaporation method, or the like is used.
  • PLD pulse laser deposition
  • PECVD plasma chemical vapor deposition
  • thermal CVD Thermal CVD
  • ALD Atomic Layer Deposition
  • a vacuum evaporation method or the like.
  • An example of the thermal CVD method is a MOCVD (Metal Organic Chemical Vapor Deposition) method.
  • the metal oxide film of one embodiment of the present invention can be applied to a semiconductor device such as a transistor.
  • a metal oxide film having semiconductor characteristics hereinafter referred to as an oxide semiconductor film
  • composition First, the composition of the oxide semiconductor film is described.
  • the oxide semiconductor film includes indium (In), M (M represents Al, Ga, Y, or Sn), and Zn (zinc).
  • the element M is aluminum, gallium, yttrium, or tin, but as elements applicable to the element M, in addition to the above, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, Cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be used. Further, as the element M, a plurality of the aforementioned elements may be combined.
  • FIGS. 13A, 13B, and 13C a preferable range of the atomic ratio of indium, element M, and zinc included in the oxide semiconductor film of one embodiment of the present invention is described with reference to FIGS.
  • the atomic ratio of oxygen is not described.
  • the terms of the atomic ratio of indium, element M, and zinc included in the oxide semiconductor film are [In], [M], and [Zn].
  • 13A and 13B illustrate an example of a preferable range of the atomic ratio of indium, element M, and zinc included in the oxide semiconductor film of one embodiment of the present invention.
  • FIG. 14 shows a crystal structure of InMZnO 4 when observed from a direction parallel to the b-axis.
  • a metal element in a layer containing M, Zn, and oxygen (hereinafter, (M, Zn) layer) illustrated in FIG. 14 represents the element M or zinc.
  • the ratio of the element M and zinc shall be equal.
  • the element M and zinc can be substituted and the arrangement is irregular.
  • InMZnO 4 has a layered crystal structure (also referred to as a layered structure). As shown in FIG. 14, a layer containing indium and oxygen (hereinafter referred to as an In layer) contains 1 element M, zinc, and oxygen. The (M, Zn) layer having 2 is 2.
  • indium and element M can be substituted for each other. Therefore, the element M in the (M, Zn) layer can be replaced with indium and expressed as an (In, M, Zn) layer. In that case, a layered structure in which the In layer is 1 and the (In, M, Zn) layer is 2 is employed.
  • the number of (M, Zn) layers is non-integer with respect to one In layer
  • the number of (M, Zn) layers is integer with respect to one In layer.
  • a film having an atomic ratio that deviates from the atomic ratio of the target is formed.
  • [Zn] of the film may be smaller than [Zn] of the target.
  • a plurality of phases may coexist in the oxide semiconductor film (two-phase coexistence, three-phase coexistence, etc.).
  • a grain boundary also referred to as a grain boundary
  • a grain boundary may be formed between different crystal structures.
  • the oxide semiconductor of one embodiment of the present invention have an atomic ratio shown in a region A in FIG. 13A in which a carrier mobility is high and a layered structure with few grain boundaries is likely to be formed.
  • An oxide semiconductor film having an atomic ratio represented by the region B is an excellent oxide semiconductor film that has particularly high crystallinity and high carrier mobility.
  • the conditions under which the oxide semiconductor film forms a layered structure are not uniquely determined by the atomic ratio. Depending on the atomic ratio, there is a difference in difficulty for forming a layered structure. On the other hand, even if the atomic ratio is the same, there may be a layered structure or a layered structure depending on the formation conditions. Therefore, the illustrated region is a region that exhibits an atomic ratio in which the oxide semiconductor film has a layered structure, and the boundaries between the regions A to C are not strict.
  • an oxide semiconductor film for a transistor for example, carrier scattering at a crystal grain boundary can be reduced as compared with a transistor using polycrystalline silicon for a channel region.
  • a transistor can be realized.
  • a highly reliable transistor can be realized.
  • the oxide semiconductor film of one embodiment of the present invention is a film in which a crystal part having orientation and a crystal part not having orientation are mixed. By using such an oxide semiconductor film having crystallinity, a transistor having both high field-effect mobility and high reliability can be realized.
  • oxygen vacancies (Vo) in the oxide semiconductor film As a factor that affects the carrier density of the oxide semiconductor film, oxygen vacancies (Vo) in the oxide semiconductor film, impurities in the oxide semiconductor film, and the like can be given.
  • the density of defect states increases when hydrogen is bonded to the oxygen vacancies (this state is also referred to as VoH).
  • the carrier density of the oxide semiconductor film can be controlled by controlling the density of defect states in the oxide semiconductor film.
  • the object is to suppress a negative shift in the threshold voltage of the transistor or to reduce the off-state current of the transistor, it is preferable to reduce the carrier density of the oxide semiconductor film.
  • the impurity concentration in the oxide semiconductor film may be decreased and the defect level density may be decreased.
  • a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic.
  • the carrier density of the high-purity intrinsic oxide semiconductor film is less than 8 ⁇ 10 15 cm ⁇ 3 , preferably less than 1 ⁇ 10 11 cm ⁇ 3 , more preferably less than 1 ⁇ 10 10 cm ⁇ 3 , and 1 ⁇ What is necessary is just to set it as 10 ⁇ -9 > cm ⁇ -3 > or more.
  • the carrier density of an oxide semiconductor film it is preferable to increase the carrier density of an oxide semiconductor film.
  • the impurity concentration of the oxide semiconductor film may be slightly increased or the defect state density of the oxide semiconductor film may be slightly increased.
  • the band gap of the oxide semiconductor film is preferably made smaller.
  • an oxide semiconductor film with a slightly high impurity concentration or a slightly high defect state density within a range where the on / off ratio of the Id-Vg characteristics of the transistor can be obtained can be regarded as substantially intrinsic.
  • the oxide semiconductor film with the increased carrier density is slightly n-type. Therefore, an oxide semiconductor film with an increased carrier density may be referred to as “Slightly-n”.
  • the carrier density of the substantially intrinsic oxide semiconductor film is preferably 1 ⁇ 10 5 cm ⁇ 3 or more and less than 1 ⁇ 10 18 cm ⁇ 3 , preferably 1 ⁇ 10 7 cm ⁇ 3 or more and 1 ⁇ 10 17 cm ⁇ 3 or less. More preferably, it is 1 ⁇ 10 9 cm ⁇ 3 or more and 5 ⁇ 10 16 cm ⁇ 3 or less, more preferably 1 ⁇ 10 10 cm ⁇ 3 or more and 1 ⁇ 10 16 cm ⁇ 3 or less, and further preferably 1 ⁇ 10 11 cm ⁇ 3. More preferably, it is 1 ⁇ 10 15 cm ⁇ 3 or less.
  • FIG. 15 illustrates an energy band in a transistor in which an oxide semiconductor film is used for a channel region.
  • FIG. 15 illustrates an example of the energy band of the gate electrode, the gate insulating film, the oxide semiconductor film, and the source or drain electrode in contact with the oxide semiconductor film.
  • a silicon oxide film is used as the gate insulating film and an In—Ga—Zn oxide is used as the oxide semiconductor film.
  • the transition level ( ⁇ f) of defects that can be formed in the silicon oxide film is formed at a position about 3.1 eV away from the lower end of the conduction band of the gate insulating film, and the gate voltage (Vg) is 30V.
  • the Fermi level (Ef) of the silicon oxide film at the interface between the oxide semiconductor film and the silicon oxide film is formed at a position about 3.6 eV away from the lower end of the conduction band of the gate insulating film. Note that the Fermi level of the silicon oxide film varies depending on the gate voltage.
  • the Fermi level (Ef) of the silicon oxide film at the interface between the oxide semiconductor film and the silicon oxide film is lowered.
  • white circles in FIG. 15 represent electrons (carriers), and X in FIG. 15 represents a defect level in the silicon oxide film.
  • the depth at which the Fermi level at the interface between the gate insulating film and the oxide semiconductor film is formed may be different.
  • the lower end of the conduction band of the gate insulating film is relatively high in the vicinity of the interface between the gate insulating film and the oxide semiconductor film.
  • a defect level (X in FIG. 15) that can be formed in the gate insulating film is also relatively high, an energy difference between the Fermi level of the gate insulating film and the Fermi level of the oxide semiconductor film is increased. growing. As the energy difference increases, the charge trapped in the gate insulating film decreases. For example, the change in the charge state of the defect level that can be formed in the above-described silicon oxide film is reduced, and variation in the threshold voltage of the transistor due to gate bias thermal (also referred to as GBT) stress can be reduced. .
  • the charge trapped in the defect level of the oxide semiconductor film takes a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor film with a high defect level density may have unstable electrical characteristics.
  • Impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.
  • the concentration of silicon or carbon in the oxide semiconductor film and the concentration of silicon or carbon in the vicinity of the interface with the oxide semiconductor film are obtained. 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the concentration of alkali metal or alkaline earth metal in the oxide semiconductor film obtained by SIMS is set to 1 ⁇ 10 18 atoms / cm 3 or lower, preferably 2 ⁇ 10 16 atoms / cm 3 or lower.
  • the nitrogen in the oxide semiconductor film is preferably reduced as much as possible.
  • the nitrogen concentration in the oxide semiconductor film is less than 5 ⁇ 10 19 atoms / cm 3 in SIMS, preferably 5 ⁇ . 10 18 atoms / cm 3 or less, more preferably 1 ⁇ 10 18 atoms / cm 3 or less, and even more preferably 5 ⁇ 10 17 atoms / cm 3 or less.
  • hydrogen contained in the oxide semiconductor film reacts with oxygen bonded to a metal atom to become water, so that an oxygen vacancy may be formed in some cases.
  • oxygen vacancy may be formed in some cases.
  • electrons serving as carriers may be generated.
  • a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor including an oxide semiconductor film containing hydrogen is likely to be normally on. For this reason, it is preferable that hydrogen in the oxide semiconductor film be reduced as much as possible.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , more preferably 5 ⁇ 10 18 atoms / cm 3. Less than cm 3 , more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • the oxide semiconductor film preferably has an energy gap of 2 eV or more, or 2.5 eV or more.
  • the thickness of the oxide semiconductor film is 3 nm to 200 nm, preferably 3 nm to 100 nm, more preferably 3 nm to 60 nm.
  • the oxide semiconductor film is an In-M-Zn oxide
  • FIG. 16A is a top view of the transistor 100
  • FIG. 16B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 16A
  • FIG. 16C is FIG. It is sectional drawing between dashed-dotted lines Y1-Y2.
  • components such as the insulating film 110 are omitted for clarity.
  • some components may be omitted in the following drawings as in FIG. 16A.
  • alternate long and short dash line X1-X2 direction may be referred to as a channel length (L) direction
  • the alternate long and short dash line Y1-Y2 direction may be referred to as a channel width (W) direction.
  • 16A, 16B, and 16C includes an insulating film 104 over a substrate 102, an oxide semiconductor film 108 over the insulating film 104, an insulating film 110 over the oxide semiconductor film 108, The conductive film 112 over the insulating film 110, the insulating film 104, the oxide semiconductor film 108, and the insulating film 116 over the conductive film 112 are included.
  • the oxide semiconductor film 108 includes a channel region 108 i overlapping with the conductive film 112, a source region 108 s in contact with the insulating film 116, and a drain region 108 d in contact with the insulating film 116.
  • the insulating film 116 has nitrogen or hydrogen.
  • nitrogen or hydrogen in the insulating film 116 is added to the source region 108s and the drain region 108d.
  • the carrier density is increased by adding nitrogen or hydrogen.
  • the transistor 100 includes an insulating film 118 over the insulating film 116, a conductive film 120a electrically connected to the source region 108s through the opening 141a provided in the insulating films 116 and 118, and the insulating film 116. , 118 may be provided, and the conductive film 120b electrically connected to the drain region 108d through the opening 141b provided in the opening 118b.
  • the insulating film 104 is a first insulating film
  • the insulating film 110 is a second insulating film
  • the insulating film 116 is a third insulating film
  • the insulating film 118 is a fourth insulating film.
  • the conductive film 112 functions as a gate electrode
  • the conductive film 120a functions as a source electrode
  • the conductive film 120b functions as a drain electrode.
  • the insulating film 110 functions as a gate insulating film.
  • the insulating film 110 has an excess oxygen region.
  • excess oxygen can be supplied to the channel region 108 i included in the oxide semiconductor film 108. Accordingly, oxygen vacancies that can be formed in the channel region 108i can be filled with excess oxygen, so that a highly reliable semiconductor device can be provided.
  • excess oxygen may be supplied to the insulating film 104 formed below the oxide semiconductor film 108.
  • excess oxygen contained in the insulating film 104 can be supplied also to the source region 108s and the drain region 108d included in the oxide semiconductor film 108.
  • the resistance of the source region 108s and the drain region 108d may increase.
  • the insulating film 110 formed over the oxide semiconductor film 108 has excess oxygen, it is possible to selectively supply excess oxygen only to the channel region 108i.
  • the carrier density in the source region 108s and the drain region 108d is selectively increased, so that the source region 108s and the drain region 108d It can suppress that resistance becomes high.
  • the source region 108s and the drain region 108d included in the oxide semiconductor film 108 preferably each include an element that forms oxygen vacancies or an element that combines with oxygen vacancies.
  • an element that forms oxygen vacancies or an element that combines with oxygen vacancies typically, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, a rare gas, or the like can be given.
  • rare gas elements include helium, neon, argon, krypton, and xenon.
  • the oxygen vacancies diffuse into the source region 108 s and the drain region 108 d.
  • the element that forms oxygen vacancies is added to the source region 108s and the drain region 108d by impurity addition treatment.
  • the bond between the metal element and oxygen in the oxide semiconductor film is cut, and oxygen vacancies are formed.
  • oxygen bonded to the metal element in the oxide semiconductor film is bonded to the impurity element, so that oxygen is released from the metal element and oxygen vacancies are formed. The As a result, the carrier density in the oxide semiconductor film is increased and the conductivity is increased.
  • FIGS. 16A, 16B, and 16C Details of the components of the semiconductor device shown in FIGS. 16A, 16B, and 16C will be described.
  • a material having heat resistance high enough to withstand heat treatment in a manufacturing process can be used.
  • alkali-free glass soda-lime glass, alkali glass, crystal glass, quartz, sapphire, or the like can be used.
  • an inorganic insulating film may be used. Examples of the inorganic insulating film include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film.
  • the non-alkali glass may have a thickness of 0.2 mm to 0.7 mm, for example.
  • the above-described thickness may be obtained by polishing alkali-free glass.
  • the sixth generation (1500 mm ⁇ 1850 mm), the seventh generation (1870 mm ⁇ 2200 mm), the eighth generation (2200 mm ⁇ 2400 mm), the ninth generation (2400 mm ⁇ 2800 mm), the tenth generation (2950 mm ⁇ 3400 mm)
  • a glass substrate having a large area such as) can be used.
  • a large display device can be manufactured.
  • a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like may be used.
  • an inorganic material such as a metal may be used as the substrate 102.
  • inorganic materials such as metals include stainless steel and aluminum.
  • an organic material such as resin, resin film, or plastic may be used as the substrate 102.
  • the resin film include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, polyurethane, acrylic resin, epoxy resin, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES). Or a resin having a siloxane bond.
  • a composite material in which an inorganic material and an organic material are combined may be used as the substrate 102.
  • a composite material a material obtained by bonding a metal plate or a thin glass plate and a resin film, a fibrous metal, a particulate metal, a fibrous glass, or a particulate glass is dispersed in a resin film Or a material obtained by dispersing a fibrous resin or a particulate resin in an inorganic material.
  • the substrate 102 may be any substrate as long as it can support at least a film or a layer formed thereon or below, and may be any one or more of an insulating film, a semiconductor film, and a conductive film.
  • the insulating film 104 can be formed using a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like as appropriate.
  • a sputtering method for example, an oxide insulating film or a nitride insulating film can be formed as a single layer or a stacked layer.
  • at least a region in contact with the oxide semiconductor film 108 in the insulating film 104 is preferably formed using an oxide insulating film.
  • oxygen contained in the insulating film 104 can be transferred to the oxide semiconductor film 108 by heat treatment.
  • the thickness of the insulating film 104 can be 50 nm or more, 100 nm or more and 3000 nm or less, or 200 nm or more and 1000 nm or less.
  • the insulating film 104 for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga—Zn oxide, or the like may be used, and the insulating film 104 can be provided as a single layer or a stacked layer.
  • a stacked structure of a silicon nitride film and a silicon oxynitride film is used as the insulating film 104.
  • oxygen can be efficiently introduced into the oxide semiconductor film 108 by using the insulating film 104 as a stacked structure and using a silicon nitride film on the lower layer side and a silicon oxynitride film on the upper layer side.
  • oxide semiconductor film As the oxide semiconductor film 108, the metal oxide film described in Embodiment 1 can be used.
  • the oxide semiconductor film 108 is preferably formed by a sputtering method because the film density can be increased.
  • a rare gas typically argon
  • oxygen or a mixed gas of a rare gas and oxygen is used as the sputtering gas as appropriate.
  • oxygen gas or argon gas used as a sputtering gas has a dew point of ⁇ 60 ° C. or lower, preferably ⁇ 100 ° C. or lower, so that moisture or the like is taken into the oxide semiconductor film 108 by using a highly purified gas. It can be prevented as much as possible.
  • an adsorption-type vacuum exhaust pump such as a cryopump is used to remove as much impurities as possible from the oxide semiconductor film 108 in the chamber of the sputtering apparatus. Is preferably exhausted to a high vacuum (from about 5 ⁇ 10 ⁇ 7 Pa to about 1 ⁇ 10 ⁇ 4 Pa).
  • the partial pressure of gas molecules corresponding to H 2 O in the chamber is 1 ⁇ 10 ⁇ 4 Pa or less, preferably 5 ⁇ 10 ⁇ 5. It is preferable to set it to Pa or less.
  • the insulating film 110 functions as a gate insulating film of the transistor 100.
  • the insulating film 110 has a function of supplying oxygen to the oxide semiconductor film 108, particularly the channel region 108i.
  • the insulating film 110 can be formed using a single layer or a stacked layer of an oxide insulating film or a nitride insulating film.
  • a region in the insulating film 110 which is in contact with the oxide semiconductor film 108 is preferably formed using at least the oxide insulating film.
  • the insulating film 110 for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like may be used.
  • the thickness of the insulating film 110 can be 5 nm to 400 nm, 5 nm to 300 nm, or 10 nm to 250 nm.
  • the insulating film 110 preferably has few defects. Typically, it is preferable that the number of signals observed by an electron spin resonance (ESR) be small.
  • the signal described above includes the E ′ center where the g value is observed at 2.001.
  • the E ′ center is caused by silicon dangling bonds.
  • As the insulating film 110 a silicon oxide film or a silicon oxynitride film whose spin density due to the E ′ center is 3 ⁇ 10 17 spins / cm 3 or less, preferably 5 ⁇ 10 6 spins / cm 3 or less is used. Good.
  • a signal due to nitrogen dioxide (NO 2 ) may be observed in addition to the above signal.
  • the signal is split into three signals by N nuclear spins, each having a g value of 2.037 or more and 2.039 or less (referred to as the first signal), and a g value of 2.001 or more and 2.003.
  • the g value is observed below (referred to as the second signal) and from 1.964 to 1.966 (referred to as the third signal).
  • the insulating film 110 an insulating film whose spin density due to nitrogen dioxide (NO 2 ) is 1 ⁇ 10 17 spins / cm 3 or more and less than 1 ⁇ 10 18 spins / cm 3 is preferably used.
  • NO 2 nitrogen dioxide
  • nitrogen oxide (NO x ) containing nitrogen dioxide (NO 2 ) forms a level in the insulating film 110.
  • the level is located in the energy gap of the oxide semiconductor film 108. Therefore, when nitrogen oxide (NOx) diffuses to the interface between the insulating film 110 and the oxide semiconductor film 108, the level may trap electrons on the insulating film 110 side. As a result, trapped electrons remain in the vicinity of the interface between the insulating film 110 and the oxide semiconductor film 108, so that the threshold voltage of the transistor is shifted in the positive direction. Therefore, when the insulating film 110 is a film with a low content of nitrogen oxides, the threshold voltage shift of the transistor can be reduced.
  • a silicon oxynitride film can be used as the insulating film that emits less nitrogen oxide (NO x ).
  • the silicon oxynitride film is a film in which the amount of ammonia released is larger than the amount of nitrogen oxide (NO x ) released in a temperature programmed desorption gas analysis (TDS).
  • TDS temperature programmed desorption gas analysis
  • the discharge amount is 1 ⁇ 10 18 / cm 3 or more and 5 ⁇ 10 19 / cm 3 or less. Note that the amount of ammonia released is the total amount when the temperature of the heat treatment in TDS is in the range of 50 ° C. to 650 ° C. or 50 ° C. to 550 ° C.
  • nitrogen oxide (NO x ) reacts with ammonia and oxygen in the heat treatment, nitrogen oxide (NO x ) is reduced by using an insulating film that releases a large amount of ammonia.
  • the nitrogen concentration in the film is preferably 6 ⁇ 10 20 atoms / cm 3 or less.
  • hafnium silicate HfSiO x
  • hafnium silicate added with nitrogen HfSi x O y N z
  • hafnium aluminate added with nitrogen HfAl x O y N z
  • hafnium oxide or the like
  • High-k materials may be used. By using the high-k material, gate leakage of the transistor can be reduced.
  • the insulating film 116 includes nitrogen or hydrogen.
  • the insulating film 116 may contain fluorine.
  • An example of the insulating film 116 is a nitride insulating film.
  • the nitride insulating film can be formed using silicon nitride, silicon nitride oxide, silicon oxynitride, silicon nitride fluoride, silicon fluoronitride, or the like.
  • the concentration of hydrogen contained in the insulating film 116 is preferably 1 ⁇ 10 22 atoms / cm 3 or more.
  • the insulating film 116 is in contact with the source region 108s and the drain region 108d of the oxide semiconductor film 108. Therefore, the impurity (nitrogen or hydrogen) concentration in the source region 108s and the drain region 108d in contact with the insulating film 116 is increased, and the carrier density of the source region 108s and the drain region 108d can be increased.
  • an oxide insulating film can be used.
  • a stacked film of an oxide insulating film and a nitride insulating film can be used.
  • the insulating film 118 for example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, gallium oxide, Ga—Zn oxide, or the like may be used.
  • the insulating film 118 is preferably a film that functions as a barrier film of hydrogen, water, etc. from the outside.
  • the thickness of the insulating film 118 can be greater than or equal to 30 nm and less than or equal to 500 nm, or greater than or equal to 100 nm and less than or equal to 400 nm.
  • the conductive films 112, 120a, and 120b can be formed by a sputtering method, a vacuum evaporation method, a pulse laser deposition (PLD) method, a thermal CVD method, or the like.
  • a conductive metal film, a conductive film having a function of reflecting visible light, or a conductive film having a function of transmitting visible light may be used.
  • a material containing a metal element selected from aluminum, gold, platinum, silver, copper, chromium, tantalum, titanium, molybdenum, tungsten, nickel, iron, cobalt, palladium, or manganese is used. It can. Alternatively, an alloy containing the above metal element may be used.
  • the conductive metal film described above includes a two-layer structure in which a copper film is stacked on a titanium film, a two-layer structure in which a copper film is stacked on a titanium nitride film, and a copper film on a tantalum nitride film.
  • a two-layer structure to be laminated, a three-layer structure in which a copper film is laminated on a titanium film, and a titanium film is further formed thereon may be used.
  • examples of the conductive film containing a copper element include an alloy film containing copper and manganese. The alloy film is preferable because it can be processed by a wet etching method.
  • a tantalum nitride film is preferably used as the conductive films 112, 120a, and 120b.
  • the tantalum nitride film has conductivity and high barrier properties against copper or hydrogen.
  • the tantalum nitride film can be most preferably used as a metal film in contact with the oxide semiconductor film 108 or a metal film in the vicinity of the oxide semiconductor film 108 because it emits less hydrogen from itself.
  • a conductive polymer or a conductive polymer may be used as the conductive film having the above-described conductivity.
  • the conductive film having a function of reflecting visible light a material containing a metal element selected from gold, silver, copper, or palladium can be used.
  • a conductive film containing a silver element because the reflectance in visible light can be increased.
  • a material containing an element selected from indium, tin, zinc, gallium, or silicon can be used as the conductive film having a function of transmitting visible light.
  • a material containing an element selected from indium, tin, zinc, gallium, or silicon can be used.
  • a film containing graphene or graphite may be used as the conductive film having a function of transmitting visible light.
  • a film containing graphene a film containing graphene can be formed by forming a film containing graphene oxide and reducing the film containing graphene oxide. Examples of the reduction method include a method of applying heat and a method of using a reducing agent.
  • the conductive films 112, 120a, and 120b can be formed by an electroless plating method.
  • a material that can be formed by the electroless plating method for example, any one or more selected from Cu, Ni, Al, Au, Sn, Co, Ag, and Pd can be used.
  • the use of Cu or Ag is preferable because the resistance of the conductive film can be lowered.
  • a diffusion prevention film may be formed under the conductive film so that constituent elements of the conductive film do not diffuse outside.
  • a seed layer capable of growing a conductive film may be formed between the diffusion prevention film and the conductive film.
  • the diffusion preventing film can be formed using, for example, a sputtering method.
  • a tantalum nitride film or a titanium nitride film can be used.
  • the seed layer can be formed by an electroless plating method.
  • a material similar to the material of the conductive film that can be formed by an electroless plating method can be used.
  • an oxide semiconductor typified by an In—Ga—Zn oxide may be used as the conductive film 112.
  • the oxide semiconductor has high carrier density when nitrogen or hydrogen is supplied from the insulating film 116.
  • the oxide semiconductor functions as an oxide conductor (OC: Oxide Conductor). Therefore, the oxide semiconductor can be used as a gate electrode.
  • examples of the conductive film 112 include a single layer structure of an oxide conductor (OC), a single layer structure of a metal film, or a stacked structure of an oxide conductor (OC) and a metal film.
  • the conductive film 112 is formed below the conductive film 112 in the case where a single-layer structure of a light-blocking metal film or a stacked structure of an oxide conductor (OC) and a light-blocking metal film is used. This is preferable because the channel region 108i can be shielded from light.
  • the metal film is formed over the oxide semiconductor or the oxide conductor (OC).
  • the constituent elements in the metal film diffuse to the oxide semiconductor or oxide conductor (OC) side and the resistance is reduced. The resistance is reduced by damage (for example, sputtering damage) or oxygen in the oxide semiconductor or the oxide conductor (OC) is diffused in the metal film, so that oxygen deficiency is formed and the resistance is reduced.
  • the thickness of the conductive films 112, 120a, and 120b can be 30 nm to 500 nm, or 100 nm to 400 nm.
  • FIG. 17A is a top view of the transistor 100A
  • FIG. 17B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 17A
  • FIG. 17C is FIG. It is sectional drawing between dashed-dotted lines Y1-Y2.
  • a transistor 100A illustrated in FIGS. 17A to 17C includes a conductive film 106 over a substrate 102, an insulating film 104 over the conductive film 106, an oxide semiconductor film 108 over the insulating film 104, and an oxide.
  • the insulating film 110 over the semiconductor film 108, the conductive film 112 over the insulating film 110, the insulating film 104, the oxide semiconductor film 108, and the insulating film 116 over the conductive film 112 are included.
  • the oxide semiconductor film 108 includes a channel region 108 i overlapping with the conductive film 112, a source region 108 s in contact with the insulating film 116, and a drain region 108 d in contact with the insulating film 116.
  • the transistor 100A includes a conductive film 106 and an opening 143 in addition to the structure of the transistor 100 described above.
  • the opening 143 is provided in the insulating films 104 and 110.
  • the conductive film 106 is electrically connected to the conductive film 112 through the opening 143. Therefore, the same potential is applied to the conductive film 106 and the conductive film 112. Note that different potentials may be applied to the conductive film 106 and the conductive film 112 without providing the opening 143.
  • the conductive film 106 may be used as a light-blocking film without providing the opening 143. For example, when the conductive film 106 is formed using a light-blocking material, light from below irradiated to the channel region 108 i can be suppressed.
  • the conductive film 106 functions as a first gate electrode (also referred to as a bottom gate electrode), and the conductive film 112 is also referred to as a second gate electrode (also referred to as a top gate electrode). ).
  • the insulating film 104 has a function as a first gate insulating film, and the insulating film 110 has a function as a second gate insulating film.
  • the conductive film 106 As the conductive film 106, the same material as the conductive films 112, 120a, and 120b described above can be used. In particular, the conductive film 106 is preferably formed using a material containing copper because the resistance can be lowered.
  • the conductive film 106 has a stacked structure in which a copper film is provided over a titanium nitride film, a tantalum nitride film, or a tungsten film, and the conductive films 120a and 120b are provided with a copper film over the titanium nitride film, the tantalum nitride film, or the tungsten film. A laminated structure is preferable.
  • the transistor 100A for one or both of the pixel transistor and the driving transistor of the display device, parasitic capacitance generated between the conductive film 106 and the conductive film 120a, and the conductive film 106 and the conductive film 120b The parasitic capacitance generated between them can be reduced. Therefore, the conductive film 106, the conductive film 120a, and the conductive film 120b are used not only as the first gate electrode, the source electrode, and the drain electrode of the transistor 100A, but also for power supply wiring and signal supply of the display device. It can also be used for wiring or wiring for connection.
  • the transistor 100A illustrated in FIGS. 17A to 17C has a structure including conductive films functioning as gate electrodes above and below the oxide semiconductor film 108.
  • the semiconductor device of one embodiment of the present invention may include a plurality of gate electrodes.
  • the oxide semiconductor film 108 is opposite to the conductive film 106 functioning as the first gate electrode and the conductive film 112 functioning as the second gate electrode, respectively. And is sandwiched between conductive films functioning as two gate electrodes.
  • the length of the conductive film 112 in the channel width direction is longer than the length of the oxide semiconductor film 108 in the channel width direction, and the entire length of the oxide semiconductor film 108 in the channel width direction is conductive with the insulating film 110 interposed therebetween.
  • the film 112 is covered. Further, since the conductive film 112 and the conductive film 106 are connected to each other in the insulating film 104 and the opening 143 provided in the insulating film 110, one of the side surfaces in the channel width direction of the oxide semiconductor film 108 is the insulating film 110. Is opposed to the conductive film 112.
  • the conductive film 106 and the conductive film 112 are connected to each other through the insulating film 104 and the opening 143 provided in the insulating film 110, and the insulating film 104 and the insulating film 110 are interposed between them.
  • the oxide semiconductor film 108 is surrounded by the structure.
  • the oxide semiconductor film 108 included in the transistor 100A is electrically connected to the conductive film 106 functioning as the first gate electrode and the conductive film 112 functioning as the second gate electrode. Can be surrounded.
  • a device structure of a transistor that electrically surrounds the oxide semiconductor film 108 in which a channel region is formed by an electric field of the first gate electrode and the second gate electrode is a surround channel (S-channel) structure. Can be called.
  • the transistor 100A Since the transistor 100A has an S-channel structure, an electric field for inducing a channel by the conductive film 106 or the conductive film 112 can be effectively applied to the oxide semiconductor film 108; thus, the current driving capability of the transistor 100A Thus, high on-current characteristics can be obtained. Further, since the on-state current can be increased, the transistor 100A can be miniaturized. In addition, since the transistor 100A has a structure surrounded by the conductive film 106 and the conductive film 112, the mechanical strength of the transistor 100A can be increased.
  • an opening different from the opening 143 may be formed on the side where the opening 143 of the oxide semiconductor film 108 is not formed in the channel width direction of the transistor 100A.
  • the signal A is supplied to one gate electrode and the fixed potential is supplied to the other gate electrode.
  • Vb may be given.
  • the signal A may be given to one gate electrode, and the signal B may be given to the other gate electrode.
  • One gate electrode may be given a fixed potential Va, and the other gate electrode may be given a fixed potential Vb.
  • the signal A is a signal for controlling, for example, a conduction state or a non-conduction state.
  • the signal A may be a digital signal that takes two kinds of potentials, that is, the potential V1 or the potential V2 (V1> V2).
  • the potential V1 can be a high power supply potential and the potential V2 can be a low power supply potential.
  • the signal A may be an analog signal.
  • the fixed potential Vb is a potential for controlling the threshold voltage VthA of the transistor, for example.
  • the fixed potential Vb may be the potential V1 or the potential V2. In this case, it is preferable that a potential generating circuit for generating the fixed potential Vb does not need to be provided separately.
  • the fixed potential Vb may be a potential different from the potential V1 or the potential V2.
  • the threshold voltage VthA can be increased by lowering the fixed potential Vb. As a result, the drain current when the gate-source voltage Vgs is 0 V can be reduced, and the leakage current of a circuit including a transistor can be reduced in some cases.
  • the fixed potential Vb may be set lower than the low power supply potential.
  • the threshold voltage VthA can be lowered by increasing the fixed potential Vb.
  • the drain current when the gate-source voltage Vgs is at a high power supply potential can be improved, and the operation speed of a circuit including a transistor can be improved in some cases.
  • the fixed potential Vb may be higher than the low power supply potential.
  • the signal B is a signal for controlling a conduction state or a non-conduction state, for example.
  • the signal B may be a digital signal that takes two kinds of potentials, that is, the potential V3 or the potential V4 (V3> V4).
  • the potential V3 can be a high power supply potential and the potential V4 can be a low power supply potential.
  • the signal B may be an analog signal.
  • the signal B may be a signal having the same digital value as the signal A.
  • the on-state current of the transistor can be improved and the operation speed of the circuit including the transistor can be improved in some cases.
  • the potential V1 and the potential V2 in the signal A may be different from the potential V3 and the potential V4 in the signal B.
  • the potential amplitude (V3 to V4) of the signal B is It may be larger than the potential amplitude (V1-V2). By doing so, the influence of the signal A and the influence of the signal B on the conduction state or non-conduction state of the transistor may be approximately the same.
  • the signal B may be a signal having a digital value different from that of the signal A.
  • the transistor can be controlled separately by the signal A and the signal B, and a higher function may be realized.
  • the transistor is an n-channel transistor
  • the transistor A is in a conductive state only when the signal A is the potential V1 and the signal B is the potential V3, or the signal A is the potential V2 and the signal B is In the case where a non-conducting state is obtained only when the potential is V4, functions such as a NAND circuit and a NOR circuit may be realized with one transistor.
  • the signal B may be a signal for controlling the threshold voltage VthA.
  • the signal B may be a signal having a different potential between a period in which a circuit including a transistor is operating and a period in which the circuit is not operating.
  • the signal B may be a signal having a different potential according to the operation mode of the circuit. In this case, the potential of the signal B may not be switched as frequently as the signal A.
  • the signal B is an analog signal having the same potential as the signal A, an analog signal obtained by multiplying the potential of the signal A by a constant, or the potential of the signal A is added or subtracted by a constant.
  • An analog signal or the like may be used.
  • the on-state current of the transistor can be improved and the operation speed of the circuit including the transistor can be improved in some cases.
  • the signal B may be an analog signal different from the signal A. In this case, the transistor can be controlled separately by the signal A and the signal B, and a higher function may be realized.
  • the signal A may be a digital signal and the signal B may be an analog signal.
  • the signal A may be an analog signal and the signal B may be a digital signal.
  • the transistor When a fixed potential is applied to both gate electrodes of a transistor, the transistor may function as an element equivalent to a resistance element.
  • the effective resistance of the transistor can be decreased (increased) by increasing (decreasing) the fixed potential Va or the fixed potential Vb in some cases.
  • an effective resistance lower (higher) than that obtained by a transistor having only one gate may be obtained.
  • FIGS. 18A and 18B are cross-sectional views of the transistor 100B.
  • a top view of the transistor 100B is similar to that of the transistor 100A illustrated in FIG. 17A; therefore, description thereof is omitted here.
  • 18A and 18B includes the insulating film 122 over the conductive films 120a and 120b and the insulating film 118.
  • the transistor 100B illustrated in FIGS. Other configurations are similar to those of the transistor 100A, and have the same effects.
  • the insulating film 122 has a function of flattening unevenness caused by a transistor or the like.
  • the insulating film 122 only needs to be insulative and is formed using an inorganic material or an organic material.
  • the inorganic material include a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, and an aluminum nitride film.
  • photosensitive resin materials such as an acrylic resin or a polyimide resin, are mentioned, for example.
  • FIGS. 19A and 19B are cross-sectional views of the transistor 100C
  • FIGS. 20A and 20B are cross-sectional views of the transistor 100D
  • FIGS. 21A and 21B are cross-sectional views of the transistor 100E.
  • FIG. Note that top views of the transistor 100C, the transistor 100D, and the transistor 100E are the same as those of the transistor 100A illustrated in FIG. 17A, and thus description thereof is omitted here.
  • 19A and 19B is different from the transistor 100A in the stacked structure of the conductive film 112, the shape of the conductive film 112, and the shape of the insulating film 110.
  • the conductive film 112 of the transistor 100C includes a conductive film 112_1 over the insulating film 110 and a conductive film 112_2 over the conductive film 112_1.
  • excess oxide can be added to the insulating film 110 by using an oxide conductive film as the conductive film 112_1.
  • the oxide conductive film can be formed in an atmosphere containing oxygen gas by a sputtering method.
  • an oxide having indium and tin an oxide having tungsten and indium, an oxide having tungsten, indium, and zinc, an oxide having titanium and indium
  • examples thereof include an oxide having titanium, indium, and tin, an oxide having indium and zinc, an oxide having silicon, indium, and tin, and an oxide having indium, gallium, and zinc.
  • the conductive film 112_2 and the conductive film 106 are connected to each other in the opening 143.
  • the opening 143 is formed, after the conductive film to be the conductive film 112_1 is formed, the opening 143 is formed, whereby the shape illustrated in FIG. 19B can be obtained.
  • the connection resistance between the conductive film 112 and the conductive film 106 can be reduced by connecting the conductive film 112_2 and the conductive film 106.
  • the conductive film 112 and the insulating film 110 of the transistor 100C are tapered. More specifically, the lower end portion of the conductive film 112 is formed outside the upper end portion of the conductive film 112. The lower end portion of the insulating film 110 is formed outside the upper end portion of the insulating film 110. Further, the lower end portion of the conductive film 112 is formed at substantially the same position as the upper end portion of the insulating film 110.
  • the conductive film 112 and the insulating film 110 of the transistor 100C have a tapered shape because the coverage of the insulating film 116 can be increased as compared with the case where the conductive film 112 and the insulating film 110 of the transistor 100A are rectangular. is there.
  • 20A and 20B is different from the transistor 100A in the stacked structure of the conductive film 112, the shape of the conductive film 112, and the shape of the insulating film 110.
  • the conductive film 112 of the transistor 100D includes a conductive film 112_1 over the insulating film 110 and a conductive film 112_2 over the conductive film 112_1.
  • the lower end portion of the conductive film 112_1 is formed outside the upper end portion of the conductive film 112_2.
  • the conductive film 112_1, the conductive film 112_2, and the insulating film 110 are processed with the same mask, the conductive film 112_2 is processed with a wet etching method, and the conductive film 112_1 and the insulating film 110 are processed with a dry etching method.
  • the above structure can be obtained.
  • the region 108f may be formed in the oxide semiconductor film 108 in some cases.
  • the region 108f is formed between the channel region 108i and the source region 108s, and between the channel region 108i and the drain region 108d.
  • the region 108f functions as either a high resistance region or a low resistance region.
  • the high resistance region is a region which has a resistance equivalent to that of the channel region 108 i and does not overlap with the conductive film 112 functioning as a gate electrode.
  • the region 108f functions as a so-called offset region.
  • the region 108f may be 1 ⁇ m or less in the channel length (L) direction in order to suppress a decrease in on-state current of the transistor 100D.
  • the low resistance region is a region having a resistance lower than that of the channel region 108i and higher than that of the source region 108s and the drain region 108d.
  • the region 108f functions as a so-called LDD (Lightly Doped Drain) region.
  • LDD Lightly Doped Drain
  • the region 108f is an LDD region
  • one or more of nitrogen, hydrogen, and fluorine is supplied from the insulating film 116 to the region 108f, or the conductive film 112_1 is used with the insulating film 110 and the conductive film 112_1 as a mask.
  • the impurity can be formed by being added to the oxide semiconductor film 108 through the conductive film 112_1 and the insulating film 110.
  • the conductive film 112_2 and the conductive film 106 are connected to each other in the opening 143.
  • 21A and 21B is different from the transistor 100A in the stacked structure of the conductive film 112, the shape of the conductive film 112, and the shape of the insulating film 110.
  • the conductive film 112 of the transistor 100E includes a conductive film 112_1 over the insulating film 110 and a conductive film 112_2 over the conductive film 112_1.
  • the lower end portion of the conductive film 112_1 is formed outside the lower end portion of the conductive film 112_2.
  • the lower end portion of the insulating film 110 is formed outside the lower end portion of the conductive film 112_1.
  • the conductive film 112_1, the conductive film 112_, and the insulating film 110 are processed using the same mask
  • the conductive film 112_2 and the conductive film 112_1 are processed using a wet etching method
  • the insulating film 110 is processed using a dry etching method.
  • the transistor 100E may have a region 108f formed in the oxide semiconductor film 108.
  • the region 108f is formed between the channel region 108i and the source region 108s, and between the channel region 108i and the drain region 108d.
  • the conductive film 112_2 and the conductive film 106 are connected to each other in the opening 143.
  • FIGS. 22A and 22B are cross-sectional views of the transistor 100F
  • FIGS. 23A and 23B are cross-sectional views of the transistor 100G
  • FIGS. 24A and 24B are cross-sectional views of the transistor 100H
  • 25A and 25B are cross-sectional views of the transistor 100J
  • FIGS. 26A and 26B are cross-sectional views of the transistor 100K. Note that the top view of the transistor 100F, the transistor 100G, the transistor 100H, the transistor 100J, and the transistor 100K is similar to the transistor 100A illustrated in FIG. 17A; therefore, description thereof is omitted here.
  • the transistor 100F, the transistor 100G, the transistor 100H, the transistor 100J, and the transistor 100K are different from each other in the structure of the transistor 100A and the oxide semiconductor film 108 described above.
  • Other configurations are similar to those of the transistor 100A described above, and have the same effects.
  • 22A and 22B includes an oxide semiconductor film 108_1 over the insulating film 104, an oxide semiconductor film 108_2 over the oxide semiconductor film 108_1, and an oxide semiconductor.
  • the channel region 108i, the source region 108s, and the drain region 108d each have a three-layer structure of the oxide semiconductor film 108_1, the oxide semiconductor film 108_2, and the oxide semiconductor film 108_3.
  • the oxide semiconductor film 108 included in the transistor 100G includes an oxide semiconductor film 108_2 over the insulating film 104 and an oxide semiconductor film 108_3 over the oxide semiconductor film 108_2.
  • the channel region 108i, the source region 108s, and the drain region 108d each have a two-layer structure of an oxide semiconductor film 108_2 and an oxide semiconductor film 108_3.
  • the oxide semiconductor film 108 included in the transistor 100H includes an oxide semiconductor film 108_1 over the insulating film 104 and an oxide semiconductor film 108_2 over the oxide semiconductor film 108_1.
  • the channel region 108i, the source region 108s, and the drain region 108d each have a two-layer structure of the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2.
  • An oxide semiconductor film 108 included in the transistor 100J illustrated in FIGS. 25A and 25B includes an oxide semiconductor film 108_1 over the insulating film 104, an oxide semiconductor film 108_2 over the oxide semiconductor film 108_1, and an oxide semiconductor.
  • the channel region 108i has a three-layer structure of the oxide semiconductor film 108_1, the oxide semiconductor film 108_2, and the oxide semiconductor film 108_3.
  • the source region 108s and the drain region 108d each have an oxide semiconductor film.
  • the oxide semiconductor film 108 included in the transistor 100K illustrated in FIGS. 26A and 26B includes an oxide semiconductor film 108_2 over the insulating film 104 and an oxide semiconductor film 108_3 over the oxide semiconductor film 108_2.
  • the channel region 108i has a two-layer structure of an oxide semiconductor film 108_2 and an oxide semiconductor film 108_3, and the source region 108s and the drain region 108d have a single layer structure of the oxide semiconductor film 108_2, respectively. is there. Note that in the cross section of the transistor 100K in the channel width (W) direction, the oxide semiconductor film 108_3 covers the side surface of the oxide semiconductor film 108_2.
  • the channel region 108i in the channel width (W) direction or in the vicinity thereof defects (for example, oxygen vacancies) are likely to be formed due to damage in processing, or contamination due to adhesion of impurities. Therefore, even when the channel region 108i is substantially intrinsic, application of stress such as an electric field activates the side surface of the channel region 108i in the channel width (W) direction or the vicinity thereof, thereby reducing low resistance (n Type) area.
  • stress such as an electric field activates the side surface of the channel region 108i in the channel width (W) direction or the vicinity thereof, thereby reducing low resistance (n Type) area.
  • the side surface in the channel width (W) direction of the channel region 108i or the vicinity thereof is an n-type region, a parasitic channel may be formed because the n-type region serves as a carrier path.
  • the channel region 108i has a stacked structure, and the side surface in the channel width (W) direction of the channel region 108i is covered with one layer of the stacked structure.
  • defects on the side surface of the channel region 108i or the vicinity thereof can be suppressed, or adhesion of impurities to the side surface of the channel region 108i or the vicinity thereof can be reduced.
  • FIG. 27A illustrates an example of a band structure in a film thickness direction of a stacked structure including the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3, and the insulating film 110.
  • FIG. 27B illustrates an example of a band structure in the film thickness direction of a stacked structure including the insulating film 104, the oxide semiconductor films 108_2 and 108_3, and the insulating film 110.
  • FIG. 27C illustrates an example of a band structure in the film thickness direction of a stacked structure including the insulating film 104, the oxide semiconductor films 108_1 and 108_2, and the insulating film 110.
  • the band structure indicates the energy level (Ec) of the lower end of the conduction band of the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3, and the insulating film 110 for easy understanding.
  • FIG. 10 is a band diagram of a structure using an oxide semiconductor film.
  • FIG. 10 is a band diagram of a structure using an oxide semiconductor film formed using an oxide semiconductor film.
  • the energy level at the lower end of the conduction band changes gently.
  • the energy level at the lower end of the conduction band in the oxide semiconductor films 108_1 and 108_2 changes gently. In other words, it can be said that it is continuously changed or continuously joined.
  • a trap center or a recombination center is formed at the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2 or the interface between the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3. It is assumed that there is no impurity that forms such a defect level.
  • each film is continuously formed without being exposed to the air using a multi-chamber film formation apparatus (sputtering apparatus) including a load lock chamber. It is necessary to laminate them.
  • sputtering apparatus sputtering apparatus
  • the oxide semiconductor film 108_2 becomes a well, and a channel region is formed in the oxide semiconductor film 108_2 in the transistor including the above stacked structure.
  • the trap level can be further away from the oxide semiconductor film 108_2.
  • the defect level may be farther from the vacuum level than the energy level (Ec) at the lower end of the conduction band of the oxide semiconductor film 108_2 functioning as a channel region, and electrons are likely to accumulate in the defect level. . Accumulation of electrons at the defect level results in a negative fixed charge, and the threshold voltage of the transistor shifts in the positive direction. Therefore, it is preferable that the defect level be closer to the vacuum level than the energy level (Ec) at the lower end of the conduction band of the oxide semiconductor film 108_2. Thus, electrons are less likely to accumulate at the defect level, the on-state current of the transistor can be increased, and field effect mobility can be increased.
  • the oxide semiconductor films 108_1 and 108_3 each have an energy level at the lower end of the conduction band that is closer to the vacuum level than the oxide semiconductor film 108_2. Typically, the energy level at the lower end of the conduction band of the oxide semiconductor film 108_2. And the energy level at the lower end of the conduction band of the oxide semiconductor films 108_1 and 108_3 is 0.15 eV or more, 0.5 eV or more, 2 eV or less, or 1 eV or less.
  • the difference between the electron affinity of the oxide semiconductor films 108_1 and 108_3 and the electron affinity of the oxide semiconductor film 108_2 is 0.15 eV or more, 0.5 eV or more, 2 eV or less, or 1 eV or less.
  • the oxide semiconductor film 108_2 becomes a main current path.
  • the oxide semiconductor film 108_2 functions as a channel region
  • the oxide semiconductor films 108_1 and 108_3 function as oxide insulating films.
  • the oxide semiconductor films 108_1 and 108_3 are preferably formed using one or more metal elements included in the oxide semiconductor film 108_2 in which a channel region is formed.
  • the oxide semiconductor films 108_1 and 108_3 are formed using a material with sufficiently low conductivity in order to prevent the oxide semiconductor films 108_1 and 108_3 from functioning as part of the channel region. Therefore, the oxide semiconductor films 108_1 and 108_3 can also be referred to as oxide insulating films because of their physical properties and / or functions.
  • the electron affinity difference between the vacuum level and the energy level at the bottom of the conduction band
  • the energy level at the bottom of the conduction band is an oxide.
  • a material having a difference (band offset) from the lower energy level of the conduction band of the semiconductor film 108_2 is used.
  • the energy level at the lower end of the conduction band of the oxide semiconductor films 108_1 and 108_3 is determined so that the conduction level of the oxide semiconductor film 108_2 is reduced. It is preferable to use a material closer to the vacuum level than the energy level at the lower end of the band.
  • the difference between the energy level at the bottom of the conduction band of the oxide semiconductor film 108_2 and the energy level at the bottom of the conduction bands of the oxide semiconductor films 108_1 and 108_3 is 0.2 eV or more, preferably 0.5 eV or more. It is preferable.
  • the oxide semiconductor films 108_1 and 108_3 do not include a spinel crystal structure.
  • the constituent elements of the conductive films 120a and 120b enter the oxide semiconductor film 108_2 at the interface between the spinel crystal structure and another region. May diffuse.
  • the oxide semiconductor films 108_1 and 108_3 be a CAAC-OS to be described later because the blocking properties of constituent elements of the conductive films 120a and 120b, for example, a copper element are increased.
  • the configuration using the film is exemplified, the configuration is not limited thereto.
  • the oxide semiconductor films 108_1 and 108_3 are preferable because the difference from the energy level at the lower end of the conduction band can be 0.6 eV or more.
  • FIG. 28A is a top view of the transistor 300A
  • FIG. 28B corresponds to a cross-sectional view of a cross section taken along dashed-dotted line X1-X2 in FIG. 28A.
  • some components such as an insulating film functioning as a gate insulating film
  • the direction of the alternate long and short dash line X1-X2 may be referred to as a channel length direction, and the direction of the alternate long and short dash line Y1-Y2 may be referred to as a channel width direction. Note that in the top view of the transistor, some components may be omitted in the following drawings as in FIG. 28A.
  • a transistor 300A illustrated in FIG. 28 includes a conductive film 304 over a substrate 302, an insulating film 306 over the substrate 302 and the conductive film 304, an insulating film 307 over the insulating film 306, and an oxide semiconductor film 308 over the insulating film 307.
  • a conductive film 312 a over the oxide semiconductor film 308 and a conductive film 312 b over the oxide semiconductor film 308.
  • insulating films 314 and 316 and an insulating film 318 are provided over the transistor 300A, more specifically, over the conductive films 312a and 312b and the oxide semiconductor film 308.
  • the insulating films 306 and 307 function as gate insulating films of the transistor 300A, and the insulating films 314, 316, and 318 function as protective insulating films of the transistor 300A.
  • the conductive film 304 functions as a gate electrode
  • the conductive film 312a functions as a source electrode
  • the conductive film 312b functions as a drain electrode.
  • the insulating films 306 and 307 may be referred to as a first insulating film, the insulating films 314 and 316 as a second insulating film, and the insulating film 318 as a third insulating film, respectively. is there.
  • the transistor 300A shown in FIG. 28 has a channel etch type transistor structure.
  • the oxide semiconductor film of one embodiment of the present invention can be favorably used for a channel-etched transistor.
  • FIG. 29A is a top view of the transistor 300B, and FIG. 29B corresponds to a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 29A. Corresponds to a cross-sectional view of a cut surface taken along the alternate long and short dash line Y1-Y2 shown in FIG.
  • a transistor 300B illustrated in FIG. 29 includes a conductive film 304 over a substrate 302, an insulating film 306 over the substrate 302 and the conductive film 304, an insulating film 307 over the insulating film 306, and an oxide semiconductor film 308 over the insulating film 307. And the insulating film 314 over the oxide semiconductor film 308, the insulating film 316 over the insulating film 314, and the oxide semiconductor film 308 through the openings 341a provided in the insulating film 314 and the insulating film 316. And a conductive film 312b which is electrically connected to the oxide semiconductor film 308 through an opening 341b provided in the insulating film 314 and the insulating film 316. An insulating film 318 is provided over the transistor 300B, more specifically, over the conductive films 312a and 312b and the insulating film 316.
  • the insulating films 306 and 307 function as gate insulating films of the transistor 300B, and the insulating films 314 and 316 have functions as protective insulating films of the oxide semiconductor film 308.
  • the film 318 functions as a protective insulating film of the transistor 300B.
  • the conductive film 304 functions as a gate electrode
  • the conductive film 312a functions as a source electrode
  • the conductive film 312b functions as a drain electrode.
  • the transistor 300B shown in FIGS. 29A, 29B, and 29C has a channel protection type structure.
  • the oxide semiconductor film of one embodiment of the present invention can be favorably used for a channel protection transistor.
  • FIG. 30A is a top view of the transistor 300C
  • FIG. 30B corresponds to a cross-sectional view of a cross section taken along dashed-dotted line X1-X2 in FIG. 30A.
  • FIG. 31A is a top view of the transistor 300D
  • FIG. 31B corresponds to a cross-sectional view of a cross section taken along dashed-dotted line X1-X2 in FIG.
  • a transistor 300D illustrated in FIG. 31 includes a conductive film 304 over a substrate 302, an insulating film 306 over the substrate 302 and the conductive film 304, an insulating film 307 over the insulating film 306, and an oxide semiconductor film 308 over the insulating film 307.
  • An insulating film 316, an insulating film 318 over the insulating film 316, and conductive films 320a and 320b over the insulating film 318 are included.
  • the insulating films 306 and 307 function as a first gate insulating film of the transistor 300D
  • the insulating films 314, 316, and 318 function as a second gate insulating film of the transistor 300D.
  • the conductive film 304 has a function as a first gate electrode
  • the conductive film 320a has a function as a second gate electrode
  • the conductive film 320b is a pixel used for a display device. It has a function as an electrode.
  • the conductive film 312a functions as a source electrode
  • the conductive film 312b functions as a drain electrode.
  • the conductive film 320a is connected to the conductive film 304 in openings 342b and 342c provided in the insulating films 306, 307, 314, 316, and 318. Therefore, the same potential is applied to the conductive film 320a and the conductive film 304.
  • the opening portions 342b and 342c are provided and the conductive film 320a and the conductive film 304 are connected to each other, but the invention is not limited thereto.
  • a structure in which only one of the opening 342b and the opening 342c is formed and the conductive film 320a and the conductive film 304 are connected, or the conductive film 320a without the opening 342b and the opening 342c is provided.
  • the conductive film 304 may not be connected. Note that in the case where the conductive film 320a and the conductive film 304 are not connected to each other, different potentials can be applied to the conductive film 320a and the conductive film 304, respectively.
  • the conductive film 320b is connected to the conductive film 312b through the opening 342a provided in the insulating films 314, 316, and 318.
  • transistor 300D has the S-channel structure described above.
  • the oxide semiconductor film 308 included in the transistor 300A illustrated in FIGS. 28A, 28B, and 28C may have a stacked structure. Examples of such cases are shown in FIGS. 32A and 32B and FIGS. 33A and 33B.
  • FIGS. 33A and 33B are cross-sectional views of the transistor 300E
  • FIGS. 33A and 33B are cross-sectional views of the transistor 300F. Note that top views of the transistors 300E and 300F are similar to those of the transistor 300A illustrated in FIG.
  • the oxide semiconductor film 308 included in the transistor 300E includes an oxide semiconductor film 308_1, an oxide semiconductor film 308_2, and an oxide semiconductor film 308_3.
  • the oxide semiconductor film 308 included in the transistor 300F illustrated in FIGS. 33A and 33B includes an oxide semiconductor film 308_2 and an oxide semiconductor film 308_3.
  • the conductive film 304, the insulating film 306, the insulating film 307, the oxide semiconductor film 308, the oxide semiconductor film 308_1, the oxide semiconductor film 308_2, the oxide semiconductor film 308_3, the conductive films 312a and 312b, the insulating film 314, and the insulating film 316, the insulating film 318, and the conductive films 320a and 320b include the conductive film 106, the insulating film 116, the insulating film 114, the oxide semiconductor film 108, the oxide semiconductor film 108_1, the oxide semiconductor film 108_2, and the like described above, respectively.
  • a material similar to that of the oxide semiconductor film 108_3, the conductive films 120a and 120b, the insulating film 104, the insulating film 118, the insulating film 116, and the conductive film 112 can be used.
  • FIG. 34A is a top view of the transistor 300G
  • FIG. 34B corresponds to a cross-sectional view of a cross section taken along dashed-dotted line X1-X2 in FIG. 34A.
  • the upper insulating film 316, the conductive film 320a over the insulating film 316, and the conductive film 320b over the insulating film 316 are included.
  • the insulating film 306 and the insulating film 307 have an opening 351, and a conductive film 312c that is electrically connected to the conductive film 304 through the opening 351 is formed over the insulating film 306 and the insulating film 307. Is done.
  • the insulating film 314 and the insulating film 316 include an opening 352a reaching the conductive film 312b and an opening 352b reaching the conductive film 312c.
  • the oxide semiconductor film 308 includes an oxide semiconductor film 308_2 on the conductive film 304 side and an oxide semiconductor film 308_3 over the oxide semiconductor film 308_2.
  • an insulating film 318 is provided over the transistor 300G.
  • the insulating film 318 is formed so as to cover the insulating film 316, the conductive film 320a, and the conductive film 320b.
  • the insulating films 306 and 307 have a function as a first gate insulating film of the transistor 300G, and the insulating films 314 and 316 have a function as a second gate insulating film of the transistor 300G.
  • the insulating film 318 functions as a protective insulating film of the transistor 300G.
  • the conductive film 304 functions as a first gate electrode
  • the conductive film 320a functions as a second gate electrode
  • the conductive film 320b is a pixel used for a display device. It has a function as an electrode.
  • the conductive film 312a functions as a source electrode
  • the conductive film 312b functions as a drain electrode.
  • the conductive film 312c functions as a connection electrode.
  • transistor 300G has the S-channel structure described above.
  • the structures of the transistors 300A to 300G may be used in any combination.
  • FIG. 35 is a top view showing an example of the display device.
  • a display device 700 illustrated in FIG. 35 includes a pixel portion 702 provided over a first substrate 701, a source driver circuit portion 704 and a gate driver circuit portion 706 provided over the first substrate 701, a pixel portion 702,
  • the sealant 712 is disposed so as to surround the source driver circuit portion 704 and the gate driver circuit portion 706, and the second substrate 705 is provided so as to face the first substrate 701.
  • the first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are sealed with the first substrate 701, the sealant 712, and the second substrate 705.
  • a display element is provided between the first substrate 701 and the second substrate 705.
  • the display device 700 includes a pixel portion 702, a source driver circuit portion 704, a gate driver circuit portion 706, and a gate driver circuit portion in a region different from the region surrounded by the sealant 712 over the first substrate 701. 706 and an FPC terminal portion 708 (FPC: Flexible printed circuit) electrically connected to each other.
  • FPC Flexible printed circuit
  • an FPC 716 is connected to the FPC terminal portion 708, and various signals are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 by the FPC 716.
  • a signal line 710 is connected to each of the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708.
  • Various signals and the like supplied by the FPC 716 are supplied to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708 through the signal line 710.
  • a plurality of gate driver circuit portions 706 may be provided in the display device 700.
  • the display device 700 an example in which the source driver circuit portion 704 and the gate driver circuit portion 706 are formed over the same first substrate 701 as the pixel portion 702 is shown; however, the display device 700 is not limited to this structure.
  • only the gate driver circuit portion 706 may be formed on the first substrate 701, or only the source driver circuit portion 704 may be formed on the first substrate 701.
  • a substrate on which a source driver circuit, a gate driver circuit, or the like is formed eg, a driver circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film
  • a connection method of a separately formed drive circuit board is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or the like can be used.
  • the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 included in the display device 700 include a plurality of transistors.
  • the display device 700 can have various elements.
  • the element include, for example, an electroluminescence (EL) element (an EL element including an organic substance and an inorganic substance, an organic EL element, an inorganic EL element, an LED, and the like), a light-emitting transistor element (a transistor that emits light in response to current), an electron Emission element, liquid crystal element, electronic ink element, electrophoretic element, electrowetting element, plasma display panel (PDP), MEMS (micro electro mechanical system) display (for example, grating light valve (GLV), digital micromirror Devices (DMD), digital micro shutter (DMS) elements, interferometric modulation (IMOD) elements, etc.), piezoelectric ceramic displays, and the like.
  • EL electroluminescence
  • a light-emitting transistor element a transistor that emits light in response to current
  • an electron Emission element for example, grating light valve (GLV), digital micromirror Devices (DMD), digital micro shutter (DMS) elements,
  • An example of a display device using an EL element is an EL display.
  • a display device using an electron-emitting device there is a field emission display (FED), a SED type flat display (SED: Surface-conduction Electron-emitter Display), or the like.
  • FED field emission display
  • SED SED type flat display
  • a display device using a liquid crystal element there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like.
  • An example of a display device using an electronic ink element or an electrophoretic element is electronic paper.
  • part or all of the pixel electrode may have a function as a reflective electrode.
  • part or all of the pixel electrode may have aluminum, silver, or the like.
  • a memory circuit such as an SRAM can be provided under the reflective electrode. Thereby, power consumption can be further reduced.
  • the color elements controlled by the pixels when performing color display are not limited to three colors of RGB (R represents red, G represents green, and B represents blue).
  • RGB red
  • G represents green
  • B represents blue
  • it may be composed of four pixels: an R pixel, a G pixel, a B pixel, and a W (white) pixel.
  • one color element may be configured by two colors of RGB, and two different colors may be selected and configured depending on the color element.
  • one or more colors such as yellow, cyan, and magenta may be added to RGB.
  • the size of the display area may be different for each dot of the color element.
  • the disclosed invention is not limited to a display device for color display, and can be applied to a display device for monochrome display.
  • a colored layer (also referred to as a color filter) may be used in order to display white light (W) in a backlight (an organic EL element, an inorganic EL element, an LED, a fluorescent lamp, or the like) and display a full color display device.
  • a backlight an organic EL element, an inorganic EL element, an LED, a fluorescent lamp, or the like
  • red (R), green (G), blue (B), yellow (Y), and the like can be used in appropriate combination for the colored layer.
  • the colored layer the color reproducibility can be increased as compared with the case where the colored layer is not used.
  • white light in a region having no colored layer may be directly used for display by arranging a region having a colored layer and a region having no colored layer.
  • a decrease in luminance due to the colored layer can be reduced during bright display, and power consumption can be reduced by about 20% to 30%.
  • a self-luminous element such as an organic EL element or an inorganic EL element
  • R, G, B, Y, and W may be emitted from elements having respective emission colors.
  • power consumption may be further reduced as compared with the case where a colored layer is used.
  • colorization method in addition to a method (color filter method) in which part of the light emission from the white light emission described above is converted into red, green, and blue through a color filter, red, green, and blue light emission is performed.
  • a method of using each (three-color method) or a method of converting a part of light emission from blue light emission into red or green (color conversion method, quantum dot method) may be applied.
  • FIGS. 36 and FIG. 37 are cross-sectional views taken along one-dot chain line QR shown in FIG. 35, in which a liquid crystal element is used as a display element.
  • FIG. 38 is a cross-sectional view taken along one-dot chain line QR shown in FIG. 35 and has a configuration using an EL element as a display element.
  • a display device 700 illustrated in FIGS. 36 to 38 includes a lead wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. Further, the lead wiring portion 711 includes a signal line 710. In addition, the pixel portion 702 includes a transistor 750 and a capacitor 790. In addition, the source driver circuit portion 704 includes a transistor 752.
  • the transistor 750 and the transistor 752 have the same structure as the transistor 100B described above. Note that as the structures of the transistor 750 and the transistor 752, other transistors described in the above embodiment may be used.
  • the transistor used in this embodiment includes an oxide semiconductor film which is highly purified and suppresses formation of oxygen vacancies.
  • the transistor can have low off-state current. Therefore, the holding time of an electric signal such as an image signal can be increased, and the writing interval can be set longer in the power-on state. Therefore, since the frequency of the refresh operation can be reduced, there is an effect of suppressing power consumption.
  • the transistor used in this embodiment can be driven at high speed because relatively high field-effect mobility can be obtained.
  • the switching transistor in the pixel portion and the driver transistor used in the driver circuit portion can be formed over the same substrate. That is, since it is not necessary to use a semiconductor device formed of a silicon wafer or the like as a separate drive circuit, the number of parts of the semiconductor device can be reduced.
  • a high-quality image can be provided by using a transistor that can be driven at high speed.
  • the capacitor 790 includes a lower electrode formed through a step of processing the same conductive film as the conductive film that functions as the first gate electrode included in the transistor 750, and a conductive function that functions as a source electrode and a drain electrode included in the transistor 750. And an upper electrode formed through a process of processing the same conductive film as the film. Further, between the lower electrode and the upper electrode, an insulating film formed through a process of forming the same insulating film as the first gate insulating film of the transistor 750 and protection of the transistor 750 An insulating film formed through a step of forming the same insulating film as the insulating film functioning as the insulating film is provided. That is, the capacitor 790 has a stacked structure in which an insulating film functioning as a dielectric film is sandwiched between a pair of electrodes.
  • a planarization insulating film 770 is provided over the transistor 750, the transistor 752, and the capacitor 790.
  • the pixel portion 702 and the source driver circuit portion 704 may use different transistors. Specifically, a top-gate transistor is used for the pixel portion 702 and a bottom-gate transistor is used for the source driver circuit portion 704, or a bottom-gate transistor is used for the pixel portion 702, and the source driver circuit portion 704 is used. In addition, a configuration using a top gate type transistor can be given. Note that the source driver circuit portion 704 may be replaced with a gate driver circuit portion.
  • the signal line 710 is formed through the same process as the conductive film functioning as the source electrode and the drain electrode of the transistors 750 and 752. For example, when a material containing a copper element is used as the signal line 710, signal delay due to wiring resistance is small and display on a large screen is possible.
  • the FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 716.
  • the connection electrode 760 is formed through the same process as the conductive film functioning as the source and drain electrodes of the transistors 750 and 752.
  • the connection electrode 760 is electrically connected to a terminal included in the FPC 716 through an anisotropic conductive film 780.
  • first substrate 701 and the second substrate 705 for example, glass substrates can be used.
  • a flexible substrate may be used as the first substrate 701 and the second substrate 705.
  • the flexible substrate include a plastic substrate.
  • a structure body 778 is provided between the first substrate 701 and the second substrate 705.
  • the structure body 778 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Note that a spherical spacer may be used as the structure body 778.
  • a light shielding film 738 functioning as a black matrix, a colored film 736 functioning as a color filter, and an insulating film 734 in contact with the light shielding film 738 and the colored film 736 are provided.
  • a display device 700 illustrated in FIG. 36 includes a liquid crystal element 775.
  • the liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776.
  • the conductive film 774 is provided on the second substrate 705 side and functions as a counter electrode.
  • a display device 700 illustrated in FIG. 36 can display an image by controlling transmission and non-transmission of light by changing the alignment state of the liquid crystal layer 776 depending on voltages applied to the conductive films 772 and 774.
  • the conductive film 772 is electrically connected to a conductive film functioning as a source electrode and a drain electrode of the transistor 750.
  • the conductive film 772 is formed over the planarization insulating film 770 and functions as one electrode of the pixel electrode or the display element.
  • a conductive film that is transparent to visible light or a conductive film that is reflective to visible light can be used.
  • a material containing one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used.
  • a material containing aluminum or silver is preferably used.
  • the display device 700 is a reflective liquid crystal display device. In the case where a conductive film that transmits visible light is used for the conductive film 772, the display device 700 is a transmissive liquid crystal display device.
  • the driving method of the liquid crystal element can be changed by changing the structure over the conductive film 772.
  • FIG. A display device 700 illustrated in FIG. 37 is an example of a configuration using a horizontal electric field method (eg, an FFS mode) as a driving method of a liquid crystal element.
  • the insulating film 773 is provided over the conductive film 772, and the conductive film 774 is provided over the insulating film 773.
  • the conductive film 774 functions as a common electrode (also referred to as a common electrode), and the alignment of the liquid crystal layer 776 is generated by an electric field generated between the conductive film 772 and the conductive film 774 through the insulating film 773. The state can be controlled.
  • an alignment film may be provided on one or both of the conductive film 772 and the conductive film 774 on the side in contact with the liquid crystal layer 776.
  • an optical member optical substrate
  • a polarizing member such as a polarizing member, a retardation member, or an antireflection member
  • circularly polarized light using a polarizing substrate and a retardation substrate may be used.
  • a backlight, a sidelight, or the like may be used as the light source.
  • thermotropic liquid crystal When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like depending on conditions.
  • a liquid crystal exhibiting a blue phase without using an alignment film may be used.
  • the blue phase is one of the liquid crystal phases.
  • the temperature of the cholesteric liquid crystal is increased, the blue phase appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with several percent by weight or more of a chiral agent is used for the liquid crystal layer in order to improve the temperature range.
  • a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed and is optically isotropic, so that alignment treatment is unnecessary.
  • a liquid crystal material exhibiting a blue phase has a small viewing angle dependency.
  • a liquid crystal element when used as a display element, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axial Symmetrical Aligned MicroOcell) mode.
  • a Compensated Birefringence mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (Antiferroelectric Liquid Crystal) mode, and the like can be used.
  • a normally black liquid crystal display device such as a transmissive liquid crystal display device employing a vertical alignment (VA) mode may be used.
  • VA vertical alignment
  • the vertical alignment mode There are several examples of the vertical alignment mode. For example, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV mode, and the like can be used.
  • a display device 700 illustrated in FIG. 38 includes a light-emitting element 782.
  • the light-emitting element 782 includes a conductive film 772, an EL layer 786, and a conductive film 788.
  • the display device 700 illustrated in FIG. 38 can display an image when the EL layer 786 included in the light-emitting element 782 emits light.
  • the EL layer 786 includes an organic compound or an inorganic compound such as a quantum dot.
  • Examples of materials that can be used for the organic compound include fluorescent materials and phosphorescent materials.
  • Examples of materials that can be used for the quantum dots include colloidal quantum dot materials, alloy type quantum dot materials, core / shell type quantum dot materials, and core type quantum dot materials.
  • a material including an element group of Group 12 and Group 16, Group 13 and Group 15, or Group 14 and Group 16 may be used.
  • a quantum dot material having an element such as aluminum (Al) may be used.
  • the organic compound and inorganic compound for example, a deposition method (including a vacuum deposition method), a droplet discharge method (also referred to as an inkjet method), a coating method, a gravure printing method, or the like is used. be able to.
  • the EL layer 786 may include a low molecular material, a medium molecular material (including an oligomer and a dendrimer), or a high molecular material.
  • FIGS. FIG. 39A to FIG. 39D are cross-sectional views illustrating a method for manufacturing the EL layer 786.
  • a conductive film 772 is formed over the planarization insulating film 770, and an insulating film 730 is formed so as to cover part of the conductive film 772 (see FIG. 39A).
  • a droplet 784 is discharged from a droplet discharge device 783 to an exposed portion of the conductive film 772 which is an opening of the insulating film 730, so that a layer 785 containing a composition is formed.
  • the droplet 784 is a composition including a solvent and is attached to the conductive film 772 (see FIG. 39B).
  • step of discharging the droplet 784 may be performed under reduced pressure.
  • an EL layer 786 is formed by removing the solvent from the layer 785 containing the composition and solidifying the layer (see FIG. 39C).
  • a conductive film 788 is formed over the EL layer 786, so that the light-emitting element 782 is formed (see FIG. 39D).
  • the composition can be selectively discharged, so that material loss can be reduced.
  • the process can be simplified and cost reduction can be achieved.
  • the droplet discharge method described above is a general term for a device having means for discharging droplets such as a nozzle having a composition discharge port or a head having one or a plurality of nozzles.
  • FIG. 40 is a conceptual diagram for explaining the droplet discharge device 1400.
  • the droplet discharge device 1400 has droplet discharge means 1403.
  • the droplet discharge unit 1403 includes a head 1405 and a head 1412.
  • the head 1405 and the head 1412 are connected to the control means 1407, and can be drawn in a pre-programmed pattern by being controlled by the computer 1410.
  • the drawing timing may be performed with reference to the marker 1411 formed on the substrate 1402, for example.
  • the reference point may be determined based on the outer edge of the substrate 1402.
  • the marker 1411 is detected by the image pickup means 1404, the digital signal converted by the image processing means 1409 is recognized by the computer 1410, a control signal is generated and sent to the control means 1407.
  • an image sensor using a charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS) can be used as the imaging means 1404.
  • Information on the pattern to be formed on the substrate 1402 is stored in the storage medium 1408. Based on this information, a control signal is sent to the control means 1407, and the individual heads 1405 of the droplet discharge means 1403 are sent.
  • the heads 1412 can be individually controlled.
  • the material to be discharged is supplied from the material supply source 1413 and the material supply source 1414 to the head 1405 and the head 1412 through piping.
  • the interior of the head 1405 has a structure having a space filled with a liquid material as indicated by a dotted line 1406 and a nozzle that is a discharge port.
  • the head 1412 has the same internal structure as the head 1405.
  • the nozzles of the head 1405 and the head 1412 are provided in different sizes, different materials can be drawn simultaneously with different widths.
  • a single head can discharge and draw multiple types of light emitting materials, and when drawing over a wide area, the same material can be simultaneously discharged and drawn from multiple nozzles to improve throughput. it can.
  • the head 1405 and the head 1412 can freely scan on the substrate in the directions of arrows X, Y, and Z shown in FIG. Can be drawn on a single substrate.
  • the step of discharging the composition may be performed under reduced pressure.
  • the substrate may be heated at the time of discharge.
  • steps of drying and baking are performed.
  • the drying and firing steps are both heat treatment steps, but their purpose, temperature and time are different.
  • the drying process and the firing process are performed under normal pressure or reduced pressure by laser light irradiation, rapid thermal annealing, a heating furnace, or the like. Note that the timing of performing this heat treatment and the number of heat treatments are not particularly limited. In order to satisfactorily perform the drying and firing steps, the temperature at that time depends on the material of the substrate and the properties of the composition.
  • the EL layer 786 can be manufactured using a droplet discharge device.
  • an insulating film 730 is provided over the planarization insulating film 770 and the conductive film 772.
  • the insulating film 730 covers part of the conductive film 772.
  • the light-emitting element 782 has a top emission structure. Therefore, the conductive film 788 has a light-transmitting property and transmits light emitted from the EL layer 786.
  • the top emission structure is illustrated, but is not limited thereto. For example, a bottom emission structure in which light is emitted to the conductive film 772 side or a dual emission structure in which light is emitted to both the conductive film 772 and the conductive film 788 can be used.
  • a coloring film 736 is provided at a position overlapping with the light emitting element 782, and a light shielding film 738 is provided at a position overlapping with the insulating film 730, the lead wiring portion 711, and the source driver circuit portion 704. Further, the coloring film 736 and the light shielding film 738 are covered with an insulating film 734. A space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. Note that in the display device 700 illustrated in FIG. 38, the structure in which the colored film 736 is provided is illustrated, but the present invention is not limited to this. For example, in the case where the EL layer 786 is formed by separate coating, the coloring film 736 may not be provided.
  • an input / output device may be provided in the display device 700 illustrated in FIGS.
  • Examples of the input / output device include a touch panel.
  • FIG. 37 shows a configuration in which the touch panel 791 is provided in the display device 700 shown in FIG. 37
  • FIG. 42 shows a configuration in which the touch panel 791 is provided in the display device 700 shown in FIG.
  • FIG. 41 is a cross-sectional view of a configuration in which the touch panel 791 is provided on the display device 700 shown in FIG. 37
  • FIG. 42 is a cross-sectional view of a configuration in which the touch panel 791 is provided on the display device 700 shown in FIG.
  • a touch panel 791 shown in FIGS. 41 and 42 is a so-called in-cell type touch panel provided between the substrate 705 and the colored film 736.
  • the touch panel 791 may be formed on the substrate 705 side before the light shielding film 738 and the coloring film 736 are formed.
  • the touch panel 791 includes a light-blocking film 738, an insulating film 792, an electrode 793, an electrode 794, an insulating film 795, an electrode 796, and an insulating film 797.
  • a change in mutual capacitance between the electrode 793 and the electrode 794 can be detected when a detection target such as a finger or a stylus comes close.
  • the intersection of the electrode 793 and the electrode 794 is clearly shown.
  • the electrode 796 is electrically connected to two electrodes 793 sandwiching the electrode 794 through an opening provided in the insulating film 795.
  • 41 and FIG. 42 exemplify the configuration in which the region where the electrode 796 is provided is provided in the pixel portion 702, but the present invention is not limited to this.
  • the region may be formed in the source driver circuit portion 704.
  • the electrode 793 and the electrode 794 are provided in a region overlapping with the light shielding film 738. As shown in FIG. 41, the electrode 793 is preferably provided so as not to overlap with the light-emitting element 782. As shown in FIG. 42, the electrode 793 is preferably provided so as not to overlap with the liquid crystal element 775. In other words, the electrode 793 has an opening in a region overlapping with the light-emitting element 782 and the liquid crystal element 775. That is, the electrode 793 has a mesh shape. With such a structure, the electrode 793 can be configured not to block light emitted from the light-emitting element 782. Alternatively, the electrode 793 can have a structure that does not block light transmitted through the liquid crystal element 775. Therefore, since the reduction in luminance due to the arrangement of the touch panel 791 is extremely small, a display device with high visibility and low power consumption can be realized. Note that the electrode 794 may have a similar structure.
  • a metal material with low visible light transmittance can be used for the electrode 793 and the electrode 794.
  • a metal material with low visible light transmittance can be used for the electrode 793 and the electrode 794.
  • the resistance of the electrode 793 and the electrode 794 can be reduced as compared with an electrode using an oxide material having a high visible light transmittance, and the sensor sensitivity of the touch panel can be improved.
  • conductive nanowires may be used for the electrodes 793, 794, and 796.
  • the nanowire may have an average diameter of 1 nm to 100 nm, preferably 5 nm to 50 nm, more preferably 5 nm to 25 nm.
  • metal nanowires such as Ag nanowire, Cu nanowire, or Al nanowire, or a carbon nanotube etc. may be used.
  • the light transmittance in visible light can be 89% or more
  • the sheet resistance value can be 40 ⁇ / ⁇ or more and 100 ⁇ / ⁇ or less.
  • 41 and 42 illustrate the configuration of the in-cell type touch panel, but the present invention is not limited to this.
  • a so-called on-cell touch panel formed over the display device 700 or a so-called out-cell touch panel used by being attached to the display device 700 may be used.
  • the display device of one embodiment of the present invention can be used in combination with various forms of touch panels.
  • a display device illustrated in FIG. 43A includes a region having a pixel of a display element (hereinafter referred to as a pixel portion 502) and a circuit portion (hereinafter referred to as a pixel portion 502) which is disposed outside the pixel portion 502 and has a circuit for driving the pixel. , A driver circuit portion 504), a circuit having a function of protecting an element (hereinafter referred to as a protection circuit 506), and a terminal portion 507. Note that the protection circuit 506 may be omitted.
  • part or all of the drive circuit portion 504 is formed on the same substrate as the pixel portion 502. Thereby, the number of parts and the number of terminals can be reduced.
  • part or all of the driver circuit portion 504 is formed by COG or TAB (Tape Automated Bonding). Can be implemented.
  • the pixel portion 502 includes a circuit (hereinafter referred to as a pixel circuit 501) for driving a plurality of display elements arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more).
  • the driver circuit portion 504 outputs a signal for selecting a pixel (scanning signal) (hereinafter referred to as a gate driver 504a) and a circuit for supplying a signal (data signal) for driving a display element of the pixel (a data signal).
  • a drive circuit such as a source driver 504b).
  • the gate driver 504a has a shift register and the like.
  • the gate driver 504a receives a signal for driving the shift register via the terminal portion 507, and outputs a signal.
  • the gate driver 504a receives a start pulse signal, a clock signal, and the like and outputs a pulse signal.
  • the gate driver 504a has a function of controlling the potential of a wiring to which a scan signal is supplied (hereinafter referred to as scan lines GL_1 to GL_X).
  • scan lines GL_1 to GL_X a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a.
  • the gate driver 504a has a function of supplying an initialization signal.
  • the present invention is not limited to this, and the gate driver 504a can supply another signal.
  • the source driver 504b has a shift register and the like. In addition to a signal for driving the shift register, the source driver 504b receives a signal (image signal) as a source of a data signal through the terminal portion 507.
  • the source driver 504b has a function of generating a data signal to be written in the pixel circuit 501 based on the image signal.
  • the source driver 504b has a function of controlling output of a data signal in accordance with a pulse signal obtained by inputting a start pulse, a clock signal, or the like.
  • the source driver 504b has a function of controlling the potential of a wiring to which a data signal is supplied (hereinafter referred to as data lines DL_1 to DL_Y).
  • the source driver 504b has a function of supplying an initialization signal.
  • the present invention is not limited to this, and the source driver 504b can supply another signal.
  • the source driver 504b is configured using a plurality of analog switches, for example.
  • the source driver 504b can output a signal obtained by time-dividing the image signal as a data signal by sequentially turning on the plurality of analog switches. Further, the source driver 504b may be configured using a shift register or the like.
  • Each of the plurality of pixel circuits 501 receives a pulse signal through one of the plurality of scanning lines GL to which the scanning signal is applied, and receives the data signal through one of the plurality of data lines DL to which the data signal is applied. Entered.
  • writing and holding of data signals are controlled by the gate driver 504a.
  • the pixel circuit 501 in the m-th row and the n-th column receives a pulse signal from the gate driver 504a through the scanning line GL_m (m is a natural number equal to or less than X), and the data line DL_n (n Is a natural number less than or equal to Y), a data signal is input from the source driver 504b.
  • the protection circuit 43A is connected to, for example, the scanning line GL that is a wiring between the gate driver 504a and the pixel circuit 501.
  • the protection circuit 506 illustrated in FIG. the protection circuit 506 is connected to a data line DL that is a wiring between the source driver 504 b and the pixel circuit 501.
  • the protection circuit 506 can be connected to a wiring between the gate driver 504 a and the terminal portion 507.
  • the protection circuit 506 can be connected to a wiring between the source driver 504 b and the terminal portion 507.
  • the terminal portion 507 is a portion where a terminal for inputting a power supply, a control signal, and an image signal from an external circuit to the display device is provided.
  • the protection circuit 506 is a circuit that brings the wiring and another wiring into a conductive state when a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected.
  • the configuration of the protection circuit 506 is not limited thereto, and for example, a configuration in which the protection circuit 506 is connected to the gate driver 504a or a configuration in which the protection circuit 506 is connected to the source driver 504b may be employed. Alternatively, the protection circuit 506 may be connected to the terminal portion 507.
  • FIG. 43A illustrates an example in which the driver circuit portion 504 is formed using the gate driver 504a and the source driver 504b; however, the present invention is not limited to this structure.
  • the gate driver 504a may be formed, and a substrate on which a separately prepared source driver circuit is formed (for example, a driver circuit substrate formed using a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted.
  • the plurality of pixel circuits 501 illustrated in FIG. 43A can have a structure illustrated in FIG. 43B, for example.
  • 43B includes a liquid crystal element 570, a transistor 550, and a capacitor 560.
  • One potential of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specification of the pixel circuit 501.
  • the alignment state of the liquid crystal element 570 is set by written data. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Further, a different potential may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 in each row.
  • a driving method of a display device including the liquid crystal element 570, a TN mode, an STN mode, a VA mode, an ASM (axially aligned micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, and an FLC (Frequential) mode.
  • AFLC Anti Ferroelectric Liquid Crystal
  • MVA mode MVA mode
  • PVA Powerned Vertical Alignment
  • IPS mode Packed Vertical Alignment
  • FFS mode Transverse Bend Alignment
  • TBA Transverse Bend Alignment
  • ECB Electrode Controlled Birefringence
  • PDLC Polymer Dispersed Liquid Crystal
  • PNLC Polymer Network Liquid mode
  • the present invention is not limited to this, and various liquid crystal elements and driving methods thereof can be used.
  • one of the source electrode and the drain electrode of the transistor 550 is electrically connected to the data line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570.
  • the In addition, the gate electrode of the transistor 550 is electrically connected to the scan line GL_m.
  • the transistor 550 has a function of controlling data writing of the data signal by being turned on or off.
  • One of the pair of electrodes of the capacitor 560 is electrically connected to a wiring to which a potential is supplied (hereinafter, potential supply line VL), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570.
  • potential supply line VL a wiring to which a potential is supplied
  • the capacitor 560 functions as a storage capacitor for storing written data.
  • the pixel circuits 501 in each row are sequentially selected by the gate driver 504a illustrated in FIG. Write data.
  • the pixel circuit 501 in which data is written is in a holding state when the transistor 550 is turned off. By sequentially performing this for each row, an image can be displayed.
  • the plurality of pixel circuits 501 illustrated in FIG. 43A can have a structure illustrated in FIG. 43C, for example.
  • the pixel circuit 501 illustrated in FIG. 43C includes transistors 552 and 554, a capacitor 562, and a light-emitting element 572.
  • the transistor described in any of the above embodiments can be applied to one or both of the transistor 552 and the transistor 554.
  • One of the source electrode and the drain electrode of the transistor 552 is electrically connected to a wiring to which a data signal is supplied (hereinafter referred to as a signal line DL_n). Further, the gate electrode of the transistor 552 is electrically connected to a wiring to which a gate signal is supplied (hereinafter referred to as a scanning line GL_m).
  • the transistor 552 has a function of controlling data writing of the data signal by being turned on or off.
  • One of the pair of electrodes of the capacitor 562 is electrically connected to a wiring to which a potential is applied (hereinafter referred to as a potential supply line VL_a), and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 552. Is done.
  • the capacitor element 562 functions as a storage capacitor for storing written data.
  • One of the source electrode and the drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. Further, the gate electrode of the transistor 554 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.
  • One of an anode and a cathode of the light-emitting element 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554.
  • the light-emitting element 572 for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used.
  • the light-emitting element 572 is not limited thereto, and an inorganic EL element made of an inorganic material may be used.
  • one of the potential supply line VL_a and the potential supply line VL_b is supplied with the high power supply potential VDD, and the other is supplied with the low power supply potential VSS.
  • the pixel circuits 501 in each row are sequentially selected by the gate driver 504a illustrated in FIG. Write.
  • the pixel circuit 501 in which data is written is in a holding state when the transistor 552 is turned off. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled in accordance with the potential of the written data signal, and the light-emitting element 572 emits light with luminance corresponding to the amount of flowing current. By sequentially performing this for each row, an image can be displayed.
  • FIG. 44A is a circuit diagram of an inverter that can be applied to a shift register, a buffer, or the like included in a driver circuit.
  • the inverter 800 outputs a signal obtained by inverting the logic of the signal applied to the input terminal IN to the output terminal OUT.
  • the inverter 800 includes a plurality of OS transistors.
  • the signal SBG is a signal that can switch the electrical characteristics of the OS transistor.
  • FIG. 44B is an example of the inverter 800.
  • the inverter 800 includes an OS transistor 810 and an OS transistor 820. Since the inverter 800 can be manufactured using only an n-channel transistor, it can be manufactured at a lower cost than a case where an inverter (CMOS inverter) is manufactured using a CMOS (Complementary Metal Oxide Semiconductor).
  • CMOS inverter Complementary Metal Oxide Semiconductor
  • the inverter 800 having an OS transistor can also be arranged on a CMOS composed of Si transistors. Since the inverter 800 can be arranged so as to overlap with a CMOS circuit, an increase in circuit area corresponding to the addition of the inverter 800 can be suppressed.
  • the OS transistors 810 and 820 include a first gate that functions as a front gate, a second gate that functions as a back gate, a first terminal that functions as one of a source and a drain, and a second gate that functions as the other of a source and a drain. Terminal.
  • the first gate of the OS transistor 810 is connected to the second terminal.
  • a second gate of the OS transistor 810 is connected to a wiring for supplying the signal SBG .
  • a first terminal of the OS transistor 810 is connected to a wiring that supplies the voltage VDD.
  • the second terminal of the OS transistor 810 is connected to the output terminal OUT.
  • the first gate of the OS transistor 820 is connected to the input terminal IN.
  • a second gate of the OS transistor 820 is connected to the input terminal IN.
  • the first terminal of the OS transistor 820 is connected to the output terminal OUT.
  • a second terminal of the OS transistor 820 is connected to a wiring that supplies the voltage VSS.
  • FIG. 44C is a timing chart for explaining the operation of the inverter 800.
  • the timing chart in FIG. 44C shows changes in the signal waveform of the input terminal IN, the signal waveform of the output terminal OUT, the signal waveform of the signal SBG, and the threshold voltage of the OS transistor 810.
  • the threshold voltage of the OS transistor 810 can be controlled.
  • Signal S BG has a voltage V BG_B for shifted in the positive voltage V BG_A, the threshold voltage for negative shift the threshold voltage.
  • FIG. 45A shows an Id-Vg curve which is one of the electrical characteristics of the transistor.
  • the above-described electrical characteristics of the OS transistor 810 can be shifted to a curve represented by a broken line 840 in FIG. 45A by increasing the voltage of the second gate as the voltage V BG_A .
  • the above-described electrical characteristics of the OS transistor 810 can be shifted to a curve represented by a solid line 841 in FIG. 45A by reducing the voltage of the second gate as the voltage V BG_B .
  • OS transistor 810 by switching the signal S BG and so the voltage V BG_A or voltage V BG_B, can be shifted in the positive or negative shift of the threshold voltage.
  • the OS transistor 810 can be in a state in which current does not easily flow.
  • FIG. 45B visualizes this state.
  • FIG. 45C visualizes this state. As shown in FIG. 45 (C), it can be larger than at least the current I B of the current I A flowing at this time. Therefore, when the signal supplied to the input terminal IN is at a low level and the OS transistor 820 is in an off state (OFF), the voltage of the output terminal OUT can be rapidly increased. As shown in FIG. 45C, since the current flowing through the OS transistor 810 can easily flow, the signal waveform 832 at the output terminal in the timing chart shown in FIG. Can do.
  • the control of the threshold voltage of the OS transistor 810 by the signal S BG previously the state of the OS transistor 820 is switched, i.e. it is preferably performed before a time T1 and T2.
  • the threshold voltage V TH_A is changed from the threshold voltage V TH_A to the threshold voltage V TH_B before the time T1 when the signal applied to the input terminal IN switches to the high level. It is preferable to switch the threshold voltage.
  • the OS transistor 810 is switched from the threshold voltage V TH_B to the threshold voltage V TH_A before the time T2 when the signal applied to the input terminal IN is switched to the low level. It is preferable to switch the threshold voltage.
  • the voltage for controlling the threshold voltage may be held in the second gate of the OS transistor 810 in a floating state.
  • An example of a circuit configuration that can realize this configuration is illustrated in FIG.
  • 46A includes an OS transistor 850 in addition to the circuit configuration illustrated in FIG.
  • the first terminal of the OS transistor 850 is connected to the second gate of the OS transistor 810.
  • the second terminal of the OS transistor 850 is connected to a wiring for applying the voltage V BG_B (or voltage V BG_A ).
  • the first gate of the OS transistor 850 is connected to a wiring for providing signal S F.
  • a second gate of the OS transistor 850 is connected to a wiring that supplies the voltage V BG_B (or the voltage V BG_A ).
  • FIG. 46A The operation in FIG. 46A will be described with reference to the timing chart in FIG.
  • the voltage for controlling the threshold voltage of the OS transistor 810 is applied to the second gate of the OS transistor 810 before the time T3 when the signal applied to the input terminal IN switches to the high level.
  • the OS transistor 850 is turned on the signal S F to the high level, providing a voltage V BG_B for controlling a threshold voltage in the node N BG.
  • FIGS. 44B and 46A a configuration in which the voltage applied to the second gate of the OS transistor 810 is given by external control is shown, but another configuration may be used.
  • a voltage for controlling the threshold voltage may be generated based on a signal supplied to the input terminal IN and supplied to the second gate of the OS transistor 810.
  • FIG. 47A illustrates an example of a circuit configuration that can realize this configuration.
  • a CMOS inverter 860 is provided between the input terminal IN and the second gate of the OS transistor 810.
  • the input terminal of the CMOS inverter 860 is connected to the input terminal IN.
  • the output terminal of the CMOS inverter 860 is connected to the second gate of the OS transistor 810.
  • FIG. 47A The operation in FIG. 47A will be described with reference to the timing chart in FIG.
  • the timing chart in FIG. 47B shows changes in the signal waveform of the input terminal IN, the signal waveform of the output terminal OUT, the output waveform IN_B of the CMOS inverter 860, and the threshold voltage of the OS transistor 810.
  • the output waveform IN_B which is a signal obtained by inverting the logic of the signal applied to the input terminal IN, can be a signal for controlling the threshold voltage of the OS transistor 810. Therefore, as described with reference to FIGS. 45A to 45C, the threshold voltage of the OS transistor 810 can be controlled. For example, at time T4 in FIG. 47B, the signal applied to the input terminal IN is at a high level and the OS transistor 820 is turned on. At this time, the output waveform IN_B is at a low level. Therefore, the OS transistor 810 can be set in a state in which current does not easily flow, and the voltage increase at the output terminal OUT can be sharply decreased.
  • the signal applied to the input terminal IN is at a low level, so that the OS transistor 820 is turned off.
  • the output waveform IN_B is at a high level. Therefore, the OS transistor 810 can be in a state in which current easily flows, and the voltage of the output terminal OUT can be rapidly increased.
  • the voltage of the back gate in the inverter having the OS transistor is switched in accordance with the signal logic of the input terminal IN.
  • the threshold voltage of the OS transistor can be controlled.
  • the voltage of the output terminal OUT can be changed abruptly.
  • the through current between the wirings supplying the power supply voltage can be reduced. Therefore, low power consumption can be achieved.
  • FIG. 48A is a block diagram of the semiconductor device 900.
  • the semiconductor device 900 includes a power supply circuit 901, a circuit 902, a voltage generation circuit 903, a circuit 904, a voltage generation circuit 905, and a circuit 906.
  • the power supply circuit 901 is a circuit that generates a reference voltage V ORG .
  • the voltage V ORG may be a plurality of voltages instead of a single voltage.
  • the voltage V ORG can be generated based on the voltage V 0 given from the outside of the semiconductor device 900.
  • the semiconductor device 900 can generate the voltage V ORG based on a single power supply voltage given from the outside. Therefore, the semiconductor device 900 can operate without applying a plurality of power supply voltages from the outside.
  • the circuits 902, 904, and 906 are circuits that operate with different power supply voltages.
  • the power supply voltage of the circuit 902 is a voltage applied based on the voltage V ORG and the voltage V SS (V ORG > V SS ).
  • the power supply voltage of the circuit 904 is a voltage applied based on the voltage V POG and the voltage V SS (V POG > V ORG ).
  • the power supply voltage of the circuit 906 is a voltage applied based on the voltage V ORG , the voltage V SS, and the voltage V NEG (V ORG > V SS > V NEG ). Note that if the voltage VSS is equal to the ground potential (GND), the types of voltages generated by the power supply circuit 901 can be reduced.
  • GND ground potential
  • the voltage generation circuit 903 is a circuit that generates the voltage V POG .
  • the voltage generation circuit 903 can generate the voltage V POG based on the voltage V ORG supplied from the power supply circuit 901. Therefore, the semiconductor device 900 including the circuit 904 can operate based on a single power supply voltage supplied from the outside.
  • the voltage generation circuit 905 is a circuit that generates a voltage V NEG .
  • the voltage generation circuit 905 can generate the voltage V NEG based on the voltage V ORG supplied from the power supply circuit 901. Therefore, the semiconductor device 900 including the circuit 906 can operate based on a single power supply voltage given from the outside.
  • FIG. 48B illustrates an example of a circuit 904 that operates at the voltage V POG
  • FIG. 48C illustrates an example of a waveform of a signal for operating the circuit 904.
  • the transistor 911 is illustrated.
  • Signal applied to the gate of the transistor 911 is generated, for example, based on the voltage V POG and voltage V SS.
  • the signal is a voltage V SS during operation of the conductive state of transistor 911 voltage V POG, during operation of the non-conductive state.
  • the voltage V POG is larger than the voltage V ORG as illustrated in FIG. Therefore, the transistor 911 can be more reliably connected between the source (S) and the drain (D).
  • the circuit 904 can be a circuit in which malfunctions are reduced.
  • FIG. 48D illustrates an example of a circuit 906 that operates at the voltage V NEG
  • FIG. 48E illustrates an example of a waveform of a signal for operating the circuit 906.
  • FIG. 48D illustrates a transistor 912 having a back gate.
  • Signal applied to the gate of the transistor 912 for example, generated based on the voltage V ORG and the voltage V SS.
  • the signal voltage V ORG during operation of the conductive state of transistor 912 is generated based on the voltage V SS during operation of a non-conductive state.
  • a signal given to the back gate of the transistor 912 is generated based on the voltage V NEG .
  • the voltage V NEG is smaller than the voltage V SS (GND) as illustrated in FIG. Therefore, the threshold voltage of the transistor 912 can be controlled to shift positively. Therefore, the transistor 912 can be more reliably turned off, and the current flowing between the source (S) and the drain (D) can be reduced.
  • the circuit 906 can be a circuit in which malfunctions are reduced and power consumption is reduced.
  • the voltage V NEG may be directly applied to the back gate of the transistor 912.
  • a signal to be supplied to the gate of the transistor 912 may be generated based on the voltage V ORG and the voltage V NEG and the signal may be supplied to the back gate of the transistor 912.
  • 49 (A) and 49 (B) show modified examples of FIGS. 48 (D) and 48 (E).
  • a transistor 922 whose conduction state can be controlled by the control circuit 921 is illustrated between the voltage generation circuit 905 and the circuit 906.
  • the transistor 922 is an n-channel OS transistor.
  • Control signal S BG control circuit 921 is output a signal for controlling the conduction state of the transistor 922.
  • transistors 912A and 912B included in the circuit 906 are OS transistors which are the same as the transistor 922.
  • control signal S BG is transistor 922 in a conducting state at the high level, the node N BG becomes voltage V NEG. Thereafter, when the control signal SBG is at a low level, the node NBG becomes electrically floating. Since the transistor 922 is an OS transistor, the off-state current is small. Therefore, even if the node NBG is electrically floating, the voltage V NEG once applied can be held.
  • FIG. 50A illustrates an example of a circuit configuration which can be applied to the voltage generation circuit 903 described above.
  • a voltage generation circuit 903 illustrated in FIG. 50A is a five-stage charge pump including diodes D1 to D5, capacitors C1 to C5, and an inverter INV.
  • the clock signal CLK is supplied to the capacitors C1 to C5 directly or via the inverter INV.
  • the power supply voltage of the inverter INV is a voltage applied based on the voltage V ORG and the voltage V SS
  • the voltage V POG boosted to a positive voltage five times the voltage V ORG is given by applying the clock signal CLK.
  • the forward voltage of the diodes D1 to D5 is 0V. Further, by changing the number of stages of the charge pump, it is possible to obtain a desired voltage V POG.
  • FIG. 50B illustrates an example of a circuit configuration which can be applied to the voltage generation circuit 905 described above.
  • a voltage generation circuit 905 illustrated in FIG. 50B is a four-stage charge pump including diodes D1 to D5, capacitors C1 to C5, and an inverter INV.
  • the clock signal CLK is supplied to the capacitors C1 to C5 directly or via the inverter INV.
  • the power supply voltage of the inverter INV is a voltage applied based on the voltage V ORG and the voltage V SS , by supplying the clock signal CLK, the ground, that is, the negative voltage that is four times the voltage V ORG from the voltage V SS is obtained.
  • the stepped down voltage V NEG can be obtained.
  • the forward voltage of the diodes D1 to D5 is 0V. Further, the desired voltage V NEG can be obtained by changing the number of stages of the charge pump.
  • circuit configuration of the voltage generation circuit 903 described above is not limited to the configuration of the circuit diagram illustrated in FIG.
  • modification examples of the voltage generation circuit 903 are illustrated in FIGS.
  • a modification example of the voltage generation circuit 903 includes changing the voltage applied to each wiring or changing the arrangement of elements in the voltage generation circuits 903A to 903C illustrated in FIGS. It is feasible.
  • a voltage generation circuit 903A illustrated in FIG. 51A includes transistors M1 to M10, capacitors C11 to C14, and an inverter INV1.
  • the clock signal CLK is supplied directly to the gates of the transistors M1 to M10 or via the inverter INV1.
  • By providing the clock signal CLK it is possible to obtain a voltage V POG that is boosted to a positive voltage that is four times the voltage V ORG .
  • a desired voltage V POG can be obtained by changing the number of stages.
  • the voltage generation circuit 903A illustrated in FIG. 51A can reduce off-state current by using the transistors M1 to M10 as OS transistors, and can suppress leakage of charges held in the capacitors C11 to C14. Therefore, the voltage V ORG can be efficiently boosted from the voltage V POG .
  • a voltage generation circuit 903B illustrated in FIG. 51B includes transistors M11 to M14, capacitors C15 and C16, and an inverter INV2.
  • the clock signal CLK is supplied directly to the gates of the transistors M11 to M14 or via the inverter INV2. By providing the clock signal CLK, it is possible to obtain a voltage V POG that is boosted to a positive voltage that is twice the voltage V ORG .
  • the voltage generation circuit 903B illustrated in FIG. 51B can reduce off-state current by using the transistors M11 to M14 as OS transistors, and can suppress leakage of charges held in the capacitors C15 and C16. Therefore, the voltage V ORG can be efficiently boosted from the voltage V POG .
  • a voltage generation circuit 903C illustrated in FIG. 51C includes an inductor Ind1, a transistor M15, a diode D6, and a capacitor C17.
  • the conduction state of the transistor M15 is controlled by the control signal EN.
  • a voltage V POG obtained by boosting the voltage V ORG can be obtained by the control signal EN. Since the voltage generation circuit 903C illustrated in FIG. 51C uses the inductor Ind1 to increase the voltage, the voltage generation circuit 903C can increase the voltage with high conversion efficiency.
  • a voltage necessary for a circuit included in the semiconductor device can be generated internally. Therefore, the semiconductor device can reduce the number of power supply voltages given from the outside.
  • a display module 7000 shown in FIG. 52 includes a touch panel 7004 connected to the FPC 7003, a display panel 7006 connected to the FPC 7005, a backlight 7007, a frame 7009, a printed circuit board 7010, a battery, between an upper cover 7001 and a lower cover 7002. 7011.
  • the semiconductor device of one embodiment of the present invention can be used for the display panel 7006, for example.
  • the shape and dimensions of the upper cover 7001 and the lower cover 7002 can be changed as appropriate in accordance with the sizes of the touch panel 7004 and the display panel 7006.
  • a resistive film type or capacitive type touch panel can be used by being superimposed on the display panel 7006.
  • the counter substrate (sealing substrate) of the display panel 7006 can have a touch panel function.
  • an optical sensor can be provided in each pixel of the display panel 7006 to form an optical touch panel.
  • the backlight 7007 has a light source 7008.
  • FIG. 52 illustrates the configuration in which the light source 7008 is provided over the backlight 7007, the present invention is not limited to this.
  • the light source 7008 may be disposed at the end of the backlight 7007 and a light diffusing plate may be used.
  • the backlight 7007 may not be provided.
  • the frame 7009 has a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed circuit board 7010 in addition to the protective function of the display panel 7006.
  • the frame 7009 may have a function as a heat sink.
  • the printed circuit board 7010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal.
  • the power source for supplying power to the power supply circuit may be an external commercial power source or a power source using a battery 7011 provided separately.
  • the battery 7011 can be omitted when a commercial power source is used.
  • the display module 7000 may be additionally provided with a member such as a polarizing plate, a phase difference plate, and a prism sheet.
  • FIGS. 53A to 53E illustrate examples of electronic devices.
  • FIG. 53 (A) is a diagram showing the appearance of the camera 8000 with the viewfinder 8100 attached.
  • the camera 8000 includes a housing 8001, a display portion 8002, operation buttons 8003, a shutter button 8004, and the like.
  • the camera 8000 is attached with a detachable lens 8006.
  • the camera 8000 is configured such that the lens 8006 can be removed from the housing 8001 and replaced, but the lens 8006 and the housing may be integrated.
  • the camera 8000 can take an image by pressing a shutter button 8004.
  • the display portion 8002 has a function as a touch panel and can capture an image by touching the display portion 8002.
  • the housing 8001 of the camera 8000 has a mount having electrodes, and can be connected to a stroboscope or the like in addition to the finder 8100.
  • the finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.
  • the housing 8101 has a mount that engages with the mount of the camera 8000, and the finder 8100 can be attached to the camera 8000.
  • the mount includes an electrode, and an image received from the camera 8000 via the electrode can be displayed on the display portion 8102.
  • the button 8103 has a function as a power button.
  • a button 8103 can be used to switch display on the display portion 8102 on and off.
  • the display device of one embodiment of the present invention can be applied to the display portion 8002 of the camera 8000 and the display portion 8102 of the finder 8100.
  • the camera 8000 and the viewfinder 8100 are separate electronic devices and can be attached to and detached from each other.
  • a finder including a display device is incorporated in the housing 8001 of the camera 8000. Also good.
  • FIG. 53 (B) is a diagram showing the appearance of the head mounted display 8200.
  • the head mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, a cable 8205, and the like.
  • a battery 8206 is built in the mounting portion 8201.
  • the cable 8205 supplies power from the battery 8206 to the main body 8203.
  • the main body 8203 includes a wireless receiver and the like, and can display video information such as received image data on the display portion 8204.
  • the mounting portion 8201 may be provided with a plurality of electrodes at positions where the user touches the mounting portion 8201.
  • the main body 8203 may have a function of recognizing the user's viewpoint by detecting a current flowing through the electrode in accordance with the movement of the user's eyeball. Moreover, you may have a function which monitors a user's pulse by detecting the electric current which flows into the said electrode.
  • the mounting portion 8201 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display portion 8204. Further, the movement of the user's head or the like may be detected, and the video displayed on the display unit 8204 may be changed in accordance with the movement.
  • the display device of one embodiment of the present invention can be applied to the display portion 8204.
  • FIG. 53C, 53D, and 53E are views showing the appearance of the head mounted display 8300.
  • FIG. The head mounted display 8300 includes a housing 8301, a display portion 8302, a band-shaped fixture 8304, and a pair of lenses 8305.
  • the user can visually recognize the display on the display portion 8302 through the lens 8305.
  • the display portion 8302 is preferably arranged curved. By arranging the display portion 8302 to be curved, the user can feel a high sense of realism.
  • a structure in which one display portion 8302 is provided is described in this embodiment mode, the present invention is not limited thereto, and for example, a structure in which two display portions 8302 are provided may be employed. In this case, if one display unit is arranged in one eye of the user, three-dimensional display using parallax or the like can be performed.
  • the display device of one embodiment of the present invention can be applied to the display portion 8302. Since the display device including the semiconductor device of one embodiment of the present invention has extremely high definition, the pixel is not visually recognized by the user even when the display device is enlarged using the lens 8305 as illustrated in FIG. More realistic video can be displayed.
  • FIGS. 54A to 54G examples of electronic devices that are different from the electronic devices illustrated in FIGS. 53A to 53E are illustrated in FIGS. 54A to 54G.
  • 54A to 54G includes a housing 9000, a display portion 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (force , Displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration , Including a function of measuring odor or infrared light), a microphone 9008, and the like.
  • the electronic devices illustrated in FIGS. 54A to 54G have various functions. For example, a function for displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function for displaying a calendar, date or time, a function for controlling processing by various software (programs), Wireless communication function, function for connecting to various computer networks using the wireless communication function, function for transmitting or receiving various data using the wireless communication function, and reading and displaying the program or data recorded on the recording medium It can have a function of displaying on the section. Note that the functions of the electronic devices illustrated in FIGS. 54A to 54G are not limited to these, and can have various functions. Although not illustrated in FIGS.
  • the electronic device may have a plurality of display portions.
  • the electronic device is equipped with a camera, etc., to capture still images, to capture moving images, to store captured images on a recording medium (externally or built into the camera), and to display captured images on the display unit And the like.
  • FIGS. 54A to 54G Details of the electronic devices shown in FIGS. 54A to 54G will be described below.
  • FIG. 54A is a perspective view showing the television device 9100.
  • the television device 9100 can incorporate the display portion 9001 with a large screen, for example, a display portion 9001 with a size of 50 inches or more, or 100 inches or more.
  • FIG. 54B is a perspective view showing the portable information terminal 9101.
  • the portable information terminal 9101 has one or a plurality of functions selected from, for example, a telephone, a notebook, an information browsing device, or the like. Specifically, it can be used as a smartphone.
  • the portable information terminal 9101 may include a speaker 9003, a connection terminal 9006, a sensor 9007, and the like.
  • the portable information terminal 9101 can display characters and image information on the plurality of surfaces.
  • three operation buttons 9050 also referred to as operation icons or simply icons
  • information 9051 indicated by a broken-line rectangle can be displayed on another surface of the display portion 9001.
  • a display that notifies an incoming call such as an e-mail, SNS (social networking service) or a telephone, a title such as an e-mail or SNS, a sender name such as an e-mail or SNS, a date, a time , Battery level, antenna reception strength and so on.
  • an operation button 9050 or the like may be displayed instead of the information 9051 at a position where the information 9051 is displayed.
  • FIG. 54C is a perspective view showing the portable information terminal 9102.
  • the portable information terminal 9102 has a function of displaying information on three or more surfaces of the display portion 9001.
  • information 9052, information 9053, and information 9054 are displayed on different planes.
  • the user of the portable information terminal 9102 can check the display (information 9053 here) in a state where the portable information terminal 9102 is stored in the chest pocket of clothes. Specifically, the telephone number or name of the caller of the incoming call is displayed at a position where it can be observed from above portable information terminal 9102. The user can check the display and determine whether to receive a call without taking out the portable information terminal 9102 from the pocket.
  • FIG. 54D is a perspective view showing a wristwatch-type portable information terminal 9200.
  • the portable information terminal 9200 can execute various applications such as a mobile phone, electronic mail, text browsing and creation, music playback, Internet communication, and computer games.
  • the display portion 9001 is provided with a curved display surface, and can perform display along the curved display surface.
  • the portable information terminal 9200 can execute short-range wireless communication with a communication standard. For example, it is possible to talk hands-free by communicating with a headset capable of wireless communication.
  • the portable information terminal 9200 includes a connection terminal 9006 and can directly exchange data with other information terminals via a connector. Charging can also be performed through the connection terminal 9006. Note that the charging operation may be performed by wireless power feeding without using the connection terminal 9006.
  • FIG. 54E, 54F, and 54G are perspective views showing a foldable portable information terminal 9201.
  • FIG. FIG. 54E is a perspective view of a state in which the portable information terminal 9201 is expanded
  • FIG. 54F is a state in the middle of changing from one of the expanded state or the folded state of the portable information terminal 9201 to the other.
  • FIG. 54G is a perspective view of the portable information terminal 9201 folded.
  • the portable information terminal 9201 is excellent in portability in the folded state, and in the expanded state, the portable information terminal 9201 is excellent in display listability due to a seamless wide display area.
  • a display portion 9001 included in the portable information terminal 9201 is supported by three housings 9000 connected by a hinge 9055.
  • the portable information terminal 9201 By bending between the two housings 9000 via the hinge 9055, the portable information terminal 9201 can be reversibly deformed from the expanded state to the folded state.
  • the portable information terminal 9201 can be bent with a curvature radius of 1 mm to 150 mm.
  • FIGS. 53A to 53E and the electronic device different from the electronic devices illustrated in FIGS. 54A to 54G are illustrated in FIGS.
  • Shown in 55A and 55B are perspective views of a display device having a plurality of display panels.
  • FIG. 55A is a perspective view of a form in which a plurality of display panels are wound
  • FIG. 55B is a perspective view of a state in which the plurality of display panels are developed.
  • 55A and 55B includes a plurality of display panels 9501, a shaft portion 9511, and a bearing portion 9512.
  • the plurality of display panels 9501 each include a display region 9502 and a region 9503 having a light-transmitting property.
  • the plurality of display panels 9501 have flexibility. Further, two adjacent display panels 9501 are provided so that a part of them overlap each other. For example, a light-transmitting region 9503 of two adjacent display panels 9501 can be overlapped. By using a plurality of display panels 9501, a large-screen display device can be obtained. In addition, since the display panel 9501 can be taken up depending on the use state, a display device with excellent versatility can be obtained.
  • FIGS. 55A and 55B illustrate a state in which the display area 9502 is separated by the adjacent display panel 9501, but is not limited to this.
  • the display area 9502 of the adjacent display panel 9501 is displayed.
  • the display area 9502 may be a continuous display area by overlapping them with no gap.
  • the electronic device described in this embodiment has a display portion for displaying some information. Note that the semiconductor device of one embodiment of the present invention can also be applied to an electronic device that does not include a display portion.

Abstract

To provide a metal oxide film including a crystal portion. To provide a metal oxide film having high property stability. To provide a metal oxide film having improved electrical characteristics. To provide a metal oxide film enabling to improve field-effect mobility. To provide a highly reliable semiconductor device to which the metal oxide film is applied. In X-ray diffraction of a metal oxide film of the present invention, said X-ray diffraction being in the direction perpendicular to a film surface, a diffraction intensity peak due to a crystal structure is observed, and in electron beam diffraction with a probe diameter equal to or more than 50 nm, a ring-shaped diffraction pattern and two first spots at positions overlapping the ring-shaped diffraction pattern are observed, and in electron beam diffraction with a probe diameter of 0.3-5 nm, a first spot and a plurality of second spots distributed in the circumferential direction are observed.

Description

金属酸化物膜、および半導体装置Metal oxide film and semiconductor device
　本発明の一態様は、金属酸化物膜及びその作製方法に関する。本発明の一態様は、金属酸化物膜を用いた半導体装置に関する。 One embodiment of the present invention relates to a metal oxide film and a manufacturing method thereof. One embodiment of the present invention relates to a semiconductor device including a metal oxide film.
　なお、本明細書等において、半導体装置とは、半導体特性を利用することで機能しうる装置全般を指し、トランジスタ、半導体回路などは半導体装置の一態様である。また演算装置、記憶装置、撮像装置、電気光学装置、発電装置（薄膜太陽電池、有機薄膜太陽電池等を含む）、及び電子機器は半導体装置を含む場合がある。 Note that in this specification and the like, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and a transistor, a semiconductor circuit, and the like are one embodiment of a semiconductor device. An arithmetic device, a storage device, an imaging device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, and the like) and an electronic device may include a semiconductor device.
　トランジスタに適用可能な半導体材料として、酸化物半導体が注目されている。例えば、特許文献１では、複数の酸化物半導体層を積層し、当該複数の酸化物半導体層の中で、チャネルとなる酸化物半導体層の組成がインジウム及びガリウムを含み、且つインジウムの組成をガリウムの組成よりも大きくすることで、電界効果移動度（単に移動度、またはμＦＥという場合がある）を高めた半導体装置が開示されている。 Oxide semiconductors are attracting attention as semiconductor materials applicable to transistors. For example, in Patent Document 1, a plurality of oxide semiconductor layers are stacked, and among the plurality of oxide semiconductor layers, the composition of the oxide semiconductor layer serving as a channel includes indium and gallium, and the composition of indium is gallium. A semiconductor device is disclosed in which the field effect mobility (which may be simply referred to as mobility or μFE) is increased by making the composition larger than the above composition.
　また、非特許文献１では、インジウムと、ガリウムと、亜鉛とを有する酸化物半導体は、Ｉｎ１−ｘＧａ１＋ｘＯ３（ＺｎＯ）ｍ（ｘは−１≦ｘ≦１を満たす数、ｍは自然数）で表されるホモロガス相を有することについて開示されている。また、非特許文献１では、ホモロガス相の固溶域（ｓｏｌｉｄｓｏｌｕｔｉｏｎ　ｒａｎｇｅ）について開示されている。例えば、ｍ＝１の場合のホモロガス相の固溶域は、ｘが−０．３３から０．０８の範囲であり、ｍ＝２の場合のホモロガス相の固溶域は、ｘが−０．６８から０．３２の範囲である。 In Non-Patent Document 1, an oxide semiconductor including indium, gallium, and zinc is In 1-x Ga 1 + x O 3 (ZnO) m (x is a number satisfying −1 ≦ x ≦ 1, m is It is disclosed to have a homologous phase represented by a natural number). Non-Patent Document 1 discloses a solid solution range of a homologous phase. For example, the solid solution region of the homologous phase when m = 1 is in the range of x from −0.33 to 0.08, and the solid solution region of the homologous phase when m = 2 is that x is −0. It is in the range of 68 to 0.32.
特開２０１４−７３９９号公報JP 2014-7399 A
　本発明の一態様は、結晶部を含む金属酸化物膜を提供することを課題の一とする。または、物性の安定性の高い金属酸化物膜を提供することを課題の一とする。または、電気特性が向上した金属酸化物膜を提供することを課題の一とする。または、電界効果移動度を高められる金属酸化物膜を提供することを課題の一とする。または、金属酸化物膜を適用した、信頼性の高い半導体装置を提供することを課題の一とする。 An object of one embodiment of the present invention is to provide a metal oxide film including a crystal part. Another object is to provide a metal oxide film with high stability in physical properties. Another object is to provide a metal oxide film with improved electrical characteristics. Another object is to provide a metal oxide film that can increase field-effect mobility. Another object is to provide a highly reliable semiconductor device to which a metal oxide film is applied.
　また、本発明の一態様は、低温で形成可能で且つ物性の安定性の高い金属酸化物膜を提供することを課題の一とする。または、低温で形成可能で且つ信頼性の高い半導体装置を提供することを課題の一とする。 Another object of one embodiment of the present invention is to provide a metal oxide film that can be formed at a low temperature and has high physical stability. Another object is to provide a highly reliable semiconductor device that can be formed at low temperature.
　または、本発明の一態様は、金属酸化物膜が適用され、可撓性を有する装置を提供することを課題の一とする。 Another object of one embodiment of the present invention is to provide a flexible device to which a metal oxide film is applied.
　なお、これらの課題の記載は、他の課題の存在を妨げるものではない。なお、本発明の一態様は、これらの課題の全てを解決する必要はないものとする。なお、これら以外の課題は、明細書、図面、請求項などの記載から抽出することが可能である。 Note that the description of these issues does not disturb the existence of other issues. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these can be extracted from the description, drawings, claims, and the like.
　本発明の一態様は、インジウム、Ｍ（Ｍは、Ａｌ、Ｇａ、Ｙ、またはＳｎ）、及び亜鉛を含む金属酸化物膜である。また膜面に垂直な方向におけるＸ線回折において、結晶構造に起因した回折強度のピークが観測される領域を有する。さらに１０ｎｍ以上５０ｎｍ以下の厚さに薄片化し、プローブ径を５０ｎｍ以上とした、断面に垂直な方向における電子線回折において、リング状の回折パターンと、リング状の回折パターンと重なる位置に２つの第１のスポットと、を有する第１の電子線回折パターンが観測され、且つプローブ径を０．３ｎｍ以上５ｎｍ以下とした電子線回折において、第１のスポットと、円周方向に分布する複数の第２のスポットと、を有する第２の電子線回折パターンが観測される領域を有する。 One embodiment of the present invention is a metal oxide film containing indium, M (M is Al, Ga, Y, or Sn), and zinc. Further, in X-ray diffraction in a direction perpendicular to the film surface, there is a region where a peak of diffraction intensity due to the crystal structure is observed. Further, in the electron beam diffraction in the direction perpendicular to the cross section where the thickness was reduced to 10 nm or more and 50 nm or less and the probe diameter was 50 nm or more, two ring-shaped diffraction patterns and two positions overlapping with the ring-shaped diffraction pattern were obtained. In an electron beam diffraction in which a first electron beam diffraction pattern having one spot and a probe diameter of 0.3 nm to 5 nm is observed, the first spot and a plurality of first distributions distributed in the circumferential direction are observed. And a region where a second electron beam diffraction pattern having two spots is observed.
　上記において、２つの第１のスポットは、中心に対して対称に観測され、第１のスポットの最も輝度の高い点と、中心とを通る第１の直線と、膜面の法線方向との間の角度が０度以上１０度以下である領域を有することが好ましい。 In the above, the two first spots are observed symmetrically with respect to the center, and the points of the highest brightness of the first spot, the first straight line passing through the center, and the normal direction of the film surface It is preferable to have a region where the angle between them is 0 degree or more and 10 degrees or less.
　また、上記第１の電子線回折パターンにおいて、第１の直線と直交する第２の直線とリング状の回折パターンとの交点における、リング状の回折パターンの輝度が、第１のスポットの輝度よりも小さい領域を有することが好ましい。 In the first electron beam diffraction pattern, the luminance of the ring-shaped diffraction pattern at the intersection of the second straight line orthogonal to the first straight line and the ring-shaped diffraction pattern is greater than the luminance of the first spot. It is preferable to have a small region.
　また、上記第１のスポットの輝度は、第２の直線とリング状の回折パターンとの交点におけるリング状の回折パターンの輝度に対して、１倍よりも大きく、１０倍以下である領域を有することが好ましい。 The first spot has a region in which the luminance of the first spot is greater than 1 and less than 10 times the luminance of the ring-shaped diffraction pattern at the intersection of the second straight line and the ring-shaped diffraction pattern. It is preferable.
　また、断面の透過電子顕微鏡像において、ｃ軸の方向と膜面の方向との間の角度が１０度以下である結晶部が存在する部分を除いた部分の面積の割合が、２５％以上１００未満である領域を有することが好ましい。 In the transmission electron microscope image of the cross section, the area ratio of the portion excluding the portion where the crystal portion where the angle between the c-axis direction and the film surface direction is 10 degrees or less exists is 25% or more and 100 It is preferred to have a region that is less than.
　また、断面のＴＥＭ像に対して高速フーリエ変換した第１の像に対して、周期性を示す範囲を残すマスク処理を施した後に逆フーリエ変換した第２の像において、元の像から残存した像を差し引いた面積の割合が、２５％以上１００未満である領域を有することが好ましい。 In addition, the first image obtained by fast Fourier transform of the cross-sectional TEM image was subjected to mask processing that leaves a range showing periodicity, and the second image obtained by inverse Fourier transform remained from the original image. It is preferable to have a region where the ratio of the area after subtracting the image is 25% or more and less than 100.
　また、上記第１のスポットは、円周方向に広がった形状を有し、第１のスポットの円周方向の２つの端部のそれぞれと、電子線回折パターンの中心とを通る２つの直線の角度が、４５度以内であることが好ましい。 The first spot has a shape spreading in the circumferential direction, and includes two straight lines passing through each of the two ends in the circumferential direction of the first spot and the center of the electron diffraction pattern. The angle is preferably within 45 degrees.
　また、本発明の他の一態様は、半導体層と、ゲート絶縁層と、ゲートと、を有する半導体装置であって、半導体層は、上記金属酸化物膜を含むことを特徴とする。 Another embodiment of the present invention is a semiconductor device including a semiconductor layer, a gate insulating layer, and a gate, and the semiconductor layer includes the metal oxide film.
　本発明の一態様によれば、結晶部を含む金属酸化物膜を提供できる。または、物性の安定性の高い金属酸化物膜を提供できる。または、金属酸化物膜を適用した、信頼性の高い半導体装置を提供できる。 According to one embodiment of the present invention, a metal oxide film including a crystal part can be provided. Alternatively, a metal oxide film with high physical properties can be provided. Alternatively, a highly reliable semiconductor device to which a metal oxide film is applied can be provided.
　また、本発明の一態様によれば、低温で形成可能で且つ物性の安定性の高い金属酸化物膜を提供できる。または、低温で形成可能で且つ信頼性の高い半導体装置を提供できる。 Further, according to one embodiment of the present invention, a metal oxide film that can be formed at a low temperature and has high physical stability can be provided. Alternatively, a highly reliable semiconductor device that can be formed at low temperature can be provided.
　または、本発明の一態様によれば、金属酸化物膜が適用され、可撓性を有する装置を提供できる。 Alternatively, according to one embodiment of the present invention, a metal oxide film is applied to provide a flexible device.
金属酸化物のＸＲＤ測定結果。The XRD measurement result of a metal oxide. 金属酸化物の断面観察像。Cross-sectional observation image of metal oxide. 金属酸化物の電子線回折パターン。Electron diffraction pattern of metal oxide. 金属酸化物の電子線回折パターン。Electron diffraction pattern of metal oxide. 金属酸化物の電子線回折パターン。Electron diffraction pattern of metal oxide. 金属酸化物の電子線回折パターン。Electron diffraction pattern of metal oxide. 金属酸化物の電子線回折パターンと、輝度のプロファイル。Electron diffraction pattern of metal oxide and luminance profile. 金属酸化物の電子線回折パターンから見積もった相対輝度。Relative luminance estimated from electron diffraction pattern of metal oxide. 金属酸化物の電子線回折パターン。Electron diffraction pattern of metal oxide. 金属酸化物の結晶部の配向の揺らぎの測定結果。The measurement result of the fluctuation of the orientation of the crystal part of the metal oxide. 金属酸化物の断面観察像及び画像解析後の断面観察像。Cross-sectional observation image of metal oxide and cross-sectional observation image after image analysis. トランジスタの電気特性。Transistor electrical characteristics. 酸化物半導体膜の原子数比の範囲を説明する図。6A and 6B illustrate a range of the atomic ratio of an oxide semiconductor film. ＩｎＭＺｎＯ４の結晶を説明する図。FIG. 6 illustrates a crystal of InMZnO 4 . 酸化物半導体膜をチャネル領域に用いるトランジスタにおけるエネルギーバンドを説明する図。6A and 6B illustrate energy bands in a transistor in which an oxide semiconductor film is used for a channel region. 半導体装置を説明する上面図及び断面図。8A and 8B are a top view and cross-sectional views illustrating a semiconductor device. 半導体装置を説明する上面図及び断面図。8A and 8B are a top view and cross-sectional views illustrating a semiconductor device. 半導体装置を説明する断面図。FIG. 10 is a cross-sectional view illustrating a semiconductor device. 半導体装置を説明する断面図。FIG. 10 is a cross-sectional view illustrating a semiconductor device. 半導体装置を説明する断面図。FIG. 10 is a cross-sectional view illustrating a semiconductor device. 半導体装置を説明する断面図。FIG. 10 is a cross-sectional view illustrating a semiconductor device. 半導体装置を説明する断面図。FIG. 10 is a cross-sectional view illustrating a semiconductor device. 半導体装置を説明する断面図。FIG. 10 is a cross-sectional view illustrating a semiconductor device. 半導体装置を説明する断面図。FIG. 10 is a cross-sectional view illustrating a semiconductor device. 半導体装置を説明する断面図。FIG. 10 is a cross-sectional view illustrating a semiconductor device. 半導体装置を説明する断面図。FIG. 10 is a cross-sectional view illustrating a semiconductor device. バンド構造を説明する図。The figure explaining a band structure. 半導体装置を説明する上面図及び断面図。8A and 8B are a top view and cross-sectional views illustrating a semiconductor device. 半導体装置を説明する上面図及び断面図。8A and 8B are a top view and cross-sectional views illustrating a semiconductor device. 半導体装置を説明する上面図及び断面図。8A and 8B are a top view and cross-sectional views illustrating a semiconductor device. 半導体装置を説明する上面図及び断面図。8A and 8B are a top view and cross-sectional views illustrating a semiconductor device. 半導体装置を説明する断面図。FIG. 10 is a cross-sectional view illustrating a semiconductor device. 半導体装置を説明する断面図。FIG. 10 is a cross-sectional view illustrating a semiconductor device. 半導体装置を説明する上面図及び断面図。8A and 8B are a top view and cross-sectional views illustrating a semiconductor device. 表示装置の一態様を示す上面図。FIG. 14 is a top view illustrating one embodiment of a display device. 表示装置の一態様を示す断面図。FIG. 14 is a cross-sectional view illustrating one embodiment of a display device. 表示装置の一態様を示す断面図。FIG. 14 is a cross-sectional view illustrating one embodiment of a display device. 表示装置の一態様を示す断面図。FIG. 14 is a cross-sectional view illustrating one embodiment of a display device. ＥＬ層の作製方法を説明する断面図。Sectional drawing explaining the preparation method of EL layer. 液滴吐出装置を説明する概念図。The conceptual diagram explaining a droplet discharge device. 表示装置の一態様を示す断面図。FIG. 14 is a cross-sectional view illustrating one embodiment of a display device. 表示装置の一態様を示す断面図。FIG. 14 is a cross-sectional view illustrating one embodiment of a display device. 表示装置を説明するブロック図及び回路図。10A and 10B are a block diagram and a circuit diagram illustrating a display device. 本発明の一態様を説明するための回路図およびタイミングチャート。6A and 6B are a circuit diagram and a timing chart for illustrating one embodiment of the present invention. 本発明の一態様を説明するためのグラフおよび回路図。5A and 5B are a graph and a circuit diagram for illustrating one embodiment of the present invention. 本発明の一態様を説明するための回路図およびタイミングチャート。6A and 6B are a circuit diagram and a timing chart for illustrating one embodiment of the present invention. 本発明の一態様を説明するための回路図およびタイミングチャート。6A and 6B are a circuit diagram and a timing chart for illustrating one embodiment of the present invention. 本発明の一態様を説明するためのブロック図、回路図および波形図。4A and 4B are a block diagram, a circuit diagram, and a waveform diagram for illustrating one embodiment of the present invention. 本発明の一態様を説明するための回路図およびタイミングチャート。6A and 6B are a circuit diagram and a timing chart for illustrating one embodiment of the present invention. 本発明の一態様を説明するための回路図。FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. 本発明の一態様を説明するための回路図。FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. 表示モジュールを説明する図。The figure explaining a display module. 電子機器を説明する図。10A and 10B each illustrate an electronic device. 電子機器を説明する図。10A and 10B each illustrate an electronic device. 表示装置を説明する斜視図。FIG. 14 is a perspective view illustrating a display device.
　実施の形態について、図面を用いて詳細に説明する。但し、本発明は以下の説明に限定されず、本発明の趣旨及びその範囲から逸脱することなくその形態及び詳細を様々に変更し得ることは当業者であれば容易に理解される。従って、本発明は以下に示す実施の形態の記載内容に限定して解釈されるものではない。 Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.
　なお、以下に説明する発明の構成において、同一部分又は同様な機能を有する部分には同一の符号を異なる図面間で共通して用い、その繰り返しの説明は省略する。また、同様の機能を指す場合には、ハッチパターンを同じくし、特に符号を付さない場合がある。 Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated. In addition, in the case where the same function is indicated, the hatch pattern is the same, and there is a case where no reference numeral is given.
　なお、本明細書で説明する各図において、各構成の大きさ、層の厚さ、または領域は、明瞭化のために誇張されている場合がある。よって、必ずしもそのスケールに限定されない。 Note that in each drawing described in this specification, the size, the layer thickness, or the region of each component is exaggerated for clarity in some cases. Therefore, it is not necessarily limited to the scale.
　なお、本明細書等における「第１」、「第２」等の序数詞は、構成要素の混同を避けるために付すものであり、数的に限定するものではない。 In addition, ordinal numbers such as “first” and “second” in this specification and the like are attached to avoid confusion between components and are not limited numerically.
　トランジスタは半導体素子の一種であり、電流や電圧の増幅や、導通または非導通を制御するスイッチング動作などを実現することができる。本明細書におけるトランジスタは、ＩＧＦＥＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）や薄膜トランジスタ（ＴＦＴ：Ｔｈｉｎ　Ｆｉｌｍ　Ｔｒａｎｓｉｓｔｏｒ）を含む。 A transistor is a kind of semiconductor element, and can realize amplification of current and voltage, switching operation for controlling conduction or non-conduction, and the like. The transistors in this specification include an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT: Thin Film Transistor).
　また、「ソース」や「ドレイン」の機能は、異なる極性のトランジスタを採用する場合や、回路動作において電流の方向が変化する場合などには入れ替わることがある。このため、本明細書においては、「ソース」や「ドレイン」の用語は、入れ替えて用いることができるものとする。 Also, the functions of “source” and “drain” may be interchanged when transistors having different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.
（実施の形態１）
　本発明の一態様は、２種類の結晶部を含む金属酸化物膜である。結晶部の一（第１の結晶部ともいう）は、膜の厚さ方向（膜面方向、膜の被形成面、または膜の表面に垂直な方向ともいう）に配向性を有する結晶部である。結晶部の他の一（第２の結晶部ともいう）は、特定の配向性を有さずに様々な向きに配向する結晶部である。本発明の一態様の金属酸化物膜には、このような２種類の結晶部が混在して含まれている。 (Embodiment 1)
One embodiment of the present invention is a metal oxide film including two kinds of crystal parts. One of the crystal parts (also referred to as a first crystal part) is a crystal part having orientation in a film thickness direction (also referred to as a film surface direction, a film formation surface, or a direction perpendicular to the film surface). is there. Another of the crystal parts (also referred to as a second crystal part) is a crystal part that is oriented in various directions without having a specific orientation. The metal oxide film of one embodiment of the present invention includes such a mixture of two kinds of crystal parts.
　なおここでは説明を容易にするために、特定の配向性を有する結晶部を第１の結晶部、配向性を有さない結晶部を第２の結晶部と分けて説明しているが、これらは結晶性や結晶の大きさなどに違いがなく区別できない場合がある。そのため、本発明の一態様の金属酸化物膜はこれらを区別せずに表現することもできる。すなわち、本発明の一態様の金属酸化物膜は、複数の結晶部を有し、そのうち、膜の表面に垂直な方向に配向性を有する結晶部が、他の方向に配向する結晶部よりも多く存在する膜とも言い換えることができる。 Here, for ease of explanation, the crystal part having a specific orientation is described separately from the first crystal part, and the crystal part having no orientation is described separately from the second crystal part. May be indistinguishable due to differences in crystallinity and crystal size. Therefore, the metal oxide film of one embodiment of the present invention can be expressed without distinction. That is, the metal oxide film of one embodiment of the present invention includes a plurality of crystal parts, and of these, a crystal part having orientation in a direction perpendicular to the surface of the film is more than a crystal part oriented in another direction. It can be paraphrased as a film that exists in large numbers.
　第１の結晶部は、特定の結晶面が膜の厚さ方向に対して配向性を有する。そのため、このような第１の結晶部を含む金属酸化物膜について、膜の上面に概略垂直な方向に対するＸ線回折（ＸＲＤ：Ｘ−ｒａｙ　Ｄｉｆｆｒａｃｔｉｏｎ）測定を行うと、所定の回折角（２θ）に当該第１の結晶部に由来する回折ピークが確認される。なお回折ピークの高さ（強度）は、膜中に含まれる第１の結晶部の存在割合が高いほど大きくなり、膜の結晶性を推し量る指標にもなりえる。 In the first crystal part, a specific crystal plane has orientation with respect to the thickness direction of the film. Therefore, when X-ray diffraction (XRD) measurement in a direction substantially perpendicular to the top surface of the metal oxide film including the first crystal part is performed, a predetermined diffraction angle (2θ) A diffraction peak derived from the first crystal part is confirmed. Note that the height (intensity) of the diffraction peak increases as the proportion of the first crystal portion included in the film increases, and can be an index for estimating the crystallinity of the film.
　また、本発明の一態様の金属酸化物膜は、膜の断面に垂直な方向に対する電子線回折測定を行うと、第１の結晶部に起因する電子線回折パターンと、第２の結晶部に起因する電子線回折パターンとが混在した回折パターンが得られる。 In addition, when the metal oxide film of one embodiment of the present invention is subjected to electron beam diffraction measurement in a direction perpendicular to the cross section of the film, an electron beam diffraction pattern caused by the first crystal part and a second crystal part are formed. A diffraction pattern in which the resulting electron beam diffraction pattern is mixed is obtained.
　第１の結晶部に起因する電子線回折パターンは、結晶性に由来する明確なスポットが確認される。また当該スポットは、膜の厚さ方向に対して配向性を有する。 In the electron diffraction pattern caused by the first crystal part, a clear spot derived from crystallinity is confirmed. The spot has orientation with respect to the thickness direction of the film.
　一方、第２の結晶部は、あらゆる向きに無秩序に配向するように、膜中に存在する結晶部である。そのため電子線回折に用いる電子ビームの径（プローブ径）、すなわち観察する領域の面積によって、以下のように異なる像が確認される。 On the other hand, the second crystal part is a crystal part existing in the film so as to be randomly oriented in all directions. Therefore, different images are confirmed as follows depending on the diameter of the electron beam (probe diameter) used for electron beam diffraction, that is, the area of the region to be observed.
　電子ビームの径（プローブ径）を十分に大きくした条件（例えば２５ｎｍΦ以上、または５０ｎｍΦ以上）の電子線回折（制限視野電子線回折、ＳＡＥＤ：Ｓｅｌｅｃｔｅｄ　Ａｒｅａ　Ｅｌｅｃｔｒｏｎ　Ｄｉｆｆｒａｃｔｉｏｎともいう）像ではリング状のパターンが確認される。また当該リング状のパターンは、動径方向に輝度の分布を有する場合がある。制限視野電子線回折は、電子線回折の一つであり、照射領域を絞って微小領域に平行電子線を照射するものである。 An electron beam diffraction (restricted field electron diffraction, SAED: also called Selected Area Electron Diffraction) image with a sufficiently large electron beam diameter (probe diameter) (for example, 25 nmΦ or more, or 50 nmΦ or more) has a ring-shaped pattern. It is confirmed. In addition, the ring-shaped pattern may have a luminance distribution in the radial direction. The limited-field electron beam diffraction is one of electron beam diffractions, in which an irradiation region is narrowed and a parallel region is irradiated with a parallel electron beam.
　一方、電子ビームの径（プローブ径）を十分に小さくした条件（例えば０．３ｎｍ以上且つ１０ｎｍΦ以下または５ｎｍ以下）の電子線回折（ナノビーム電子回折、ＮＢＥＤ：Ｎａｎｏ　Ｂｅａｍ　Ｅｌｅｃｔｒｏｎ　Ｄｉｆｆｒａｃｔｉｏｎともいう）像では、制限視野電子線回折パターンで見られたリング状のパターンの位置に、円周方向（θ方向ともいう）に分布した複数のスポットが確認される。すなわち、制限視野電子線回折パターンにおいてみられる上記リング状のパターンは、当該スポットの集合体により形成されていることが確認できる。ナノビーム電子回折は、電子線回折の中でも収束電子線回折の一つであり、電子ビームを収束させて試料に照射するものである。 On the other hand, in an electron beam diffraction (nanobeam electron diffraction, NBED: also called Nano Beam Electron Diffraction) image under conditions where the electron beam diameter (probe diameter) is sufficiently small (for example, 0.3 nm to 10 nmΦ or 5 nm or less) A plurality of spots distributed in the circumferential direction (also referred to as the θ direction) are confirmed at the position of the ring-shaped pattern seen in the limited-field electron diffraction pattern. That is, it can be confirmed that the ring-shaped pattern seen in the limited-field electron diffraction pattern is formed by the aggregate of the spots. Nanobeam electron diffraction is one type of convergent electron beam diffraction among electron beam diffractions, and converges an electron beam and irradiates a sample.
　本発明の一態様の金属酸化物膜は、断面の制限視野電子線回折パターンにおいて、第１の結晶部に由来する第１のスポットと、第２の結晶部に由来するリング状のパターンが混在した回折パターンが確認される。また金属酸化物膜は、断面のナノビーム電子回折パターンにおいて、第１の結晶部に由来する第１のスポットと、第２の結晶部に由来し、円周方向に沿って散在した複数の第２のスポットが混在した回折パターンが確認される。 In the metal-oxide film of one embodiment of the present invention, the first spot derived from the first crystal portion and the ring-shaped pattern derived from the second crystal portion are mixed in the limited-field electron diffraction pattern of the cross section. Confirmed diffraction pattern. Further, the metal oxide film has a plurality of second spots that are derived from the first spot derived from the first crystal part and the second crystal part and scattered along the circumferential direction in the nanobeam electron diffraction pattern of the cross section. A diffraction pattern with mixed spots is confirmed.
　また金属酸化物膜の制限視野電子線回折パターンにおいて、第１のスポットと、リングとは動径方向において重なって位置する。またナノビーム電子回折パターンにおいて、第１のスポットと、第２のスポットとは動径方向において重なって位置する。 In the limited-field electron diffraction pattern of the metal oxide film, the first spot and the ring are positioned so as to overlap in the radial direction. In the nanobeam electron diffraction pattern, the first spot and the second spot are positioned so as to overlap in the radial direction.
　また、第１の結晶部に由来する第１のスポットは、結晶のｃ軸に垂直な結晶面に由来する回折スポットである。結晶構造がｃ軸に垂直な方向に２回対称性を有する場合、第１のスポットは電子線回折パターンの中心に対して対称に２つ観測される。なお電子線回折パターンには、この第１のスポット以外にも、ｃ軸に垂直な結晶面に由来する他のスポット、及びｃ軸に垂直な結晶面以外の結晶面に由来する回折スポットが観察される場合もある。 In addition, the first spot derived from the first crystal part is a diffraction spot derived from a crystal plane perpendicular to the c-axis of the crystal. When the crystal structure has two-fold symmetry in the direction perpendicular to the c-axis, two first spots are observed symmetrically with respect to the center of the electron beam diffraction pattern. In addition to the first spot, in the electron diffraction pattern, other spots derived from the crystal plane perpendicular to the c-axis and diffraction spots derived from crystal planes other than the crystal plane perpendicular to the c-axis are observed. Sometimes it is done.
　また、リングと第１のスポットとが動径方向において重なる場合、リングを構成する複数の第２のスポットは、それぞれ異なる向きに配向する結晶部の、ｃ軸に垂直な結晶面に由来する回折スポットであると理解できる。 Further, when the ring and the first spot overlap in the radial direction, the plurality of second spots constituting the ring are diffracted from crystal planes perpendicular to the c-axis of crystal parts oriented in different directions. Can be understood as a spot.
　また、金属酸化物膜の制限視野電子線回折パターンにおいて、径の異なる２つのリング状のパターン（内側から第１のリング、第２のリングとする）が観察される場合がある。このとき、第１の結晶部に由来する第１のスポットは、内側に位置するリング（第１のリング）と重なって位置する。また、第２のリングと重なる位置に、第１の結晶部に由来する他のスポットが観察される場合もある。 Also, in the limited-field electron diffraction pattern of the metal oxide film, two ring patterns with different diameters (referred to as the first ring and the second ring from the inside) may be observed. At this time, the first spot derived from the first crystal portion is positioned so as to overlap with the ring (first ring) positioned inside. In addition, another spot derived from the first crystal part may be observed at a position overlapping the second ring.
　ここで、金属酸化物膜中における、配向性を有する第１の結晶部の存在割合が高い場合、得られる電子線回折パターンはより異方性の高いパターンが支配的となる。例えば、制限視野電子線回折パターンにおいて、第１の結晶部に由来する第１のスポットの輝度に対して、第１のリング及び第２のリングの輝度が相対的に低くなる。またこのとき、外側に位置する第２のリングと重なる位置に、第１の結晶部に由来する異なるスポット（第３のスポット）が観察される場合もある。ここで第３のスポットと第２のリングとは、動径方向において重なるため、それぞれ同じ結晶面からの回折に由来すると推察できる。 Here, when the presence ratio of the first crystal part having orientation in the metal oxide film is high, a pattern with higher anisotropy is dominant in the obtained electron beam diffraction pattern. For example, in the limited-field electron beam diffraction pattern, the luminance of the first ring and the second ring is relatively lower than the luminance of the first spot derived from the first crystal part. At this time, a different spot (third spot) derived from the first crystal part may be observed at a position overlapping the second ring located outside. Here, since the third spot and the second ring overlap in the radial direction, it can be inferred that they originate from diffraction from the same crystal plane.
　ここで、ナノビーム電子回折パターンにおける第２の結晶部に起因した第２のスポットの輝度（回折強度）は、上記第１の結晶部に起因する第１のスポットの輝度よりも小さい。この輝度の差は、金属酸化物膜中の第１の結晶部の存在割合が高いほど大きくなり、金属酸化物膜の結晶性を推し量る指標にもなる。例えば第１のスポットの輝度が第２のスポットの輝度に対して、１倍よりも大きく以上１０倍以下であることが好ましい。 Here, the brightness (diffraction intensity) of the second spot caused by the second crystal part in the nanobeam electron diffraction pattern is smaller than the brightness of the first spot caused by the first crystal part. This difference in luminance increases as the proportion of the first crystal portion in the metal oxide film increases, and it becomes an index for estimating the crystallinity of the metal oxide film. For example, it is preferable that the brightness of the first spot is greater than 1 time and 10 times or less than the brightness of the second spot.
　本発明の一態様の金属酸化物膜は、インジウム、Ｍ（Ｍは、Ａｌ、Ｇａ、Ｙ、またはＳｎ）、及び亜鉛を含む酸化物膜である。このような酸化物膜はｃ軸に沿って層状構造を有する結晶構造を取るという特徴を有する。またこのような酸化物膜は、半導体特性を備える特徴を有する。 The metal oxide film of one embodiment of the present invention is an oxide film containing indium, M (M is Al, Ga, Y, or Sn), and zinc. Such an oxide film has a feature of taking a crystal structure having a layered structure along the c-axis. Further, such an oxide film has a characteristic of having semiconductor characteristics.
　本発明の一態様の金属酸化物膜は、トランジスタのチャネルが形成される半導体に適用することができる。 The metal oxide film of one embodiment of the present invention can be applied to a semiconductor in which a channel of a transistor is formed.
　配向性を有する第１の結晶部と配向性を有さない第２の結晶部が混在した金属酸化物膜を適用したトランジスタは、配向性を有さない第２の結晶部のみで構成される金属酸化物膜を適用したトランジスタと比較して、電気特性の安定性を高くできる、チャネル長を微細にすることが容易となる、などの特徴がある。 A transistor to which a metal oxide film in which a first crystal part having orientation and a second crystal part having no orientation are mixed is composed of only the second crystal part having no orientation. Compared with a transistor to which a metal oxide film is applied, the electrical characteristics can be increased and the channel length can be easily reduced.
　また、配向性を有する第１の結晶部と配向性を有さない第２の結晶部が混在した金属酸化物膜を適用したトランジスタは、配向性を有する第１の結晶部の存在割合が極めて高い（例えば７５％より大きい）金属酸化物膜を適用したトランジスタと比較して、特にゲート電圧が低い条件での電界効果移動度を高くできる。そのためデバイスの駆動電圧を低電圧化できる、高周波駆動が容易となる、などの特徴がある。 In addition, a transistor using a metal oxide film in which a first crystal part having orientation and a second crystal part not having orientation are mixed has a very high proportion of the first crystal part having orientation. Compared with a transistor to which a high (eg, greater than 75%) metal oxide film is applied, field effect mobility can be increased particularly under a low gate voltage. Therefore, there are features such that the drive voltage of the device can be lowered and high-frequency driving is facilitated.
　以下では、より具体的な例を示しながら本発明の一態様について説明する。 Hereinafter, one embodiment of the present invention will be described with a more specific example.
［金属酸化物］
　本発明の一態様の金属酸化物膜は、インジウム（Ｉｎ）と、Ｍ（ＭはＡｌ、Ｇａ、Ｙ、またはＳｎ）と、亜鉛（Ｚｎ）と、を有する。特に、Ｍはガリウム（Ｇａ）であると好ましい。 [Metal oxide]
The metal oxide film of one embodiment of the present invention includes indium (In), M (M is Al, Ga, Y, or Sn), and zinc (Zn). In particular, M is preferably gallium (Ga).
　金属酸化物膜がＩｎを有すると、例えばキャリア移動度（電子移動度）が高くなる。また、金属酸化物膜がＧａを有すると、例えば金属酸化物膜のエネルギーギャップ（Ｅｇ）が大きくなる。なお、Ｇａは、酸素との結合エネルギーが高い元素であり、酸素との結合エネルギーがＩｎよりも高い。また、金属酸化物膜がＺｎを有すると、金属酸化物膜の結晶化が起こり易い。 When the metal oxide film contains In, for example, carrier mobility (electron mobility) increases. Further, when the metal oxide film contains Ga, for example, the energy gap (Eg) of the metal oxide film is increased. Note that Ga is an element having a high binding energy with oxygen, and has a higher binding energy with oxygen than In. In addition, when the metal oxide film contains Zn, the metal oxide film is easily crystallized.
　なお、本発明の一態様の金属酸化物膜としては、単一相、特にホモロガス相を示す結晶構造を有すると好適である。例えば、金属酸化物膜を、Ｉｎ１＋ｘＭ１−ｘＯ３（ＺｎＯ）ｙ（ｘは０＜ｘ＜０．５を満たす数、ｙは１近傍を表す。）構造の組成とし、ＭよりもＩｎの含有率を多くすることで、金属酸化物膜のキャリア移動度（電子移動度）を高くすることができる。 Note that the metal oxide film of one embodiment of the present invention preferably has a crystal structure exhibiting a single phase, particularly a homologous phase. For example, the metal oxide film has a composition of In 1 + x M 1-x O 3 (ZnO) y (x is a number satisfying 0 <x <0.5, and y is near 1). By increasing the In content, the carrier mobility (electron mobility) of the metal oxide film can be increased.
　特に、本発明の一態様の金属酸化物膜は、Ｉｎ１＋ｘＭ１−ｘＯ３（ＺｎＯ）ｙ（ｘは０＜ｘ＜０．５を満たす数、ｙは１近傍を表す。）構造の中でも、Ｉｎ：Ｍ：Ｚｎ＝１．３３：０．６７：１（概ねＩｎ：Ｍ：Ｚｎ＝４：２：３）近傍の組成とすることが好ましい。このような組成の金属酸化物膜は、高いキャリア移動度と、高い膜の安定性を兼ね備えることができる。 In particular, the metal oxide film of one embodiment of the present invention has a structure of In 1 + x M 1-x O 3 (ZnO) y (x represents a number satisfying 0 <x <0.5, and y represents 1 vicinity). Especially, it is preferable to set it as the composition of In: M: Zn = 1.33: 0.67: 1 (generally In: M: Zn = 4: 2: 3) vicinity. A metal oxide film having such a composition can have both high carrier mobility and high film stability.
　なお、金属酸化物膜の組成はこれに限られず、層状の結晶構造を取り得る組成であればよい。 Note that the composition of the metal oxide film is not limited to this, and may be any composition that can take a layered crystal structure.
　なお、本明細書等において、近傍とは、ある金属原子の原子数比に対して、プラス・マイナス１以内、さらに好ましくはプラス・マイナス０．５以内の範囲とすればよい。例えば、酸化物半導体膜の組成がＩｎ：Ｇａ：Ｚｎ＝４：２：３であり、Ｉｎが４の場合、Ｇａが１以上３以下（１≦Ｇａ≦３）であり、且つＺｎが２以上４以下（２≦Ｚｎ≦４）、好ましくはＧａが１．５以上２．５以下（１．５≦Ｇａ≦２．５）であり、且つＺｎが２以上４以下（２≦Ｚｎ≦４）であればよい。 In this specification and the like, the vicinity may be within a range of plus or minus 1 and more preferably within a plus or minus 0.5 with respect to the atomic ratio of a certain metal atom. For example, when the composition of the oxide semiconductor film is In: Ga: Zn = 4: 2: 3 and In is 4, Ga is 1 to 3 (1 ≦ Ga ≦ 3) and Zn is 2 or more 4 or less (2 ≦ Zn ≦ 4), preferably Ga is 1.5 or more and 2.5 or less (1.5 ≦ Ga ≦ 2.5), and Zn is 2 or more and 4 or less (2 ≦ Zn ≦ 4) If it is.
［金属酸化物膜の形成］
　以下では、条件の異なる３つの金属酸化物膜が形成された試料を作製した。まず、試料１乃至試料４の作製方法について、説明する。 [Formation of metal oxide film]
Below, the sample in which three metal oxide films with different conditions were formed was produced. First, a method for manufacturing Sample 1 to Sample 4 will be described.
〔試料１〕
　試料１は、ガラス基板上に厚さ約１００ｎｍのインジウムと、ガリウムと、亜鉛とを有する金属酸化物膜が成膜された試料である。試料１の金属酸化物膜は、基板を１３０℃に加熱し、流量１８０ｓｃｃｍのアルゴンガスと流量２０ｓｃｃｍの酸素ガスとをスパッタリング装置のチャンバー内に導入し、圧力を０．６Ｐａとし、インジウムと、ガリウムと、亜鉛とを有する金属酸化物ターゲット（Ｉｎ：Ｇａ：Ｚｎ＝４：２：４．１［原子数比］）に、２．５ｋｗの交流電力を印加することで形成した。上述のガス流量比は、全体のガス流量に対する酸素流量の割合から、酸素流量比と記載する場合がある。このとき、試料１の作製条件における酸素流量比は１０％である。 [Sample 1]
Sample 1 is a sample in which a metal oxide film including indium, gallium, and zinc having a thickness of about 100 nm is formed over a glass substrate. In the metal oxide film of Sample 1, the substrate is heated to 130 ° C., argon gas with a flow rate of 180 sccm and oxygen gas with a flow rate of 20 sccm are introduced into the chamber of the sputtering apparatus, the pressure is 0.6 Pa, indium, and gallium. And a metal oxide target (In: Ga: Zn = 4: 2: 4.1 [atomic number ratio]) containing zinc and 2.5 kw of alternating current power. The above gas flow ratio may be described as an oxygen flow ratio from the ratio of the oxygen flow rate to the total gas flow rate. At this time, the oxygen flow ratio in the production conditions of the sample 1 is 10%.
〔試料２〕
　試料２は、ガラス基板上に厚さ約１００ｎｍの金属酸化物膜が成膜された試料である。試料２の金属酸化物膜は、基板を１７０℃に加熱し、基板温度以外の条件は試料１と同様の条件で形成した。試料２の作製条件における酸素流量比は１０％である。 [Sample 2]
Sample 2 is a sample in which a metal oxide film having a thickness of about 100 nm is formed on a glass substrate. The metal oxide film of Sample 2 was formed under the same conditions as Sample 1 except that the substrate was heated to 170 ° C. and conditions other than the substrate temperature. The oxygen flow rate ratio under the production conditions of Sample 2 is 10%.
〔試料３〕
　試料３は、ガラス基板上に厚さ約１００ｎｍの金属酸化物膜が成膜された試料である。試料３の金属酸化物膜は、基板を１７０℃に加熱し、流量１４０ｓｃｃｍのアルゴンガスと、流量６０ｓｃｃｍの酸素ガスとをスパッタリング装置のチャンバー内に導入し、基板温度とガス流量比以外は試料１と同様の条件で形成した。試料３の作製条件における酸素流量比は３０％である。 [Sample 3]
Sample 3 is a sample in which a metal oxide film having a thickness of about 100 nm is formed on a glass substrate. In the metal oxide film of sample 3, the substrate is heated to 170 ° C., argon gas having a flow rate of 140 sccm and oxygen gas having a flow rate of 60 sccm are introduced into the chamber of the sputtering apparatus. Formed under the same conditions. The oxygen flow rate ratio under the production conditions of Sample 3 is 30%.
〔試料４〕
　試料４は、ガラス基板上に厚さ約１００ｎｍの金属酸化物が成膜された試料である。試料４の金属酸化物膜は、基板を加熱せずに、流量２０ｓｃｃｍのアルゴンガスと流量１０ｓｃｃｍの酸素ガスとをスパッタリング装置のチャンバー内に導入し、圧力を０．４Ｐａとし、インジウムと、ガリウムと、亜鉛とを有する金属酸化物ターゲット（Ｉｎ：Ｇａ：Ｚｎ＝１：１：１［原子数比］）に、０．２ｋｗ交流電力を印加することで形成した。試料４の作製条件における酸素流量比は３３％である。 [Sample 4]
Sample 4 is a sample in which a metal oxide having a thickness of about 100 nm is formed on a glass substrate. In the metal oxide film of Sample 4, an argon gas having a flow rate of 20 sccm and an oxygen gas having a flow rate of 10 sccm were introduced into a sputtering apparatus chamber without heating the substrate, the pressure was set to 0.4 Pa, indium, gallium, And 0.2 kw alternating current power was applied to a metal oxide target (In: Ga: Zn = 1: 1: 1 [atomic ratio]) having zinc. The oxygen flow rate ratio under the production conditions of Sample 4 is 33%.
［Ｘ線回折測定］
　図１（Ａ）、（Ｂ）、（Ｃ）に、試料１乃至試料３についてＸＲＤ測定を行った結果を示す。ここでは、ｏｕｔ−ｏｆ−ｐｌａｎｅ法の一種である粉末法（θ−２θ法ともいう。）を用いて測定した。θー２θ法は、Ｘ線の入射角を変化させるとともに、Ｘ線源に対向して設けられる検出器の角度を入射角と同じにしてＸ線回折強度を測定する方法である。なお、Ｘ線を膜表面から約０．４０°の角度から入射し、検出器の角度を変化させてＸ線回折強度を測定するｏｕｔ−ｏｆ−ｐｌａｎｅ法の一種であるＧＩＸＲＤ（Ｇｒａｚｉｎｇ−Ｉｎｃｉｄｅｎｃｅ　ＸＲＤ）法（薄膜法またはＳｅｅｍａｎｎ−Ｂｏｈｌｉｎ法ともいう。）を用いてもよい。図１の各図における横軸は角度２θであり、縦軸は回折強度を任意単位で示している。 [X-ray diffraction measurement]
FIGS. 1A, 1B, and 1C show the results of XRD measurement performed on samples 1 to 3. FIG. Here, measurement was performed using a powder method (also referred to as a θ-2θ method) which is a kind of out-of-plane method. The θ-2θ method is a method of measuring the X-ray diffraction intensity by changing the incident angle of the X-ray and setting the angle of the detector provided facing the X-ray source to be the same as the incident angle. Note that GIXRD (Grazing-Incidence XRD) is a kind of out-of-plane method in which X-rays are incident from the film surface at an angle of about 0.40 ° and the X-ray diffraction intensity is measured by changing the angle of the detector. ) Method (also referred to as a thin film method or a Seemann-Bohlin method) may be used. In each figure of FIG. 1, the horizontal axis represents the angle 2θ, and the vertical axis represents the diffraction intensity in arbitrary units.
　図１の各図に示すように、いずれの試料においても２θ＝３１°付近に回折強度のピークが確認された。またピーク強度は試料３、試料２、試料１の順で高い結果となった。 As shown in each figure of FIG. 1, a peak of diffraction intensity was confirmed in the vicinity of 2θ = 31 ° in any sample. The peak intensity was higher in the order of sample 3, sample 2, and sample 1.
　回折強度のピークがみられた回折角（２θ＝３１°付近）は、単結晶ＩｎＧａＺｎＯ４の構造モデルにおける（００９）面の回折角と一致する。したがってこのピークが観測されることから、いずれの試料においてもｃ軸が膜厚方向に配向する結晶部（以下、配向性を有する結晶部、または第１の結晶部ともいう）が含まれていることが確認できる。また強度の比較から、配向性を有する結晶部の存在割合が、試料３、試料２、試料１の順で高いことがわかる。 The diffraction angle at which the peak of diffraction intensity was observed (2θ = around 31 °) coincides with the diffraction angle of the (009) plane in the structural model of single crystal InGaZnO 4 . Therefore, since this peak is observed, any sample includes a crystal part in which the c-axis is oriented in the film thickness direction (hereinafter also referred to as an oriented crystal part or a first crystal part). I can confirm that. In addition, it can be seen from the comparison of the strength that the proportion of crystal parts having orientation is higher in the order of Sample 3, Sample 2, and Sample 1.
　この結果から、成膜時の基板温度が高いほど、また酸素流量比が大きいほど、配向性を有する結晶部の存在割合が高くなる傾向が確認できた。 From this result, it was confirmed that the higher the substrate temperature during film formation and the larger the oxygen flow rate ratio, the higher the proportion of crystal parts having orientation.
［断面観察］
　図２（Ａ）~（Ｃ）は、それぞれ試料１乃至試料３における、透過型電子顕微鏡（ＴＥＭ：Ｔｒａｎｓｍｉｓｓｉｏｎ　Ｅｌｅｃｔｒｏｎ　Ｍｉｃｒｏｓｃｏｐｙ）像である。 [Section observation]
2A to 2C are transmission electron microscope (TEM) images of Sample 1 to Sample 3, respectively.
　試料２及び試料３では、原子が膜厚方向に層状に配列している結晶部が観察される。また試料２よりも試料３の方が、より膜厚方向に配向している領域の割合が多いように見える。一方試料１では、原子が周期的に配列する領域はあるものの、膜厚方向へ配向している結晶部の割合は、試料２及び試料３に比べると多くない。 In sample 2 and sample 3, a crystal part in which atoms are arranged in layers in the film thickness direction is observed. Further, it seems that the ratio of the region oriented in the film thickness direction is larger in the sample 3 than in the sample 2. On the other hand, in Sample 1, although there are regions where atoms are periodically arranged, the proportion of crystal parts oriented in the film thickness direction is not as large as in Sample 2 and Sample 3.
［電子線回折］
　続いて、試料１乃至試料４について、電子線回折測定を行った結果について説明する。電子線回折測定は、試料の断面に対して電子線を垂直に入射したときの電子線回折パターンを取得した。また電子線はビーム径が１ｎｍから１００ｎｍまで変化させて測定した。また試料の厚さは約５０ｎｍとした。 [Electron diffraction]
Subsequently, the results of electron beam diffraction measurement performed on samples 1 to 4 will be described. In the electron beam diffraction measurement, an electron beam diffraction pattern was obtained when the electron beam was incident perpendicularly to the cross section of the sample. The electron beam was measured by changing the beam diameter from 1 nm to 100 nm. The thickness of the sample was about 50 nm.
　以降で、各試料における電子線回折パターンを示すが、ここで示す電子線回折パターンは、明瞭化のために、回折パターンが明瞭になるようにコントラストを調整したものである。また、以降に示す回折パターンの輝度解析においては、図に示すコントラストを調整した画像データではなく、調整をしていないを用いている。 Hereinafter, the electron beam diffraction pattern of each sample is shown. For the sake of clarity, the electron beam diffraction pattern shown here is obtained by adjusting the contrast so that the diffraction pattern becomes clear. Further, in the luminance analysis of the diffraction pattern shown below, not adjusted image data but not adjusted image data shown in the figure is used.
　ここで、電子線回折に用いる試料の厚さについて説明する。電子線回折において、入射する電子線の径だけでなく、試料の厚さが厚いほど、電子線回折パターンには、その奥行き方向の情報が現れることとなる。そのため、電子線の径（プローブ径）を小さくするだけでなく、試料を薄くすることで、より局所的な領域の情報を得ることができる。一方で、試料が薄すぎる場合、例えば５ｎｍ以下の厚さの場合には、極微細な領域の情報しか得られないため、その領域に極微細な結晶が存在していた場合には、得られる電子線回折パターンは、単結晶のものと同様のパターンとなる場合がある。極微細な領域を解析する目的でない場合には、試料の厚さは、例えば１０ｎｍ以上１００ｎｍ以下、代表的には１０ｎｍ以上５０ｎｍ以下とすることが好ましい。 Here, the thickness of the sample used for electron beam diffraction will be described. In electron diffraction, not only the diameter of the incident electron beam but also the thickness of the sample, the more information in the depth direction appears in the electron diffraction pattern. Therefore, not only the diameter of the electron beam (probe diameter) is reduced, but also information on a more local area can be obtained by making the sample thinner. On the other hand, when the sample is too thin, for example, when the thickness is 5 nm or less, only information on a very fine region can be obtained. The electron beam diffraction pattern may be a pattern similar to that of a single crystal. If the purpose is not to analyze an extremely fine region, the thickness of the sample is preferably 10 nm to 100 nm, typically 10 nm to 50 nm.
〔試料１〕
　図３（Ａ）、（Ｂ）に試料１の電子線回折パターンを示す。図３（Ａ）、（Ｂ）はそれぞれ、ビーム径を１００ｎｍ、１ｎｍとしたときの電子線回折パターンである。図３（Ａ）、（Ｂ）において、中央の最も明るい輝点は入射される電子線ビームによるものであり、電子線回折パターンの中心（ダイレクトスポットともいう）である。 [Sample 1]
3A and 3B show the electron diffraction patterns of Sample 1. FIG. 3A and 3B are electron beam diffraction patterns when the beam diameter is 100 nm and 1 nm, respectively. In FIGS. 3A and 3B, the brightest bright spot at the center is due to the incident electron beam, and is the center (also referred to as a direct spot) of the electron diffraction pattern.
　図３（Ａ）において、半径の異なる２つのリング状の回折パターンが確認できる。ここで、径の小さいほうから第１のリング、第２のリングと呼ぶこととする。第２のリングに比べて、第１のリングの方が輝度が高いことが確認できる。また、第１のリングと重なる位置に、矢印で示す２つのスポット（第１のスポット）が確認される。 In FIG. 3A, two ring-shaped diffraction patterns having different radii can be confirmed. Here, the first ring and the second ring are referred to from the smaller diameter. It can be confirmed that the brightness of the first ring is higher than that of the second ring. Further, two spots (first spots) indicated by arrows are confirmed at positions overlapping the first ring.
　第１のリング及び２つの第１のスポットの中心からの動径方向の距離は、単結晶ＩｎＧａＺｎＯ４の構造モデルにおける（００９）面の回折スポットの中心からの動径方向の距離とほぼ一致する。 The radial distance from the center of the first ring and the two first spots substantially coincides with the radial distance from the center of the diffraction spot on the (009) plane in the structural model of single crystal InGaZnO 4. .
　リング状の回折パターンが見られていることから、金属酸化物膜中には、あらゆる向きに配向している結晶部（以下、配向性を有さない結晶部、または第２の結晶部ともいう）が存在することが確認できる。 Since a ring-shaped diffraction pattern is observed, in the metal oxide film, crystal parts that are oriented in all directions (hereinafter also referred to as crystal parts having no orientation or second crystal parts). ) Can be confirmed.
　また２つの第１のスポットは、電子線回折パターンの中心点に対して対称に配置され、輝度が同程度であることから、この第１のスポットに由来する結晶部は２回対称性を有することが推察される。また上述のように、２つの第１のスポットはｃ軸に垂直な結晶面による回折スポットであることから、２つの第１のスポットと中心を結ぶ直線（破線で示す直線）の方向が、結晶部のｃ軸の向きと一致する。図３（Ａ）において上下方向が膜厚方向であることから、金属酸化物膜中には、ｃ軸が膜厚方向に配向する結晶部が存在していることが分かる。 Further, the two first spots are symmetrically arranged with respect to the center point of the electron beam diffraction pattern and have the same luminance, so that the crystal part derived from the first spot has twofold symmetry. It is inferred. Further, as described above, since the two first spots are diffraction spots by a crystal plane perpendicular to the c-axis, the direction of a straight line (a straight line indicated by a broken line) connecting the two first spots and the center is the crystal. This coincides with the direction of the c-axis of the part. In FIG. 3A, since the vertical direction is the film thickness direction, it can be seen that there is a crystal part in which the c-axis is oriented in the film thickness direction in the metal oxide film.
　続いて図３（Ｂ）では、図３（Ａ）で見られていた第１のリングの位置に、円周状に分布した複数のスポット（第２のスポット）が確認できる。さらに、２つの第１のスポットも確認できる。 Subsequently, in FIG. 3 (B), a plurality of circumferentially distributed spots (second spots) can be confirmed at the position of the first ring seen in FIG. 3 (A). Furthermore, two first spots can also be confirmed.
　図３（Ｂ）に示すように、入射する電子ビームの径を極めて小さくした場合に、円周状に分布した複数の第２のスポットがみられることから、金属酸化物膜は、極めて微小で且つ面方位があらゆる向きに配向した複数の結晶部が混在していることが分かる。そして、図３（Ａ）で見られていた第１のリングは、観察領域が広くなることで、この微細な結晶部からの複数の回折スポットが連なり、輝度が平均化された結果であることが理解できる。 As shown in FIG. 3 (B), when the diameter of the incident electron beam is extremely small, a plurality of second spots distributed in a circumferential shape are seen, so that the metal oxide film is extremely small. Further, it can be seen that a plurality of crystal parts having plane orientations oriented in all directions are mixed. The first ring seen in FIG. 3A is the result of averaging the brightness by connecting a plurality of diffraction spots from this fine crystal part by widening the observation region. Can understand.
　このように、試料１の金属酸化物膜は、配向性を有する結晶部と、配向性を持たない結晶部とが混在している膜であることが確認できる。また配向性を有する結晶部からの第１のスポットの輝度が、第２のスポットの輝度よりも高いことから、膜中に存在する結晶部のうち、配向性を有する結晶部の存在割合が高いことが確認できる。 Thus, it can be confirmed that the metal oxide film of Sample 1 is a film in which crystal parts having orientation and crystal parts having no orientation are mixed. In addition, since the luminance of the first spot from the crystal part having orientation is higher than the luminance of the second spot, the crystal part having orientation is high in the crystal part existing in the film. I can confirm that.
〔試料２、３〕
　図４（Ａ）、（Ｂ）に試料２の電子線回折パターンを、図４（Ｃ）、（Ｄ）に試料３の電子線回折パターンをそれぞれ示す。図４（Ａ）、（Ｃ）はそれぞれビーム径を１００ｎｍとしたものであり、図４（Ｂ）、（Ｄ）はそれぞれビーム径を１ｎｍとしたものである。 [Samples 2 and 3]
4A and 4B show the electron diffraction pattern of the sample 2, and FIGS. 4C and 4D show the electron diffraction pattern of the sample 3, respectively. 4A and 4C each show a beam diameter of 100 nm, and FIGS. 4B and 4D each show a beam diameter of 1 nm.
　図４（Ａ）、（Ｃ）に示すように、試料２及び試料３において、試料１よりも明瞭に配向性を有する結晶部に由来する２つの第１のスポットが確認できる。当該スポットの輝度は、試料３、試料２、試料１の順で明るくなっており、配向性を有する結晶部の存在割合が、この順で高いことが示唆される。 As shown in FIGS. 4A and 4C, in Sample 2 and Sample 3, two first spots derived from crystal parts having orientation more clearly than Sample 1 can be confirmed. The brightness of the spot is brighter in the order of Sample 3, Sample 2, and Sample 1, suggesting that the proportion of crystal parts having orientation is higher in this order.
　また図４（Ａ）、（Ｃ）に示すように、試料２及び試料３では、第２のリングと重なる位置に、第１のスポットより暗い２つのスポット（第３のスポット）が確認される。なお図３（Ａ）に示すように試料１では、この第３のスポットは第２のリングと区別がつかない輝度である。２つの第３のスポットは、第１のスポットに対して９０度回転させた向きに位置している。この第３のスポットは、ｃ軸に垂直な結晶面以外の面に由来する回折スポットである。 Further, as shown in FIGS. 4A and 4C, in the sample 2 and the sample 3, two spots (third spot) that are darker than the first spot are confirmed at the position overlapping the second ring. . As shown in FIG. 3A, in the sample 1, the third spot has a luminance that cannot be distinguished from the second ring. The two third spots are positioned in a direction rotated 90 degrees with respect to the first spot. This third spot is a diffraction spot derived from a plane other than the crystal plane perpendicular to the c-axis.
　また、図４（Ｃ）において、破線で囲った箇所では、第１のスポットに対して３０度回転させた位置、及び６０度回転させた位置にも、輝度の高い領域が確認されている。このように、試料３は第１のスポット以外の回折スポットが明瞭に観察されるほど、配向性を有する結晶部の存在割合が高い、すなわち結晶性が高い膜であることが確認できる。 Further, in FIG. 4C, high brightness regions are also confirmed at the positions surrounded by the broken lines at positions rotated by 30 degrees and positions rotated by 60 degrees with respect to the first spot. Thus, it can be confirmed that the sample 3 is a film having a higher proportion of crystal parts having orientation, that is, higher crystallinity, as the diffraction spots other than the first spot are clearly observed.
　図４（Ｂ）、（Ｄ）に示すように、ビーム径を極めて微小にした条件では、第１のリングが見られていた位置に第２のスポットが観測されていることが分かる。また試料２及び試料３では、試料１に見られなかった第３のスポットも確認されている。 As shown in FIGS. 4B and 4D, it can be seen that the second spot is observed at the position where the first ring was seen under the condition that the beam diameter was extremely small. In Sample 2 and Sample 3, a third spot that was not found in Sample 1 was also confirmed.
〔試料４〕
　図５に、試料４に対してビーム径を１００ｎｍとした条件で測定した電子線回折パターンを示す。 [Sample 4]
FIG. 5 shows an electron diffraction pattern measured on the sample 4 under the condition that the beam diameter is 100 nm.
　試料４では、第１のリングはみられるものの、試料１乃至試料３でみられていた第１のスポットは観測されなかった。このことから、試料４では第１のリングに由来する複数の結晶部を有し、且つ、配向性を有する結晶部の存在割合が、他の方向に配向している結晶部の存在割合と同等であることが示唆される。 In sample 4, although the first ring was seen, the first spot seen in samples 1 to 3 was not observed. From this, sample 4 has a plurality of crystal parts derived from the first ring, and the ratio of crystal parts having orientation is equal to the ratio of crystal parts oriented in other directions. It is suggested that
〔電子線回折パターンのスポットの輝度について〕
　上述のように、第１のリングの輝度と、第１のスポットの輝度の差は、配向性を有する結晶部の存在割合を推し量る点で重要な情報である。 [Brightness of electron diffraction pattern spot]
As described above, the difference between the luminance of the first ring and the luminance of the first spot is important information in terms of estimating the existence ratio of crystal parts having orientation.
　図６（Ａ）には、図４（Ｃ）を拡大した図を示している。ここで理想的な単結晶のＩｎＧａＺｎＯ４の電子線回折パターンでは、動径方向において第１のリングと重なる位置において、第１のスポットを電子線回折パターンの中心を中心として３０度、９０度、１２０度それぞれ回転させた位置（図６（Ａ）中破線で囲った領域）には、回折スポットは観測されないことが分かっている。すなわち、この領域に現れる輝度は、金属酸化物膜中の、配向性を有する結晶部以外の結晶部から回折された電子、若しくは膜中の結晶部以外の領域または基板など領域からの散乱された電子に由来すると考えられる。なお、後者の散乱電子については、動径が等しい位置では同等の強度で観測されると考えられるため、ここでは無視することができる。したがって例えば、第１のスポットの輝度と、これと９０度回転した位置の輝度の差は、配向性を有する結晶部の存在割合を知るうえで重要なパラメータとなる。 FIG. 6A shows an enlarged view of FIG. Here, in an electron diffraction pattern of an ideal single crystal InGaZnO 4 , the first spot is 30 degrees, 90 degrees around the center of the electron diffraction pattern at a position overlapping the first ring in the radial direction, It is known that a diffraction spot is not observed at a position rotated by 120 degrees (a region surrounded by a broken line in FIG. 6A). That is, the luminance that appears in this region is scattered from electrons diffracted from a crystal part other than the crystal part having orientation in the metal oxide film, or from a region other than the crystal part in the film or a region such as a substrate. It is thought to be derived from electrons. Note that the latter scattered electrons are considered to be observed at the same intensity at positions where the radius is equal, and can be ignored here. Therefore, for example, the difference between the brightness of the first spot and the brightness at a position rotated by 90 degrees is an important parameter for knowing the existence ratio of crystal parts having orientation.
　ここで、第１のスポットの輝度と、ここから所定の角度で回転した位置の輝度の差は、電子線回折パターンの中心位置に現れるダイレクトスポットの輝度で規格化することにより求めることができる。またこれにより、各試料間での相対的な比較を行うことができる。 Here, the difference between the luminance of the first spot and the luminance of the position rotated by a predetermined angle from here can be obtained by normalizing with the luminance of the direct spot appearing at the center position of the electron beam diffraction pattern. This also allows a relative comparison between the samples.
　図７（Ａ１）には、試料１における電子線回折パターン（図３（Ａ）と同じもの）を示し、図７（Ａ２）には、図中の第１のスポットとダイレクトスポットを通るＡ−Ａ’及びこれと直交するＢ−Ｂ’の各線に沿った動径方向の位置に対する規格化した輝度のプロファイルを示す。図７（Ａ２）に示すように、ダイレクトスポットのピークを挟んで２つのピークが観測されている。また２つのピーク輝度は、Ａ−Ａ’とＢ−Ｂ’とで、明確な差が見られている。 FIG. 7 (A1) shows an electron beam diffraction pattern (same as FIG. 3 (A)) in the sample 1, and FIG. 7 (A2) shows A− passing through the first spot and the direct spot in the figure. The normalized luminance profile with respect to the radial position along each line of A ′ and BB ′ orthogonal thereto is shown. As shown in FIG. 7A2, two peaks are observed across the peak of the direct spot. Further, there is a clear difference between the two peak luminances between A-A 'and B-B'.
　図７（Ｂ１）及び図７（Ｂ２）は、それぞれ試料２における電子線回折パターンと規格化輝度のプロファイルである。また図７（Ｃ１）及び図７（Ｃ２）は、それぞれ試料３における電子線回折パターンと規格化輝度のプロファイルである。試料２は試料１よりも、第１のスポットのピーク輝度と、これと９０度回転させた位置のピーク輝度の差が大きくなっている。また、試料３では試料２よりも、この差がより大きいことがわかる。 7 (B1) and 7 (B2) are the electron diffraction pattern and the normalized luminance profile in the sample 2, respectively. FIGS. 7C1 and 7C2 are profiles of an electron beam diffraction pattern and a normalized luminance in the sample 3, respectively. In the sample 2, the difference between the peak luminance of the first spot and the peak luminance at the position rotated by 90 degrees is larger than that of the sample 1. Further, it can be seen that the difference is larger in the sample 3 than in the sample 2.
　また、試料２及び試料３におけるＢ−Ｂ’方向では、第２のリングに相当する位置に、試料１では見られなかったピークが確認できている。したがって、試料２及び試料３は、試料１に比べて明確に結晶性が高いことが確認できる。 Further, in the B-B ′ direction in the sample 2 and the sample 3, a peak that was not seen in the sample 1 can be confirmed at a position corresponding to the second ring. Therefore, it can be confirmed that Sample 2 and Sample 3 clearly have higher crystallinity than Sample 1.
　図７（Ｄ１）及び図７（Ｄ２）は、それぞれ試料４における電子線回折パターンと規格化輝度のプロファイルである。試料４では、２つの方向でプロファイルがほぼ一致していることが分かる。すなわち、試料４は配向性を有する結晶部がほとんど含まれておらず、結晶面が様々な方向を向いている複数の結晶部を含んでいることが確認できる。 FIG. 7 (D1) and FIG. 7 (D2) are an electron beam diffraction pattern and a normalized luminance profile in the sample 4, respectively. In sample 4, it can be seen that the profiles are almost the same in the two directions. That is, it can be confirmed that the sample 4 contains few crystal parts having orientation, and contains a plurality of crystal parts whose crystal planes face in various directions.
　また、ビーム径が小さい条件で測定した場合、電子線回折パターンには第１のリングが離散的な輝点の集合として現れるため、ある位置に対して局所的な輝度を比較すると、第１のリングの輝度が正確に求められない場合がある。その場合には、図６（Ｂ）に破線で示すように、特定の幅を持ち、長辺方向が動径方向と一致する長方形の領域について、長方形の幅方向（図６（Ｂ）における長方形の短辺方向）に平均化した輝度の値を用いて、その動径方向の輝度のプロファイルから、所定の位置の輝度を算出してもよい。 Further, when the measurement is performed under a condition where the beam diameter is small, the first ring appears as a set of discrete bright spots in the electron diffraction pattern. The ring brightness may not be accurately determined. In that case, as indicated by a broken line in FIG. 6B, a rectangular region having a specific width and having a long side direction coincident with the radial direction is a rectangle in the rectangular width direction (FIG. 6B). The luminance at a predetermined position may be calculated from the luminance profile in the radial direction using the luminance value averaged in the short side direction).
　また、動径方向の輝度のプロファイルを算出する際に、試料からの非弾性散乱等に起因する輝度の成分を、バックグラウンドとして差し引くと、より精度の高い比較を行うことができる。ここで非弾性散乱に起因する輝度の成分は、動径方向において極めてブロードなプロファイルを取るため、バックグラウンドの輝度を直線近似で算出してもよい。例えば、対象となるピークの両側の裾に沿って直線を引き、その直線よりも低輝度側に位置する領域をバックグラウンドとして差し引くことができる。 Also, when calculating the luminance profile in the radial direction, a higher-accuracy comparison can be performed by subtracting the luminance component caused by inelastic scattering or the like from the sample as the background. Here, since the luminance component caused by inelastic scattering takes a very broad profile in the radial direction, the background luminance may be calculated by linear approximation. For example, a straight line can be drawn along the skirts on both sides of the target peak, and a region located on the lower luminance side than the straight line can be subtracted as the background.
　ここでは、上述の方法によりバックグラウンドを差し引いたデータから、第１のスポットの輝度、及び第１のスポットの位置から９０度回転させた位置の輝度を算出した。そして、第１のスポットの輝度を、第１のスポットから９０度回転させた位置の輝度で割った値を、相対輝度Ｒとして求めた。 Here, the luminance of the first spot and the luminance of the position rotated by 90 degrees from the position of the first spot were calculated from the data obtained by subtracting the background by the method described above. Then, a value obtained by dividing the luminance of the first spot by the luminance at the position rotated 90 degrees from the first spot was obtained as the relative luminance R.
　試料１乃至試料４のそれぞれについて、ビーム径を１００ｎｍとした条件で測定した電子線回折パターンから、相対輝度Ｒを見積もった結果を図８に示す。 FIG. 8 shows the result of estimating the relative luminance R from the electron beam diffraction pattern measured for each of the samples 1 to 4 under the condition that the beam diameter is 100 nm.
　試料４では、２つの位置で輝度差が確認されず、相対輝度Ｒは１となっている。また相対輝度は試料１、試料２、及び試料３の順で高くなっている。 In sample 4, the luminance difference is not confirmed at the two positions, and the relative luminance R is 1. The relative luminance increases in the order of sample 1, sample 2, and sample 3.
　例えば金属酸化物膜をトランジスタのチャネルが形成される半導体層に用いる場合には、相対輝度Ｒが１倍よりも大きく１０倍以下、好ましくは１．２倍よりも大きく８倍以下、より好ましくは１．５倍よりも大きく６倍以下、さらに好ましくは、１．５倍よりも大きく４倍以下の範囲となる金属酸化物膜を用いることが好ましい。このような金属酸化物膜を半導体層に用いることで、電気特性の高い安定性と、ゲート電圧が低い領域での高い電界効果移動度を両立することができる。 For example, in the case where a metal oxide film is used for a semiconductor layer in which a channel of a transistor is formed, the relative luminance R is more than 1 time and 10 times or less, preferably more than 1.2 times and 8 times or less, more preferably It is preferable to use a metal oxide film that is larger than 1.5 times and smaller than 6 times, more preferably larger than 1.5 times and smaller than 4 times. By using such a metal oxide film for a semiconductor layer, both stability with high electrical characteristics and high field-effect mobility in a region with a low gate voltage can be achieved.
〔配向性の揺らぎについて〕
　金属酸化物膜に含まれる結晶部のうち、配向性を有する結晶部は、各々の配向が完全に一致しているのではなく、配向方向に揺らぎが存在する。以下では、その配向方向の揺らぎについて説明する。 [About fluctuation of orientation]
Among crystal parts included in the metal oxide film, crystal parts having orientation do not completely coincide with each other but have fluctuations in the alignment direction. Below, the fluctuation | variation of the orientation direction is demonstrated.
　配向方向の揺らぎは以下のようにして評価することができる。金属酸化物膜の断面に対する電子線回折パターンを複数の箇所で測定し、得られた各像に対して、電子線回折パターンの中心及び第１のスポットを通る直線と、金属酸化物膜の膜厚方向との傾きを測定することにより、各領域に存在する結晶部の配向方向のばらつきを見積もることができる。 The fluctuation in the orientation direction can be evaluated as follows. The electron diffraction pattern for the cross section of the metal oxide film is measured at a plurality of locations, and for each of the obtained images, a straight line passing through the center of the electron beam diffraction pattern and the first spot, and the film of the metal oxide film By measuring the inclination with respect to the thickness direction, it is possible to estimate the variation in the orientation direction of the crystal part existing in each region.
　ここでは、電子線のビーム径を１ｎｍとした条件で、電子線を膜面方向に平行な方向にスキャンしながら電子線回折パターンを動画像として取得した。スキャンは約２５０ｎｍの距離を１００秒かけて行った。 Here, an electron beam diffraction pattern was acquired as a moving image while scanning the electron beam in a direction parallel to the film surface direction under the condition that the beam diameter of the electron beam was 1 nm. The scan was performed at a distance of about 250 nm for 100 seconds.
　図９に、試料１、試料２及び試料３について、撮像した動画像の一部の電子線回折パターンを示す。図９では、それぞれ９枚の電子線回折パターンを示しており、それぞれの間隔は約１０秒である。 FIG. 9 shows a part of electron beam diffraction patterns of the captured moving images of Sample 1, Sample 2, and Sample 3. FIG. 9 shows nine electron beam diffraction patterns, each interval being about 10 seconds.
　図９では、第１のスポットと電子線回折パターンの中心とを通る直線を破線で示している。図９に示すように、観察する領域によって結晶部の配向方向にばらつきがあることが確認される。 In FIG. 9, a straight line passing through the first spot and the center of the electron diffraction pattern is indicated by a broken line. As shown in FIG. 9, it is confirmed that the orientation direction of the crystal part varies depending on the region to be observed.
　図１０には、図９に示した各電子線回折パターンから見積もった配向方向の分布図を示している。横軸は撮像開始位置を原点としたときの距離であり、縦軸は各位置で測定した配向方向の平均値を０度としたときの、それぞれの位置における配向方向の角度である。ここでは、時計回りの向きを正として示している。図１０に示すように、各試料で配向方向のばらつきの大きさにほとんど差はみられず、いずれの試料でも１０度未満の範囲に収まっている。 FIG. 10 shows a distribution diagram of the orientation direction estimated from each electron diffraction pattern shown in FIG. The horizontal axis is the distance when the imaging start position is the origin, and the vertical axis is the orientation direction angle at each position when the average value of the orientation direction measured at each position is 0 degree. Here, the clockwise direction is shown as positive. As shown in FIG. 10, there is almost no difference in the variation in the orientation direction between the samples, and any sample is within a range of less than 10 degrees.
　金属酸化物膜中の、結晶部の配向方向は、電子線のビーム径を大きくした条件で測定した電子線回折パターン中における、スポットの円周方向の広がりによっても見積もることができる。電子線のビーム径を大きくし測定範囲を広げることにより、測定範囲に存在する結晶部の情報が平均化された電子線回折パターンが得られる。そのためスポットの円周方向の広がりは、結晶部の配向方向のばらつきが大きくなるほど広くなる。またその輝度の円周方向の分布は、特定の方向に配向している結晶部の存在割合を反映した分布となる。 The orientation direction of the crystal part in the metal oxide film can be estimated by the spread of the spot in the circumferential direction in the electron beam diffraction pattern measured under the condition that the beam diameter of the electron beam is increased. By increasing the beam diameter of the electron beam and expanding the measurement range, an electron beam diffraction pattern in which information on crystal parts existing in the measurement range is averaged can be obtained. Therefore, the spread of the spot in the circumferential direction becomes wider as the variation in the orientation direction of the crystal part becomes larger. Further, the luminance distribution in the circumferential direction is a distribution reflecting the existence ratio of the crystal parts oriented in a specific direction.
　例えば図６（Ａ）に示すように、第１のスポットは完全な点（または円）形状ではなく、円周方向に広がった、楕円形状に近い形状となっている。このスポットの円周方向の２つの端部のそれぞれと、電子線回折パターンの中心点とを結んだ２つの直線の間の角度が、結晶部の配向方向のばらつきを表している。第１のスポットの端部が不明瞭な場合には、例えば第１のスポットの輝度の最も明るい点を基準として、１σまたは２σの位置を端部とすればよい。また、第１のリングと第１のスポットの輝度の差が小さい場合などでは、第１のスポットの輝度から第１のリングの輝度を差し引いた輝度分布をもとに見積もるとよい。なお、この方法では、電子線回折パターンの測定条件によっては、輝度が高いほどスポットの広がりが大きくなり、実際の配向のばらつきよりも大きく見積もられる場合がある。 For example, as shown in FIG. 6A, the first spot is not a perfect point (or circle) shape, but has a shape close to an elliptical shape extending in the circumferential direction. The angle between two straight lines connecting each of the two end portions in the circumferential direction of the spot and the center point of the electron beam diffraction pattern represents variation in the orientation direction of the crystal portion. When the end of the first spot is unclear, for example, the position of 1σ or 2σ may be set as the end with respect to the brightest point of the first spot. In addition, when the difference in luminance between the first ring and the first spot is small, it may be estimated based on a luminance distribution obtained by subtracting the luminance of the first ring from the luminance of the first spot. In this method, depending on the measurement conditions of the electron beam diffraction pattern, the spread of the spot increases as the luminance increases, and it may be estimated to be larger than the actual orientation variation.
　例えば、電子線回折パターンの中心を中心とした第１のスポットの両端の中心角は、０度以上４５度以下、好ましくは０度以上４０度以下、より好ましくは０度以上３５度以下、さらに好ましくは０度以上３０度以下であるとよい。配向性が高いほど、金属酸化物膜の電気特性の安定性が向上する。 For example, the central angle of both ends of the first spot centered on the center of the electron beam diffraction pattern is 0 degree or more and 45 degrees or less, preferably 0 degree or more and 40 degrees or less, more preferably 0 degree or more and 35 degrees or less, Preferably it is 0 degree or more and 30 degrees or less. The higher the orientation, the more stable the electrical characteristics of the metal oxide film.
［結晶部の存在割合］
　金属酸化物膜中の結晶部の存在割合は、断面観察像を解析することで見積もることができる。 [Abundance ratio of crystal part]
The existence ratio of the crystal part in the metal oxide film can be estimated by analyzing the cross-sectional observation image.
　画像解析の方法について、説明する。画像処理は、高分解能で撮像されたＴＥＭ像に対して２次元高速フーリエ変換（ＦＦＴ：Ｆａｓｔ　Ｆｏｕｒｉｅｒ　Ｔｒａｎｓｆｏｒｍ）処理し、ＦＦＴ像を取得する。得られたＦＦＴ像に対し、周期性を有する範囲を残し、それ以外を除去するマスク処理を施す。そしてマスク処理したＦＦＴ像を、２次元逆フーリエ変換（ＩＦＦＴ：Ｉｎｖｅｒｓｅ　Ｆａｓｔ　Ｆｏｕｒｉｅｒ　Ｔｒａｎｓｆｏｒｍ）処理し、ＦＦＴフィルタリング像を取得する。 Describe the method of image analysis. In the image processing, a two-dimensional fast Fourier transform (FFT: Fast Fourier Transform) process is performed on a TEM image captured at a high resolution to obtain an FFT image. The obtained FFT image is subjected to a mask process that leaves a range having periodicity and removes the rest. The masked FFT image is then subjected to a two-dimensional inverse Fourier transform (IFFT: Inverse Fast Fourier Transform) to obtain an FFT filtered image.
　これにより、結晶部のみを抽出した実空間像を得ることができる。ここで、残存した像の面積の割合から、結晶部の存在割合を見積もることができる。また、画像処理に用いた領域（元の像の面積ともいう）の面積から、残存した面積を差し引くことにより、結晶部以外の部分の存在割合を見積もることができる。 Thereby, a real space image in which only the crystal part is extracted can be obtained. Here, the existence ratio of the crystal part can be estimated from the ratio of the area of the remaining image. Further, by subtracting the remaining area from the area of the region used for image processing (also referred to as the area of the original image), it is possible to estimate the existence ratio of the part other than the crystal part.
　図１１（Ａ）（Ｂ）に、それぞれ試料３と試料１における画像処理前の断面ＴＥＭ観察像を示し、図１１（Ｃ）、（Ｄ）に、それぞれ画像処理後に得られた像を示す。画像処理後の画像において、金属酸化物膜中の白く表示されている領域が、結晶部を含む領域に対応する。 FIGS. 11A and 11B show cross-sectional TEM observation images of Sample 3 and Sample 1 before image processing, and FIGS. 11C and 11D show images obtained after image processing, respectively. In the image after image processing, a white area in the metal oxide film corresponds to an area including a crystal part.
　図１１（Ｃ）より、試料３における結晶部を含む領域を除く面積の割合は約２１．０％であった。また図１１（Ｄ）より見積もった、試料１における配向性を有する結晶部を含む領域を除く面積の割合は約３９．８％であった。 From FIG. 11C, the ratio of the area excluding the region including the crystal part in the sample 3 was about 21.0%. Further, the ratio of the area excluding the region including the crystal part having orientation in the sample 1 estimated from FIG. 11D was about 39.8%.
　このように見積もられた、金属酸化物膜中の結晶部を除く部分の割合が、５％以上２５％未満である場合、その金属酸化物膜は極めて結晶性の高い膜であり、電気特性の安定性が高いため好ましい。また、金属酸化物膜中の結晶部を除く部分の割合が、２５％以上１００％未満、好ましくは２５％以上９０％以下、より好ましくは２５％以上８０％以下である場合、その金属酸化物膜は配向性を有する結晶部と配向性を有さない結晶部が混在し、電気特性の安定性と高移動度化を両立させることができる。 When the ratio of the portion excluding the crystal part in the metal oxide film estimated in this way is 5% or more and less than 25%, the metal oxide film is a film having extremely high crystallinity, and electrical characteristics. Is preferable because of its high stability. Further, when the proportion of the portion excluding the crystal part in the metal oxide film is 25% or more and less than 100%, preferably 25% or more and 90% or less, more preferably 25% or more and 80% or less, the metal oxide In the film, crystal parts having orientation and crystal parts having no orientation are mixed, and both stability of electric characteristics and high mobility can be achieved.
　ここで、断面観察像、またはこの画像解析等により明瞭に確認できる結晶部を除く部分のことを、Ａｔｏｍｉｃ　Ｖｏｉｄと呼称することもできる。特に、Ａｔｏｍｉｃ　Ｖｏｉｄ領域は、面方位が不規則であって、極めて微細で且つ大きさの異なる結晶部が複数混在する領域である。当該結晶部の存在は、ビーム径（プローブ径）が大きい（例えば２５ｎｍΦ以上、または５０ｎｍΦ以上）電子線回折パターンにおいてはスポットが観察されず、且つビーム径の極めて小さい（例えば０．３ｎｍ以上且つ１０ｎｍΦ以下または５ｎｍ以下）電子線回折パターンにおいてようやくスポットとして観察されることから理解でき、当該結晶部は極めて微細である。 Here, a cross-sectional observation image or a portion excluding a crystal portion that can be clearly confirmed by image analysis or the like can be referred to as an atomic void. In particular, the atomic void region is a region in which a plurality of crystal parts having irregular surface orientations and extremely fine and different sizes are mixed. Presence of the crystal part is such that no spot is observed in an electron diffraction pattern having a large beam diameter (probe diameter) (for example, 25 nmΦ or more, or 50 nmΦ or more), and the beam diameter is extremely small (for example, 0.3 nm or more and 10 nmΦ). It can be understood from the fact that it is finally observed as a spot in the electron diffraction pattern, and the crystal part is extremely fine.
［トランジスタの電気特性］
　以下では、上記試料１及び試料３の金属酸化物を用いて、トランジスタを作製し、その電気特性を測定した結果について説明する。 [Electrical characteristics of transistors]
Hereinafter, a result of manufacturing a transistor using the metal oxides of Sample 1 and Sample 3 and measuring electric characteristics thereof will be described.
　トランジスタの構造は、実施の形態２で例示する図１８に示す構造を用いた。ここではそれぞれ、半導体層の形成条件の異なる試料Ａ１、試料Ａ２の２種類の試料を作製した。 The structure of the transistor shown in FIG. 18 illustrated in Embodiment Mode 2 was used. Here, two types of samples, Sample A1 and Sample A2, which have different semiconductor layer formation conditions, were produced.
〔トランジスタの作製〕
　まず、ガラス基板上に厚さ１０ｎｍのチタン膜と、厚さ１００ｎｍの銅膜とを、スパッタリング装置を用いて形成した。続いて当該導電膜をフォトリソグラフィ法により加工した。 [Production of transistors]
First, a titanium film with a thickness of 10 nm and a copper film with a thickness of 100 nm were formed on a glass substrate using a sputtering apparatus. Subsequently, the conductive film was processed by a photolithography method.
　次に、基板及び導電膜上に絶縁膜を４層積層して形成した。絶縁膜は、プラズマ化学気相堆積（ＰＥＣＶＤ）装置を用いて、真空中で連続して形成した。絶縁膜は、下から厚さ５０ｎｍの窒化シリコン膜、厚さ３００ｎｍの窒化シリコン膜、厚さ５０ｎｍの窒化シリコン膜、厚さ５０ｎｍの酸化窒化シリコン膜をそれぞれ用いた。 Next, four layers of insulating films were formed on the substrate and the conductive film. The insulating film was continuously formed in a vacuum using a plasma enhanced chemical vapor deposition (PECVD) apparatus. As the insulating film, a silicon nitride film with a thickness of 50 nm, a silicon nitride film with a thickness of 300 nm, a silicon nitride film with a thickness of 50 nm, and a silicon oxynitride film with a thickness of 50 nm were used from the bottom.
　次に、絶縁膜上に酸化物半導体膜を形成し、当該酸化物半導体膜を島状に加工することで、半導体層を形成した。酸化物半導体膜１０８としては、厚さ４０ｎｍの酸化物半導体膜を形成した。 Next, an oxide semiconductor film was formed over the insulating film, and the semiconductor layer was formed by processing the oxide semiconductor film into an island shape. As the oxide semiconductor film 108, an oxide semiconductor film with a thickness of 40 nm was formed.
　試料Ａ１において、酸化物半導体膜に用いた金属酸化物膜は、試料１と同様の条件である。すなわち、基板温度を１３０℃として、流量１８０ｓｃｃｍのアルゴンガスと、流量２０ｓｃｃｍの酸素ガスとをスパッタリング装置のチャンバー内に導入し、圧力を０．６Ｐａとし、インジウムと、ガリウムと、亜鉛とを有する金属酸化物ターゲット（Ｉｎ：Ｇａ：Ｚｎ＝４：２：４．１［原子数比］）に、２．５ｋｗの交流電力を印加することで形成した。なお、酸素流量比は１０％である。厚さは約４０ｎｍとした。 In sample A1, the metal oxide film used for the oxide semiconductor film has the same conditions as in sample 1. That is, a metal having indium, gallium, and zinc at a substrate temperature of 130 ° C., an argon gas with a flow rate of 180 sccm and an oxygen gas with a flow rate of 20 sccm are introduced into the chamber of the sputtering apparatus, the pressure is 0.6 Pa. The oxide target (In: Ga: Zn = 4: 2: 4.1 [atomic ratio]) was formed by applying 2.5 kw AC power. The oxygen flow rate ratio is 10%. The thickness was about 40 nm.
　試料Ａ２において、酸化物半導体膜に用いた金属酸化物膜は、試料３と同様の条件である。すなわち、基板温度を１７０℃として、流量１４０ｓｃｃｍのアルゴンガスと、流量６０ｓｃｃｍの酸素ガスとをスパッタリング装置のチャンバー内に導入し、圧力を０．６Ｐａとし、インジウムと、ガリウムと、亜鉛とを有する金属酸化物ターゲット（Ｉｎ：Ｇａ：Ｚｎ＝４：２：４．１［原子数比］）に、２．５ｋｗの交流電力を印加することで形成した。なお、酸素流量比は３０％である。厚さは約４０ｎｍとした。 In Sample A2, the metal oxide film used for the oxide semiconductor film has the same conditions as Sample 3. That is, a metal having indium, gallium, and zinc at a substrate temperature of 170 ° C., an argon gas having a flow rate of 140 sccm and an oxygen gas having a flow rate of 60 sccm are introduced into the chamber of the sputtering apparatus, the pressure is 0.6 Pa. The oxide target (In: Ga: Zn = 4: 2: 4.1 [atomic ratio]) was formed by applying 2.5 kw AC power. The oxygen flow rate ratio is 30%. The thickness was about 40 nm.
　次に、絶縁膜及び酸化物半導体層上に、絶縁膜を形成した。絶縁膜としては、厚さ１５０ｎｍの酸化窒化シリコン膜を、ＰＥＣＶＤ装置を用いて形成した。 Next, an insulating film was formed over the insulating film and the oxide semiconductor layer. As the insulating film, a 150 nm thick silicon oxynitride film was formed using a PECVD apparatus.
　次に、熱処理を行った。当該熱処理としては、窒素と酸素との混合ガス雰囲気下で、３５０℃　１時間の熱処理とした。 Next, heat treatment was performed. As the heat treatment, heat treatment was performed at 350 ° C. for 1 hour in a mixed gas atmosphere of nitrogen and oxygen.
　次に、絶縁膜の所望の領域に開口部を形成した。開口部の形成方法としては、ドライエッチング法を用いた。 Next, an opening was formed in a desired region of the insulating film. A dry etching method was used as a method for forming the opening.
　次に、開口部を覆うように絶縁膜上に厚さ１００ｎｍの酸化物半導体膜を形成し、当該酸化物半導体膜を島状に加工することで、導電膜を形成した。また、導電膜を形成後、続けて、導電膜の下側に接する絶縁膜を加工することで、絶縁膜を形成した。 Next, an oxide semiconductor film having a thickness of 100 nm was formed over the insulating film so as to cover the opening, and the oxide semiconductor film was processed into an island shape, whereby a conductive film was formed. In addition, after forming the conductive film, the insulating film in contact with the lower side of the conductive film was processed to form the insulating film.
　導電膜としては、厚さ１００ｎｍの酸化物半導体膜を形成した。なお、当該酸化物半導体膜としては、２層の積層構造とした。１層目の酸化物半導体膜の成膜条件としては、基板温度を１７０℃として、流量２００ｓｃｃｍの酸素ガスをスパッタリング装置のチャンバー内に導入し、圧力を０．６Ｐａとし、インジウムと、ガリウムと、亜鉛とを有する金属酸化物ターゲット（Ｉｎ：Ｇａ：Ｚｎ＝４：２：４．１［原子数比］）に、２．５ｋｗの交流電力を印加することで、膜厚が１０ｎｍになるように形成した。２層目の酸化物半導体膜の成膜条件としては、基板温度を１７０℃として、流量１８０ｓｃｃｍのアルゴンガスと、流量２０ｓｃｃｍの酸素ガスとをスパッタリング装置のチャンバー内に導入し、圧力を０．６Ｐａとし、インジウムと、ガリウムと、亜鉛とを有する金属酸化物ターゲット（Ｉｎ：Ｇａ：Ｚｎ＝４：２：４．１［原子数比］）に、２．５ｋｗの交流電力を印加することで、膜厚が９０ｎｍになるように形成した。 As the conductive film, an oxide semiconductor film having a thickness of 100 nm was formed. Note that the oxide semiconductor film has a two-layer structure. As the conditions for forming the first oxide semiconductor film, the substrate temperature was 170 ° C., an oxygen gas with a flow rate of 200 sccm was introduced into the chamber of the sputtering apparatus, the pressure was 0.6 Pa, indium, gallium, By applying 2.5 kw of AC power to a metal oxide target (In: Ga: Zn = 4: 2: 4.1 [atomic ratio]) having zinc, the film thickness becomes 10 nm. Formed. As the conditions for forming the second oxide semiconductor film, the substrate temperature was set to 170 ° C., argon gas having a flow rate of 180 sccm and oxygen gas having a flow rate of 20 sccm were introduced into the chamber of the sputtering apparatus, and the pressure was set to 0.6 Pa. And applying a 2.5 kw AC power to a metal oxide target (In: Ga: Zn = 4: 2: 4.1 [atomic ratio]) containing indium, gallium, and zinc, The film thickness was 90 nm.
　次に、酸化物半導体膜、絶縁膜、及び導電膜上からプラズマ処理を行った。当該プラズマ処理としては、ＰＥＣＶＤ装置を用い、基板温度を２２０℃とし、アルゴンガスと窒素ガスとの混合ガス雰囲気下で行った。 Next, plasma treatment was performed on the oxide semiconductor film, the insulating film, and the conductive film. The plasma treatment was performed using a PECVD apparatus at a substrate temperature of 220 ° C. in a mixed gas atmosphere of argon gas and nitrogen gas.
　次に、酸化物半導体膜、絶縁膜、及び導電膜上に絶縁膜を形成した。絶縁膜としては、厚さ１００ｎｍの窒化シリコン膜及び厚さ３００ｎｍの酸化窒化シリコン膜をＰＥＣＶＤ装置を用いて積層して形成した。 Next, an insulating film was formed over the oxide semiconductor film, the insulating film, and the conductive film. As the insulating film, a silicon nitride film with a thickness of 100 nm and a silicon oxynitride film with a thickness of 300 nm were stacked using a PECVD apparatus.
　次に、形成した絶縁膜上にマスクを形成し、当該マスクを用いて絶縁膜に開口部を形成した。 Next, a mask was formed on the formed insulating film, and an opening was formed in the insulating film using the mask.
　次に、開口部を充填するように、導電膜を形成し、当該導電膜を島状に加工することで、ソース電極及びドレイン電極となる導電膜を形成した。当該導電膜としては、厚さ１０ｎｍのチタン膜と、厚さ１００ｎｍの銅膜とを、スパッタリング装置を用いて、それぞれ形成した。 Next, a conductive film was formed so as to fill the opening, and the conductive film was processed into an island shape, thereby forming a conductive film to be a source electrode and a drain electrode. As the conductive film, a titanium film with a thickness of 10 nm and a copper film with a thickness of 100 nm were formed using a sputtering apparatus, respectively.
　次に、絶縁膜、及び導電膜上に絶縁膜を形成した。絶縁膜としては、厚さ１．５μｍのアクリル系の感光性樹脂を用いた。 Next, an insulating film was formed over the insulating film and the conductive film. As the insulating film, an acrylic photosensitive resin having a thickness of 1.5 μm was used.
　以上のようにして、２種類のトランジスタを作製した。 Two types of transistors were manufactured as described above.
〔トランジスタの電気特性〕
　次に、上記作製した試料Ａ１及び試料Ａ２のトランジスタのＩｄ−Ｖｇ特性を測定した。 [Electrical characteristics of transistors]
Next, the Id-Vg characteristics of the transistors of Sample A1 and Sample A2 manufactured above were measured.
　なお、トランジスタのＩｄ−Ｖｇ特性の測定条件としては、第１のゲート電極として機能する導電膜に印加する電圧（以下、ゲート電圧（Ｖｇ）ともいう）、及び第２のゲート電極として機能する導電膜に印加する電圧（Ｖｂｇ）ともいう）を、−１５Ｖから＋２０Ｖまで０．２５Ｖのステップで印加した。また、ソース電極として機能する導電膜に印加する電圧（以下、ソース電圧（Ｖｓ）ともいう）を０Ｖ（ｃｏｍｍ）とし、ドレイン電極として機能する導電膜に印加する電圧（以下、ドレイン電圧（Ｖｄ）ともいう）を、０．１Ｖ及び２０Ｖとした。 Note that measurement conditions for the Id-Vg characteristics of the transistor include a voltage applied to a conductive film functioning as a first gate electrode (hereinafter also referred to as a gate voltage (Vg)) and a conductive function functioning as a second gate electrode. A voltage (also referred to as Vbg) applied to the film was applied from −15V to + 20V in steps of 0.25V. In addition, a voltage applied to the conductive film functioning as the source electrode (hereinafter also referred to as source voltage (Vs)) is 0 V (comm), and a voltage applied to the conductive film functioning as the drain electrode (hereinafter referred to as drain voltage (Vd)). Also referred to as 0.1V and 20V.
　図１２（Ａ）、（Ｂ）に、それぞれ試料Ａ１、試料Ａ２のＩｄ−Ｖｇ特性結果を示す。なお、図１２において、第１縦軸がＩｄ（Ａ）を、第２縦軸が電界効果移動度（μＦＥ（ｃｍ２／Ｖｓ））を、横軸がＶｇ（Ｖ）を、それぞれ表す。また、図１２において、合計５個のトランジスタのＩｄ−Ｖｇ特性結果を、それぞれ重ねて示している。 FIGS. 12A and 12B show the Id-Vg characteristic results of Sample A1 and Sample A2, respectively. In FIG. 12, the first vertical axis represents Id (A), the second vertical axis represents field effect mobility (μFE (cm 2 / Vs)), and the horizontal axis represents Vg (V). In FIG. 12, the Id-Vg characteristic results of a total of five transistors are shown in an overlapping manner.
　図１２（Ａ）、（Ｂ）に示すように、試料Ａ１、試料Ａ２共に良好な電気特性を示すことが確認された。また、試料Ａ２と比べて試料Ａ１では、電界効果移動度が高いことが確認できた。また特に、低いＶｇ（例えばＶｇが１０Ｖ以下）の範囲において、その傾向が顕著である。 As shown in FIGS. 12A and 12B, it was confirmed that both the sample A1 and the sample A2 showed good electrical characteristics. Further, it was confirmed that the sample A1 had higher field effect mobility than the sample A2. In particular, the tendency is remarkable in the range of low Vg (for example, Vg is 10 V or less).
　すなわち、本発明の一態様である、配向性の結晶部と配向性を有さない結晶部が混在した金属酸化物膜を、チャネルが形成される半導体層に用いたトランジスタは、高い電界効果移動度を示すことが確認できた。特に、ゲート電圧が低い条件において、高い電界効果移動度、高いドレイン電流を示すことが確認できた。 That is, a transistor in which a metal oxide film including a crystal part with orientation and a crystal part without orientation, which is one embodiment of the present invention, is used for a semiconductor layer in which a channel is formed has high field-effect mobility. It was confirmed that the degree was shown. In particular, it was confirmed that a high field-effect mobility and a high drain current were exhibited under conditions where the gate voltage was low.
［金属酸化物膜の成膜方法］
　以下では、本発明の一態様の金属酸化物膜の成膜方法について説明する。 [Method of forming metal oxide film]
Hereinafter, a method for forming a metal oxide film of one embodiment of the present invention is described.
　本発明の一態様の金属酸化物膜は、酸素を含む雰囲気下にて基板を加熱した状態で、スパッタリング法によって成膜することができる。 The metal oxide film of one embodiment of the present invention can be formed by a sputtering method in a state where the substrate is heated in an atmosphere containing oxygen.
　成膜時の基板温度は８０℃以上１５０℃以下、好ましくは１００℃以上１５０℃以下、代表的には１３０℃の温度とすることが好ましい。基板の温度を高めることにより、配向性を有する結晶部をより多く形成することができる。 The substrate temperature during film formation is 80 ° C. or higher and 150 ° C. or lower, preferably 100 ° C. or higher and 150 ° C. or lower, typically 130 ° C. By increasing the temperature of the substrate, more crystal parts having orientation can be formed.
　また、成膜時の酸素の流量比（酸素分圧）を、１％以上３３％未満、好ましくは５％以上３０％以下、より好ましくは５％以上２０％以下、さらに好ましくは５％以上１５％以下、代表的には１０％とすることが好ましい。酸素流量を低減することにより、配向性を有さない結晶部をより多く膜中に含ませることができる。 In addition, the flow rate ratio of oxygen during film formation (oxygen partial pressure) is 1% to less than 33%, preferably 5% to 30%, more preferably 5% to 20%, and even more preferably 5% to 15%. % Or less, typically 10%. By reducing the oxygen flow rate, more crystal parts having no orientation can be included in the film.
　したがって、成膜時の基板温度と、成膜時の酸素流量を上述の範囲とすることで、配向性を有する結晶部と、配向性を有さない結晶部とが混在した金属酸化物膜を得ることができる。また、基板温度と酸素流量を上述の範囲内で最適化することにより、配向性を有する結晶部と配向性を有さない結晶部の存在割合を制御することが可能となる。 Therefore, by setting the substrate temperature at the time of film formation and the oxygen flow rate at the time of film formation within the above range, a metal oxide film in which a crystal part having orientation and a crystal part having no orientation are mixed can be obtained. Obtainable. Further, by optimizing the substrate temperature and the oxygen flow rate within the above-described ranges, it is possible to control the existence ratio of the crystal part having orientation and the crystal part not having orientation.
　金属酸化物膜の成膜に用いることの可能な酸化物ターゲットとしては、Ｉｎ−Ｇａ−Ｚｎ系酸化物に限られず、例えば、Ｉｎ−Ｍ−Ｚｎ系酸化物（Ｍは、Ａｌ、Ｇａ、Ｙ、またはＳｎ）を適用することができる。 An oxide target that can be used for forming a metal oxide film is not limited to an In—Ga—Zn-based oxide, and includes, for example, an In—M—Zn-based oxide (M is Al, Ga, Y). Or Sn) can be applied.
　また、複数の結晶粒を有する多結晶酸化物を含むスパッタリングターゲットを用いて、金属酸化物膜である結晶部を含む金属酸化物膜を成膜すると、多結晶酸化物を含まないスパッタリングターゲットを用いた場合に比べて、結晶性を有する金属酸化物膜が得られやすい。 In addition, when a metal oxide film including a crystal part, which is a metal oxide film, is formed using a sputtering target including a polycrystalline oxide having a plurality of crystal grains, a sputtering target not including a polycrystalline oxide is used. Compared with the case where it had, the metal oxide film which has crystallinity is easy to be obtained.
　以下に、金属酸化物膜の成膜メカニズムにおける一考察について説明する。スパッタリング用ターゲットが複数の結晶粒を有し、且つ、その結晶粒が層状構造を有しており、当該結晶粒に劈開しやすい界面が存在する場合、当該スパッタリング用ターゲットにイオンを衝突させることで、結晶粒が劈開して、平板状又はペレット状のスパッタリング粒子が得られることがある。該得られた平板状又はペレット状のスパッタリング粒子が、基板上に堆積することでナノ結晶を含む金属酸化物膜が成膜されると考えられる。また、基板を加熱することにより、基板表面において当該ナノ結晶同士の結合、または再配列が進むことにより、配向性を有する結晶部を含む金属酸化物膜が形成されやすくなると考えられる。 In the following, a consideration on the film formation mechanism of the metal oxide film will be described. When the sputtering target has a plurality of crystal grains and the crystal grains have a layered structure, and there is an interface that is easily cleaved, the ions are allowed to collide with the sputtering target. The crystal grains may be cleaved to obtain flat or pellet-like sputtered particles. It is considered that the obtained flat or pellet-like sputtered particles are deposited on a substrate to form a metal oxide film containing nanocrystals. In addition, it is considered that by heating the substrate, bonding or rearrangement of the nanocrystals progresses on the substrate surface, so that a metal oxide film including a crystal part having orientation is easily formed.
　なお、ここではスパッタリング法により形成する方法について説明したが、特にスパッタリング法を用いることで、結晶性の制御が容易であるため好ましい。なお、スパッタリング法以外に、例えばパルスレーザ堆積（ＰＬＤ）法、プラズマ化学気相堆積（ＰＥＣＶＤ）法、熱ＣＶＤ（Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、ＡＬＤ（Ａｔｏｍｉｃ　Ｌａｙｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、真空蒸着法などを用いてもよい。熱ＣＶＤ法の例としては、ＭＯＣＶＤ（Ｍｅｔａｌ　Ｏｒｇａｎｉｃ　Ｃｈｅｍｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法が挙げられる。 Note that although a method of forming by a sputtering method has been described here, a sputtering method is particularly preferable because the crystallinity can be easily controlled. In addition to the sputtering method, for example, a pulse laser deposition (PLD) method, a plasma chemical vapor deposition (PECVD) method, a thermal CVD (Chemical Vapor Deposition) method, an ALD (Atomic Layer Deposition) method, a vacuum evaporation method, or the like is used. Also good. An example of the thermal CVD method is a MOCVD (Metal Organic Chemical Vapor Deposition) method.
［金属酸化物膜の組成及び構造について］
　本発明の一態様の金属酸化物膜をトランジスタなどの半導体装置に適用することができる。以下では、特に半導体特性を有する金属酸化物膜（以降、酸化物半導体膜と呼ぶ）について説明する。 [Composition and structure of metal oxide film]
The metal oxide film of one embodiment of the present invention can be applied to a semiconductor device such as a transistor. Hereinafter, a metal oxide film having semiconductor characteristics (hereinafter referred to as an oxide semiconductor film) will be described.
〔組成について〕
　まず、酸化物半導体膜の組成について説明する。 [Composition]
First, the composition of the oxide semiconductor film is described.
　酸化物半導体膜は、先の記載のように、インジウム（Ｉｎ）と、Ｍ（ＭはＡｌ、Ｇａ、Ｙ、またはＳｎを表す。）と、Ｚｎ（亜鉛）と、を有する。 As described above, the oxide semiconductor film includes indium (In), M (M represents Al, Ga, Y, or Sn), and Zn (zinc).
　なお、元素Ｍは、アルミニウム、ガリウム、イットリウムまたはスズとするが、元素Ｍに適用可能な元素としては、上記以外にも、ホウ素、シリコン、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、マグネシウムなどを用いてもよい。また、元素Ｍとして、前述の元素を複数組み合わせても構わない。 Note that the element M is aluminum, gallium, yttrium, or tin, but as elements applicable to the element M, in addition to the above, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, Cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be used. Further, as the element M, a plurality of the aforementioned elements may be combined.
　次に、本発明の一態様に係る酸化物半導体膜が有するインジウム、元素Ｍ及び亜鉛の原子数比の好ましい範囲について、図１３（Ａ）、（Ｂ）、（Ｃ）を用いて説明する。なお、図１３（Ａ）、（Ｂ）、（Ｃ）には、酸素の原子数比については記載しない。また、酸化物半導体膜が有するインジウム、元素Ｍ、及び亜鉛の原子数比のそれぞれの項を［Ｉｎ］、［Ｍ］、及び［Ｚｎ］とする。 Next, a preferable range of the atomic ratio of indium, element M, and zinc included in the oxide semiconductor film of one embodiment of the present invention is described with reference to FIGS. In FIGS. 13A, 13B, and 13C, the atomic ratio of oxygen is not described. The terms of the atomic ratio of indium, element M, and zinc included in the oxide semiconductor film are [In], [M], and [Zn].
　図１３（Ａ）、（Ｂ）、（Ｃ）において、破線は、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝（１＋α）：（１−α）：１の原子数比（−１≦α≦１）となるライン、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝（１＋α）：（１−α）：２の原子数比となるライン、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝（１＋α）：（１−α）：３の原子数比となるライン、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝（１＋α）：（１−α）：４の原子数比となるライン、及び［Ｉｎ］：［Ｍ］：［Ｚｎ］＝（１＋α）：（１−α）：５の原子数比となるラインを表す。 13 (A), (B), and (C), the broken line indicates the atomic ratio of [In]: [M]: [Zn] = (1 + α) :( 1-α): 1 (−1 ≦ α ≦ 1), [In]: [M]: [Zn] = (1 + α) :( 1−α): line having an atomic ratio of 2 [In]: [M]: [Zn] = (1 + α): (1-α): a line having an atomic ratio of 3; [In]: [M]: [Zn] = (1 + α): (1-α): a line having an atomic ratio of 4; And [In]: [M]: [Zn] = (1 + α) :( 1-α): A line having an atomic ratio of 5.
　また、一点鎖線は、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝１：１：βの原子数比（β≧０）となるライン、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝１：２：βの原子数比となるライン、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝１：３：βの原子数比となるライン、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝１：４：βの原子数比となるライン、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝２：１：βの原子数比となるライン、及び［Ｉｎ］：［Ｍ］：［Ｚｎ］＝５：１：βの原子数比となるラインを表す。 A one-dot chain line is a line having an atomic ratio of [In]: [M]: [Zn] = 1: 1: β (β ≧ 0), [In]: [M]: [Zn] = 1: 2: A line with an atomic ratio of β, [In]: [M]: [Zn] = 1: 3: A line with an atomic ratio of β, [In]: [M]: [Zn] = 1: 4: Line with an atomic ratio of β, [In]: [M]: [Zn] = 2: 1: Line with an atomic ratio of β, and [In]: [M]: [Zn] = 5 : Represents a line with an atomic ratio of 1: β.
　また、図１３に示す、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝０：２：１の原子数比またはその近傍値の酸化物半導体は、スピネル型の結晶構造をとりやすい。 Further, an oxide semiconductor having an atomic ratio of [In]: [M]: [Zn] = 0: 2: 1 or a value close to it shown in FIG. 13 is likely to have a spinel crystal structure.
　図１３（Ａ）、（Ｂ）では、本発明の一態様の酸化物半導体膜が有する、インジウム、元素Ｍ、及び亜鉛の原子数比の好ましい範囲の一例について示している。 13A and 13B illustrate an example of a preferable range of the atomic ratio of indium, element M, and zinc included in the oxide semiconductor film of one embodiment of the present invention.
　一例として、図１４に、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝１：１：１である、ＩｎＭＺｎＯ４の結晶構造を示す。また、図１４は、ｂ軸に平行な方向から観察した場合のＩｎＭＺｎＯ４の結晶構造である。なお、図１４に示すＭ、Ｚｎ、酸素を有する層（以下、（Ｍ，Ｚｎ）層）における金属元素は、元素Ｍまたは亜鉛を表している。この場合、元素Ｍと亜鉛の割合が等しいものとする。元素Ｍと亜鉛とは、置換が可能であり、配列は不規則である。 As an example, FIG. 14 shows a crystal structure of InMZnO 4 in which [In]: [M]: [Zn] = 1: 1: 1. FIG. 14 shows a crystal structure of InMZnO 4 when observed from a direction parallel to the b-axis. Note that a metal element in a layer containing M, Zn, and oxygen (hereinafter, (M, Zn) layer) illustrated in FIG. 14 represents the element M or zinc. In this case, the ratio of the element M and zinc shall be equal. The element M and zinc can be substituted and the arrangement is irregular.
　ＩｎＭＺｎＯ４は、層状の結晶構造（層状構造ともいう）をとり、図１４に示すように、インジウム、及び酸素を有する層（以下、Ｉｎ層）が１に対し、元素Ｍ、亜鉛、及び酸素を有する（Ｍ，Ｚｎ）層が２となる。 InMZnO 4 has a layered crystal structure (also referred to as a layered structure). As shown in FIG. 14, a layer containing indium and oxygen (hereinafter referred to as an In layer) contains 1 element M, zinc, and oxygen. The (M, Zn) layer having 2 is 2.
　また、インジウムと元素Ｍは、互いに置換可能である。そのため、（Ｍ，Ｚｎ）層の元素Ｍがインジウムと置換し、（Ｉｎ，Ｍ，Ｚｎ）層と表すこともできる。その場合、Ｉｎ層が１に対し、（Ｉｎ，Ｍ，Ｚｎ）層が２である層状構造をとる。 Also, indium and element M can be substituted for each other. Therefore, the element M in the (M, Zn) layer can be replaced with indium and expressed as an (In, M, Zn) layer. In that case, a layered structure in which the In layer is 1 and the (In, M, Zn) layer is 2 is employed.
　［Ｉｎ］：［Ｍ］：［Ｚｎ］＝１：１：２となる原子数比の酸化物は、Ｉｎ層が１に対し、（Ｍ，Ｚｎ）層が３である層状構造をとる。つまり、［Ｉｎ］および［Ｍ］に対し［Ｚｎ］が大きくなると、酸化物が結晶化した場合、Ｉｎ層に対する（Ｍ，Ｚｎ）層の割合が増加する。 An oxide having an atomic ratio of [In]: [M]: [Zn] = 1: 1: 2 has a layered structure in which the In layer is 1 and the (M, Zn) layer is 3. That is, when [Zn] increases with respect to [In] and [M], when the oxide is crystallized, the ratio of the (M, Zn) layer to the In layer increases.
　ただし、酸化物中において、Ｉｎ層が１層に対し、（Ｍ，Ｚｎ）層の層数が非整数である場合、Ｉｎ層が１層に対し、（Ｍ，Ｚｎ）層の層数が整数である層状構造を複数種有する場合がある。例えば、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝１：１：１．５である場合、Ｉｎ層が１に対し、（Ｍ，Ｚｎ）層が２である層状構造と、（Ｍ，Ｚｎ）層が３である層状構造とが混在する層状構造となる場合がある。 However, in the oxide, when the number of (M, Zn) layers is non-integer with respect to one In layer, the number of (M, Zn) layers is integer with respect to one In layer. In some cases, a plurality of layered structures are present. For example, when [In]: [M]: [Zn] = 1: 1: 1.5, a layered structure in which the In layer is 1 and the (M, Zn) layer is 2, and (M, Zn) ) There may be a layered structure in which a layered structure having three layers is mixed.
　例えば、酸化物半導体膜をスパッタリング装置にて成膜する場合、ターゲットの原子数比からずれた原子数比の膜が形成される。特に、成膜時の基板温度によっては、ターゲットの［Ｚｎ］よりも、膜の［Ｚｎ］が小さくなる場合がある。 For example, when an oxide semiconductor film is formed using a sputtering apparatus, a film having an atomic ratio that deviates from the atomic ratio of the target is formed. In particular, depending on the substrate temperature during film formation, [Zn] of the film may be smaller than [Zn] of the target.
　また、酸化物半導体膜中に複数の相が共存する場合がある（二相共存、三相共存など）。例えば、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝０：２：１の原子数比の近傍値である原子数比では、スピネル型の結晶構造と層状の結晶構造との二相が共存しやすい。また、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝１：０：０を示す原子数比の近傍値である原子数比では、ビックスバイト型の結晶構造と層状の結晶構造との二相が共存しやすい。酸化物半導体膜中に複数の相が共存する場合、異なる結晶構造の間において、粒界（グレインバウンダリーともいう）が形成される場合がある。 In addition, a plurality of phases may coexist in the oxide semiconductor film (two-phase coexistence, three-phase coexistence, etc.). For example, at an atomic ratio which is a value close to the atomic ratio of [In]: [M]: [Zn] = 0: 2: 1, two phases of a spinel crystal structure and a layered crystal structure coexist. Cheap. In addition, when the atomic ratio is a value close to the atomic ratio indicating [In]: [M]: [Zn] = 1: 0: 0, the biphasic crystal structure and the layered crystal structure have two phases. Easy to coexist. In the case where a plurality of phases coexist in an oxide semiconductor film, a grain boundary (also referred to as a grain boundary) may be formed between different crystal structures.
　酸化物半導体膜中のインジウム及び亜鉛の含有率が低くなると、キャリア移動度が低くなる。従って、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝０：１：０を示す原子数比、及びその近傍値である原子数比（例えば図１３（Ｃ）に示す領域Ｃ）では、絶縁性が高くなる。 When the content ratio of indium and zinc in the oxide semiconductor film is lowered, the carrier mobility is lowered. Therefore, in the atomic number ratio indicating [In]: [M]: [Zn] = 0: 1: 0 and the atomic number ratio which is a neighborhood value thereof (for example, the region C shown in FIG. 13C), the insulating property is increased. Becomes higher.
　従って、本発明の一態様の酸化物半導体は、キャリア移動度が高く、かつ、粒界が少ない層状構造となりやすい、図１３（Ａ）の領域Ａで示される原子数比を有することが好ましい。 Therefore, it is preferable that the oxide semiconductor of one embodiment of the present invention have an atomic ratio shown in a region A in FIG. 13A in which a carrier mobility is high and a layered structure with few grain boundaries is likely to be formed.
　また、図１３（Ｂ）に示す領域Ｂは、［Ｉｎ］：［Ｍ］：［Ｚｎ］＝４：２：３から４．１、及びその近傍値を示している。近傍値には、例えば、原子数比が［Ｉｎ］：［Ｍ］：［Ｚｎ］＝５：３：４が含まれる。領域Ｂで示される原子数比を有する酸化物半導体膜は、特に、結晶性が高く、キャリア移動度も高い優れた酸化物半導体膜である。 In addition, a region B shown in FIG. 13B shows [In]: [M]: [Zn] = 4: 2: 3 to 4.1 and its neighborhood values. The neighborhood value includes, for example, an atomic ratio of [In]: [M]: [Zn] = 5: 3: 4. An oxide semiconductor film having an atomic ratio represented by the region B is an excellent oxide semiconductor film that has particularly high crystallinity and high carrier mobility.
　なお、酸化物半導体膜が、層状構造を形成する条件は、原子数比によって一義的に定まらない。原子数比により、層状構造を形成するための難易の差はある。一方、同じ原子数比であっても、形成条件により、層状構造になる場合も層状構造にならない場合もある。従って、図示する領域は、酸化物半導体膜が層状構造を有する原子数比を示す領域であり、領域Ａ乃至領域Ｃの境界は厳密ではない。 Note that the conditions under which the oxide semiconductor film forms a layered structure are not uniquely determined by the atomic ratio. Depending on the atomic ratio, there is a difference in difficulty for forming a layered structure. On the other hand, even if the atomic ratio is the same, there may be a layered structure or a layered structure depending on the formation conditions. Therefore, the illustrated region is a region that exhibits an atomic ratio in which the oxide semiconductor film has a layered structure, and the boundaries between the regions A to C are not strict.
〔酸化物半導体膜をトランジスタに用いる構成〕
　続いて、酸化物半導体膜をトランジスタに用いる構成について説明する。 [Configuration using oxide semiconductor film for transistor]
Next, a structure in which the oxide semiconductor film is used for a transistor is described.
　なお、酸化物半導体膜をトランジスタに用いることで、例えば、多結晶シリコンをチャネル領域に用いたトランジスタと比較し、結晶粒界におけるキャリア散乱等を減少させることができるため、高い電界効果移動度のトランジスタを実現することができる。また、信頼性の高いトランジスタを実現することができる。 Note that by using an oxide semiconductor film for a transistor, for example, carrier scattering at a crystal grain boundary can be reduced as compared with a transistor using polycrystalline silicon for a channel region. A transistor can be realized. In addition, a highly reliable transistor can be realized.
　本発明の一態様の酸化物半導体膜は、配向性を有する結晶部と、配向性を有さない結晶部とが混在している膜である。このような結晶性を有する酸化物半導体膜を用いることで、高い電界効果移動度と、高い信頼性を両立したトランジスタを実現することができる。 The oxide semiconductor film of one embodiment of the present invention is a film in which a crystal part having orientation and a crystal part not having orientation are mixed. By using such an oxide semiconductor film having crystallinity, a transistor having both high field-effect mobility and high reliability can be realized.
〔酸化物半導体のキャリア密度〕
　酸化物半導体膜のキャリア密度について、以下に説明を行う。 [Carrier density of oxide semiconductor]
The carrier density of the oxide semiconductor film is described below.
　酸化物半導体膜のキャリア密度に影響を与える因子としては、酸化物半導体膜中の酸素欠損（Ｖｏ）、または酸化物半導体膜中の不純物などが挙げられる。 As a factor that affects the carrier density of the oxide semiconductor film, oxygen vacancies (Vo) in the oxide semiconductor film, impurities in the oxide semiconductor film, and the like can be given.
　酸化物半導体膜中の酸素欠損が多くなると、該酸素欠損に水素が結合（この状態をＶｏＨともいう）した際に、欠陥準位密度が高くなる。または、酸化物半導体膜中の不純物が多くなると、該不純物に起因し欠陥準位密度が高くなる。したがって、酸化物半導体膜中の欠陥準位密度を制御することで、酸化物半導体膜のキャリア密度を制御することができる。 When the number of oxygen vacancies in the oxide semiconductor film increases, the density of defect states increases when hydrogen is bonded to the oxygen vacancies (this state is also referred to as VoH). Alternatively, when the number of impurities in the oxide semiconductor film is increased, the density of defect states is increased due to the impurities. Therefore, the carrier density of the oxide semiconductor film can be controlled by controlling the density of defect states in the oxide semiconductor film.
　ここで、酸化物半導体膜をチャネル領域に用いるトランジスタを考える。 Here, a transistor using an oxide semiconductor film for a channel region is considered.
　トランジスタのしきい値電圧のマイナスシフトの抑制、またはトランジスタのオフ電流の低減を目的とする場合においては、酸化物半導体膜のキャリア密度を低くする方が好ましい。酸化物半導体膜のキャリア密度を低くする場合においては、酸化物半導体膜中の不純物濃度を低くし、欠陥準位密度を低くすればよい。本明細書等において、不純物濃度が低く、欠陥準位密度の低いことを高純度真性または実質的に高純度真性と言う。高純度真性の酸化物半導体膜のキャリア密度としては、８×１０１５ｃｍ−３未満、好ましくは１×１０１１ｃｍ−３未満、さらに好ましくは１×１０１０ｃｍ−３未満であり、１×１０−９ｃｍ−３以上とすればよい。 In the case where the object is to suppress a negative shift in the threshold voltage of the transistor or to reduce the off-state current of the transistor, it is preferable to reduce the carrier density of the oxide semiconductor film. In the case where the carrier density of the oxide semiconductor film is decreased, the impurity concentration in the oxide semiconductor film may be decreased and the defect level density may be decreased. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic. The carrier density of the high-purity intrinsic oxide semiconductor film is less than 8 × 10 15 cm −3 , preferably less than 1 × 10 11 cm −3 , more preferably less than 1 × 10 10 cm −3 , and 1 × What is necessary is just to set it as 10 <-9 > cm <-3 > or more.
　一方で、トランジスタのオン電流の向上、またはトランジスタの電界効果移動度の向上を目的とする場合においては、酸化物半導体膜のキャリア密度を高くする方が好ましい。酸化物半導体膜のキャリア密度を高くする場合においては、酸化物半導体膜の不純物濃度をわずかに高める、または酸化物半導体膜の欠陥準位密度をわずかに高めればよい。あるいは、酸化物半導体膜のバンドギャップをより小さくするとよい。例えば、トランジスタのＩｄ−Ｖｇ特性のオン／オフ比が取れる範囲において、不純物濃度がわずかに高い、または欠陥準位密度がわずかに高い酸化物半導体膜は、実質的に真性とみなせる。また、電子親和力が大きく、それにともなってバンドギャップが小さくなり、その結果、熱励起された電子（キャリア）の密度が増加した酸化物半導体膜は、実質的に真性とみなせる。なお、より電子親和力が大きな酸化物半導体膜を用いた場合には、トランジスタのしきい値電圧がより低くなる。 On the other hand, for the purpose of improving the on-state current of a transistor or improving the field-effect mobility of a transistor, it is preferable to increase the carrier density of an oxide semiconductor film. In the case of increasing the carrier density of the oxide semiconductor film, the impurity concentration of the oxide semiconductor film may be slightly increased or the defect state density of the oxide semiconductor film may be slightly increased. Alternatively, the band gap of the oxide semiconductor film is preferably made smaller. For example, an oxide semiconductor film with a slightly high impurity concentration or a slightly high defect state density within a range where the on / off ratio of the Id-Vg characteristics of the transistor can be obtained can be regarded as substantially intrinsic. In addition, an oxide semiconductor film in which the electron affinity is large and the band gap is accordingly reduced, and as a result, the density of thermally excited electrons (carriers) is increased, can be substantially regarded as intrinsic. Note that in the case where an oxide semiconductor film with higher electron affinity is used, the threshold voltage of the transistor is lower.
　上述のキャリア密度が高められた酸化物半導体膜は、わずかにｎ型化している。したがって、キャリア密度が高められた酸化物半導体膜を、「Ｓｌｉｇｈｔｌｙ−ｎ」と呼称してもよい。 The oxide semiconductor film with the increased carrier density is slightly n-type. Therefore, an oxide semiconductor film with an increased carrier density may be referred to as “Slightly-n”.
　実質的に真性の酸化物半導体膜のキャリア密度は、１×１０５ｃｍ−３以上１×１０１８ｃｍ−３未満が好ましく、１×１０７ｃｍ−３以上１×１０１７ｃｍ−３以下がより好ましく、１×１０９ｃｍ−３以上５×１０１６ｃｍ−３以下がさらに好ましく、１×１０１０ｃｍ−３以上１×１０１６ｃｍ−３以下がさらに好ましく、１×１０１１ｃｍ−３以上１×１０１５ｃｍ−３以下がさらに好ましい。 The carrier density of the substantially intrinsic oxide semiconductor film is preferably 1 × 10 5 cm −3 or more and less than 1 × 10 18 cm −3 , preferably 1 × 10 7 cm −3 or more and 1 × 10 17 cm −3 or less. More preferably, it is 1 × 10 9 cm −3 or more and 5 × 10 16 cm −3 or less, more preferably 1 × 10 10 cm −3 or more and 1 × 10 16 cm −3 or less, and further preferably 1 × 10 11 cm −3. More preferably, it is 1 × 10 15 cm −3 or less.
　また、上述の実質的に真性の酸化物半導体膜を用いることで、トランジスタの信頼性が向上する場合がある。ここで、図１５を用いて、酸化物半導体膜をチャネル領域に用いるトランジスタの信頼性が向上する理由について説明する。図１５は、酸化物半導体膜をチャネル領域に用いるトランジスタにおけるエネルギーバンドを説明する図である。 In addition, the use of the above-described substantially intrinsic oxide semiconductor film may improve the reliability of the transistor. Here, the reason why the reliability of a transistor in which an oxide semiconductor film is used for a channel region is improved will be described with reference to FIGS. FIG. 15 illustrates an energy band in a transistor in which an oxide semiconductor film is used for a channel region.
　図１５において、ＧＥはゲート電極を、ＧＩはゲート絶縁膜を、ＯＳは酸化物半導体膜を、ＳＤはソース電極またはドレイン電極を、それぞれ表す。すなわち、図１５は、ゲート電極と、ゲート絶縁膜と、酸化物半導体膜と、酸化物半導体膜に接するソース電極またはドレイン電極のエネルギーバンドの一例である。 15, GE represents a gate electrode, GI represents a gate insulating film, OS represents an oxide semiconductor film, and SD represents a source electrode or a drain electrode. That is, FIG. 15 illustrates an example of the energy band of the gate electrode, the gate insulating film, the oxide semiconductor film, and the source or drain electrode in contact with the oxide semiconductor film.
　また、図１５において、ゲート絶縁膜としては、酸化シリコン膜を用い、酸化物半導体膜にＩｎ−Ｇａ−Ｚｎ酸化物を用いる構成である。また、酸化シリコン膜中に形成されうる欠陥の遷移レベル（εｆ）はゲート絶縁膜の伝導帯下端から約３．１ｅＶ離れた位置に形成されるものとし、ゲート電圧（Ｖｇ）が３０Ｖの場合の酸化物半導体膜と酸化シリコン膜との界面における酸化シリコン膜のフェルミ準位（Ｅｆ）はゲート絶縁膜の伝導帯下端から約３．６ｅＶ離れた位置に形成されるものとする。なお、酸化シリコン膜のフェルミ準位は、ゲート電圧に依存し変動する。例えば、ゲート電圧を大きくすることで、酸化物半導体膜と、酸化シリコン膜との界面における酸化シリコン膜のフェルミ準位（Ｅｆ）は低くなる。また、図１５中の白丸は電子（キャリア）を表し、図１５中のＸは酸化シリコン膜中の欠陥準位を表す。 Further, in FIG. 15, a silicon oxide film is used as the gate insulating film and an In—Ga—Zn oxide is used as the oxide semiconductor film. Further, the transition level (εf) of defects that can be formed in the silicon oxide film is formed at a position about 3.1 eV away from the lower end of the conduction band of the gate insulating film, and the gate voltage (Vg) is 30V. The Fermi level (Ef) of the silicon oxide film at the interface between the oxide semiconductor film and the silicon oxide film is formed at a position about 3.6 eV away from the lower end of the conduction band of the gate insulating film. Note that the Fermi level of the silicon oxide film varies depending on the gate voltage. For example, when the gate voltage is increased, the Fermi level (Ef) of the silicon oxide film at the interface between the oxide semiconductor film and the silicon oxide film is lowered. Further, white circles in FIG. 15 represent electrons (carriers), and X in FIG. 15 represents a defect level in the silicon oxide film.
　図１５に示すように、ゲート電圧が印加された状態で、例えばキャリアが熱励起されると、欠陥準位（図中Ｘ）にキャリアがトラップされ、プラス（“＋”）からニュートラル（“０”）に欠陥準位の荷電状態が変化する。すなわち、酸化シリコン膜のフェルミ準位（Ｅｆ）に上述の熱励起のエネルギーを足した値が欠陥の遷移レベル（εｆ）よりも高くなる場合、酸化シリコン膜中の欠陥準位の荷電状態は正の状態から中性となり、トランジスタのしきい値電圧がプラス方向に変動することになる。 As shown in FIG. 15, for example, when carriers are thermally excited in a state where a gate voltage is applied, carriers are trapped at a defect level (X in the figure) and neutral ("0") from plus ("+"). ”), The charge state of the defect level changes. That is, when the value obtained by adding the above-described thermal excitation energy to the Fermi level (Ef) of the silicon oxide film becomes higher than the defect transition level (εf), the charge state of the defect level in the silicon oxide film is positive. From this state, the transistor becomes neutral, and the threshold voltage of the transistor fluctuates in the positive direction.
　また、電子親和力が異なる酸化物半導体膜を用いると、ゲート絶縁膜と酸化物半導体膜との界面のフェルミ準位が形成される深さが異なることがある。電子親和力の大きな酸化物半導体膜を用いると、ゲート絶縁膜と酸化物半導体膜との界面近傍において、ゲート絶縁膜の伝導帯下端が相対的に高くなる。この場合、ゲート絶縁膜中に形成されうる欠陥準位（図１５中Ｘ）も相対的に高くなるため、ゲート絶縁膜のフェルミ準位と、酸化物半導体膜のフェルミ準位とのエネルギー差が大きくなる。該エネルギー差が大きくなることにより、ゲート絶縁膜中にトラップされる電荷が少なくなる。例えば、上述の酸化シリコン膜中に形成されうる欠陥準位の荷電状態の変化が少なくなり、ゲートバイアス熱（Ｇａｔｅ　Ｂｉａｓ　Ｔｅｍｐｅｒａｔｕｒｅ：ＧＢＴともいう）ストレスにおける、トランジスタのしきい値電圧の変動を小さくできる。 In addition, when oxide semiconductor films having different electron affinities are used, the depth at which the Fermi level at the interface between the gate insulating film and the oxide semiconductor film is formed may be different. When an oxide semiconductor film with high electron affinity is used, the lower end of the conduction band of the gate insulating film is relatively high in the vicinity of the interface between the gate insulating film and the oxide semiconductor film. In this case, since a defect level (X in FIG. 15) that can be formed in the gate insulating film is also relatively high, an energy difference between the Fermi level of the gate insulating film and the Fermi level of the oxide semiconductor film is increased. growing. As the energy difference increases, the charge trapped in the gate insulating film decreases. For example, the change in the charge state of the defect level that can be formed in the above-described silicon oxide film is reduced, and variation in the threshold voltage of the transistor due to gate bias thermal (also referred to as GBT) stress can be reduced. .
　また、酸化物半導体膜の欠陥準位に捕獲された電荷は、消失するまでに要する時間が長く、あたかも固定電荷のように振る舞うことがある。そのため、欠陥準位密度の高い酸化物半導体膜にチャネル領域が形成されるトランジスタは、電気特性が不安定となる場合がある。 In addition, the charge trapped in the defect level of the oxide semiconductor film takes a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor film with a high defect level density may have unstable electrical characteristics.
　従って、トランジスタの電気特性を安定にするためには、酸化物半導体膜中の不純物濃度を低減することが有効である。また、酸化物半導体膜中の不純物濃度を低減するためには、近接する膜中の不純物濃度も低減することが好ましい。不純物としては、水素、窒素、アルカリ金属、アルカリ土類金属、鉄、ニッケル、シリコン等がある。 Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor film. In order to reduce the impurity concentration in the oxide semiconductor film, it is preferable to reduce the impurity concentration in an adjacent film. Impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.
　ここで、酸化物半導体膜中における各不純物の影響について説明する。 Here, the influence of each impurity in the oxide semiconductor film will be described.
　酸化物半導体膜において、第１４族元素の一つであるシリコンや炭素が含まれると、酸化物半導体膜において欠陥準位が形成される。このため、酸化物半導体膜におけるシリコンや炭素の濃度と、酸化物半導体膜との界面近傍のシリコンや炭素の濃度（二次イオン質量分析法（ＳＩＭＳ：Ｓｅｃｏｎｄａｒｙ　Ｉｏｎ　Ｍａｓｓ　Ｓｐｅｃｔｒｏｍｅｔｒｙ）により得られる濃度）を、２×１０１８ａｔｏｍｓ／ｃｍ３以下、好ましくは２×１０１７ａｔｏｍｓ／ｃｍ３以下とする。 In the oxide semiconductor film, when silicon or carbon which is one of Group 14 elements is included, a defect level is formed in the oxide semiconductor film. Therefore, the concentration of silicon or carbon in the oxide semiconductor film and the concentration of silicon or carbon in the vicinity of the interface with the oxide semiconductor film (concentration obtained by secondary ion mass spectrometry (SIMS)) are obtained. 2 × 10 18 atoms / cm 3 or less, preferably 2 × 10 17 atoms / cm 3 or less.
　また、酸化物半導体膜にアルカリ金属またはアルカリ土類金属が含まれると、欠陥準位を形成し、キャリアを生成する場合がある。従って、アルカリ金属またはアルカリ土類金属が含まれている酸化物半導体膜を用いたトランジスタはノーマリーオン特性となりやすい。このため、酸化物半導体膜中のアルカリ金属またはアルカリ土類金属の濃度を低減することが好ましい。具体的には、ＳＩＭＳにより得られる酸化物半導体膜中のアルカリ金属またはアルカリ土類金属の濃度を、１×１０１８ａｔｏｍｓ／ｃｍ３以下、好ましくは２×１０１６ａｔｏｍｓ／ｃｍ３以下にする。 In addition, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor film, a defect level may be formed and carriers may be generated. Therefore, a transistor including an oxide semiconductor film containing an alkali metal or an alkaline earth metal is likely to be normally on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor film. Specifically, the concentration of alkali metal or alkaline earth metal in the oxide semiconductor film obtained by SIMS is set to 1 × 10 18 atoms / cm 3 or lower, preferably 2 × 10 16 atoms / cm 3 or lower.
　また、酸化物半導体膜において、窒素が含まれると、キャリアである電子が生じ、キャリア密度が増加し、ｎ型になりやすい。この結果、窒素が含まれている酸化物半導体膜を半導体に用いたトランジスタはノーマリーオン特性となりやすい。従って、該酸化物半導体膜において、窒素はできる限り低減されていることが好ましい、例えば、酸化物半導体膜中の窒素濃度は、ＳＩＭＳにおいて、５×１０１９ａｔｏｍｓ／ｃｍ３未満、好ましくは５×１０１８ａｔｏｍｓ／ｃｍ３以下、より好ましくは１×１０１８ａｔｏｍｓ／ｃｍ３以下、さらに好ましくは５×１０１７ａｔｏｍｓ／ｃｍ３以下とする。 In addition, when nitrogen is contained in the oxide semiconductor film, electrons as carriers are generated, the carrier density is increased, and the oxide semiconductor film is likely to be n-type. As a result, a transistor using an oxide semiconductor film containing nitrogen as a semiconductor is likely to be normally on. Therefore, nitrogen in the oxide semiconductor film is preferably reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor film is less than 5 × 10 19 atoms / cm 3 in SIMS, preferably 5 ×. 10 18 atoms / cm 3 or less, more preferably 1 × 10 18 atoms / cm 3 or less, and even more preferably 5 × 10 17 atoms / cm 3 or less.
　また、酸化物半導体膜に含まれる水素は、金属原子と結合する酸素と反応して水になるため、酸素欠損を形成する場合がある。該酸素欠損に水素が入ることで、キャリアである電子が生成される場合がある。また、水素の一部が金属原子と結合する酸素と結合して、キャリアである電子を生成することがある。従って、水素が含まれている酸化物半導体膜を用いたトランジスタはノーマリーオン特性となりやすい。このため、酸化物半導体膜中の水素はできる限り低減されていることが好ましい。具体的には、酸化物半導体膜において、ＳＩＭＳにより得られる水素濃度を、１×１０２０ａｔｏｍｓ／ｃｍ３未満、好ましくは１×１０１９ａｔｏｍｓ／ｃｍ３未満、より好ましくは５×１０１８ａｔｏｍｓ／ｃｍ３未満、さらに好ましくは１×１０１８ａｔｏｍｓ／ｃｍ３未満とする。 In addition, hydrogen contained in the oxide semiconductor film reacts with oxygen bonded to a metal atom to become water, so that an oxygen vacancy may be formed in some cases. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor including an oxide semiconductor film containing hydrogen is likely to be normally on. For this reason, it is preferable that hydrogen in the oxide semiconductor film be reduced as much as possible. Specifically, in the oxide semiconductor film, the hydrogen concentration obtained by SIMS is less than 1 × 10 20 atoms / cm 3 , preferably less than 1 × 10 19 atoms / cm 3 , more preferably 5 × 10 18 atoms / cm 3. Less than cm 3 , more preferably less than 1 × 10 18 atoms / cm 3 .
　不純物が十分に低減された酸化物半導体膜をトランジスタのチャネル形成領域に用いることで、安定した電気特性を付与することができる。 By using an oxide semiconductor film in which impurities are sufficiently reduced for a channel formation region of a transistor, stable electric characteristics can be provided.
　また、酸化物半導体膜は、エネルギーギャップが２ｅＶ以上、または２．５ｅＶ以上であると好ましい。 In addition, the oxide semiconductor film preferably has an energy gap of 2 eV or more, or 2.5 eV or more.
　また、酸化物半導体膜の厚さは、３ｎｍ以上２００ｎｍ以下、好ましくは３ｎｍ以上１００ｎｍ以下、さらに好ましくは３ｎｍ以上６０ｎｍ以下である。 The thickness of the oxide semiconductor film is 3 nm to 200 nm, preferably 3 nm to 100 nm, more preferably 3 nm to 60 nm.
　また、酸化物半導体膜がＩｎ−Ｍ−Ｚｎ酸化物の場合、Ｉｎ−Ｍ−Ｚｎ酸化物を成膜するために用いるスパッタリングターゲットの金属元素の原子数比として、Ｉｎ：Ｍ：Ｚｎ＝１：１：０．５、Ｉｎ：Ｍ：Ｚｎ＝１：１：１、Ｉｎ：Ｍ：Ｚｎ＝１：１：１．２、Ｉｎ：Ｍ：Ｚｎ＝２：１：１．５、Ｉｎ：Ｍ：Ｚｎ＝２：１：２．３、Ｉｎ：Ｍ：Ｚｎ＝２：１：３、Ｉｎ：Ｍ：Ｚｎ＝３：１：２、Ｉｎ：Ｍ：Ｚｎ＝４：２：４．１、Ｉｎ：Ｍ：Ｚｎ＝５：１：７等が好ましい。 In the case where the oxide semiconductor film is an In-M-Zn oxide, the atomic ratio of metal elements of a sputtering target used for forming the In-M-Zn oxide is In: M: Zn = 1: 1: 0.5, In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 2: 1: 1.5, In: M: Zn = 2: 1: 2.3, In: M: Zn = 2: 1: 3, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 4.1, In: M: Zn = 5: 1: 7 etc. are preferable.
　本実施の形態は、少なくともその一部を本明細書中に記載する他の実施の形態と適宜組み合わせて実施することができる。 Note that at least part of this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate.
（実施の形態２）
　本実施の形態では、本発明の一態様の半導体装置に用いることのできるトランジスタについて、詳細に説明する。 (Embodiment 2)
In this embodiment, a transistor that can be used for the semiconductor device of one embodiment of the present invention will be described in detail.
　なお、本実施の形態では、トップゲート構造のトランジスタについて、図１６乃至図２７を用いて説明する。 Note that in this embodiment, a top-gate transistor is described with reference to FIGS.
［２−１．トランジスタの構成例１］
　図１６（Ａ）は、トランジスタ１００の上面図であり、図１６（Ｂ）は図１６（Ａ）の一点鎖線Ｘ１−Ｘ２間の断面図であり、図１６（Ｃ）は図１６（Ａ）の一点鎖線Ｙ１−Ｙ２間の断面図である。なお、図１６（Ａ）では、明瞭化のため、絶縁膜１１０などの構成要素を省略して図示している。なお、トランジスタの上面図においては、以降の図面においても図１６（Ａ）と同様に、構成要素の一部を省略して図示する場合がある。また、一点鎖線Ｘ１−Ｘ２方向をチャネル長（Ｌ）方向、一点鎖線Ｙ１−Ｙ２方向をチャネル幅（Ｗ）方向と呼称する場合がある。 [2-1. Transistor configuration example 1]
16A is a top view of the transistor 100, FIG. 16B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 16A, and FIG. 16C is FIG. It is sectional drawing between dashed-dotted lines Y1-Y2. Note that in FIG. 16A, components such as the insulating film 110 are omitted for clarity. Note that in the top view of the transistor, some components may be omitted in the following drawings as in FIG. 16A. In addition, the alternate long and short dash line X1-X2 direction may be referred to as a channel length (L) direction, and the alternate long and short dash line Y1-Y2 direction may be referred to as a channel width (W) direction.
　図１６（Ａ）（Ｂ）（Ｃ）に示すトランジスタ１００は、基板１０２上の絶縁膜１０４と、絶縁膜１０４上の酸化物半導体膜１０８と、酸化物半導体膜１０８上の絶縁膜１１０と、絶縁膜１１０上の導電膜１１２と、絶縁膜１０４、酸化物半導体膜１０８、及び導電膜１１２上の絶縁膜１１６と、を有する。なお、酸化物半導体膜１０８は、導電膜１１２と重なるチャネル領域１０８ｉと、絶縁膜１１６と接するソース領域１０８ｓと、絶縁膜１１６と接するドレイン領域１０８ｄと、を有する。 16A, 16B, and 16C includes an insulating film 104 over a substrate 102, an oxide semiconductor film 108 over the insulating film 104, an insulating film 110 over the oxide semiconductor film 108, The conductive film 112 over the insulating film 110, the insulating film 104, the oxide semiconductor film 108, and the insulating film 116 over the conductive film 112 are included. Note that the oxide semiconductor film 108 includes a channel region 108 i overlapping with the conductive film 112, a source region 108 s in contact with the insulating film 116, and a drain region 108 d in contact with the insulating film 116.
　また、絶縁膜１１６は、窒素または水素を有する。絶縁膜１１６と、ソース領域１０８ｓ及びドレイン領域１０８ｄと、が接することで、絶縁膜１１６中の窒素または水素がソース領域１０８ｓ及びドレイン領域１０８ｄ中に添加される。ソース領域１０８ｓ及びドレイン領域１０８ｄは、窒素または水素が添加されることで、キャリア密度が高くなる。 Further, the insulating film 116 has nitrogen or hydrogen. When the insulating film 116 is in contact with the source region 108s and the drain region 108d, nitrogen or hydrogen in the insulating film 116 is added to the source region 108s and the drain region 108d. In the source region 108s and the drain region 108d, the carrier density is increased by adding nitrogen or hydrogen.
　また、トランジスタ１００は、絶縁膜１１６上の絶縁膜１１８と、絶縁膜１１６、１１８に設けられた開口部１４１ａを介して、ソース領域１０８ｓに電気的に接続される導電膜１２０ａと、絶縁膜１１６、１１８に設けられた開口部１４１ｂを介して、ドレイン領域１０８ｄに電気的に接続される導電膜１２０ｂと、を有していてもよい。 Further, the transistor 100 includes an insulating film 118 over the insulating film 116, a conductive film 120a electrically connected to the source region 108s through the opening 141a provided in the insulating films 116 and 118, and the insulating film 116. , 118 may be provided, and the conductive film 120b electrically connected to the drain region 108d through the opening 141b provided in the opening 118b.
　なお、本明細書等において、絶縁膜１０４を第１の絶縁膜と、絶縁膜１１０を第２の絶縁膜と、絶縁膜１１６を第３の絶縁膜と、絶縁膜１１８を第４の絶縁膜と、それぞれ呼称する場合がある。また、導電膜１１２は、ゲート電極としての機能を有し、導電膜１２０ａは、ソース電極としての機能を有し、導電膜１２０ｂは、ドレイン電極としての機能を有する。 Note that in this specification and the like, the insulating film 104 is a first insulating film, the insulating film 110 is a second insulating film, the insulating film 116 is a third insulating film, and the insulating film 118 is a fourth insulating film. And may be called respectively. In addition, the conductive film 112 functions as a gate electrode, the conductive film 120a functions as a source electrode, and the conductive film 120b functions as a drain electrode.
　また、絶縁膜１１０は、ゲート絶縁膜としての機能を有する。また、絶縁膜１１０は、過剰酸素領域を有する。絶縁膜１１０が過剰酸素領域を有することで、酸化物半導体膜１０８が有するチャネル領域１０８ｉ中に過剰酸素を供給することができる。よって、チャネル領域１０８ｉに形成されうる酸素欠損を過剰酸素により補填することができるため、信頼性の高い半導体装置を提供することができる。 In addition, the insulating film 110 functions as a gate insulating film. In addition, the insulating film 110 has an excess oxygen region. When the insulating film 110 includes the excess oxygen region, excess oxygen can be supplied to the channel region 108 i included in the oxide semiconductor film 108. Accordingly, oxygen vacancies that can be formed in the channel region 108i can be filled with excess oxygen, so that a highly reliable semiconductor device can be provided.
　なお、酸化物半導体膜１０８中に過剰酸素を供給させるためには、酸化物半導体膜１０８の下方に形成される絶縁膜１０４に過剰酸素を供給してもよい。この場合、絶縁膜１０４中に含まれる過剰酸素は、酸化物半導体膜１０８が有するソース領域１０８ｓ、及びドレイン領域１０８ｄにも供給されうる。ソース領域１０８ｓ、及びドレイン領域１０８ｄ中に過剰酸素が供給されると、ソース領域１０８ｓ、及びドレイン領域１０８ｄの抵抗が高くなる場合がある。 Note that in order to supply excess oxygen into the oxide semiconductor film 108, excess oxygen may be supplied to the insulating film 104 formed below the oxide semiconductor film 108. In this case, excess oxygen contained in the insulating film 104 can be supplied also to the source region 108s and the drain region 108d included in the oxide semiconductor film 108. When excess oxygen is supplied into the source region 108s and the drain region 108d, the resistance of the source region 108s and the drain region 108d may increase.
　一方で、酸化物半導体膜１０８の上方に形成される絶縁膜１１０に過剰酸素を有する構成とすることで、チャネル領域１０８ｉにのみ選択的に過剰酸素を供給させることが可能となる。あるいは、チャネル領域１０８ｉ、ソース領域１０８ｓ、及びドレイン領域１０８ｄに過剰酸素を供給させたのち、ソース領域１０８ｓ及びドレイン領域１０８ｄのキャリア密度を選択的に高めることで、ソース領域１０８ｓ、及びドレイン領域１０８ｄの抵抗が高くなることを抑制することができる。 On the other hand, when the insulating film 110 formed over the oxide semiconductor film 108 has excess oxygen, it is possible to selectively supply excess oxygen only to the channel region 108i. Alternatively, after supplying excess oxygen to the channel region 108i, the source region 108s, and the drain region 108d, the carrier density in the source region 108s and the drain region 108d is selectively increased, so that the source region 108s and the drain region 108d It can suppress that resistance becomes high.
　また、酸化物半導体膜１０８が有するソース領域１０８ｓ及びドレイン領域１０８ｄは、それぞれ、酸素欠損を形成する元素、または酸素欠損と結合する元素を有すると好ましい。当該酸素欠損を形成する元素、または酸素欠損と結合する元素としては、代表的には水素、ホウ素、炭素、窒素、フッ素、リン、硫黄、塩素、チタン、希ガス等が挙げられる。また、希ガス元素の代表例としては、ヘリウム、ネオン、アルゴン、クリプトン、及びキセノン等がある。上記酸素欠損を形成する元素が、絶縁膜１１６中に１つまたは複数含まれる場合、絶縁膜１１６からソース領域１０８ｓ、及びドレイン領域１０８ｄに拡散する。または、上記酸素欠損を形成する元素は、不純物添加処理によりソース領域１０８ｓ、及びドレイン領域１０８ｄ中に添加される。 The source region 108s and the drain region 108d included in the oxide semiconductor film 108 preferably each include an element that forms oxygen vacancies or an element that combines with oxygen vacancies. As an element that forms oxygen vacancies or an element that combines with oxygen vacancies, typically, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, a rare gas, or the like can be given. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon. In the case where one or more elements that form oxygen vacancies are included in the insulating film 116, the oxygen vacancies diffuse into the source region 108 s and the drain region 108 d. Alternatively, the element that forms oxygen vacancies is added to the source region 108s and the drain region 108d by impurity addition treatment.
　不純物元素が酸化物半導体膜に添加されると、酸化物半導体膜中の金属元素と酸素の結合が切断され、酸素欠損が形成される。または、不純物元素が酸化物半導体膜に添加されると、酸化物半導体膜中の金属元素と結合していた酸素が不純物元素と結合し、金属元素から酸素が脱離され、酸素欠損が形成される。これらの結果、酸化物半導体膜においてキャリア密度が増加し、導電性が高くなる。 When the impurity element is added to the oxide semiconductor film, the bond between the metal element and oxygen in the oxide semiconductor film is cut, and oxygen vacancies are formed. Alternatively, when an impurity element is added to the oxide semiconductor film, oxygen bonded to the metal element in the oxide semiconductor film is bonded to the impurity element, so that oxygen is released from the metal element and oxygen vacancies are formed. The As a result, the carrier density in the oxide semiconductor film is increased and the conductivity is increased.
　次に、図１６（Ａ）（Ｂ）（Ｃ）に示す半導体装置の構成要素の詳細について説明する。 Next, details of the components of the semiconductor device shown in FIGS. 16A, 16B, and 16C will be described.
〔基板〕
　基板１０２としては、作製工程中の熱処理に耐えうる程度の耐熱性を有する材料を用いることができる。 〔substrate〕
As the substrate 102, a material having heat resistance high enough to withstand heat treatment in a manufacturing process can be used.
　具体的には、無アルカリガラス、ソーダ石灰ガラス、アルカリガラス、クリスタルガラス、石英またはサファイア等を用いることができる。また、無機絶縁膜を用いてもよい。当該無機絶縁膜としては、例えば、酸化シリコン膜、窒化シリコン膜、酸化窒化シリコン膜、酸化アルミニウム膜等が挙げられる。 Specifically, alkali-free glass, soda-lime glass, alkali glass, crystal glass, quartz, sapphire, or the like can be used. In addition, an inorganic insulating film may be used. Examples of the inorganic insulating film include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film.
　また、上記無アルカリガラスとしては、例えば、０．２ｍｍ以上０．７ｍｍ以下の厚さとすればよい。または、無アルカリガラスを研磨することで、上記の厚さとしてもよい。 The non-alkali glass may have a thickness of 0.2 mm to 0.7 mm, for example. Alternatively, the above-described thickness may be obtained by polishing alkali-free glass.
　また、無アルカリガラスとして、第６世代（１５００ｍｍ×１８５０ｍｍ）、第７世代（１８７０ｍｍ×２２００ｍｍ）、第８世代（２２００ｍｍ×２４００ｍｍ）、第９世代（２４００ｍｍ×２８００ｍｍ）、第１０世代（２９５０ｍｍ×３４００ｍｍ）等の面積が大きなガラス基板を用いることができる。これにより、大型の表示装置を作製することができる。 Further, as alkali-free glass, the sixth generation (1500 mm × 1850 mm), the seventh generation (1870 mm × 2200 mm), the eighth generation (2200 mm × 2400 mm), the ninth generation (2400 mm × 2800 mm), the tenth generation (2950 mm × 3400 mm) A glass substrate having a large area such as) can be used. Thus, a large display device can be manufactured.
　また、基板１０２として、シリコンや炭化シリコンからなる単結晶半導体基板、多結晶半導体基板、シリコンゲルマニウム等の化合物半導体基板、ＳＯＩ基板等を用いてもよい。 As the substrate 102, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like may be used.
　また、基板１０２として、金属等の無機材料を用いてもよい。金属等の無機材料としては、ステンレススチールまたはアルミニウム等が挙げられる。 Further, as the substrate 102, an inorganic material such as a metal may be used. Examples of inorganic materials such as metals include stainless steel and aluminum.
　また、基板１０２として、樹脂、樹脂フィルムまたはプラスチック等の有機材料を用いてもよい。当該樹脂フィルムとしては、ポリエステル、ポリオレフィン、ポリアミド（ナイロン、アラミド等）、ポリイミド、ポリカーボネート、ポリウレタン、アクリル樹脂、エポキシ樹脂、ポリエチレンテレフタレート（ＰＥＴ）、ポリエチレンナフタレート（ＰＥＮ）、ポリエーテルサルフォン（ＰＥＳ）、またはシロキサン結合を有する樹脂等が挙げられる。 Further, as the substrate 102, an organic material such as resin, resin film, or plastic may be used. Examples of the resin film include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, polyurethane, acrylic resin, epoxy resin, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES). Or a resin having a siloxane bond.
　また、基板１０２として、無機材料と有機材料とを組み合わせた複合材料を用いてもよい。当該複合材料としては、金属板または薄板状のガラス板と、樹脂フィルムとを貼り合わせた材料、繊維状の金属、粒子状の金属、繊維状のガラス、または粒子状のガラスを樹脂フィルムに分散した材料、もしくは繊維状の樹脂、粒子状の樹脂を無機材料に分散した材料等が挙げられる。 Further, as the substrate 102, a composite material in which an inorganic material and an organic material are combined may be used. As the composite material, a material obtained by bonding a metal plate or a thin glass plate and a resin film, a fibrous metal, a particulate metal, a fibrous glass, or a particulate glass is dispersed in a resin film Or a material obtained by dispersing a fibrous resin or a particulate resin in an inorganic material.
　なお、基板１０２としては、少なくとも上または下に形成される膜または層を支持できるものであればよく、絶縁膜、半導体膜、導電膜のいずれか一つまたは複数であってもよい。 Note that the substrate 102 may be any substrate as long as it can support at least a film or a layer formed thereon or below, and may be any one or more of an insulating film, a semiconductor film, and a conductive film.
〔第１の絶縁膜〕
　絶縁膜１０４としては、スパッタリング法、ＣＶＤ法、蒸着法、パルスレーザー堆積（ＰＬＤ）法、印刷法、塗布法等を適宜用いて形成することができる。また、絶縁膜１０４としては、例えば、酸化物絶縁膜または窒化物絶縁膜を単層または積層して形成することができる。なお、酸化物半導体膜１０８との界面特性を向上させるため、絶縁膜１０４において少なくとも酸化物半導体膜１０８と接する領域は酸化物絶縁膜で形成することが好ましい。また、絶縁膜１０４として加熱により酸素を放出する酸化物絶縁膜を用いることで、加熱処理により絶縁膜１０４に含まれる酸素を、酸化物半導体膜１０８に移動させることが可能である。 [First insulating film]
The insulating film 104 can be formed using a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like as appropriate. As the insulating film 104, for example, an oxide insulating film or a nitride insulating film can be formed as a single layer or a stacked layer. Note that in order to improve interface characteristics with the oxide semiconductor film 108, at least a region in contact with the oxide semiconductor film 108 in the insulating film 104 is preferably formed using an oxide insulating film. In addition, by using an oxide insulating film from which oxygen is released by heating as the insulating film 104, oxygen contained in the insulating film 104 can be transferred to the oxide semiconductor film 108 by heat treatment.
　絶縁膜１０４の厚さは、５０ｎｍ以上、または１００ｎｍ以上３０００ｎｍ以下、または２００ｎｍ以上１０００ｎｍ以下とすることができる。絶縁膜１０４を厚くすることで、絶縁膜１０４の酸素放出量を増加させることができると共に、絶縁膜１０４と酸化物半導体膜１０８との界面における界面準位、並びに酸化物半導体膜１０８のチャネル領域１０８ｉに含まれる酸素欠損を低減することが可能である。 The thickness of the insulating film 104 can be 50 nm or more, 100 nm or more and 3000 nm or less, or 200 nm or more and 1000 nm or less. By increasing the thickness of the insulating film 104, the amount of oxygen released from the insulating film 104 can be increased, the interface state at the interface between the insulating film 104 and the oxide semiconductor film 108, and the channel region of the oxide semiconductor film 108 It is possible to reduce oxygen vacancies contained in 108i.
　絶縁膜１０４として、例えば酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコン、酸化アルミニウム、酸化ハフニウム、酸化ガリウムまたはＧａ−Ｚｎ酸化物などを用いればよく、単層または積層で設けることができる。本実施の形態では、絶縁膜１０４として、窒化シリコン膜と、酸化窒化シリコン膜との積層構造を用いる。このように、絶縁膜１０４を積層構造として、下層側に窒化シリコン膜を用い、上層側に酸化窒化シリコン膜を用いることで、酸化物半導体膜１０８中に効率よく酸素を導入することができる。 As the insulating film 104, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga—Zn oxide, or the like may be used, and the insulating film 104 can be provided as a single layer or a stacked layer. In this embodiment, a stacked structure of a silicon nitride film and a silicon oxynitride film is used as the insulating film 104. In this manner, oxygen can be efficiently introduced into the oxide semiconductor film 108 by using the insulating film 104 as a stacked structure and using a silicon nitride film on the lower layer side and a silicon oxynitride film on the upper layer side.
〔酸化物半導体膜〕
　酸化物半導体膜１０８としては、実施の形態１で説明した金属酸化物膜を用いることができる。 [Oxide semiconductor film]
As the oxide semiconductor film 108, the metal oxide film described in Embodiment 1 can be used.
　また、酸化物半導体膜１０８としては、スパッタリング法で形成すると膜密度を高められるため、好適である。スパッタリング法で酸化物半導体膜１０８を形成する場合、スパッタリングガスには、希ガス（代表的にはアルゴン）、酸素、または希ガス及び酸素の混合ガスが適宜用いられる。また、スパッタリングガスの高純度化も必要である。例えば、スパッタリングガスとして用いる酸素ガスやアルゴンガスは、露点が−６０℃以下、好ましくは−１００℃以下にまで高純度化したガスを用いることで酸化物半導体膜１０８に水分等が取り込まれることを可能な限り防ぐことができる。 The oxide semiconductor film 108 is preferably formed by a sputtering method because the film density can be increased. In the case where the oxide semiconductor film 108 is formed by a sputtering method, a rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen is used as the sputtering gas as appropriate. In addition, it is necessary to increase the purity of the sputtering gas. For example, oxygen gas or argon gas used as a sputtering gas has a dew point of −60 ° C. or lower, preferably −100 ° C. or lower, so that moisture or the like is taken into the oxide semiconductor film 108 by using a highly purified gas. It can be prevented as much as possible.
　また、スパッタリング法で酸化物半導体膜１０８を形成する場合、スパッタリング装置におけるチャンバーを、酸化物半導体膜１０８にとって不純物となる水等を可能な限り除去すべくクライオポンプのような吸着式の真空排気ポンプを用いて、高真空（５×１０−７Ｐａから１×１０−４Ｐａ程度まで）に排気することが好ましい。特に、スパッタリング装置の待機時における、チャンバー内のＨ２Ｏに相当するガス分子（ｍ／ｚ＝１８に相当するガス分子）の分圧を１×１０−４Ｐａ以下、好ましく５×１０−５Ｐａ以下とすることが好ましい。 In the case where the oxide semiconductor film 108 is formed by a sputtering method, an adsorption-type vacuum exhaust pump such as a cryopump is used to remove as much impurities as possible from the oxide semiconductor film 108 in the chamber of the sputtering apparatus. Is preferably exhausted to a high vacuum (from about 5 × 10 −7 Pa to about 1 × 10 −4 Pa). In particular, the partial pressure of gas molecules corresponding to H 2 O in the chamber (gas molecules corresponding to m / z = 18) in the standby state of the sputtering apparatus is 1 × 10 −4 Pa or less, preferably 5 × 10 −5. It is preferable to set it to Pa or less.
〔第２の絶縁膜〕
　絶縁膜１１０は、トランジスタ１００のゲート絶縁膜として機能する。また、絶縁膜１１０は、酸化物半導体膜１０８、特にチャネル領域１０８ｉに酸素を供給する機能を有する。例えば、絶縁膜１１０としては、酸化物絶縁膜または窒化物絶縁膜を単層または積層して形成することができる。なお、酸化物半導体膜１０８との界面特性を向上させるため、絶縁膜１１０において、酸化物半導体膜１０８と接する領域は、少なくとも酸化物絶縁膜を用いて形成することが好ましい。絶縁膜１１０として、例えば酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、窒化シリコンなどを用いればよい。 [Second insulating film]
The insulating film 110 functions as a gate insulating film of the transistor 100. The insulating film 110 has a function of supplying oxygen to the oxide semiconductor film 108, particularly the channel region 108i. For example, the insulating film 110 can be formed using a single layer or a stacked layer of an oxide insulating film or a nitride insulating film. Note that in order to improve interface characteristics with the oxide semiconductor film 108, a region in the insulating film 110 which is in contact with the oxide semiconductor film 108 is preferably formed using at least the oxide insulating film. As the insulating film 110, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like may be used.
　また、絶縁膜１１０の厚さは、５ｎｍ以上４００ｎｍ以下、または５ｎｍ以上３００ｎｍ以下、または１０ｎｍ以上２５０ｎｍ以下とすることができる。 The thickness of the insulating film 110 can be 5 nm to 400 nm, 5 nm to 300 nm, or 10 nm to 250 nm.
　また、絶縁膜１１０は、欠陥が少ないことが好ましく、代表的には、電子スピン共鳴法（ＥＳＲ：Ｅｌｅｃｔｒｏｎ　Ｓｐｉｎ　Ｒｅｓｏｎａｎｃｅ）で観察されるシグナルが少ない方が好ましい。例えば、上述のシグナルとしては、ｇ値が２．００１に観察されるＥ’センターが挙げられる。なお、Ｅ’センターは、シリコンのダングリングボンドに起因する。絶縁膜１１０としては、Ｅ’センター起因のスピン密度が、３×１０１７ｓｐｉｎｓ／ｃｍ３以下、好ましくは５×１０１６ｓｐｉｎｓ／ｃｍ３以下である酸化シリコン膜、または酸化窒化シリコン膜を用いればよい。 The insulating film 110 preferably has few defects. Typically, it is preferable that the number of signals observed by an electron spin resonance (ESR) be small. For example, the signal described above includes the E ′ center where the g value is observed at 2.001. The E ′ center is caused by silicon dangling bonds. As the insulating film 110, a silicon oxide film or a silicon oxynitride film whose spin density due to the E ′ center is 3 × 10 17 spins / cm 3 or less, preferably 5 × 10 6 spins / cm 3 or less is used. Good.
　また、絶縁膜１１０には、上述のシグナル以外に二酸化窒素（ＮＯ２）に起因するシグナルが観察される場合がある。当該シグナルは、Ｎの核スピンにより３つのシグナルに分裂しており、それぞれのｇ値が２．０３７以上２．０３９以下（第１のシグナルとする）、ｇ値が２．００１以上２．００３以下（第２のシグナルとする）、及びｇ値が１．９６４以上１．９６６以下（第３のシグナルとする）に観察される。 In addition, in the insulating film 110, a signal due to nitrogen dioxide (NO 2 ) may be observed in addition to the above signal. The signal is split into three signals by N nuclear spins, each having a g value of 2.037 or more and 2.039 or less (referred to as the first signal), and a g value of 2.001 or more and 2.003. The g value is observed below (referred to as the second signal) and from 1.964 to 1.966 (referred to as the third signal).
　例えば、絶縁膜１１０として、二酸化窒素（ＮＯ２）起因のスピン密度が、１×１０１７ｓｐｉｎｓ／ｃｍ３以上１×１０１８ｓｐｉｎｓ／ｃｍ３未満である絶縁膜を用いると好適である。 For example, as the insulating film 110, an insulating film whose spin density due to nitrogen dioxide (NO 2 ) is 1 × 10 17 spins / cm 3 or more and less than 1 × 10 18 spins / cm 3 is preferably used.
　なお、二酸化窒素（ＮＯ２）を含む窒素酸化物（ＮＯｘ）は、絶縁膜１１０中に準位を形成する。当該準位は、酸化物半導体膜１０８のエネルギーギャップ内に位置する。そのため、窒素酸化物（ＮＯｘ）が、絶縁膜１１０及び酸化物半導体膜１０８の界面に拡散すると、当該準位が絶縁膜１１０側において電子をトラップする場合がある。この結果、トラップされた電子が、絶縁膜１１０及び酸化物半導体膜１０８界面近傍に留まるため、トランジスタのしきい値電圧をプラス方向にシフトさせてしまう。したがって、絶縁膜１１０としては、窒素酸化物の含有量が少ない膜を用いると、トランジスタのしきい値電圧のシフトを低減することができる。 Note that nitrogen oxide (NO x ) containing nitrogen dioxide (NO 2 ) forms a level in the insulating film 110. The level is located in the energy gap of the oxide semiconductor film 108. Therefore, when nitrogen oxide (NOx) diffuses to the interface between the insulating film 110 and the oxide semiconductor film 108, the level may trap electrons on the insulating film 110 side. As a result, trapped electrons remain in the vicinity of the interface between the insulating film 110 and the oxide semiconductor film 108, so that the threshold voltage of the transistor is shifted in the positive direction. Therefore, when the insulating film 110 is a film with a low content of nitrogen oxides, the threshold voltage shift of the transistor can be reduced.
　窒素酸化物（ＮＯｘ）の放出量が少ない絶縁膜としては、例えば、酸化窒化シリコン膜を用いることができる。当該酸化窒化シリコン膜は、昇温脱離ガス分析法（ＴＤＳ：Ｔｈｅｒｍａｌ　Ｄｅｓｏｒｐｔｉｏｎ　Ｓｐｅｃｔｒｏｓｃｏｐｙ）において、窒素酸化物（ＮＯｘ）の放出量よりアンモニアの放出量が多い膜であり、代表的にはアンモニアの放出量が１×１０１８／ｃｍ３以上５×１０１９／ｃｍ３以下である。なお、上記のアンモニアの放出量は、ＴＤＳにおける加熱処理の温度が５０℃以上６５０℃以下、または５０℃以上５５０℃以下の範囲での総量である。 For example, a silicon oxynitride film can be used as the insulating film that emits less nitrogen oxide (NO x ). The silicon oxynitride film is a film in which the amount of ammonia released is larger than the amount of nitrogen oxide (NO x ) released in a temperature programmed desorption gas analysis (TDS). The discharge amount is 1 × 10 18 / cm 3 or more and 5 × 10 19 / cm 3 or less. Note that the amount of ammonia released is the total amount when the temperature of the heat treatment in TDS is in the range of 50 ° C. to 650 ° C. or 50 ° C. to 550 ° C.
　窒素酸化物（ＮＯｘ）は、加熱処理においてアンモニア及び酸素と反応するため、アンモニアの放出量が多い絶縁膜を用いることで窒素酸化物（ＮＯｘ）が低減される。 Since nitrogen oxide (NO x ) reacts with ammonia and oxygen in the heat treatment, nitrogen oxide (NO x ) is reduced by using an insulating film that releases a large amount of ammonia.
　なお、絶縁膜１１０をＳＩＭＳで分析した場合、膜中の窒素濃度が６×１０２０ａｔｏｍｓ／ｃｍ３以下であると好ましい。 Note that when the insulating film 110 is analyzed by SIMS, the nitrogen concentration in the film is preferably 6 × 10 20 atoms / cm 3 or less.
　また、絶縁膜１１０として、ハフニウムシリケート（ＨｆＳｉＯｘ）、窒素が添加されたハフニウムシリケート（ＨｆＳｉｘＯｙＮｚ）、窒素が添加されたハフニウムアルミネート（ＨｆＡｌｘＯｙＮｚ）、酸化ハフニウムなどのｈｉｇｈ−ｋ材料を用いてもよい。当該ｈｉｇｈ−ｋ材料を用いることでトランジスタのゲートリークを低減できる。 Further, as the insulating film 110, hafnium silicate (HfSiO x ), hafnium silicate added with nitrogen (HfSi x O y N z ), hafnium aluminate added with nitrogen (HfAl x O y N z ), hafnium oxide, or the like High-k materials may be used. By using the high-k material, gate leakage of the transistor can be reduced.
〔第３の絶縁膜〕
　絶縁膜１１６は、窒素または水素を有する。また、絶縁膜１１６は、フッ素を有していてもよい。絶縁膜１１６としては、例えば、窒化物絶縁膜が挙げられる。該窒化物絶縁膜としては、窒化シリコン、窒化酸化シリコン、酸化窒化シリコン、窒化フッ化シリコン、フッ化窒化シリコン等を用いて形成することができる。絶縁膜１１６に含まれる水素濃度は、１×１０２２ａｔｏｍｓ／ｃｍ３以上であると好ましい。また、絶縁膜１１６は、酸化物半導体膜１０８のソース領域１０８ｓ、及びドレイン領域１０８ｄと接する。したがって、絶縁膜１１６と接するソース領域１０８ｓ、及びドレイン領域１０８ｄ中の不純物（窒素または水素）濃度が高くなり、ソース領域１０８ｓ、及びドレイン領域１０８ｄのキャリア密度を高めることができる。 [Third insulating film]
The insulating film 116 includes nitrogen or hydrogen. The insulating film 116 may contain fluorine. An example of the insulating film 116 is a nitride insulating film. The nitride insulating film can be formed using silicon nitride, silicon nitride oxide, silicon oxynitride, silicon nitride fluoride, silicon fluoronitride, or the like. The concentration of hydrogen contained in the insulating film 116 is preferably 1 × 10 22 atoms / cm 3 or more. The insulating film 116 is in contact with the source region 108s and the drain region 108d of the oxide semiconductor film 108. Therefore, the impurity (nitrogen or hydrogen) concentration in the source region 108s and the drain region 108d in contact with the insulating film 116 is increased, and the carrier density of the source region 108s and the drain region 108d can be increased.
〔第４の絶縁膜〕
　絶縁膜１１８としては、酸化物絶縁膜を用いることができる。また、絶縁膜１１８としては、酸化物絶縁膜と、窒化物絶縁膜との積層膜を用いることができる。絶縁膜１１８として、例えば酸化シリコン、酸化窒化シリコン、窒化酸化シリコン、酸化アルミニウム、酸化ハフニウム、酸化ガリウムまたはＧａ−Ｚｎ酸化物などを用いればよい。 [Fourth insulating film]
As the insulating film 118, an oxide insulating film can be used. As the insulating film 118, a stacked film of an oxide insulating film and a nitride insulating film can be used. As the insulating film 118, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, gallium oxide, Ga—Zn oxide, or the like may be used.
　また、絶縁膜１１８としては、外部からの水素、水等のバリア膜として機能する膜であることが好ましい。 Further, the insulating film 118 is preferably a film that functions as a barrier film of hydrogen, water, etc. from the outside.
　絶縁膜１１８の厚さは、３０ｎｍ以上５００ｎｍ以下、または１００ｎｍ以上４００ｎｍ以下とすることができる。 The thickness of the insulating film 118 can be greater than or equal to 30 nm and less than or equal to 500 nm, or greater than or equal to 100 nm and less than or equal to 400 nm.
〔導電膜〕
　導電膜１１２、１２０ａ、１２０ｂとしては、スパッタリング法、真空蒸着法、パルスレーザー堆積（ＰＬＤ）法、熱ＣＶＤ法等を用いて形成することができる。また、導電膜１１２、１２０ａ、１２０ｂとしては、導電性を有する金属膜、可視光を反射する機能を有する導電膜、または可視光を透過する機能を有する導電膜を用いればよい。 [Conductive film]
The conductive films 112, 120a, and 120b can be formed by a sputtering method, a vacuum evaporation method, a pulse laser deposition (PLD) method, a thermal CVD method, or the like. As the conductive films 112, 120a, and 120b, a conductive metal film, a conductive film having a function of reflecting visible light, or a conductive film having a function of transmitting visible light may be used.
　導電性を有する金属膜として、アルミニウム、金、白金、銀、銅、クロム、タンタル、チタン、モリブデン、タングステン、ニッケル、鉄、コバルト、パラジウムまたはマンガンから選ばれた金属元素を含む材料を用いることができる。または、上述した金属元素を含む合金を用いてもよい。 As the conductive metal film, a material containing a metal element selected from aluminum, gold, platinum, silver, copper, chromium, tantalum, titanium, molybdenum, tungsten, nickel, iron, cobalt, palladium, or manganese is used. it can. Alternatively, an alloy containing the above metal element may be used.
　上述の導電性を有する金属膜として、具体的には、チタン膜上に銅膜を積層する二層構造、窒化チタン膜上に銅膜を積層する二層構造、窒化タンタル膜上に銅膜を積層する二層構造、チタン膜上に銅膜を積層し、さらにその上にチタン膜を形成する三層構造等を用いればよい。特に、銅元素を含む導電膜を用いることで、抵抗を低くすることが出来るため好適である。また、銅元素を含む導電膜としては、または、銅とマンガンとを含む合金膜が挙げられる。当該合金膜は、ウエットエッチング法を用いて加工できるため好適である。 Specifically, the conductive metal film described above includes a two-layer structure in which a copper film is stacked on a titanium film, a two-layer structure in which a copper film is stacked on a titanium nitride film, and a copper film on a tantalum nitride film. A two-layer structure to be laminated, a three-layer structure in which a copper film is laminated on a titanium film, and a titanium film is further formed thereon may be used. In particular, it is preferable to use a conductive film containing a copper element because resistance can be lowered. In addition, examples of the conductive film containing a copper element include an alloy film containing copper and manganese. The alloy film is preferable because it can be processed by a wet etching method.
　なお、導電膜１１２、１２０ａ、１２０ｂとしては、窒化タンタル膜を用いると好適である。当該窒化タンタル膜は、導電性を有し、且つ、銅または水素に対して、高いバリア性を有する。また、窒化タンタル膜は、さらに自身からの水素の放出が少ないため、酸化物半導体膜１０８と接する金属膜、または酸化物半導体膜１０８の近傍の金属膜として、最も好適に用いることができる。 Note that a tantalum nitride film is preferably used as the conductive films 112, 120a, and 120b. The tantalum nitride film has conductivity and high barrier properties against copper or hydrogen. Further, the tantalum nitride film can be most preferably used as a metal film in contact with the oxide semiconductor film 108 or a metal film in the vicinity of the oxide semiconductor film 108 because it emits less hydrogen from itself.
　また、上述の導電性を有する導電膜として、導電性高分子または導電性ポリマーを用いてもよい。 Alternatively, a conductive polymer or a conductive polymer may be used as the conductive film having the above-described conductivity.
　また、上述の可視光を反射する機能を有する導電膜としては、金、銀、銅、またはパラジウムから選ばれた金属元素を含む材料を用いることができる。特に、銀元素を含む導電膜を用いることで、可視光における反射率を高めることができるため好適である。 Further, as the conductive film having a function of reflecting visible light, a material containing a metal element selected from gold, silver, copper, or palladium can be used. In particular, it is preferable to use a conductive film containing a silver element because the reflectance in visible light can be increased.
　また、上述の可視光を透過する機能を有する導電膜としては、インジウム、錫、亜鉛、ガリウム、またはシリコンから選ばれた元素を含む材料を用いることができる。具体的には、Ｉｎ酸化物、Ｚｎ酸化物、Ｉｎ−Ｓｎ酸化物（ＩＴＯともいう）、Ｉｎ−Ｓｎ−Ｓｉ酸化物（ＩＴＳＯともいう）、Ｉｎ−Ｚｎ酸化物、Ｉｎ−Ｇａ−Ｚｎ酸化物等が挙げられる。 Further, as the conductive film having a function of transmitting visible light, a material containing an element selected from indium, tin, zinc, gallium, or silicon can be used. Specifically, In oxide, Zn oxide, In—Sn oxide (also referred to as ITO), In—Sn—Si oxide (also referred to as ITSO), In—Zn oxide, In—Ga—Zn oxide Etc.
　また、上述の可視光を透過する機能を有する導電膜としては、グラフェンまたはグラファイトを含む膜を用いてもよい。グラフェンを含む膜としては、酸化グラフェンを含む膜を形成し、酸化グラフェンを含む膜を還元することにより、グラフェンを含む膜を形成することができる。還元する方法としては、熱を加える方法や還元剤を用いる方法等が挙げられる。 Further, as the conductive film having a function of transmitting visible light, a film containing graphene or graphite may be used. As the film containing graphene, a film containing graphene can be formed by forming a film containing graphene oxide and reducing the film containing graphene oxide. Examples of the reduction method include a method of applying heat and a method of using a reducing agent.
　また、導電膜１１２、１２０ａ、１２０ｂを、無電解めっき法により形成することができる。当該無電解めっき法により形成できる材料としては、例えば、Ｃｕ、Ｎｉ、Ａｌ、Ａｕ、Ｓｎ、Ｃｏ、Ａｇ、及びＰｄの中から選ばれるいずれか一つまたは複数を用いることが可能である。特に、ＣｕまたはＡｇを用いると、導電膜の抵抗を低くすることができるため、好適である。 Further, the conductive films 112, 120a, and 120b can be formed by an electroless plating method. As a material that can be formed by the electroless plating method, for example, any one or more selected from Cu, Ni, Al, Au, Sn, Co, Ag, and Pd can be used. In particular, the use of Cu or Ag is preferable because the resistance of the conductive film can be lowered.
　また、無電解めっき法により導電膜を形成した場合、当該導電膜の構成元素が外部に拡散しないように、当該導電膜の下に、拡散防止膜を形成してもよい。また、当該拡散防止膜と、当該導電膜との間に、導電膜を成長させることが出来るシード層を形成してもよい。上記拡散防止膜としては、例えば、スパッタリング法を用いて形成することができる。また、当該拡散防止膜としては、例えば、窒化タンタル膜または窒化チタン膜を用いることができる。また、上記シード層としては、無電解めっき法により形成することができる。また、当該シード層としては、無電解めっき法により形成することができる導電膜の材料と同様の材料を用いることができる。 In addition, when a conductive film is formed by an electroless plating method, a diffusion prevention film may be formed under the conductive film so that constituent elements of the conductive film do not diffuse outside. Further, a seed layer capable of growing a conductive film may be formed between the diffusion prevention film and the conductive film. The diffusion preventing film can be formed using, for example, a sputtering method. As the diffusion preventing film, for example, a tantalum nitride film or a titanium nitride film can be used. The seed layer can be formed by an electroless plating method. Further, as the seed layer, a material similar to the material of the conductive film that can be formed by an electroless plating method can be used.
　なお、導電膜１１２として、Ｉｎ−Ｇａ−Ｚｎ酸化物に代表される酸化物半導体を用いてよい。当該酸化物半導体は、絶縁膜１１６から窒素または水素が供給されることで、キャリア密度が高くなる。別言すると、酸化物半導体は、酸化物導電体（ＯＣ：Ｏｘｉｄｅ　Ｃｏｎｄｕｃｔｏｒ）として機能する。したがって、酸化物半導体は、ゲート電極として用いることができる。 Note that an oxide semiconductor typified by an In—Ga—Zn oxide may be used as the conductive film 112. The oxide semiconductor has high carrier density when nitrogen or hydrogen is supplied from the insulating film 116. In other words, the oxide semiconductor functions as an oxide conductor (OC: Oxide Conductor). Therefore, the oxide semiconductor can be used as a gate electrode.
　例えば、導電膜１１２としては、酸化物導電体（ＯＣ）の単層構造、金属膜の単層構造、または酸化物導電体（ＯＣ）と、金属膜との積層構造等が挙げられる。 For example, examples of the conductive film 112 include a single layer structure of an oxide conductor (OC), a single layer structure of a metal film, or a stacked structure of an oxide conductor (OC) and a metal film.
　なお、導電膜１１２として、遮光性を有する金属膜の単層構造、または酸化物導電体（ＯＣ）と遮光性を有する金属膜との積層構造を用いる場合、導電膜１１２の下方に形成されるチャネル領域１０８ｉを遮光することができるため、好適である。また、導電膜１１２として、酸化物半導体または酸化物導電体（ＯＣ）と、遮光性を有する金属膜との積層構造を用いる場合、酸化物半導体または酸化物導電体（ＯＣ）上に、金属膜（例えば、チタン膜、タングステン膜など）を形成することで、金属膜中の構成元素が酸化物半導体または酸化物導電体（ＯＣ）側に拡散し低抵抗化する、金属膜の成膜時のダメージ（例えば、スパッタリングダメージなど）により低抵抗化する、あるいは金属膜中に酸化物半導体または酸化物導電体（ＯＣ）中の酸素が拡散することで、酸素欠損が形成され低抵抗化する。 Note that the conductive film 112 is formed below the conductive film 112 in the case where a single-layer structure of a light-blocking metal film or a stacked structure of an oxide conductor (OC) and a light-blocking metal film is used. This is preferable because the channel region 108i can be shielded from light. In the case where a stacked structure of an oxide semiconductor or an oxide conductor (OC) and a light-shielding metal film is used as the conductive film 112, the metal film is formed over the oxide semiconductor or the oxide conductor (OC). (For example, titanium film, tungsten film, etc.), the constituent elements in the metal film diffuse to the oxide semiconductor or oxide conductor (OC) side and the resistance is reduced. The resistance is reduced by damage (for example, sputtering damage) or oxygen in the oxide semiconductor or the oxide conductor (OC) is diffused in the metal film, so that oxygen deficiency is formed and the resistance is reduced.
　導電膜１１２、１２０ａ、１２０ｂの厚さとしては、３０ｎｍ以上５００ｎｍ以下、または１００ｎｍ以上４００ｎｍ以下とすることができる。 The thickness of the conductive films 112, 120a, and 120b can be 30 nm to 500 nm, or 100 nm to 400 nm.
［２−２．トランジスタの構成例２］
　次に、図１６（Ａ）（Ｂ）（Ｃ）に示すトランジスタと異なる構成について、図１７（Ａ）（Ｂ）（Ｃ）を用いて説明する。 [2-2. Transistor configuration example 2]
Next, a structure different from the transistors illustrated in FIGS. 16A, 16B, and 16C is described with reference to FIGS.
　図１７（Ａ）は、トランジスタ１００Ａの上面図であり、図１７（Ｂ）は図１７（Ａ）の一点鎖線Ｘ１−Ｘ２間の断面図であり、図１７（Ｃ）は図１７（Ａ）の一点鎖線Ｙ１−Ｙ２間の断面図である。 17A is a top view of the transistor 100A, FIG. 17B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 17A, and FIG. 17C is FIG. It is sectional drawing between dashed-dotted lines Y1-Y2.
　図１７（Ａ）（Ｂ）（Ｃ）に示すトランジスタ１００Ａは、基板１０２上の導電膜１０６と、導電膜１０６上の絶縁膜１０４と、絶縁膜１０４上の酸化物半導体膜１０８と、酸化物半導体膜１０８上の絶縁膜１１０と、絶縁膜１１０上の導電膜１１２と、絶縁膜１０４、酸化物半導体膜１０８、及び導電膜１１２上の絶縁膜１１６と、を有する。なお、酸化物半導体膜１０８は、導電膜１１２と重なるチャネル領域１０８ｉと、絶縁膜１１６と接するソース領域１０８ｓと、絶縁膜１１６と接するドレイン領域１０８ｄと、を有する。 A transistor 100A illustrated in FIGS. 17A to 17C includes a conductive film 106 over a substrate 102, an insulating film 104 over the conductive film 106, an oxide semiconductor film 108 over the insulating film 104, and an oxide. The insulating film 110 over the semiconductor film 108, the conductive film 112 over the insulating film 110, the insulating film 104, the oxide semiconductor film 108, and the insulating film 116 over the conductive film 112 are included. Note that the oxide semiconductor film 108 includes a channel region 108 i overlapping with the conductive film 112, a source region 108 s in contact with the insulating film 116, and a drain region 108 d in contact with the insulating film 116.
　トランジスタ１００Ａは、先に示すトランジスタ１００の構成に加え、導電膜１０６と、開口部１４３と、を有する。 The transistor 100A includes a conductive film 106 and an opening 143 in addition to the structure of the transistor 100 described above.
　なお、開口部１４３は、絶縁膜１０４、１１０に設けられる。また、導電膜１０６は、開口部１４３を介して、導電膜１１２と、電気的に接続される。よって、導電膜１０６と導電膜１１２には、同じ電位が与えられる。なお、開口部１４３を設けずに、導電膜１０６と、導電膜１１２と、に異なる電位を与えてもよい。または、開口部１４３を設けずに、導電膜１０６を遮光膜として用いてもよい。例えば、導電膜１０６を遮光性の材料により形成することで、チャネル領域１０８ｉに照射される下方からの光を抑制することができる。 Note that the opening 143 is provided in the insulating films 104 and 110. In addition, the conductive film 106 is electrically connected to the conductive film 112 through the opening 143. Therefore, the same potential is applied to the conductive film 106 and the conductive film 112. Note that different potentials may be applied to the conductive film 106 and the conductive film 112 without providing the opening 143. Alternatively, the conductive film 106 may be used as a light-blocking film without providing the opening 143. For example, when the conductive film 106 is formed using a light-blocking material, light from below irradiated to the channel region 108 i can be suppressed.
　また、トランジスタ１００Ａの構成とする場合、導電膜１０６は、第１のゲート電極（ボトムゲート電極ともいう）としての機能を有し、導電膜１１２は、第２のゲート電極（トップゲート電極ともいう）としての機能を有する。また、絶縁膜１０４は、第１のゲート絶縁膜としての機能を有し、絶縁膜１１０は、第２のゲート絶縁膜としての機能を有する。 In the case of the structure of the transistor 100A, the conductive film 106 functions as a first gate electrode (also referred to as a bottom gate electrode), and the conductive film 112 is also referred to as a second gate electrode (also referred to as a top gate electrode). ). The insulating film 104 has a function as a first gate insulating film, and the insulating film 110 has a function as a second gate insulating film.
　導電膜１０６としては、先に記載の導電膜１１２、１２０ａ、１２０ｂと同様の材料を用いることができる。特に導電膜１０６として、銅を含む材料により形成することで抵抗を低くすることができるため好適である。例えば、導電膜１０６を窒化チタン膜、窒化タンタル膜、またはタングステン膜上に銅膜を設ける積層構造とし、導電膜１２０ａ、１２０ｂを窒化チタン膜、窒化タンタル膜、またはタングステン膜上に銅膜を設ける積層構造とすると好適である。この場合、トランジスタ１００Ａを表示装置の画素トランジスタ及び駆動トランジスタのいずれか一方または双方に用いることで、導電膜１０６と導電膜１２０ａとの間に生じる寄生容量、及び導電膜１０６と導電膜１２０ｂとの間に生じる寄生容量を低くすることができる。したがって、導電膜１０６、導電膜１２０ａ、及び導電膜１２０ｂを、トランジスタ１００Ａの第１のゲート電極、ソース電極、及びドレイン電極として用いるのみならず、表示装置の電源供給用の配線、信号供給用の配線、または接続用の配線等に用いる事も可能となる。 As the conductive film 106, the same material as the conductive films 112, 120a, and 120b described above can be used. In particular, the conductive film 106 is preferably formed using a material containing copper because the resistance can be lowered. For example, the conductive film 106 has a stacked structure in which a copper film is provided over a titanium nitride film, a tantalum nitride film, or a tungsten film, and the conductive films 120a and 120b are provided with a copper film over the titanium nitride film, the tantalum nitride film, or the tungsten film. A laminated structure is preferable. In this case, by using the transistor 100A for one or both of the pixel transistor and the driving transistor of the display device, parasitic capacitance generated between the conductive film 106 and the conductive film 120a, and the conductive film 106 and the conductive film 120b The parasitic capacitance generated between them can be reduced. Therefore, the conductive film 106, the conductive film 120a, and the conductive film 120b are used not only as the first gate electrode, the source electrode, and the drain electrode of the transistor 100A, but also for power supply wiring and signal supply of the display device. It can also be used for wiring or wiring for connection.
　このように、図１７（Ａ）（Ｂ）（Ｃ）に示すトランジスタ１００Ａは、先に説明したトランジスタ１００と異なり、酸化物半導体膜１０８の上下にゲート電極として機能する導電膜を有する構造である。トランジスタ１００Ａに示すように、本発明の一態様の半導体装置には、複数のゲート電極を設けてもよい。 As described above, unlike the transistor 100 described above, the transistor 100A illustrated in FIGS. 17A to 17C has a structure including conductive films functioning as gate electrodes above and below the oxide semiconductor film 108. . As illustrated in the transistor 100A, the semiconductor device of one embodiment of the present invention may include a plurality of gate electrodes.
　また、図１７（Ｂ）（Ｃ）に示すように、酸化物半導体膜１０８は、第１のゲート電極として機能する導電膜１０６と、第２のゲート電極として機能する導電膜１１２のそれぞれと対向するように位置し、２つのゲート電極として機能する導電膜に挟まれている。 17B and 17C, the oxide semiconductor film 108 is opposite to the conductive film 106 functioning as the first gate electrode and the conductive film 112 functioning as the second gate electrode, respectively. And is sandwiched between conductive films functioning as two gate electrodes.
　また、導電膜１１２のチャネル幅方向の長さは、酸化物半導体膜１０８のチャネル幅方向の長さよりも長く、酸化物半導体膜１０８のチャネル幅方向全体は、絶縁膜１１０を間に挟んで導電膜１１２に覆われている。また、導電膜１１２と導電膜１０６とは、絶縁膜１０４、及び絶縁膜１１０に設けられる開口部１４３において接続されるため、酸化物半導体膜１０８のチャネル幅方向の側面の一方は、絶縁膜１１０を間に挟んで導電膜１１２と対向している。 The length of the conductive film 112 in the channel width direction is longer than the length of the oxide semiconductor film 108 in the channel width direction, and the entire length of the oxide semiconductor film 108 in the channel width direction is conductive with the insulating film 110 interposed therebetween. The film 112 is covered. Further, since the conductive film 112 and the conductive film 106 are connected to each other in the insulating film 104 and the opening 143 provided in the insulating film 110, one of the side surfaces in the channel width direction of the oxide semiconductor film 108 is the insulating film 110. Is opposed to the conductive film 112.
　別言すると、トランジスタ１００Ａのチャネル幅方向において、導電膜１０６及び導電膜１１２は、絶縁膜１０４、及び絶縁膜１１０に設けられる開口部１４３において接続すると共に、絶縁膜１０４、及び絶縁膜１１０を間に挟んで酸化物半導体膜１０８を取り囲む構成である。 In other words, in the channel width direction of the transistor 100A, the conductive film 106 and the conductive film 112 are connected to each other through the insulating film 104 and the opening 143 provided in the insulating film 110, and the insulating film 104 and the insulating film 110 are interposed between them. The oxide semiconductor film 108 is surrounded by the structure.
　このような構成を有することで、トランジスタ１００Ａに含まれる酸化物半導体膜１０８を、第１のゲート電極として機能する導電膜１０６及び第２のゲート電極として機能する導電膜１１２の電界によって電気的に取り囲むことができる。トランジスタ１００Ａのように、第１のゲート電極及び第２のゲート電極の電界によって、チャネル領域が形成される酸化物半導体膜１０８を電気的に取り囲むトランジスタのデバイス構造をＳｕｒｒｏｕｎｄｅｄ　ｃｈａｎｎｅｌ（Ｓ−ｃｈａｎｎｅｌ）構造と呼ぶことができる。 With such a structure, the oxide semiconductor film 108 included in the transistor 100A is electrically connected to the conductive film 106 functioning as the first gate electrode and the conductive film 112 functioning as the second gate electrode. Can be surrounded. As in the transistor 100A, a device structure of a transistor that electrically surrounds the oxide semiconductor film 108 in which a channel region is formed by an electric field of the first gate electrode and the second gate electrode is a surround channel (S-channel) structure. Can be called.
　トランジスタ１００Ａは、Ｓ−ｃｈａｎｎｅｌ構造を有するため、導電膜１０６または導電膜１１２によってチャネルを誘起させるための電界を効果的に酸化物半導体膜１０８に印加することができるため、トランジスタ１００Ａの電流駆動能力が向上し、高いオン電流特性を得ることが可能となる。また、オン電流を高くすることが可能であるため、トランジスタ１００Ａを微細化することが可能となる。また、トランジスタ１００Ａは、導電膜１０６、及び導電膜１１２によって取り囲まれた構造を有するため、トランジスタ１００Ａの機械的強度を高めることができる。 Since the transistor 100A has an S-channel structure, an electric field for inducing a channel by the conductive film 106 or the conductive film 112 can be effectively applied to the oxide semiconductor film 108; thus, the current driving capability of the transistor 100A Thus, high on-current characteristics can be obtained. Further, since the on-state current can be increased, the transistor 100A can be miniaturized. In addition, since the transistor 100A has a structure surrounded by the conductive film 106 and the conductive film 112, the mechanical strength of the transistor 100A can be increased.
　なお、トランジスタ１００Ａのチャネル幅方向において、酸化物半導体膜１０８の開口部１４３が形成されていない側に、開口部１４３と異なる開口部を形成してもよい。 Note that an opening different from the opening 143 may be formed on the side where the opening 143 of the oxide semiconductor film 108 is not formed in the channel width direction of the transistor 100A.
　また、トランジスタ１００Ａに示すように、トランジスタが、半導体膜を間に挟んで存在する一対のゲート電極を有している場合、一方のゲート電極には信号Ａが、他方のゲート電極には固定電位Ｖｂが与えられてもよい。また、一方のゲート電極には信号Ａが、他方のゲート電極には信号Ｂが与えられてもよい。また、一方のゲート電極には固定電位Ｖａが、他方のゲート電極には固定電位Ｖｂが与えられてもよい。 In addition, as illustrated in the transistor 100A, in the case where the transistor includes a pair of gate electrodes with a semiconductor film interposed therebetween, the signal A is supplied to one gate electrode and the fixed potential is supplied to the other gate electrode. Vb may be given. Further, the signal A may be given to one gate electrode, and the signal B may be given to the other gate electrode. One gate electrode may be given a fixed potential Va, and the other gate electrode may be given a fixed potential Vb.
　信号Ａは、例えば、導通状態または非導通状態を制御するための信号である。信号Ａは、電位Ｖ１、または電位Ｖ２（Ｖ１＞Ｖ２とする）の２種類の電位をとるデジタル信号であってもよい。例えば、電位Ｖ１を高電源電位とし、電位Ｖ２を低電源電位とすることができる。信号Ａは、アナログ信号であってもよい。 The signal A is a signal for controlling, for example, a conduction state or a non-conduction state. The signal A may be a digital signal that takes two kinds of potentials, that is, the potential V1 or the potential V2 (V1> V2). For example, the potential V1 can be a high power supply potential and the potential V2 can be a low power supply potential. The signal A may be an analog signal.
　固定電位Ｖｂは、例えば、トランジスタのしきい値電圧ＶｔｈＡを制御するための電位である。固定電位Ｖｂは、電位Ｖ１、または電位Ｖ２であってもよい。この場合、固定電位Ｖｂを生成するための電位発生回路を、別途設ける必要がなく好ましい。固定電位Ｖｂは、電位Ｖ１、または電位Ｖ２と異なる電位であってもよい。固定電位Ｖｂを低くすることで、しきい値電圧ＶｔｈＡを高くできる場合がある。その結果、ゲートーソース間電圧Ｖｇｓが０Ｖのときのドレイン電流を低減し、トランジスタを有する回路のリーク電流を低減できる場合がある。例えば、固定電位Ｖｂを低電源電位よりも低くしてもよい。一方で、固定電位Ｖｂを高くすることで、しきい値電圧ＶｔｈＡを低くできる場合がある。その結果、ゲート−ソース間電圧Ｖｇｓが高電源電位のときのドレイン電流を向上させ、トランジスタを有する回路の動作速度を向上できる場合がある。例えば、固定電位Ｖｂを低電源電位よりも高くしてもよい。 The fixed potential Vb is a potential for controlling the threshold voltage VthA of the transistor, for example. The fixed potential Vb may be the potential V1 or the potential V2. In this case, it is preferable that a potential generating circuit for generating the fixed potential Vb does not need to be provided separately. The fixed potential Vb may be a potential different from the potential V1 or the potential V2. In some cases, the threshold voltage VthA can be increased by lowering the fixed potential Vb. As a result, the drain current when the gate-source voltage Vgs is 0 V can be reduced, and the leakage current of a circuit including a transistor can be reduced in some cases. For example, the fixed potential Vb may be set lower than the low power supply potential. On the other hand, there is a case where the threshold voltage VthA can be lowered by increasing the fixed potential Vb. As a result, the drain current when the gate-source voltage Vgs is at a high power supply potential can be improved, and the operation speed of a circuit including a transistor can be improved in some cases. For example, the fixed potential Vb may be higher than the low power supply potential.
　信号Ｂは、例えば、導通状態または非導通状態を制御するための信号である。信号Ｂは、電位Ｖ３、または電位Ｖ４（Ｖ３＞Ｖ４とする）の２種類の電位をとるデジタル信号であってもよい。例えば、電位Ｖ３を高電源電位とし、電位Ｖ４を低電源電位とすることができる。信号Ｂは、アナログ信号であってもよい。 The signal B is a signal for controlling a conduction state or a non-conduction state, for example. The signal B may be a digital signal that takes two kinds of potentials, that is, the potential V3 or the potential V4 (V3> V4). For example, the potential V3 can be a high power supply potential and the potential V4 can be a low power supply potential. The signal B may be an analog signal.
　信号Ａと信号Ｂが共にデジタル信号である場合、信号Ｂは、信号Ａと同じデジタル値を持つ信号であってもよい。この場合、トランジスタのオン電流を向上し、トランジスタを有する回路の動作速度を向上できる場合がある。このとき、信号Ａにおける電位Ｖ１及び電位Ｖ２は、信号Ｂにおける電位Ｖ３及び電位Ｖ４と、異なっていても良い。例えば、信号Ｂが入力されるゲートに対応するゲート絶縁膜が、信号Ａが入力されるゲートに対応するゲート絶縁膜よりも厚い場合、信号Ｂの電位振幅（Ｖ３−Ｖ４）を、信号Ａの電位振幅（Ｖ１−Ｖ２）より大きくしても良い。そうすることで、トランジスタの導通状態または非導通状態に対して、信号Ａが与える影響と、信号Ｂが与える影響と、を同程度とすることができる場合がある。 When both the signal A and the signal B are digital signals, the signal B may be a signal having the same digital value as the signal A. In this case, the on-state current of the transistor can be improved and the operation speed of the circuit including the transistor can be improved in some cases. At this time, the potential V1 and the potential V2 in the signal A may be different from the potential V3 and the potential V4 in the signal B. For example, when the gate insulating film corresponding to the gate to which the signal B is input is thicker than the gate insulating film corresponding to the gate to which the signal A is input, the potential amplitude (V3 to V4) of the signal B is It may be larger than the potential amplitude (V1-V2). By doing so, the influence of the signal A and the influence of the signal B on the conduction state or non-conduction state of the transistor may be approximately the same.
　信号Ａと信号Ｂが共にデジタル信号である場合、信号Ｂは、信号Ａと異なるデジタル値を持つ信号であってもよい。この場合、トランジスタの制御を信号Ａと信号Ｂによって別々に行うことができ、より高い機能を実現できる場合がある。例えば、トランジスタがｎチャネル型である場合、信号Ａが電位Ｖ１であり、かつ、信号Ｂが電位Ｖ３である場合のみ導通状態となる場合や、信号Ａが電位Ｖ２であり、かつ、信号Ｂが電位Ｖ４である場合のみ非導通状態となる場合には、一つのトランジスタでＮＡＮＤ回路やＮＯＲ回路等の機能を実現できる場合がある。また、信号Ｂは、しきい値電圧ＶｔｈＡを制御するための信号であってもよい。例えば、信号Ｂは、トランジスタを有する回路が動作している期間と、当該回路が動作していない期間と、で電位が異なる信号であっても良い。信号Ｂは、回路の動作モードに合わせて電位が異なる信号であってもよい。この場合、信号Ｂは信号Ａほど頻繁には電位が切り替わらない場合がある。 When both the signal A and the signal B are digital signals, the signal B may be a signal having a digital value different from that of the signal A. In this case, the transistor can be controlled separately by the signal A and the signal B, and a higher function may be realized. For example, when the transistor is an n-channel transistor, the transistor A is in a conductive state only when the signal A is the potential V1 and the signal B is the potential V3, or the signal A is the potential V2 and the signal B is In the case where a non-conducting state is obtained only when the potential is V4, functions such as a NAND circuit and a NOR circuit may be realized with one transistor. The signal B may be a signal for controlling the threshold voltage VthA. For example, the signal B may be a signal having a different potential between a period in which a circuit including a transistor is operating and a period in which the circuit is not operating. The signal B may be a signal having a different potential according to the operation mode of the circuit. In this case, the potential of the signal B may not be switched as frequently as the signal A.
　信号Ａと信号Ｂが共にアナログ信号である場合、信号Ｂは、信号Ａと同じ電位のアナログ信号、信号Ａの電位を定数倍したアナログ信号、または、信号Ａの電位を定数だけ加算もしくは減算したアナログ信号等であってもよい。この場合、トランジスタのオン電流が向上し、トランジスタを有する回路の動作速度を向上できる場合がある。信号Ｂは、信号Ａと異なるアナログ信号であってもよい。この場合、トランジスタの制御を信号Ａと信号Ｂによって別々に行うことができ、より高い機能を実現できる場合がある。 When both the signal A and the signal B are analog signals, the signal B is an analog signal having the same potential as the signal A, an analog signal obtained by multiplying the potential of the signal A by a constant, or the potential of the signal A is added or subtracted by a constant. An analog signal or the like may be used. In this case, the on-state current of the transistor can be improved and the operation speed of the circuit including the transistor can be improved in some cases. The signal B may be an analog signal different from the signal A. In this case, the transistor can be controlled separately by the signal A and the signal B, and a higher function may be realized.
　信号Ａがデジタル信号であり、信号Ｂがアナログ信号であってもよい。または信号Ａがアナログ信号であり、信号Ｂがデジタル信号であってもよい。 The signal A may be a digital signal and the signal B may be an analog signal. Alternatively, the signal A may be an analog signal and the signal B may be a digital signal.
　トランジスタの両方のゲート電極に固定電位を与える場合、トランジスタを、抵抗素子と同等の素子として機能させることができる場合がある。例えば、トランジスタがｎチャネル型である場合、固定電位Ｖａまたは固定電位Ｖｂを高く（低く）することで、トランジスタの実効抵抗を低く（高く）することができる場合がある。固定電位Ｖａ及び固定電位Ｖｂを共に高く（低く）することで、一つのゲートしか有さないトランジスタによって得られる実効抵抗よりも低い（高い）実効抵抗が得られる場合がある。 When a fixed potential is applied to both gate electrodes of a transistor, the transistor may function as an element equivalent to a resistance element. For example, in the case where the transistor is an n-channel transistor, the effective resistance of the transistor can be decreased (increased) by increasing (decreasing) the fixed potential Va or the fixed potential Vb in some cases. By making both the fixed potential Va and the fixed potential Vb higher (lower), an effective resistance lower (higher) than that obtained by a transistor having only one gate may be obtained.
　なお、トランジスタ１００Ａのその他の構成は、先に示すトランジスタ１００と同様であり、同様の効果を奏する。 Note that the other structure of the transistor 100A is similar to that of the transistor 100 described above, and has the same effect.
　また、トランジスタ１００Ａ上にさらに、絶縁膜を形成してもよい。その場合の一例を図１８（Ａ）（Ｂ）に示す。図１８（Ａ）（Ｂ）は、トランジスタ１００Ｂの断面図である。トランジスタ１００Ｂの上面図としては、図１７（Ａ）に示すトランジスタ１００Ａと同様であるため、ここでの説明は省略する。 Further, an insulating film may be further formed over the transistor 100A. An example in that case is shown in FIGS. 18A and 18B are cross-sectional views of the transistor 100B. A top view of the transistor 100B is similar to that of the transistor 100A illustrated in FIG. 17A; therefore, description thereof is omitted here.
　図１８（Ａ）（Ｂ）に示すトランジスタ１００Ｂは、導電膜１２０ａ、１２０ｂ、絶縁膜１１８上に絶縁膜１２２を有する。それ以外の構成については、トランジスタ１００Ａと同様であり、同様の効果を奏する。 18A and 18B includes the insulating film 122 over the conductive films 120a and 120b and the insulating film 118. The transistor 100B illustrated in FIGS. Other configurations are similar to those of the transistor 100A, and have the same effects.
　絶縁膜１２２は、トランジスタ等に起因する凹凸等を平坦化させる機能を有する。絶縁膜１２２としては、絶縁性であればよく、無機材料または有機材料を用いて形成される。該無機材料としては、酸化シリコン膜、酸化窒化シリコン膜、窒化酸化シリコン膜、窒化シリコン膜、酸化アルミニウム膜、窒化アルミニウム膜等が挙げられる。該有機材料としては、例えば、アクリル樹脂、またはポリイミド樹脂等の感光性の樹脂材料が挙げられる。 The insulating film 122 has a function of flattening unevenness caused by a transistor or the like. The insulating film 122 only needs to be insulative and is formed using an inorganic material or an organic material. Examples of the inorganic material include a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, and an aluminum nitride film. As this organic material, photosensitive resin materials, such as an acrylic resin or a polyimide resin, are mentioned, for example.
［２−３．トランジスタの構成例３］
　次に、図１７（Ａ）（Ｂ）（Ｃ）に示すトランジスタと異なる構成について、図１９乃至図２１を用いて説明する。 [2-3. Transistor configuration example 3]
Next, a structure different from the transistors illustrated in FIGS. 17A to 17C is described with reference to FIGS.
　図１９（Ａ）（Ｂ）は、トランジスタ１００Ｃの断面図であり、図２０（Ａ）（Ｂ）は、トランジスタ１００Ｄの断面図であり、図２１（Ａ）（Ｂ）は、トランジスタ１００Ｅの断面図である。なお、トランジスタ１００Ｃ、トランジスタ１００Ｄ、及びトランジスタ１００Ｅの上面図としては、図１７（Ａ）に示すトランジスタ１００Ａと同様であるため、ここでの説明は省略する。 19A and 19B are cross-sectional views of the transistor 100C, FIGS. 20A and 20B are cross-sectional views of the transistor 100D, and FIGS. 21A and 21B are cross-sectional views of the transistor 100E. FIG. Note that top views of the transistor 100C, the transistor 100D, and the transistor 100E are the same as those of the transistor 100A illustrated in FIG. 17A, and thus description thereof is omitted here.
　図１９（Ａ）（Ｂ）に示すトランジスタ１００Ｃは、導電膜１１２の積層構造、導電膜１１２の形状、及び絶縁膜１１０の形状がトランジスタ１００Ａと異なる。 19A and 19B is different from the transistor 100A in the stacked structure of the conductive film 112, the shape of the conductive film 112, and the shape of the insulating film 110.
　トランジスタ１００Ｃの導電膜１１２は、絶縁膜１１０上の導電膜１１２＿１と、導電膜１１２＿１上の導電膜１１２＿２と、を有する。例えば、導電膜１１２＿１として、酸化物導電膜を用いることにより、絶縁膜１１０に過剰酸素を添加することができる。上記酸化物導電膜としては、スパッタリング法を用い、酸素ガスを含む雰囲気にて形成することができる。また、上記酸化物導電膜としては、例えば、インジウムと錫とを有する酸化物、タングステンとインジウムとを有する酸化物、タングステンとインジウムと亜鉛とを有する酸化物、チタンとインジウムとを有する酸化物、チタンとインジウムと錫とを有する酸化物、インジウムと亜鉛とを有する酸化物、シリコンとインジウムと錫とを有する酸化物、インジウムとガリウムと亜鉛とを有する酸化物等が挙げられる。 The conductive film 112 of the transistor 100C includes a conductive film 112_1 over the insulating film 110 and a conductive film 112_2 over the conductive film 112_1. For example, excess oxide can be added to the insulating film 110 by using an oxide conductive film as the conductive film 112_1. The oxide conductive film can be formed in an atmosphere containing oxygen gas by a sputtering method. As the oxide conductive film, for example, an oxide having indium and tin, an oxide having tungsten and indium, an oxide having tungsten, indium, and zinc, an oxide having titanium and indium, Examples thereof include an oxide having titanium, indium, and tin, an oxide having indium and zinc, an oxide having silicon, indium, and tin, and an oxide having indium, gallium, and zinc.
　また、図１９（Ｂ）に示すように、開口部１４３において、導電膜１１２＿２と、導電膜１０６とが接続される。開口部１４３を形成する際に、導電膜１１２＿１となる導電膜を形成した後、開口部１４３を形成することで、図１９（Ｂ）に示す形状とすることができる。導電膜１１２＿１に酸化物導電膜を適用した場合、導電膜１１２＿２と、導電膜１０６とが接続される構成とすることで、導電膜１１２と導電膜１０６との接続抵抗を低くすることができる。 Further, as illustrated in FIG. 19B, the conductive film 112_2 and the conductive film 106 are connected to each other in the opening 143. When the opening 143 is formed, after the conductive film to be the conductive film 112_1 is formed, the opening 143 is formed, whereby the shape illustrated in FIG. 19B can be obtained. In the case where an oxide conductive film is used for the conductive film 112_1, the connection resistance between the conductive film 112 and the conductive film 106 can be reduced by connecting the conductive film 112_2 and the conductive film 106.
　また、トランジスタ１００Ｃの導電膜１１２及び絶縁膜１１０は、テーパー形状である。より具体的には、導電膜１１２の下端部は、導電膜１１２の上端部よりも外側に形成される。また、絶縁膜１１０の下端部は、絶縁膜１１０の上端部よりも外側に形成される。また、導電膜１１２の下端部は、絶縁膜１１０の上端部と概略同じ位置に形成される。 In addition, the conductive film 112 and the insulating film 110 of the transistor 100C are tapered. More specifically, the lower end portion of the conductive film 112 is formed outside the upper end portion of the conductive film 112. The lower end portion of the insulating film 110 is formed outside the upper end portion of the insulating film 110. Further, the lower end portion of the conductive film 112 is formed at substantially the same position as the upper end portion of the insulating film 110.
　トランジスタ１００Ｃの導電膜１１２及び絶縁膜１１０をテーパー形状とすることで、トランジスタ１００Ａの導電膜１１２及び絶縁膜１１０が矩形の場合と比較し、絶縁膜１１６の被覆性を高めることができるため好適である。 It is preferable that the conductive film 112 and the insulating film 110 of the transistor 100C have a tapered shape because the coverage of the insulating film 116 can be increased as compared with the case where the conductive film 112 and the insulating film 110 of the transistor 100A are rectangular. is there.
　なお、トランジスタ１００Ｃのその他の構成は、先に示すトランジスタ１００Ａと同様であり、同様の効果を奏する。 Note that the other structure of the transistor 100C is similar to that of the transistor 100A described above, and has the same effect.
　図２０（Ａ）（Ｂ）に示すトランジスタ１００Ｄは、導電膜１１２の積層構造、導電膜１１２の形状、及び絶縁膜１１０の形状がトランジスタ１００Ａと異なる。 20A and 20B is different from the transistor 100A in the stacked structure of the conductive film 112, the shape of the conductive film 112, and the shape of the insulating film 110.
　トランジスタ１００Ｄの導電膜１１２は、絶縁膜１１０上の導電膜１１２＿１と、導電膜１１２＿１上の導電膜１１２＿２と、を有する。また、導電膜１１２＿１の下端部は、導電膜１１２＿２の上端部よりも外側に形成される。例えば、導電膜１１２＿１と、導電膜１１２＿２と、絶縁膜１１０と、を同じマスクで加工し、導電膜１１２＿２をウエットエッチング法で、導電膜１１２＿１及び絶縁膜１１０をドライエッチング法で、それぞれ加工することで、上記の構造とすることができる。 The conductive film 112 of the transistor 100D includes a conductive film 112_1 over the insulating film 110 and a conductive film 112_2 over the conductive film 112_1. The lower end portion of the conductive film 112_1 is formed outside the upper end portion of the conductive film 112_2. For example, the conductive film 112_1, the conductive film 112_2, and the insulating film 110 are processed with the same mask, the conductive film 112_2 is processed with a wet etching method, and the conductive film 112_1 and the insulating film 110 are processed with a dry etching method. Thus, the above structure can be obtained.
　また、トランジスタ１００Ｄの構造とすることで、酸化物半導体膜１０８中に、領域１０８ｆが形成される場合がある。領域１０８ｆは、チャネル領域１０８ｉとソース領域１０８ｓとの間、及びチャネル領域１０８ｉとドレイン領域１０８ｄとの間に形成される。 Further, with the structure of the transistor 100D, the region 108f may be formed in the oxide semiconductor film 108 in some cases. The region 108f is formed between the channel region 108i and the source region 108s, and between the channel region 108i and the drain region 108d.
　領域１０８ｆは、高抵抗領域あるいは低抵抗領域のいずれか一方として機能する。高抵抗領域とは、チャネル領域１０８ｉと同等の抵抗を有し、ゲート電極として機能する導電膜１１２が重畳しない領域である。領域１０８ｆが高抵抗領域の場合、領域１０８ｆは、所謂オフセット領域として機能する。領域１０８ｆがオフセット領域として機能する場合においては、トランジスタ１００Ｄのオン電流の低下を抑制するために、チャネル長（Ｌ）方向において、領域１０８ｆを１μｍ以下とすればよい。 The region 108f functions as either a high resistance region or a low resistance region. The high resistance region is a region which has a resistance equivalent to that of the channel region 108 i and does not overlap with the conductive film 112 functioning as a gate electrode. When the region 108f is a high resistance region, the region 108f functions as a so-called offset region. In the case where the region 108f functions as an offset region, the region 108f may be 1 μm or less in the channel length (L) direction in order to suppress a decrease in on-state current of the transistor 100D.
　また、低抵抗領域とは、チャネル領域１０８ｉよりも抵抗が低く、且つソース領域１０８ｓ及びドレイン領域１０８ｄよりも抵抗が高い領域である。領域１０８ｆが低抵抗領域の場合、領域１０８ｆは、所謂、ＬＤＤ（Ｌｉｇｈｔｌｙ　Ｄｏｐｅｄ　Ｄｒａｉｎ）領域として機能する。領域１０８ｆがＬＤＤ領域として機能する場合においては、ドレイン領域の電界緩和が可能となるため、ドレイン領域の電界に起因したトランジスタのしきい値電圧の変動を低減することができる。 Further, the low resistance region is a region having a resistance lower than that of the channel region 108i and higher than that of the source region 108s and the drain region 108d. When the region 108f is a low resistance region, the region 108f functions as a so-called LDD (Lightly Doped Drain) region. In the case where the region 108f functions as an LDD region, electric field relaxation in the drain region is possible, so that variation in threshold voltage of the transistor due to the electric field in the drain region can be reduced.
　なお、領域１０８ｆをＬＤＤ領域とする場合には、例えば、絶縁膜１１６から領域１０８ｆに窒素、水素、フッ素の１以上を供給する、あるいは、絶縁膜１１０及び導電膜１１２＿１をマスクとして、導電膜１１２＿１の上方から不純物元素を添加することで、当該不純物が導電膜１１２＿１及び絶縁膜１１０を通過して酸化物半導体膜１０８に添加されることで形成することができる。 Note that in the case where the region 108f is an LDD region, for example, one or more of nitrogen, hydrogen, and fluorine is supplied from the insulating film 116 to the region 108f, or the conductive film 112_1 is used with the insulating film 110 and the conductive film 112_1 as a mask. By adding an impurity element from above, the impurity can be formed by being added to the oxide semiconductor film 108 through the conductive film 112_1 and the insulating film 110.
　また、図２０（Ｂ）に示すように、開口部１４３において、導電膜１１２＿２と、導電膜１０６とが接続される。 As shown in FIG. 20B, the conductive film 112_2 and the conductive film 106 are connected to each other in the opening 143.
　なお、トランジスタ１００Ｄのその他の構成は、先に示すトランジスタ１００Ａと同様であり、同様の効果を奏する。 Note that the other structure of the transistor 100D is similar to that of the transistor 100A described above, and has the same effect.
　図２１（Ａ）（Ｂ）に示すトランジスタ１００Ｅは、導電膜１１２の積層構造、導電膜１１２の形状、及び絶縁膜１１０の形状がトランジスタ１００Ａと異なる。 21A and 21B is different from the transistor 100A in the stacked structure of the conductive film 112, the shape of the conductive film 112, and the shape of the insulating film 110.
　トランジスタ１００Ｅの導電膜１１２は、絶縁膜１１０上の導電膜１１２＿１と、導電膜１１２＿１上の導電膜１１２＿２と、を有する。また、導電膜１１２＿１の下端部は、導電膜１１２＿２の下端部よりも外側に形成される。また、絶縁膜１１０の下端部は、導電膜１１２＿１の下端部よりも外側に形成される。例えば、導電膜１１２＿１と、導電膜１１２＿と、絶縁膜１１０と、を同じマスクで加工し、導電膜１１２＿２及び導電膜１１２＿１をウエットエッチング法で、絶縁膜１１０をドライエッチング法で、それぞれ加工することで、上記の構造とすることができる。 The conductive film 112 of the transistor 100E includes a conductive film 112_1 over the insulating film 110 and a conductive film 112_2 over the conductive film 112_1. The lower end portion of the conductive film 112_1 is formed outside the lower end portion of the conductive film 112_2. The lower end portion of the insulating film 110 is formed outside the lower end portion of the conductive film 112_1. For example, the conductive film 112_1, the conductive film 112_, and the insulating film 110 are processed using the same mask, the conductive film 112_2 and the conductive film 112_1 are processed using a wet etching method, and the insulating film 110 is processed using a dry etching method. Thus, the above structure can be obtained.
　また、トランジスタ１００Ｄと同様に、トランジスタ１００Ｅには、酸化物半導体膜１０８中に領域１０８ｆが形成される場合がある。領域１０８ｆは、チャネル領域１０８ｉとソース領域１０８ｓとの間、及びチャネル領域１０８ｉとドレイン領域１０８ｄとの間に形成される。 Similarly to the transistor 100D, the transistor 100E may have a region 108f formed in the oxide semiconductor film 108. The region 108f is formed between the channel region 108i and the source region 108s, and between the channel region 108i and the drain region 108d.
　また、図２１（Ｂ）に示すように、開口部１４３において、導電膜１１２＿２と、導電膜１０６とが接続される。 Further, as illustrated in FIG. 21B, the conductive film 112_2 and the conductive film 106 are connected to each other in the opening 143.
　なお、トランジスタ１００Ｅのその他の構成は、先に示すトランジスタ１００Ａと同様であり、同様の効果を奏する。 Note that the other structure of the transistor 100E is similar to that of the transistor 100A described above, and has the same effect.
［２−４．トランジスタの構成例４］
　次に、図１７（Ａ）（Ｂ）（Ｃ）に示すトランジスタ１００Ａと異なる構成について、図２２乃至図２６を用いて説明する。 [2-4. Transistor configuration example 4]
Next, a structure different from the transistor 100A illustrated in FIGS. 17A, 17B, and 17C is described with reference to FIGS.
　図２２（Ａ）（Ｂ）は、トランジスタ１００Ｆの断面図であり、図２３（Ａ）（Ｂ）は、トランジスタ１００Ｇの断面図であり、図２４（Ａ）（Ｂ）は、トランジスタ１００Ｈの断面図であり、図２５（Ａ）（Ｂ）は、トランジスタ１００Ｊの断面図であり、図２６（Ａ）（Ｂ）は、トランジスタ１００Ｋの断面図である。なお、トランジスタ１００Ｆ、トランジスタ１００Ｇ、トランジスタ１００Ｈ、トランジスタ１００Ｊ、及びトランジスタ１００Ｋの上面図としては、図１７（Ａ）に示すトランジスタ１００Ａと同様であるため、ここでの説明は省略する。 22A and 22B are cross-sectional views of the transistor 100F, FIGS. 23A and 23B are cross-sectional views of the transistor 100G, and FIGS. 24A and 24B are cross-sectional views of the transistor 100H. 25A and 25B are cross-sectional views of the transistor 100J, and FIGS. 26A and 26B are cross-sectional views of the transistor 100K. Note that the top view of the transistor 100F, the transistor 100G, the transistor 100H, the transistor 100J, and the transistor 100K is similar to the transistor 100A illustrated in FIG. 17A; therefore, description thereof is omitted here.
　トランジスタ１００Ｆ、トランジスタ１００Ｇ、トランジスタ１００Ｈ、トランジスタ１００Ｊ、及びトランジスタ１００Ｋは、先に示すトランジスタ１００Ａと酸化物半導体膜１０８の構造が異なる。それ以外の構成については、先に示すトランジスタ１００Ａと同様の構成であり、同様の効果を奏する。 The transistor 100F, the transistor 100G, the transistor 100H, the transistor 100J, and the transistor 100K are different from each other in the structure of the transistor 100A and the oxide semiconductor film 108 described above. Other configurations are similar to those of the transistor 100A described above, and have the same effects.
　図２２（Ａ）（Ｂ）に示すトランジスタ１００Ｆが有する酸化物半導体膜１０８は、絶縁膜１０４上の酸化物半導体膜１０８＿１と、酸化物半導体膜１０８＿１上の酸化物半導体膜１０８＿２と、酸化物半導体膜１０８＿２上の酸化物半導体膜１０８＿３と、を有する。また、チャネル領域１０８ｉ、ソース領域１０８ｓ、及びドレイン領域１０８ｄは、それぞれ、酸化物半導体膜１０８＿１、酸化物半導体膜１０８＿２、及び酸化物半導体膜１０８＿３の３層の積層構造である。 22A and 22B includes an oxide semiconductor film 108_1 over the insulating film 104, an oxide semiconductor film 108_2 over the oxide semiconductor film 108_1, and an oxide semiconductor. An oxide semiconductor film 108_3 over the film 108_2. The channel region 108i, the source region 108s, and the drain region 108d each have a three-layer structure of the oxide semiconductor film 108_1, the oxide semiconductor film 108_2, and the oxide semiconductor film 108_3.
　図２３（Ａ）（Ｂ）に示すトランジスタ１００Ｇが有する酸化物半導体膜１０８は、絶縁膜１０４上の酸化物半導体膜１０８＿２と、酸化物半導体膜１０８＿２上の酸化物半導体膜１０８＿３と、を有する。また、チャネル領域１０８ｉ、ソース領域１０８ｓ、及びドレイン領域１０８ｄは、それぞれ、酸化物半導体膜１０８＿２、及び酸化物半導体膜１０８＿３の２層の積層構造である。 23A and 23B, the oxide semiconductor film 108 included in the transistor 100G includes an oxide semiconductor film 108_2 over the insulating film 104 and an oxide semiconductor film 108_3 over the oxide semiconductor film 108_2. The channel region 108i, the source region 108s, and the drain region 108d each have a two-layer structure of an oxide semiconductor film 108_2 and an oxide semiconductor film 108_3.
　図２４（Ａ）（Ｂ）に示すトランジスタ１００Ｈが有する酸化物半導体膜１０８は、絶縁膜１０４上の酸化物半導体膜１０８＿１と、酸化物半導体膜１０８＿１上の酸化物半導体膜１０８＿２と、を有する。また、チャネル領域１０８ｉ、ソース領域１０８ｓ、及びドレイン領域１０８ｄは、それぞれ、酸化物半導体膜１０８＿１、及び酸化物半導体膜１０８＿２の２層の積層構造である。 24A and 24B, the oxide semiconductor film 108 included in the transistor 100H includes an oxide semiconductor film 108_1 over the insulating film 104 and an oxide semiconductor film 108_2 over the oxide semiconductor film 108_1. The channel region 108i, the source region 108s, and the drain region 108d each have a two-layer structure of the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2.
　図２５（Ａ）（Ｂ）に示すトランジスタ１００Ｊが有する酸化物半導体膜１０８は、絶縁膜１０４上の酸化物半導体膜１０８＿１と、酸化物半導体膜１０８＿１上の酸化物半導体膜１０８＿２と、酸化物半導体膜１０８＿２上の酸化物半導体膜１０８＿３と、を有する。また、チャネル領域１０８ｉは、酸化物半導体膜１０８＿１、酸化物半導体膜１０８＿２、及び酸化物半導体膜１０８＿３の３層の積層構造であり、ソース領域１０８ｓ、及びドレイン領域１０８ｄは、それぞれ、酸化物半導体膜１０８＿１、及び酸化物半導体膜１０８＿２の２層の積層構造である。なお、トランジスタ１００Ｊのチャネル幅（Ｗ）方向の断面において、酸化物半導体膜１０８＿３が、酸化物半導体膜１０８＿１及び酸化物半導体膜１０８＿２の側面を覆う。 An oxide semiconductor film 108 included in the transistor 100J illustrated in FIGS. 25A and 25B includes an oxide semiconductor film 108_1 over the insulating film 104, an oxide semiconductor film 108_2 over the oxide semiconductor film 108_1, and an oxide semiconductor. An oxide semiconductor film 108_3 over the film 108_2. The channel region 108i has a three-layer structure of the oxide semiconductor film 108_1, the oxide semiconductor film 108_2, and the oxide semiconductor film 108_3. The source region 108s and the drain region 108d each have an oxide semiconductor film. A two-layer structure of 108_1 and the oxide semiconductor film 108_2. Note that in the cross section in the channel width (W) direction of the transistor 100J, the oxide semiconductor film 108_3 covers side surfaces of the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2.
　図２６（Ａ）（Ｂ）に示すトランジスタ１００Ｋが有する酸化物半導体膜１０８は、絶縁膜１０４上の酸化物半導体膜１０８＿２と、酸化物半導体膜１０８＿２上の酸化物半導体膜１０８＿３と、を有する。また、チャネル領域１０８ｉは、酸化物半導体膜１０８＿２、及び酸化物半導体膜１０８＿３の２層の積層構造であり、ソース領域１０８ｓ、及びドレイン領域１０８ｄは、それぞれ、酸化物半導体膜１０８＿２の単層構造である。なお、トランジスタ１００Ｋのチャネル幅（Ｗ）方向の断面において、酸化物半導体膜１０８＿３が、酸化物半導体膜１０８＿２の側面を覆う。 The oxide semiconductor film 108 included in the transistor 100K illustrated in FIGS. 26A and 26B includes an oxide semiconductor film 108_2 over the insulating film 104 and an oxide semiconductor film 108_3 over the oxide semiconductor film 108_2. The channel region 108i has a two-layer structure of an oxide semiconductor film 108_2 and an oxide semiconductor film 108_3, and the source region 108s and the drain region 108d have a single layer structure of the oxide semiconductor film 108_2, respectively. is there. Note that in the cross section of the transistor 100K in the channel width (W) direction, the oxide semiconductor film 108_3 covers the side surface of the oxide semiconductor film 108_2.
　チャネル領域１０８ｉのチャネル幅（Ｗ）方向の側面またはその近傍においては、加工におけるダメージにより欠陥（例えば、酸素欠損）が形成されやすい、あるいは不純物の付着により汚染されやすい。そのため、チャネル領域１０８ｉが実質的に真性であっても、電界などのストレスが印加されることによって、チャネル領域１０８ｉのチャネル幅（Ｗ）方向の側面またはその近傍が活性化され、低抵抗（ｎ型）領域となりやすい。また、チャネル領域１０８ｉのチャネル幅（Ｗ）方向の側面またはその近傍がｎ型領域の場合、当該ｎ型領域がキャリアのパスとなるため、寄生チャネルが形成される場合がある。 In the side surface of the channel region 108i in the channel width (W) direction or in the vicinity thereof, defects (for example, oxygen vacancies) are likely to be formed due to damage in processing, or contamination due to adhesion of impurities. Therefore, even when the channel region 108i is substantially intrinsic, application of stress such as an electric field activates the side surface of the channel region 108i in the channel width (W) direction or the vicinity thereof, thereby reducing low resistance (n Type) area. When the side surface in the channel width (W) direction of the channel region 108i or the vicinity thereof is an n-type region, a parasitic channel may be formed because the n-type region serves as a carrier path.
　そこで、トランジスタ１００Ｊ、及びトランジスタ１００Ｋにおいては、チャネル領域１０８ｉを積層構造とし、チャネル領域１０８ｉのチャネル幅（Ｗ）方向の側面を、積層構造の一方の層で覆う構成とする。当該構成とすることで、チャネル領域１０８ｉの側面またはその近傍の欠陥を抑制する、あるいはチャネル領域１０８ｉの側面またはその近傍への不純物の付着を低減することが可能となる。 Therefore, in the transistor 100J and the transistor 100K, the channel region 108i has a stacked structure, and the side surface in the channel width (W) direction of the channel region 108i is covered with one layer of the stacked structure. With this structure, defects on the side surface of the channel region 108i or the vicinity thereof can be suppressed, or adhesion of impurities to the side surface of the channel region 108i or the vicinity thereof can be reduced.
［２−５．バンド構造］
　ここで、絶縁膜１０４、酸化物半導体膜１０８＿１、１０８＿２、１０８＿３、及び絶縁膜１１０のバンド構造、絶縁膜１０４、酸化物半導体膜１０８＿２、１０８＿３、及び絶縁膜１１０のバンド構造、並びに絶縁膜１０４、酸化物半導体膜１０８＿１、１０８＿２のバンド構造について、図２７（Ａ）（Ｂ）（Ｃ）を用いて説明する。なお、図２７（Ａ）（Ｂ）（Ｃ）は、チャネル領域１０８ｉにおけるバンド構造である。 [2-5. Band structure]
Here, the band structure of the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3, and the insulating film 110, the band structure of the insulating film 104, the oxide semiconductor films 108_2 and 108_3, and the insulating film 110, and the insulating film 104, The band structures of the oxide semiconductor films 108_1 and 108_2 will be described with reference to FIGS. 27A, 27B, and 27C show band structures in the channel region 108i.
　図２７（Ａ）は、絶縁膜１０４、酸化物半導体膜１０８＿１、１０８＿２、１０８＿３、及び絶縁膜１１０を有する積層構造の膜厚方向のバンド構造の一例である。また、図２７（Ｂ）は、絶縁膜１０４、酸化物半導体膜１０８＿２、１０８＿３、及び絶縁膜１１０を有する積層構造の膜厚方向のバンド構造の一例である。また、図２７（Ｃ）は、絶縁膜１０４、酸化物半導体膜１０８＿１、１０８＿２、及び絶縁膜１１０を有する積層構造の膜厚方向のバンド構造の一例である。なお、バンド構造は、理解を容易にするため絶縁膜１０４、酸化物半導体膜１０８＿１、１０８＿２、１０８＿３、及び絶縁膜１１０の伝導帯下端のエネルギー準位（Ｅｃ）を示す。 FIG. 27A illustrates an example of a band structure in a film thickness direction of a stacked structure including the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3, and the insulating film 110. FIG. 27B illustrates an example of a band structure in the film thickness direction of a stacked structure including the insulating film 104, the oxide semiconductor films 108_2 and 108_3, and the insulating film 110. FIG. 27C illustrates an example of a band structure in the film thickness direction of a stacked structure including the insulating film 104, the oxide semiconductor films 108_1 and 108_2, and the insulating film 110. Note that the band structure indicates the energy level (Ec) of the lower end of the conduction band of the insulating film 104, the oxide semiconductor films 108_1, 108_2, and 108_3, and the insulating film 110 for easy understanding.
　また、図２７（Ａ）は、絶縁膜１０４、１１０として酸化シリコン膜を用い、酸化物半導体膜１０８＿１として金属元素の原子数比をＩｎ：Ｇａ：Ｚｎ＝１：３：２の金属酸化物ターゲットを用いて形成される酸化物半導体膜を用い、酸化物半導体膜１０８＿２として金属元素の原子数比をＩｎ：Ｇａ：Ｚｎ＝４：２：４．１の金属酸化物ターゲットを用いて形成される酸化物半導体膜を用い、酸化物半導体膜１０８＿３として金属元素の原子数比をＩｎ：Ｇａ：Ｚｎ＝１：３：２の金属酸化物ターゲットを用いて形成される酸化物半導体膜を用いる構成のバンド図である。 FIG. 27A illustrates a metal oxide target in which a silicon oxide film is used as the insulating films 104 and 110 and an atomic ratio of metal elements is In: Ga: Zn = 1: 3: 2 as the oxide semiconductor film 108_1. The oxide semiconductor film 108 </ b> _ <b> 2 is formed using a metal oxide target with an atomic ratio of metal elements of In: Ga: Zn = 4: 2: 4.1. An oxide semiconductor film is used, and an oxide semiconductor film formed using a metal oxide target with an atomic ratio of In: Ga: Zn = 1: 3: 2 as an oxide semiconductor film 108_3 is used. It is a band diagram.
　また、図２７（Ｂ）は、絶縁膜１０４、１１０として酸化シリコン膜を用い、酸化物半導体膜１０８＿２として金属元素の原子数比をＩｎ：Ｇａ：Ｚｎ＝４：２：４．１の金属酸化物ターゲットを用いて形成される酸化物半導体膜を用い、酸化物半導体膜１０８＿３として金属元素の原子数比をＩｎ：Ｇａ：Ｚｎ＝１：３：２の金属酸化物ターゲットを用いて形成される酸化物半導体膜を用いる構成のバンド図である。 In FIG. 27B, a silicon oxide film is used as the insulating films 104 and 110, and a metal oxide atomic ratio of In: Ga: Zn = 4: 2: 4.1 is used as the oxide semiconductor film 108_2. An oxide semiconductor film formed using an object target is used, and the oxide semiconductor film 108_3 is formed using a metal oxide target with an atomic ratio of metal elements of In: Ga: Zn = 1: 3: 2. FIG. 10 is a band diagram of a structure using an oxide semiconductor film.
　また、図２７（Ｃ）は、絶縁膜１０４、１１０として酸化シリコン膜を用い、酸化物半導体膜１０８＿１として金属元素の原子数比をＩｎ：Ｇａ：Ｚｎ＝１：３：２の金属酸化物ターゲットを用いて形成される酸化物半導体膜を用い、酸化物半導体膜１０８＿２として金属元素の原子数比をＩｎ：Ｇａ：Ｚｎ＝４：２：４．１の金属酸化物ターゲットを用いて形成される酸化物半導体膜を用いて形成される酸化物半導体膜を用いる構成のバンド図である。 FIG. 27C illustrates a metal oxide target in which a silicon oxide film is used as the insulating films 104 and 110 and an atomic ratio of metal elements is In: Ga: Zn = 1: 3: 2 as the oxide semiconductor film 108_1. The oxide semiconductor film 108 </ b> _ <b> 2 is formed using a metal oxide target with an atomic ratio of metal elements of In: Ga: Zn = 4: 2: 4.1. FIG. 10 is a band diagram of a structure using an oxide semiconductor film formed using an oxide semiconductor film.
　図２７（Ａ）に示すように、酸化物半導体膜１０８＿１、１０８＿２、１０８＿３において、伝導帯下端のエネルギー準位はなだらかに変化する。また、図２７（Ｂ）に示すように、酸化物半導体膜１０８＿２、１０８＿３において、伝導帯下端のエネルギー準位はなだらかに変化する。また、図２７（Ｃ）に示すように、酸化物半導体膜１０８＿１、１０８＿２において、伝導帯下端のエネルギー準位はなだらかに変化する。換言すると、連続的に変化または連続接合するともいうことができる。このようなバンド構造を有するためには、酸化物半導体膜１０８＿１と酸化物半導体膜１０８＿２との界面、または酸化物半導体膜１０８＿２と酸化物半導体膜１０８＿３との界面において、トラップ中心や再結合中心のような欠陥準位を形成するような不純物が存在しないとする。 As shown in FIG. 27A, in the oxide semiconductor films 108_1, 108_2, and 108_3, the energy level at the lower end of the conduction band changes gently. In addition, as illustrated in FIG. 27B, in the oxide semiconductor films 108_2 and 108_3, the energy level at the lower end of the conduction band changes gently. As shown in FIG. 27C, the energy level at the lower end of the conduction band in the oxide semiconductor films 108_1 and 108_2 changes gently. In other words, it can be said that it is continuously changed or continuously joined. In order to have such a band structure, a trap center or a recombination center is formed at the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2 or the interface between the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3. It is assumed that there is no impurity that forms such a defect level.
　酸化物半導体膜１０８＿１、１０８＿２、１０８＿３に連続接合を形成するためには、ロードロック室を備えたマルチチャンバー方式の成膜装置（スパッタリング装置）を用いて各膜を大気に触れさせることなく連続して積層することが必要となる。 In order to form a continuous bond with the oxide semiconductor films 108_1, 108_2, and 108_3, each film is continuously formed without being exposed to the air using a multi-chamber film formation apparatus (sputtering apparatus) including a load lock chamber. It is necessary to laminate them.
　図２７（Ａ）（Ｂ）（Ｃ）に示す構成とすることで酸化物半導体膜１０８＿２がウェル（井戸）となり、上記積層構造を用いたトランジスタにおいて、チャネル領域が酸化物半導体膜１０８＿２に形成されることがわかる。 27A, 27B, and 27C, the oxide semiconductor film 108_2 becomes a well, and a channel region is formed in the oxide semiconductor film 108_2 in the transistor including the above stacked structure. I understand that
　なお、酸化物半導体膜１０８＿１、１０８＿３を設けることにより、トラップ準位を酸化物半導体膜１０８＿２より遠ざけることができる。 Note that when the oxide semiconductor films 108_1 and 108_3 are provided, the trap level can be further away from the oxide semiconductor film 108_2.
　また、欠陥準位がチャネル領域として機能する酸化物半導体膜１０８＿２の伝導帯下端のエネルギー準位（Ｅｃ）より真空準位から遠くなることがあり、欠陥準位に電子が蓄積しやすくなってしまう。欠陥準位に電子が蓄積されることで、マイナスの固定電荷となり、トランジスタのしきい値電圧はプラス方向にシフトしてしまう。したがって、欠陥準位が酸化物半導体膜１０８＿２の伝導帯下端のエネルギー準位（Ｅｃ）より真空準位に近くなるような構成にすると好ましい。このようにすることで、欠陥準位に電子が蓄積しにくくなり、トランジスタのオン電流を増大させることが可能であると共に、電界効果移動度を高めることができる。 Further, the defect level may be farther from the vacuum level than the energy level (Ec) at the lower end of the conduction band of the oxide semiconductor film 108_2 functioning as a channel region, and electrons are likely to accumulate in the defect level. . Accumulation of electrons at the defect level results in a negative fixed charge, and the threshold voltage of the transistor shifts in the positive direction. Therefore, it is preferable that the defect level be closer to the vacuum level than the energy level (Ec) at the lower end of the conduction band of the oxide semiconductor film 108_2. Thus, electrons are less likely to accumulate at the defect level, the on-state current of the transistor can be increased, and field effect mobility can be increased.
　また、酸化物半導体膜１０８＿１、１０８＿３は、酸化物半導体膜１０８＿２よりも伝導帯下端のエネルギー準位が真空準位に近く、代表的には、酸化物半導体膜１０８＿２の伝導帯下端のエネルギー準位と、酸化物半導体膜１０８＿１、１０８＿３の伝導帯下端のエネルギー準位との差が、０．１５ｅＶ以上、または０．５ｅＶ以上、かつ２ｅＶ以下、または１ｅＶ以下である。すなわち、酸化物半導体膜１０８＿１、１０８＿３の電子親和力と、酸化物半導体膜１０８＿２の電子親和力との差が、０．１５ｅＶ以上、または０．５ｅＶ以上、かつ２ｅＶ以下、または１ｅＶ以下である。 The oxide semiconductor films 108_1 and 108_3 each have an energy level at the lower end of the conduction band that is closer to the vacuum level than the oxide semiconductor film 108_2. Typically, the energy level at the lower end of the conduction band of the oxide semiconductor film 108_2. And the energy level at the lower end of the conduction band of the oxide semiconductor films 108_1 and 108_3 is 0.15 eV or more, 0.5 eV or more, 2 eV or less, or 1 eV or less. That is, the difference between the electron affinity of the oxide semiconductor films 108_1 and 108_3 and the electron affinity of the oxide semiconductor film 108_2 is 0.15 eV or more, 0.5 eV or more, 2 eV or less, or 1 eV or less.
　このような構成を有することで、酸化物半導体膜１０８＿２が主な電流経路となる。すなわち、酸化物半導体膜１０８＿２は、チャネル領域としての機能を有し、酸化物半導体膜１０８＿１、１０８＿３は、酸化物絶縁膜としての機能を有する。また、酸化物半導体膜１０８＿１、１０８＿３は、チャネル領域が形成される酸化物半導体膜１０８＿２を構成する金属元素の一種以上から構成される酸化物半導体膜を用いると好ましい。このような構成とすることで、酸化物半導体膜１０８＿１と酸化物半導体膜１０８＿２との界面、または酸化物半導体膜１０８＿２と酸化物半導体膜１０８＿３との界面において、界面散乱が起こりにくい。従って、該界面においてはキャリアの動きが阻害されないため、トランジスタの電界効果移動度が高くなる。 With such a structure, the oxide semiconductor film 108_2 becomes a main current path. In other words, the oxide semiconductor film 108_2 functions as a channel region, and the oxide semiconductor films 108_1 and 108_3 function as oxide insulating films. The oxide semiconductor films 108_1 and 108_3 are preferably formed using one or more metal elements included in the oxide semiconductor film 108_2 in which a channel region is formed. With such a structure, interface scattering hardly occurs at the interface between the oxide semiconductor film 108_1 and the oxide semiconductor film 108_2 or at the interface between the oxide semiconductor film 108_2 and the oxide semiconductor film 108_3. Accordingly, the movement of carriers is not inhibited at the interface, so that the field effect mobility of the transistor is increased.
　また、酸化物半導体膜１０８＿１、１０８＿３は、チャネル領域の一部として機能することを防止するため、導電率が十分に低い材料を用いるものとする。そのため、酸化物半導体膜１０８＿１、１０８＿３を、その物性及び／または機能から、それぞれ酸化物絶縁膜とも呼べる。または、酸化物半導体膜１０８＿１、１０８＿３には、電子親和力（真空準位と伝導帯下端のエネルギー準位との差）が酸化物半導体膜１０８＿２よりも小さく、伝導帯下端のエネルギー準位が酸化物半導体膜１０８＿２の伝導帯下端エネルギー準位と差分（バンドオフセット）を有する材料を用いるものとする。また、ドレイン電圧の大きさに依存したしきい値電圧の差が生じることを抑制するためには、酸化物半導体膜１０８＿１、１０８＿３の伝導帯下端のエネルギー準位が、酸化物半導体膜１０８＿２の伝導帯下端のエネルギー準位よりも真空準位に近い材料を用いると好適である。例えば、酸化物半導体膜１０８＿２の伝導帯下端のエネルギー準位と、酸化物半導体膜１０８＿１、１０８＿３の伝導帯下端のエネルギー準位との差が、０．２ｅＶ以上、好ましくは０．５ｅＶ以上とすることが好ましい。 The oxide semiconductor films 108_1 and 108_3 are formed using a material with sufficiently low conductivity in order to prevent the oxide semiconductor films 108_1 and 108_3 from functioning as part of the channel region. Therefore, the oxide semiconductor films 108_1 and 108_3 can also be referred to as oxide insulating films because of their physical properties and / or functions. Alternatively, in the oxide semiconductor films 108_1 and 108_3, the electron affinity (difference between the vacuum level and the energy level at the bottom of the conduction band) is lower than that of the oxide semiconductor film 108_2, and the energy level at the bottom of the conduction band is an oxide. A material having a difference (band offset) from the lower energy level of the conduction band of the semiconductor film 108_2 is used. In addition, in order to suppress the difference in threshold voltage depending on the magnitude of the drain voltage, the energy level at the lower end of the conduction band of the oxide semiconductor films 108_1 and 108_3 is determined so that the conduction level of the oxide semiconductor film 108_2 is reduced. It is preferable to use a material closer to the vacuum level than the energy level at the lower end of the band. For example, the difference between the energy level at the bottom of the conduction band of the oxide semiconductor film 108_2 and the energy level at the bottom of the conduction bands of the oxide semiconductor films 108_1 and 108_3 is 0.2 eV or more, preferably 0.5 eV or more. It is preferable.
　また、酸化物半導体膜１０８＿１、１０８＿３は、膜中にスピネル型の結晶構造が含まれないことが好ましい。酸化物半導体膜１０８＿１、１０８＿３の膜中にスピネル型の結晶構造を含む場合、該スピネル型の結晶構造と他の領域との界面において、導電膜１２０ａ、１２０ｂの構成元素が酸化物半導体膜１０８＿２へ拡散してしまう場合がある。なお、酸化物半導体膜１０８＿１、１０８＿３が後述するＣＡＡＣ−ＯＳである場合、導電膜１２０ａ、１２０ｂの構成元素、例えば、銅元素のブロッキング性が高くなり好ましい。 Further, it is preferable that the oxide semiconductor films 108_1 and 108_3 do not include a spinel crystal structure. In the case where the oxide semiconductor films 108_1 and 108_3 include a spinel crystal structure, the constituent elements of the conductive films 120a and 120b enter the oxide semiconductor film 108_2 at the interface between the spinel crystal structure and another region. May diffuse. Note that it is preferable that the oxide semiconductor films 108_1 and 108_3 be a CAAC-OS to be described later because the blocking properties of constituent elements of the conductive films 120a and 120b, for example, a copper element are increased.
　また、本実施の形態においては、酸化物半導体膜１０８＿１、１０８＿３として、金属元素の原子数比をＩｎ：Ｇａ：Ｚｎ＝１：３：２の金属酸化物ターゲットを用いて形成される酸化物半導体膜を用いる構成について例示したが、これに限定されない。例えば、酸化物半導体膜１０８＿１、１０８＿３として、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１［原子数比］、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１．２［原子数比］、Ｉｎ：Ｇａ：Ｚｎ＝１：３：４［原子数比］、Ｉｎ：Ｇａ：Ｚｎ＝１：３：６［原子数比］、Ｉｎ：Ｇａ：Ｚｎ＝１：４：５［原子数比］、Ｉｎ：Ｇａ：Ｚｎ＝１：５：６［原子数比］、またはＩｎ：Ｇａ：Ｚｎ＝１：１０：１［原子数比］の金属酸化物ターゲットを用いて形成される酸化物半導体膜を用いてもよい。あるいは、酸化物半導体膜１０８＿１、１０８＿３として、金属元素の原子数比をＧａ：Ｚｎ＝１０：１の金属酸化物ターゲットを用いて形成される酸化物半導体膜を用いてもよい。この場合、酸化物半導体膜１０８＿２として金属元素の原子数比をＩｎ：Ｇａ：Ｚｎ＝１：１：１の金属酸化物ターゲットを用いて形成される酸化物半導体膜を用い、酸化物半導体膜１０８＿１、１０８＿３として金属元素の原子数比をＧａ：Ｚｎ＝１０：１の金属酸化物ターゲットを用いて形成される酸化物半導体膜を用いると、酸化物半導体膜１０８＿２の伝導帯下端のエネルギー準位と、酸化物半導体膜１０８＿１、１０８＿３の伝導帯下端のエネルギー準位との差を０．６ｅＶ以上とすることができるため好適である。 In this embodiment, the oxide semiconductor films 108_1 and 108_3 are formed using a metal oxide target in which the atomic ratio of metal elements is In: Ga: Zn = 1: 3: 2. Although the configuration using the film is exemplified, the configuration is not limited thereto. For example, as the oxide semiconductor films 108_1 and 108_3, In: Ga: Zn = 1: 1: 1 [atomic ratio], In: Ga: Zn = 1: 1: 1.2 [atomic ratio], In: Ga : Zn = 1: 3: 4 [atomic ratio], In: Ga: Zn = 1: 3: 6 [atomic ratio], In: Ga: Zn = 1: 4: 5 [atomic ratio], In: Using an oxide semiconductor film formed using a metal oxide target of Ga: Zn = 1: 5: 6 [atomic ratio] or In: Ga: Zn = 1: 10: 1 [atomic ratio] Also good. Alternatively, an oxide semiconductor film formed using a metal oxide target with an atomic ratio of metal elements Ga: Zn = 10: 1 may be used as the oxide semiconductor films 108_1 and 108_3. In this case, as the oxide semiconductor film 108_2, an oxide semiconductor film formed using a metal oxide target with a metal element atomic ratio of In: Ga: Zn = 1: 1: 1 is used, and the oxide semiconductor film 108_1. , 108_3, an oxide semiconductor film formed using a metal oxide target with a metal element atomic ratio of Ga: Zn = 10: 1 can have an energy level at the lower end of the conduction band of the oxide semiconductor film 108_2. The oxide semiconductor films 108_1 and 108_3 are preferable because the difference from the energy level at the lower end of the conduction band can be 0.6 eV or more.
　なお、酸化物半導体膜１０８＿１、１０８＿３として、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１［原子数比］の金属酸化物ターゲットを用いる場合、酸化物半導体膜１０８＿１、１０８＿３は、Ｉｎ：Ｇａ：Ｚｎ＝１：β１（０＜β１≦２）：β２（０＜β２≦２）となる場合がある。また、酸化物半導体膜１０８＿１、１０８＿３として、Ｉｎ：Ｇａ：Ｚｎ＝１：３：４［原子数比］の金属酸化物ターゲットを用いる場合、酸化物半導体膜１０８＿１、１０８＿３は、Ｉｎ：Ｇａ：Ｚｎ＝１：β３（１≦β３≦５）：β４（２≦β４≦６）となる場合がある。また、酸化物半導体膜１０８＿１、１０８＿３として、Ｉｎ：Ｇａ：Ｚｎ＝１：３：６［原子数比］の金属酸化物ターゲットを用いる場合、酸化物半導体膜１０８＿１、１０８＿３は、Ｉｎ：Ｇａ：Ｚｎ＝１：β５（１≦β５≦５）：β６（４≦β６≦８）となる場合がある。 Note that in the case where a metal oxide target with In: Ga: Zn = 1: 1: 1 [atomic ratio] is used as the oxide semiconductor films 108_1 and 108_3, the oxide semiconductor films 108_1 and 108_3 are formed of In: Ga: Zn. = 1: β1 (0 <β1 ≦ 2): β2 (0 <β2 ≦ 2). In the case where a metal oxide target with In: Ga: Zn = 1: 3: 4 [atomic ratio] is used as the oxide semiconductor films 108_1 and 108_3, the oxide semiconductor films 108_1 and 108_3 are formed of In: Ga: Zn. = 1: β3 (1 ≦ β3 ≦ 5): β4 (2 ≦ β4 ≦ 6) in some cases. In the case where a metal oxide target with In: Ga: Zn = 1: 3: 6 [atomic ratio] is used as the oxide semiconductor films 108_1 and 108_3, the oxide semiconductor films 108_1 and 108_3 are formed of In: Ga: Zn. = 1: β5 (1 ≦ β5 ≦ 5): β6 (4 ≦ β6 ≦ 8) in some cases.
　本実施の形態は、少なくともその一部を本明細書中に記載する他の実施の形態と適宜組み合わせて実施することができる。 Note that at least part of this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate.
（実施の形態３）
　本実施の形態では、本発明の一態様の半導体装置に用いることのできるトランジスタについて、詳細に説明する。 (Embodiment 3)
In this embodiment, a transistor that can be used for the semiconductor device of one embodiment of the present invention will be described in detail.
　なお、本実施の形態では、ボトムゲート型のトランジスタについて、図２８乃至図３４を用いて説明する。 Note that in this embodiment, a bottom-gate transistor is described with reference to FIGS.
［３−１．トランジスタの構成例１］
　図２８（Ａ）は、トランジスタ３００Ａの上面図であり、図２８（Ｂ）は、図２８（Ａ）に示す一点鎖線Ｘ１−Ｘ２間における切断面の断面図に相当し、図２８（Ｃ）は、図２８（Ａ）に示す一点鎖線Ｙ１−Ｙ２間における切断面の断面図に相当する。なお、図２８（Ａ）において、煩雑になることを避けるため、トランジスタ３００Ａの構成要素の一部（ゲート絶縁膜として機能する絶縁膜等）を省略して図示している。また、一点鎖線Ｘ１−Ｘ２方向をチャネル長方向、一点鎖線Ｙ１−Ｙ２方向をチャネル幅方向と呼称する場合がある。なお、トランジスタの上面図においては、以降の図面においても図２８（Ａ）と同様に、構成要素の一部を省略して図示する場合がある。 [3-1. Transistor configuration example 1]
FIG. 28A is a top view of the transistor 300A, and FIG. 28B corresponds to a cross-sectional view of a cross section taken along dashed-dotted line X1-X2 in FIG. 28A. Corresponds to a cross-sectional view of a cut surface taken along the alternate long and short dash line Y1-Y2 shown in FIG. Note that in FIG. 28A, some components (such as an insulating film functioning as a gate insulating film) are omitted in order to avoid complexity. The direction of the alternate long and short dash line X1-X2 may be referred to as a channel length direction, and the direction of the alternate long and short dash line Y1-Y2 may be referred to as a channel width direction. Note that in the top view of the transistor, some components may be omitted in the following drawings as in FIG. 28A.
　図２８に示すトランジスタ３００Ａは、基板３０２上の導電膜３０４と、基板３０２及び導電膜３０４上の絶縁膜３０６と、絶縁膜３０６上の絶縁膜３０７と、絶縁膜３０７上の酸化物半導体膜３０８と、酸化物半導体膜３０８上の導電膜３１２ａと、酸化物半導体膜３０８上の導電膜３１２ｂと、を有する。また、トランジスタ３００Ａ上、より詳しくは、導重膜３１２ａ、３１２ｂ及び酸化物半導体膜３０８上には絶縁膜３１４、３１６、及び絶縁膜３１８が設けられる。 A transistor 300A illustrated in FIG. 28 includes a conductive film 304 over a substrate 302, an insulating film 306 over the substrate 302 and the conductive film 304, an insulating film 307 over the insulating film 306, and an oxide semiconductor film 308 over the insulating film 307. A conductive film 312 a over the oxide semiconductor film 308 and a conductive film 312 b over the oxide semiconductor film 308. In addition, insulating films 314 and 316 and an insulating film 318 are provided over the transistor 300A, more specifically, over the conductive films 312a and 312b and the oxide semiconductor film 308.
　なお、トランジスタ３００Ａにおいて、絶縁膜３０６、３０７は、トランジスタ３００Ａのゲート絶縁膜としての機能を有し、絶縁膜３１４、３１６、３１８は、トランジスタ３００Ａの保護絶縁膜としての機能を有する。また、トランジスタ３００Ａにおいて、導電膜３０４は、ゲート電極としての機能を有し、導電膜３１２ａは、ソース電極としての機能を有し、導電膜３１２ｂは、ドレイン電極としての機能を有する。 Note that in the transistor 300A, the insulating films 306 and 307 function as gate insulating films of the transistor 300A, and the insulating films 314, 316, and 318 function as protective insulating films of the transistor 300A. In the transistor 300A, the conductive film 304 functions as a gate electrode, the conductive film 312a functions as a source electrode, and the conductive film 312b functions as a drain electrode.
　なお、本明細書等において、絶縁膜３０６、３０７を第１の絶縁膜と、絶縁膜３１４、３１６を第２の絶縁膜と、絶縁膜３１８を第３の絶縁膜と、それぞれ呼称する場合がある。 Note that in this specification and the like, the insulating films 306 and 307 may be referred to as a first insulating film, the insulating films 314 and 316 as a second insulating film, and the insulating film 318 as a third insulating film, respectively. is there.
　図２８に示すトランジスタ３００Ａは、チャネルエッチ型のトランジスタ構造である。本発明の一態様の酸化物半導体膜は、チャネルエッチ型のトランジスタに好適に用いることができる。 The transistor 300A shown in FIG. 28 has a channel etch type transistor structure. The oxide semiconductor film of one embodiment of the present invention can be favorably used for a channel-etched transistor.
［３−２．トランジスタの構成例２］
　図２９（Ａ）は、トランジスタ３００Ｂの上面図であり、図２９（Ｂ）は、図２９（Ａ）に示す一点鎖線Ｘ１−Ｘ２間における切断面の断面図に相当し、図２９（Ｃ）は、図２９（Ａ）に示す一点鎖線Ｙ１−Ｙ２間における切断面の断面図に相当する。 [3-2. Transistor configuration example 2]
FIG. 29A is a top view of the transistor 300B, and FIG. 29B corresponds to a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 29A. Corresponds to a cross-sectional view of a cut surface taken along the alternate long and short dash line Y1-Y2 shown in FIG.
　図２９に示すトランジスタ３００Ｂは、基板３０２上の導電膜３０４と、基板３０２及び導電膜３０４上の絶縁膜３０６と、絶縁膜３０６上の絶縁膜３０７と、絶縁膜３０７上の酸化物半導体膜３０８と、酸化物半導体膜３０８上の絶縁膜３１４と、絶縁膜３１４上の絶縁膜３１６と、絶縁膜３１４及び絶縁膜３１６に設けられる開口部３４１ａを介して酸化物半導体膜３０８に電気的に接続される導電膜３１２ａと、絶縁膜３１４及び絶縁膜３１６に設けられる開口部３４１ｂを介して酸化物半導体膜３０８に電気的に接続される導電膜３１２ｂとを有する。また、トランジスタ３００Ｂ上、より詳しくは、導電膜３１２ａ、３１２ｂ、及び絶縁膜３１６上には絶縁膜３１８が設けられる。 A transistor 300B illustrated in FIG. 29 includes a conductive film 304 over a substrate 302, an insulating film 306 over the substrate 302 and the conductive film 304, an insulating film 307 over the insulating film 306, and an oxide semiconductor film 308 over the insulating film 307. And the insulating film 314 over the oxide semiconductor film 308, the insulating film 316 over the insulating film 314, and the oxide semiconductor film 308 through the openings 341a provided in the insulating film 314 and the insulating film 316. And a conductive film 312b which is electrically connected to the oxide semiconductor film 308 through an opening 341b provided in the insulating film 314 and the insulating film 316. An insulating film 318 is provided over the transistor 300B, more specifically, over the conductive films 312a and 312b and the insulating film 316.
　なお、トランジスタ３００Ｂにおいて、絶縁膜３０６、３０７は、トランジスタ３００Ｂのゲート絶縁膜としての機能を有し、絶縁膜３１４、３１６は、酸化物半導体膜３０８の保護絶縁膜としての機能を有し、絶縁膜３１８は、トランジスタ３００Ｂの保護絶縁膜としての機能を有する。また、トランジスタ３００Ｂにおいて、導電膜３０４は、ゲート電極としての機能を有し、導電膜３１２ａは、ソース電極としての機能を有し、導電膜３１２ｂは、ドレイン電極としての機能を有する。 Note that in the transistor 300B, the insulating films 306 and 307 function as gate insulating films of the transistor 300B, and the insulating films 314 and 316 have functions as protective insulating films of the oxide semiconductor film 308. The film 318 functions as a protective insulating film of the transistor 300B. In the transistor 300B, the conductive film 304 functions as a gate electrode, the conductive film 312a functions as a source electrode, and the conductive film 312b functions as a drain electrode.
　図２８に示すトランジスタ３００Ａにおいては、チャネルエッチ型の構造であったのに対し、図２９（Ａ）（Ｂ）（Ｃ）に示すトランジスタ３００Ｂは、チャネル保護型の構造である。本発明の一態様の酸化物半導体膜は、チャネル保護型のトランジスタにも好適に用いることができる。 28A has a channel etch type structure, the transistor 300B shown in FIGS. 29A, 29B, and 29C has a channel protection type structure. The oxide semiconductor film of one embodiment of the present invention can be favorably used for a channel protection transistor.
［３−３．トランジスタの構成例３］
　図３０（Ａ）は、トランジスタ３００Ｃの上面図であり、図３０（Ｂ）は、図３０（Ａ）に示す一点鎖線Ｘ１−Ｘ２間における切断面の断面図に相当し、図３０（Ｃ）は、図３０（Ａ）に示す一点鎖線Ｙ１−Ｙ２間における切断面の断面図に相当する。 [3-3. Transistor configuration example 3]
30A is a top view of the transistor 300C, and FIG. 30B corresponds to a cross-sectional view of a cross section taken along dashed-dotted line X1-X2 in FIG. 30A. Corresponds to a cross-sectional view of a cut surface taken along the alternate long and short dash line Y1-Y2 shown in FIG.
　図３０に示すトランジスタ３００Ｃは、図２９（Ａ）（Ｂ）（Ｃ）に示すトランジスタ３００Ｂと絶縁膜３１４、３１６の形状が相違する。具体的には、トランジスタ３００Ｃの絶縁膜３１４、３１６は、酸化物半導体膜３０８のチャネル領域上に島状に設けられる。その他の構成は、トランジスタ３００Ｂと同様である。 30 is different from the transistor 300B illustrated in FIGS. 29A, 29B, and 29C in the shape of the insulating films 314 and 316. The transistor 300C illustrated in FIG. Specifically, the insulating films 314 and 316 of the transistor 300C are provided in an island shape over the channel region of the oxide semiconductor film 308. Other structures are similar to those of the transistor 300B.
［３−４．トランジスタの構成例４］
　図３１（Ａ）は、トランジスタ３００Ｄの上面図であり、図３１（Ｂ）は、図３１（Ａ）に示す一点鎖線Ｘ１−Ｘ２間における切断面の断面図に相当し、図３１（Ｃ）は、図３１（Ａ）に示す一点鎖線Ｙ１−Ｙ２間における切断面の断面図に相当する。 [3-4. Transistor configuration example 4]
FIG. 31A is a top view of the transistor 300D, and FIG. 31B corresponds to a cross-sectional view of a cross section taken along dashed-dotted line X1-X2 in FIG. Corresponds to a cross-sectional view of a cut surface taken along the dashed-dotted line Y1-Y2 in FIG.
　図３１に示すトランジスタ３００Ｄは、基板３０２上の導電膜３０４と、基板３０２及び導電膜３０４上の絶縁膜３０６と、絶縁膜３０６上の絶縁膜３０７と、絶縁膜３０７上の酸化物半導体膜３０８と、酸化物半導体膜３０８上の導電膜３１２ａと、酸化物半導体膜３０８上の導電膜３１２ｂと、酸化物半導体膜３０８、及び導電膜３１２ａ、３１２ｂ上の絶縁膜３１４と、絶縁膜３１４上の絶縁膜３１６と、絶縁膜３１６上の絶縁膜３１８と、絶縁膜３１８上の導電膜３２０ａ、３２０ｂと、を有する。 A transistor 300D illustrated in FIG. 31 includes a conductive film 304 over a substrate 302, an insulating film 306 over the substrate 302 and the conductive film 304, an insulating film 307 over the insulating film 306, and an oxide semiconductor film 308 over the insulating film 307. A conductive film 312a over the oxide semiconductor film 308, a conductive film 312b over the oxide semiconductor film 308, an insulating film 314 over the oxide semiconductor film 308 and the conductive films 312a and 312b, and over the insulating film 314. An insulating film 316, an insulating film 318 over the insulating film 316, and conductive films 320a and 320b over the insulating film 318 are included.
　なお、トランジスタ３００Ｄにおいて、絶縁膜３０６、３０７は、トランジスタ３００Ｄの第１のゲート絶縁膜としての機能を有し、絶縁膜３１４、３１６、３１８は、トランジスタ３００Ｄの第２のゲート絶縁膜としての機能を有する。また、トランジスタ３００Ｄにおいて、導電膜３０４は、第１のゲート電極としての機能を有し、導電膜３２０ａは、第２のゲート電極としての機能を有し、導電膜３２０ｂは、表示装置に用いる画素電極としての機能を有する。また、導電膜３１２ａは、ソース電極としての機能を有し、導電膜３１２ｂは、ドレイン電極としての機能を有する。 Note that in the transistor 300D, the insulating films 306 and 307 function as a first gate insulating film of the transistor 300D, and the insulating films 314, 316, and 318 function as a second gate insulating film of the transistor 300D. Have In the transistor 300D, the conductive film 304 has a function as a first gate electrode, the conductive film 320a has a function as a second gate electrode, and the conductive film 320b is a pixel used for a display device. It has a function as an electrode. The conductive film 312a functions as a source electrode, and the conductive film 312b functions as a drain electrode.
　また、図３１（Ｃ）に示すように導電膜３２０ａは、絶縁膜３０６、３０７、３１４、３１６、３１８に設けられる開口部３４２ｂ、３４２ｃにおいて、導電膜３０４に接続される。よって、導電膜３２０ａと導電膜３０４とは、同じ電位が与えられる。 Further, as shown in FIG. 31C, the conductive film 320a is connected to the conductive film 304 in openings 342b and 342c provided in the insulating films 306, 307, 314, 316, and 318. Therefore, the same potential is applied to the conductive film 320a and the conductive film 304.
　なお、トランジスタ３００Ｄにおいては、開口部３４２ｂ、３４２ｃを設け、導電膜３２０ａと導電膜３０４を接続する構成について例示したが、これに限定されない。例えば、開口部３４２ｂまたは開口部３４２ｃのいずれか一方の開口部のみを形成し、導電膜３２０ａと導電膜３０４を接続する構成、または開口部３４２ｂ及び開口部３４２ｃを設けずに、導電膜３２０ａと導電膜３０４を接続しない構成としてもよい。なお、導電膜３２０ａと導電膜３０４とを接続しない構成の場合、導電膜３２０ａと導電膜３０４には、それぞれ異なる電位を与えることができる。 Note that in the transistor 300D, the opening portions 342b and 342c are provided and the conductive film 320a and the conductive film 304 are connected to each other, but the invention is not limited thereto. For example, a structure in which only one of the opening 342b and the opening 342c is formed and the conductive film 320a and the conductive film 304 are connected, or the conductive film 320a without the opening 342b and the opening 342c is provided. The conductive film 304 may not be connected. Note that in the case where the conductive film 320a and the conductive film 304 are not connected to each other, different potentials can be applied to the conductive film 320a and the conductive film 304, respectively.
　また、導電膜３２０ｂは、絶縁膜３１４、３１６、３１８に設けられる開口部３４２ａを介して、導電膜３１２ｂと接続される。 In addition, the conductive film 320b is connected to the conductive film 312b through the opening 342a provided in the insulating films 314, 316, and 318.
　なお、トランジスタ３００Ｄは、先に説明のＳ−ｃｈａｎｎｅｌ構造を有する。 Note that the transistor 300D has the S-channel structure described above.
［３−５．トランジスタの構成例５］
　また、図２８（Ａ）（Ｂ）（Ｃ）に示すトランジスタ３００Ａが有する酸化物半導体膜３０８を複数の積層構造としてもよい。その場合の一例を図３２（Ａ）（Ｂ）及び図３３（Ａ）（Ｂ）に示す。 [3-5. Transistor configuration example 5]
Alternatively, the oxide semiconductor film 308 included in the transistor 300A illustrated in FIGS. 28A, 28B, and 28C may have a stacked structure. Examples of such cases are shown in FIGS. 32A and 32B and FIGS. 33A and 33B.
　図３２（Ａ）（Ｂ）は、トランジスタ３００Ｅの断面図であり、図３３（Ａ）（Ｂ）は、トランジスタ３００Ｆの断面図である。なお、トランジスタ３００Ｅ、３００Ｆの上面図としては、図２８（Ａ）に示すトランジスタ３００Ａと同様である。 32A and 32B are cross-sectional views of the transistor 300E, and FIGS. 33A and 33B are cross-sectional views of the transistor 300F. Note that top views of the transistors 300E and 300F are similar to those of the transistor 300A illustrated in FIG.
　図３２（Ａ）（Ｂ）に示すトランジスタ３００Ｅが有する酸化物半導体膜３０８は、酸化物半導体膜３０８＿１と、酸化物半導体膜３０８＿２と、酸化物半導体膜３０８＿３と、を有する。また、図３３（Ａ）（Ｂ）に示すトランジスタ３００Ｆが有する酸化物半導体膜３０８は、酸化物半導体膜３０８＿２と、酸化物半導体膜３０８＿３と、を有する。 32A and 32B, the oxide semiconductor film 308 included in the transistor 300E includes an oxide semiconductor film 308_1, an oxide semiconductor film 308_2, and an oxide semiconductor film 308_3. In addition, the oxide semiconductor film 308 included in the transistor 300F illustrated in FIGS. 33A and 33B includes an oxide semiconductor film 308_2 and an oxide semiconductor film 308_3.
　なお、導電膜３０４、絶縁膜３０６、絶縁膜３０７、酸化物半導体膜３０８、酸化物半導体膜３０８＿１、酸化物半導体膜３０８＿２、酸化物半導体膜３０８＿３、導電膜３１２ａ、３１２ｂ、絶縁膜３１４、絶縁膜３１６、絶縁膜３１８、及び導電膜３２０ａ、３２０ｂとしては、それぞれ先に記載の導電膜１０６、絶縁膜１１６、絶縁膜１１４、酸化物半導体膜１０８、酸化物半導体膜１０８＿１、酸化物半導体膜１０８＿２、酸化物半導体膜１０８＿３、導電膜１２０ａ、１２０ｂ、絶縁膜１０４、絶縁膜１１８、絶縁膜１１６、及び導電膜１１２と同様な材料を用いることができる。 Note that the conductive film 304, the insulating film 306, the insulating film 307, the oxide semiconductor film 308, the oxide semiconductor film 308_1, the oxide semiconductor film 308_2, the oxide semiconductor film 308_3, the conductive films 312a and 312b, the insulating film 314, and the insulating film 316, the insulating film 318, and the conductive films 320a and 320b include the conductive film 106, the insulating film 116, the insulating film 114, the oxide semiconductor film 108, the oxide semiconductor film 108_1, the oxide semiconductor film 108_2, and the like described above, respectively. A material similar to that of the oxide semiconductor film 108_3, the conductive films 120a and 120b, the insulating film 104, the insulating film 118, the insulating film 116, and the conductive film 112 can be used.
［３−６．トランジスタの構成例６］
　図３４（Ａ）は、トランジスタ３００Ｇの上面図であり、図３４（Ｂ）は、図３４（Ａ）に示す一点鎖線Ｘ１−Ｘ２間における切断面の断面図に相当し、図３４（Ｃ）は、図３４（Ａ）に示す一点鎖線Ｙ１−Ｙ２間における切断面の断面図に相当する。 [3-6. Transistor configuration example 6]
FIG. 34A is a top view of the transistor 300G, and FIG. 34B corresponds to a cross-sectional view of a cross section taken along dashed-dotted line X1-X2 in FIG. 34A. Corresponds to a cross-sectional view of a cut surface taken along the alternate long and short dash line Y1-Y2 shown in FIG.
　図３４に示すトランジスタ３００Ｇは、基板３０２上の導電膜３０４と、基板３０２及び導電膜３０４上の絶縁膜３０６と、絶縁膜３０６上の絶縁膜３０７と、絶縁膜３０７上の酸化物半導体膜３０８と、酸化物半導体膜３０８上の導電膜３１２ａと、酸化物半導体膜３０８上の導電膜３１２ｂと、酸化物半導体膜３０８、導電膜３１２ａ、及び導電膜３１２ｂ上の絶縁膜３１４と、絶縁膜３１４上の絶縁膜３１６と、絶縁膜３１６上の導電膜３２０ａと、絶縁膜３１６上の導電膜３２０ｂと、を有する。 34 includes a conductive film 304 over a substrate 302, an insulating film 306 over the substrate 302 and the conductive film 304, an insulating film 307 over the insulating film 306, and an oxide semiconductor film 308 over the insulating film 307. A conductive film 312a over the oxide semiconductor film 308, a conductive film 312b over the oxide semiconductor film 308, an insulating film 314 over the oxide semiconductor film 308, the conductive film 312a, and the conductive film 312b, and an insulating film 314. The upper insulating film 316, the conductive film 320a over the insulating film 316, and the conductive film 320b over the insulating film 316 are included.
　また、絶縁膜３０６及び絶縁膜３０７は、開口部３５１を有し、絶縁膜３０６及び絶縁膜３０７上には、開口部３５１を介して導電膜３０４と電気的に接続される導電膜３１２ｃが形成される。また、絶縁膜３１４及び絶縁膜３１６は、導電膜３１２ｂに達する開口部３５２ａと、導電膜３１２ｃに達する開口部３５２ｂとを有する。 The insulating film 306 and the insulating film 307 have an opening 351, and a conductive film 312c that is electrically connected to the conductive film 304 through the opening 351 is formed over the insulating film 306 and the insulating film 307. Is done. The insulating film 314 and the insulating film 316 include an opening 352a reaching the conductive film 312b and an opening 352b reaching the conductive film 312c.
　また、酸化物半導体膜３０８は、導電膜３０４側の酸化物半導体膜３０８＿２と、酸化物半導体膜３０８＿２上の酸化物半導体膜３０８＿３と、を有する。 The oxide semiconductor film 308 includes an oxide semiconductor film 308_2 on the conductive film 304 side and an oxide semiconductor film 308_3 over the oxide semiconductor film 308_2.
　また、トランジスタ３００Ｇの上には、絶縁膜３１８が設けられる。絶縁膜３１８は、絶縁膜３１６、導電膜３２０ａ、及び導電膜３２０ｂを覆うように形成される。 In addition, an insulating film 318 is provided over the transistor 300G. The insulating film 318 is formed so as to cover the insulating film 316, the conductive film 320a, and the conductive film 320b.
　なお、トランジスタ３００Ｇにおいて、絶縁膜３０６、３０７は、トランジスタ３００Ｇの第１のゲート絶縁膜としての機能を有し、絶縁膜３１４、３１６は、トランジスタ３００Ｇの第２のゲート絶縁膜としての機能を有し、絶縁膜３１８は、トランジスタ３００Ｇの保護絶縁膜としての機能を有する。また、トランジスタ３００Ｇにおいて、導電膜３０４は、第１のゲート電極としての機能を有し、導電膜３２０ａは、第２のゲート電極としての機能を有し、導電膜３２０ｂは、表示装置に用いる画素電極としての機能を有する。また、トランジスタ３００Ｇにおいて、導電膜３１２ａは、ソース電極としての機能を有し、導電膜３１２ｂは、ドレイン電極としての機能を有する。また、トランジスタ３００Ｇにおいて、導電膜３１２ｃは接続電極としての機能を有する。 Note that in the transistor 300G, the insulating films 306 and 307 have a function as a first gate insulating film of the transistor 300G, and the insulating films 314 and 316 have a function as a second gate insulating film of the transistor 300G. The insulating film 318 functions as a protective insulating film of the transistor 300G. In the transistor 300G, the conductive film 304 functions as a first gate electrode, the conductive film 320a functions as a second gate electrode, and the conductive film 320b is a pixel used for a display device. It has a function as an electrode. In the transistor 300G, the conductive film 312a functions as a source electrode, and the conductive film 312b functions as a drain electrode. In the transistor 300G, the conductive film 312c functions as a connection electrode.
　なお、トランジスタ３００Ｇは、先に説明のＳ−ｃｈａｎｎｅｌ構造を有する。 Note that the transistor 300G has the S-channel structure described above.
　また、トランジスタ３００Ａ乃至トランジスタ３００Ｇの構造を、それぞれ自由に組み合わせて用いてもよい。 Further, the structures of the transistors 300A to 300G may be used in any combination.
　本実施の形態は、少なくともその一部を本明細書中に記載する他の実施の形態と適宜組み合わせて実施することができる。 Note that at least part of this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate.
（実施の形態４）
　本実施の形態においては、先の実施の形態で例示したトランジスタを有する表示装置の一例について、図３５乃至図４２を用いて以下説明を行う。 (Embodiment 4)
In this embodiment, an example of a display device including the transistor described in the above embodiment will be described below with reference to FIGS.
　図３５は、表示装置の一例を示す上面図である。図３５に示す表示装置７００は、第１の基板７０１上に設けられた画素部７０２と、第１の基板７０１に設けられたソースドライバ回路部７０４及びゲートドライバ回路部７０６と、画素部７０２、ソースドライバ回路部７０４、及びゲートドライバ回路部７０６を囲むように配置されるシール材７１２と、第１の基板７０１に対向するように設けられる第２の基板７０５と、を有する。なお、第１の基板７０１と第２の基板７０５は、シール材７１２によって封止されている。すなわち、画素部７０２、ソースドライバ回路部７０４、及びゲートドライバ回路部７０６は、第１の基板７０１とシール材７１２と第２の基板７０５によって封止されている。なお、図３５には図示しないが、第１の基板７０１と第２の基板７０５の間には表示素子が設けられる。 FIG. 35 is a top view showing an example of the display device. A display device 700 illustrated in FIG. 35 includes a pixel portion 702 provided over a first substrate 701, a source driver circuit portion 704 and a gate driver circuit portion 706 provided over the first substrate 701, a pixel portion 702, The sealant 712 is disposed so as to surround the source driver circuit portion 704 and the gate driver circuit portion 706, and the second substrate 705 is provided so as to face the first substrate 701. Note that the first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are sealed with the first substrate 701, the sealant 712, and the second substrate 705. Note that although not illustrated in FIG. 35, a display element is provided between the first substrate 701 and the second substrate 705.
　また、表示装置７００は、第１の基板７０１上のシール材７１２によって囲まれている領域とは異なる領域に、画素部７０２、ソースドライバ回路部７０４、ゲートドライバ回路部７０６、及びゲートドライバ回路部７０６と、それぞれ電気的に接続されるＦＰＣ端子部７０８（ＦＰＣ：Ｆｌｅｘｉｂｌｅ　ｐｒｉｎｔｅｄ　ｃｉｒｃｕｉｔ）が設けられる。また、ＦＰＣ端子部７０８には、ＦＰＣ７１６が接続され、ＦＰＣ７１６によって画素部７０２、ソースドライバ回路部７０４、及びゲートドライバ回路部７０６に各種信号等が供給される。また、画素部７０２、ソースドライバ回路部７０４、ゲートドライバ回路部７０６、及びＦＰＣ端子部７０８には、信号線７１０が各々接続されている。ＦＰＣ７１６により供給される各種信号等は、信号線７１０を介して、画素部７０２、ソースドライバ回路部７０４、ゲートドライバ回路部７０６、及びＦＰＣ端子部７０８に与えられる。 The display device 700 includes a pixel portion 702, a source driver circuit portion 704, a gate driver circuit portion 706, and a gate driver circuit portion in a region different from the region surrounded by the sealant 712 over the first substrate 701. 706 and an FPC terminal portion 708 (FPC: Flexible printed circuit) electrically connected to each other. In addition, an FPC 716 is connected to the FPC terminal portion 708, and various signals are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 by the FPC 716. A signal line 710 is connected to each of the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708. Various signals and the like supplied by the FPC 716 are supplied to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708 through the signal line 710.
　また、表示装置７００にゲートドライバ回路部７０６を複数設けてもよい。また、表示装置７００としては、ソースドライバ回路部７０４、及びゲートドライバ回路部７０６を画素部７０２と同じ第１の基板７０１に形成している例を示しているが、この構成に限定されない。例えば、ゲートドライバ回路部７０６のみを第１の基板７０１に形成しても良い、またはソースドライバ回路部７０４のみを第１の基板７０１に形成しても良い。この場合、ソースドライバ回路またはゲートドライバ回路等が形成された基板（例えば、単結晶半導体膜、多結晶半導体膜で形成された駆動回路基板）を、第１の基板７０１に形成する構成としても良い。なお、別途形成した駆動回路基板の接続方法は、特に限定されるものではなく、ＣＯＧ（Ｃｈｉｐ　Ｏｎ　Ｇｌａｓｓ）方法、ワイヤボンディング方法などを用いることができる。 Further, a plurality of gate driver circuit portions 706 may be provided in the display device 700. In addition, as the display device 700, an example in which the source driver circuit portion 704 and the gate driver circuit portion 706 are formed over the same first substrate 701 as the pixel portion 702 is shown; however, the display device 700 is not limited to this structure. For example, only the gate driver circuit portion 706 may be formed on the first substrate 701, or only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, a substrate on which a source driver circuit, a gate driver circuit, or the like is formed (eg, a driver circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be formed over the first substrate 701. . Note that a connection method of a separately formed drive circuit board is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or the like can be used.
　また、表示装置７００が有する画素部７０２、ソースドライバ回路部７０４及びゲートドライバ回路部７０６は、複数のトランジスタを有している。 Further, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 included in the display device 700 include a plurality of transistors.
　また、表示装置７００は、様々な素子を有することが出来る。該素子の一例としては、例えば、エレクトロルミネッセンス（ＥＬ）素子（有機物及び無機物を含むＥＬ素子、有機ＥＬ素子、無機ＥＬ素子、ＬＥＤなど）、発光トランジスタ素子（電流に応じて発光するトランジスタ）、電子放出素子、液晶素子、電子インク素子、電気泳動素子、エレクトロウェッティング素子、プラズマディスプレイパネル（ＰＤＰ）、ＭＥＭＳ（マイクロ・エレクトロ・メカニカル・システム）ディスプレイ（例えば、グレーティングライトバルブ（ＧＬＶ）、デジタルマイクロミラーデバイス（ＤＭＤ）、デジタル・マイクロ・シャッター（ＤＭＳ）素子、インターフェロメトリック・モジュレーション（ＩＭＯＤ）素子など）、圧電セラミックディスプレイなどが挙げられる。 In addition, the display device 700 can have various elements. Examples of the element include, for example, an electroluminescence (EL) element (an EL element including an organic substance and an inorganic substance, an organic EL element, an inorganic EL element, an LED, and the like), a light-emitting transistor element (a transistor that emits light in response to current), an electron Emission element, liquid crystal element, electronic ink element, electrophoretic element, electrowetting element, plasma display panel (PDP), MEMS (micro electro mechanical system) display (for example, grating light valve (GLV), digital micromirror Devices (DMD), digital micro shutter (DMS) elements, interferometric modulation (IMOD) elements, etc.), piezoelectric ceramic displays, and the like.
　また、ＥＬ素子を用いた表示装置の一例としては、ＥＬディスプレイなどがある。電子放出素子を用いた表示装置の一例としては、フィールドエミッションディスプレイ（ＦＥＤ）又はＳＥＤ方式平面型ディスプレイ（ＳＥＤ：Ｓｕｒｆａｃｅ−ｃｏｎｄｕｃｔｉｏｎ　Ｅｌｅｃｔｒｏｎ−ｅｍｉｔｔｅｒ　Ｄｉｓｐｌａｙ）などがある。液晶素子を用いた表示装置の一例としては、液晶ディスプレイ（透過型液晶ディスプレイ、半透過型液晶ディスプレイ、反射型液晶ディスプレイ、直視型液晶ディスプレイ、投射型液晶ディスプレイ）などがある。電子インク素子又は電気泳動素子を用いた表示装置の一例としては、電子ペーパーなどがある。なお、半透過型液晶ディスプレイや反射型液晶ディスプレイを実現する場合には、画素電極の一部、または、全部が、反射電極としての機能を有するようにすればよい。例えば、画素電極の一部、または、全部が、アルミニウム、銀、などを有するようにすればよい。さらに、その場合、反射電極の下に、ＳＲＡＭなどの記憶回路を設けることも可能である。これにより、さらに、消費電力を低減することができる。 An example of a display device using an EL element is an EL display. As an example of a display device using an electron-emitting device, there is a field emission display (FED), a SED type flat display (SED: Surface-conduction Electron-emitter Display), or the like. As an example of a display device using a liquid crystal element, there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like. An example of a display device using an electronic ink element or an electrophoretic element is electronic paper. Note that in the case of realizing a transflective liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrode may have a function as a reflective electrode. For example, part or all of the pixel electrode may have aluminum, silver, or the like. Further, in that case, a memory circuit such as an SRAM can be provided under the reflective electrode. Thereby, power consumption can be further reduced.
　なお、表示装置７００における表示方式は、プログレッシブ方式やインターレース方式等を用いることができる。また、カラー表示する際に画素で制御する色要素としては、ＲＧＢ（Ｒは赤、Ｇは緑、Ｂは青を表す）の三色に限定されない。例えば、Ｒの画素とＧの画素とＢの画素とＷ（白）の画素の四画素から構成されてもよい。または、ペンタイル配列のように、ＲＧＢのうちの２色分で一つの色要素を構成し、色要素によって、異なる２色を選択して構成してもよい。またはＲＧＢに、イエロー、シアン、マゼンタ等を一色以上追加してもよい。なお、色要素のドット毎にその表示領域の大きさが異なっていてもよい。ただし、開示する発明はカラー表示の表示装置に限定されるものではなく、モノクロ表示の表示装置に適用することもできる。 Note that as a display method in the display device 700, a progressive method, an interlace method, or the like can be used. Further, the color elements controlled by the pixels when performing color display are not limited to three colors of RGB (R represents red, G represents green, and B represents blue). For example, it may be composed of four pixels: an R pixel, a G pixel, a B pixel, and a W (white) pixel. Alternatively, as in a pen tile arrangement, one color element may be configured by two colors of RGB, and two different colors may be selected and configured depending on the color element. Alternatively, one or more colors such as yellow, cyan, and magenta may be added to RGB. The size of the display area may be different for each dot of the color element. Note that the disclosed invention is not limited to a display device for color display, and can be applied to a display device for monochrome display.
　また、バックライト（有機ＥＬ素子、無機ＥＬ素子、ＬＥＤ、蛍光灯など）に白色発光（Ｗ）を用いて表示装置をフルカラー表示させるために、着色層（カラーフィルタともいう。）を用いてもよい。着色層は、例えば、レッド（Ｒ）、グリーン（Ｇ）、ブルー（Ｂ）、イエロー（Ｙ）などを適宜組み合わせて用いることができる。着色層を用いることで、着色層を用いない場合と比べて色の再現性を高くすることができる。このとき、着色層を有する領域と、着色層を有さない領域と、を配置することによって、着色層を有さない領域における白色光を直接表示に利用しても構わない。一部に着色層を有さない領域を配置することで、明るい表示の際に、着色層による輝度の低下を少なくでき、消費電力を２割から３割程度低減できる場合がある。ただし、有機ＥＬ素子や無機ＥＬ素子などの自発光素子を用いてフルカラー表示する場合、Ｒ、Ｇ、Ｂ、Ｙ、Ｗを、それぞれの発光色を有する素子から発光させても構わない。自発光素子を用いることで、着色層を用いた場合よりも、さらに消費電力を低減できる場合がある。 In addition, a colored layer (also referred to as a color filter) may be used in order to display white light (W) in a backlight (an organic EL element, an inorganic EL element, an LED, a fluorescent lamp, or the like) and display a full color display device. Good. For example, red (R), green (G), blue (B), yellow (Y), and the like can be used in appropriate combination for the colored layer. By using the colored layer, the color reproducibility can be increased as compared with the case where the colored layer is not used. At this time, white light in a region having no colored layer may be directly used for display by arranging a region having a colored layer and a region having no colored layer. By disposing a region that does not have a colored layer in part, a decrease in luminance due to the colored layer can be reduced during bright display, and power consumption can be reduced by about 20% to 30%. However, when a full color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, R, G, B, Y, and W may be emitted from elements having respective emission colors. By using a self-luminous element, power consumption may be further reduced as compared with the case where a colored layer is used.
　また、カラー化方式としては、上述の白色発光からの発光の一部をカラーフィルタを通すことで赤色、緑色、青色に変換する方式（カラーフィルタ方式）の他、赤色、緑色、青色の発光をそれぞれ用いる方式（３色方式）、または青色発光からの発光の一部を赤色や緑色に変換する方式（色変換方式、量子ドット方式）を適用してもよい。 In addition, as a colorization method, in addition to a method (color filter method) in which part of the light emission from the white light emission described above is converted into red, green, and blue through a color filter, red, green, and blue light emission is performed. A method of using each (three-color method) or a method of converting a part of light emission from blue light emission into red or green (color conversion method, quantum dot method) may be applied.
　本実施の形態においては、表示素子として液晶素子及びＥＬ素子を用いる構成について、図３６乃至図３８を用いて説明する。なお、図３６及び図３７は、図３５に示す一点鎖線Ｑ−Ｒにおける断面図であり、表示素子として液晶素子を用いた構成である。また、図３８は、図３５に示す一点鎖線Ｑ−Ｒにおける断面図であり、表示素子としてＥＬ素子を用いた構成である。 In this embodiment mode, a structure in which a liquid crystal element and an EL element are used as display elements will be described with reference to FIGS. 36 and FIG. 37 are cross-sectional views taken along one-dot chain line QR shown in FIG. 35, in which a liquid crystal element is used as a display element. FIG. 38 is a cross-sectional view taken along one-dot chain line QR shown in FIG. 35 and has a configuration using an EL element as a display element.
　まず、図３６乃至図３８に示す共通部分について最初に説明し、次に異なる部分について以下説明する。 First, common parts shown in FIGS. 36 to 38 will be described first, and then different parts will be described below.
［４−１．表示装置の共通部分に関する説明］
　図３６乃至図３８に示す表示装置７００は、引き回し配線部７１１と、画素部７０２と、ソースドライバ回路部７０４と、ＦＰＣ端子部７０８と、を有する。また、引き回し配線部７１１は、信号線７１０を有する。また、画素部７０２は、トランジスタ７５０及び容量素子７９０を有する。また、ソースドライバ回路部７０４は、トランジスタ７５２を有する。 [4-1. Explanation regarding common parts of display device]
A display device 700 illustrated in FIGS. 36 to 38 includes a lead wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. Further, the lead wiring portion 711 includes a signal line 710. In addition, the pixel portion 702 includes a transistor 750 and a capacitor 790. In addition, the source driver circuit portion 704 includes a transistor 752.
　トランジスタ７５０及びトランジスタ７５２は、先に示すトランジスタ１００Ｂと同様の構成である。なお、トランジスタ７５０及びトランジスタ７５２の構成については、先の実施の形態に示す、その他のトランジスタを用いてもよい。 The transistor 750 and the transistor 752 have the same structure as the transistor 100B described above. Note that as the structures of the transistor 750 and the transistor 752, other transistors described in the above embodiment may be used.
　本実施の形態で用いるトランジスタは、高純度化し、酸素欠損の形成を抑制した酸化物半導体膜を有する。該トランジスタは、オフ電流を低くすることができる。よって、画像信号等の電気信号の保持時間を長くすることができ、電源オン状態では書き込み間隔も長く設定できる。よって、リフレッシュ動作の頻度を少なくすることができるため、消費電力を抑制する効果を奏する。 The transistor used in this embodiment includes an oxide semiconductor film which is highly purified and suppresses formation of oxygen vacancies. The transistor can have low off-state current. Therefore, the holding time of an electric signal such as an image signal can be increased, and the writing interval can be set longer in the power-on state. Therefore, since the frequency of the refresh operation can be reduced, there is an effect of suppressing power consumption.
　また、本実施の形態で用いるトランジスタは、比較的高い電界効果移動度が得られるため、高速駆動が可能である。例えば、このような高速駆動が可能なトランジスタを液晶表示装置に用いることで、画素部のスイッチングトランジスタと、駆動回路部に使用するドライバトランジスタを同一基板上に形成することができる。すなわち、別途駆動回路として、シリコンウェハ等により形成された半導体装置を用いる必要がないため、半導体装置の部品点数を削減することができる。また、画素部においても、高速駆動が可能なトランジスタを用いることで、高画質な画像を提供することができる。 The transistor used in this embodiment can be driven at high speed because relatively high field-effect mobility can be obtained. For example, by using such a transistor that can be driven at high speed in a liquid crystal display device, the switching transistor in the pixel portion and the driver transistor used in the driver circuit portion can be formed over the same substrate. That is, since it is not necessary to use a semiconductor device formed of a silicon wafer or the like as a separate drive circuit, the number of parts of the semiconductor device can be reduced. In the pixel portion, a high-quality image can be provided by using a transistor that can be driven at high speed.
　容量素子７９０は、トランジスタ７５０が有する第１のゲート電極と機能する導電膜と同一の導電膜を加工する工程を経て形成される下部電極と、トランジスタ７５０が有するソース電極及びドレイン電極として機能する導電膜と同一の導電膜を加工する工程を経て形成される上部電極と、を有する。また、下部電極と上部電極との間には、トランジスタ７５０が有する第１のゲート絶縁膜として機能する絶縁膜と同一の絶縁膜を形成する工程を経て形成される絶縁膜と、トランジスタ７５０の保護絶縁膜として機能する絶縁膜と同一の絶縁膜を形成する工程を経て形成される絶縁膜とが設けられる。すなわち、容量素子７９０は、一対の電極間に誘電体膜として機能する絶縁膜が挟持された積層型の構造である。 The capacitor 790 includes a lower electrode formed through a step of processing the same conductive film as the conductive film that functions as the first gate electrode included in the transistor 750, and a conductive function that functions as a source electrode and a drain electrode included in the transistor 750. And an upper electrode formed through a process of processing the same conductive film as the film. Further, between the lower electrode and the upper electrode, an insulating film formed through a process of forming the same insulating film as the first gate insulating film of the transistor 750 and protection of the transistor 750 An insulating film formed through a step of forming the same insulating film as the insulating film functioning as the insulating film is provided. That is, the capacitor 790 has a stacked structure in which an insulating film functioning as a dielectric film is sandwiched between a pair of electrodes.
　また、図３６乃至図３８において、トランジスタ７５０、トランジスタ７５２、及び容量素子７９０上に平坦化絶縁膜７７０が設けられている。 36 to 38, a planarization insulating film 770 is provided over the transistor 750, the transistor 752, and the capacitor 790.
　また、図３６乃至図３８においては、画素部７０２が有するトランジスタ７５０と、ソースドライバ回路部７０４が有するトランジスタ７５２と、を同じ構造のトランジスタを用いる構成について例示したが、これに限定されない。例えば、画素部７０２と、ソースドライバ回路部７０４とは、異なるトランジスタを用いてもよい。具体的には、画素部７０２にトップゲート型のトランジスタを用い、ソースドライバ回路部７０４にボトムゲート型のトランジスタを用いる構成、あるいは画素部７０２にボトムゲート型のトランジスタを用い、ソースドライバ回路部７０４にトップゲート型のトランジスタを用いる構成などが挙げられる。なお、上記のソースドライバ回路部７０４を、ゲートドライバ回路部と読み替えてもよい。 36 to 38 illustrate the structure in which the transistor 750 included in the pixel portion 702 and the transistor 752 included in the source driver circuit portion 704 are formed using transistors having the same structure; however, the present invention is not limited to this. For example, the pixel portion 702 and the source driver circuit portion 704 may use different transistors. Specifically, a top-gate transistor is used for the pixel portion 702 and a bottom-gate transistor is used for the source driver circuit portion 704, or a bottom-gate transistor is used for the pixel portion 702, and the source driver circuit portion 704 is used. In addition, a configuration using a top gate type transistor can be given. Note that the source driver circuit portion 704 may be replaced with a gate driver circuit portion.
　また、信号線７１０は、トランジスタ７５０、７５２のソース電極及びドレイン電極として機能する導電膜と同じ工程を経て形成される。信号線７１０として、例えば、銅元素を含む材料を用いた場合、配線抵抗に起因する信号遅延等が少なく、大画面での表示が可能となる。 Further, the signal line 710 is formed through the same process as the conductive film functioning as the source electrode and the drain electrode of the transistors 750 and 752. For example, when a material containing a copper element is used as the signal line 710, signal delay due to wiring resistance is small and display on a large screen is possible.
　また、ＦＰＣ端子部７０８は、接続電極７６０、異方性導電膜７８０、及びＦＰＣ７１６を有する。なお、接続電極７６０は、トランジスタ７５０、７５２のソース電極及びドレイン電極として機能する導電膜と同じ工程を経て形成される。また、接続電極７６０は、ＦＰＣ７１６が有する端子と異方性導電膜７８０を介して、電気的に接続される。 The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. Note that the connection electrode 760 is formed through the same process as the conductive film functioning as the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is electrically connected to a terminal included in the FPC 716 through an anisotropic conductive film 780.
　また、第１の基板７０１及び第２の基板７０５としては、例えばガラス基板を用いることができる。また、第１の基板７０１及び第２の基板７０５として、可撓性を有する基板を用いてもよい。該可撓性を有する基板としては、例えばプラスチック基板等が挙げられる。 Further, as the first substrate 701 and the second substrate 705, for example, glass substrates can be used. Alternatively, a flexible substrate may be used as the first substrate 701 and the second substrate 705. Examples of the flexible substrate include a plastic substrate.
　また、第１の基板７０１と第２の基板７０５の間には、構造体７７８が設けられる。構造体７７８は、絶縁膜を選択的にエッチングすることで得られる柱状のスペーサであり、第１の基板７０１と第２の基板７０５の間の距離（セルギャップ）を制御するために設けられる。なお、構造体７７８として、球状のスペーサを用いていても良い。 In addition, a structure body 778 is provided between the first substrate 701 and the second substrate 705. The structure body 778 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Note that a spherical spacer may be used as the structure body 778.
　また、第２の基板７０５側には、ブラックマトリクスとして機能する遮光膜７３８と、カラーフィルタとして機能する着色膜７３６と、遮光膜７３８及び着色膜７３６に接する絶縁膜７３４が設けられる。 Further, on the second substrate 705 side, a light shielding film 738 functioning as a black matrix, a colored film 736 functioning as a color filter, and an insulating film 734 in contact with the light shielding film 738 and the colored film 736 are provided.
［４−２．液晶素子を用いる表示装置の構成例］
　図３６に示す表示装置７００は、液晶素子７７５を有する。液晶素子７７５は、導電膜７７２、導電膜７７４、及び液晶層７７６を有する。導電膜７７４は、第２の基板７０５側に設けられ、対向電極としての機能を有する。図３６に示す表示装置７００は、導電膜７７２と導電膜７７４に印加される電圧によって、液晶層７７６の配向状態が変わることによって光の透過、非透過が制御され画像を表示することができる。 [4-2. Configuration example of display device using liquid crystal element]
A display device 700 illustrated in FIG. 36 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is provided on the second substrate 705 side and functions as a counter electrode. A display device 700 illustrated in FIG. 36 can display an image by controlling transmission and non-transmission of light by changing the alignment state of the liquid crystal layer 776 depending on voltages applied to the conductive films 772 and 774.
　また、導電膜７７２は、トランジスタ７５０が有するソース電極及びドレイン電極として機能する導電膜と電気的に接続される。導電膜７７２は、平坦化絶縁膜７７０上に形成され画素電極、すなわら表示素子の一方の電極として機能する。 The conductive film 772 is electrically connected to a conductive film functioning as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is formed over the planarization insulating film 770 and functions as one electrode of the pixel electrode or the display element.
　導電膜７７２としては、可視光において透光性のある導電膜、または可視光において反射性のある導電膜を用いることができる。可視光において透光性のある導電膜としては、例えば、インジウム（Ｉｎ）、亜鉛（Ｚｎ）、錫（Ｓｎ）の中から選ばれた一種を含む材料を用いるとよい。可視光において反射性のある導電膜としては、例えば、アルミニウム、または銀を含む材料を用いるとよい。 As the conductive film 772, a conductive film that is transparent to visible light or a conductive film that is reflective to visible light can be used. As the conductive film that transmits visible light, for example, a material containing one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film having reflectivity in visible light, for example, a material containing aluminum or silver is preferably used.
　導電膜７７２に可視光において反射性のある導電膜を用いる場合、表示装置７００は、反射型の液晶表示装置となる。また、導電膜７７２に可視光において透光性のある導電膜を用いる場合、表示装置７００は、透過型の液晶表示装置となる。 In the case where a conductive film that reflects visible light is used for the conductive film 772, the display device 700 is a reflective liquid crystal display device. In the case where a conductive film that transmits visible light is used for the conductive film 772, the display device 700 is a transmissive liquid crystal display device.
　また、導電膜７７２上の構成を変えることで、液晶素子の駆動方式を変えることができる。この場合の一例を図３７に示す。また、図３７に示す表示装置７００は、液晶素子の駆動方式として横電界方式（例えば、ＦＦＳモード）を用いる構成の一例である。図３７に示す構成の場合、導電膜７７２上に絶縁膜７７３が設けられ、絶縁膜７７３上に導電膜７７４が設けられる。この場合、導電膜７７４は、共通電極（コモン電極ともいう）としての機能を有し、絶縁膜７７３を介して、導電膜７７２と導電膜７７４との間に生じる電界によって、液晶層７７６の配向状態を制御することができる。 Further, the driving method of the liquid crystal element can be changed by changing the structure over the conductive film 772. An example of this case is shown in FIG. A display device 700 illustrated in FIG. 37 is an example of a configuration using a horizontal electric field method (eg, an FFS mode) as a driving method of a liquid crystal element. In the case of the structure illustrated in FIG. 37, the insulating film 773 is provided over the conductive film 772, and the conductive film 774 is provided over the insulating film 773. In this case, the conductive film 774 functions as a common electrode (also referred to as a common electrode), and the alignment of the liquid crystal layer 776 is generated by an electric field generated between the conductive film 772 and the conductive film 774 through the insulating film 773. The state can be controlled.
　また、図３６及び図３７において図示しないが、導電膜７７２または導電膜７７４のいずれか一方または双方に、液晶層７７６と接する側に、それぞれ配向膜を設ける構成としてもよい。また、図３６及び図３７において図示しないが、偏光部材、位相差部材、反射防止部材などの光学部材（光学基板）などは適宜設けてもよい。例えば、偏光基板及び位相差基板による円偏光を用いてもよい。また、光源としてバックライト、サイドライトなどを用いてもよい。 Although not illustrated in FIGS. 36 and 37, an alignment film may be provided on one or both of the conductive film 772 and the conductive film 774 on the side in contact with the liquid crystal layer 776. Although not shown in FIGS. 36 and 37, an optical member (optical substrate) such as a polarizing member, a retardation member, or an antireflection member may be provided as appropriate. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a sidelight, or the like may be used as the light source.
　表示素子として液晶素子を用いる場合、サーモトロピック液晶、低分子液晶、高分子液晶、高分子分散型液晶、強誘電性液晶、反強誘電性液晶等を用いることができる。これらの液晶材料は、条件により、コレステリック相、スメクチック相、キュービック相、カイラルネマチック相、等方相等を示す。 When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like depending on conditions.
　また、横電界方式を採用する場合、配向膜を用いないブルー相を示す液晶を用いてもよい。ブルー相は液晶相の一つであり、コレステリック液晶を昇温していくと、コレステリック相から等方相へ転移する直前に発現する相である。ブルー相は狭い温度範囲でしか発現しないため、温度範囲を改善するために数重量％以上のカイラル剤を混合させた液晶組成物を液晶層に用いる。ブルー相を示す液晶とカイラル剤をを含む液晶組成物は、応答速度が短く、光学的等方性であるため配向処理が不要である。また配向膜を設けなくてもよいのでラビング処理も不要となるため、ラビング処理によって引き起こされる静電破壊を防止することができ、作製工程中の液晶表示装置の不良や破損を軽減することができる、また、ブルー相を示す液晶材料は、視野角依存性が小さい。 In addition, when the horizontal electric field method is adopted, a liquid crystal exhibiting a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of the cholesteric liquid crystal is increased, the blue phase appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with several percent by weight or more of a chiral agent is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed and is optically isotropic, so that alignment treatment is unnecessary. Further, since it is not necessary to provide an alignment film, a rubbing process is not required, so that electrostatic breakdown caused by the rubbing process can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. A liquid crystal material exhibiting a blue phase has a small viewing angle dependency.
　また、表示素子として液晶素子を用いる場合、ＴＮ（Ｔｗｉｓｔｅｄ　Ｎｅｍａｔｉｃ）モード、ＩＰＳ（Ｉｎ−Ｐｌａｎｅ−Ｓｗｉｔｃｈｉｎｇ）モード、ＦＦＳ（Ｆｒｉｎｇｅ　Ｆｉｅｌｄ　Ｓｗｉｔｃｈｉｎｇ）モード、ＡＳＭ（Ａｘｉａｌｌｙ　Ｓｙｍｍｅｔｒｉｃ　ａｌｉｇｎｅｄ　Ｍｉｃｒｏ−ｃｅｌｌ）モード、ＯＣＢ（Ｏｐｔｉｃａｌ　Ｃｏｍｐｅｎｓａｔｅｄ　Ｂｉｒｅｆｒｉｎｇｅｎｃｅ）モード、ＦＬＣ（Ｆｅｒｒｏｅｌｅｃｔｒｉｃ　Ｌｉｑｕｉｄ　Ｃｒｙｓｔａｌ）モード、ＡＦＬＣ（ＡｎｔｉＦｅｒｒｏｅｌｅｃｔｒｉｃ　Ｌｉｑｕｉｄ　Ｃｒｙｓｔａｌ）モードなどを用いることができる。 In addition, when a liquid crystal element is used as a display element, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axial Symmetrical Aligned MicroOcell) mode. A Compensated Birefringence mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (Antiferroelectric Liquid Crystal) mode, and the like can be used.
　また、ノーマリーブラック型の液晶表示装置、例えば垂直配向（ＶＡ）モードを採用した透過型の液晶表示装置としてもよい。垂直配向モードとしては、いくつか挙げられるが、例えば、ＭＶＡ（Ｍｕｌｔｉ−Ｄｏｍａｉｎ　Ｖｅｒｔｉｃａｌ　Ａｌｉｇｎｍｅｎｔ）モード、ＰＶＡ（Ｐａｔｔｅｒｎｅｄ　Ｖｅｒｔｉｃａｌ　Ａｌｉｇｎｍｅｎｔ）モード、ＡＳＶモードなどを用いることができる。 Alternatively, a normally black liquid crystal display device such as a transmissive liquid crystal display device employing a vertical alignment (VA) mode may be used. There are several examples of the vertical alignment mode. For example, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV mode, and the like can be used.
［４−３．発光素子を用いる表示装置］
　図３８に示す表示装置７００は、発光素子７８２を有する。発光素子７８２は、導電膜７７２、ＥＬ層７８６、及び導電膜７８８を有する。図３８に示す表示装置７００は、発光素子７８２が有するＥＬ層７８６が発光することによって、画像を表示することができる。なお、ＥＬ層７８６は、有機化合物、または量子ドットなどの無機化合物を有する。 [4-3. Display device using light emitting element]
A display device 700 illustrated in FIG. 38 includes a light-emitting element 782. The light-emitting element 782 includes a conductive film 772, an EL layer 786, and a conductive film 788. The display device 700 illustrated in FIG. 38 can display an image when the EL layer 786 included in the light-emitting element 782 emits light. Note that the EL layer 786 includes an organic compound or an inorganic compound such as a quantum dot.
　有機化合物に用いることのできる材料としては、蛍光性材料または燐光性材料などが挙げられる。また、量子ドットに用いることのできる材料としては、コロイド状量子ドット材料、合金型量子ドット材料、コア・シェル型量子ドット材料、コア型量子ドット材料、などが挙げられる。また、１２族と１６族、１３族と１５族、または１４族と１６族の元素グループを含む材料を用いてもよい。または、カドミウム（Ｃｄ）、セレン（Ｓｅ）、亜鉛（Ｚｎ）、硫黄（Ｓ）、リン（Ｐ）、インジウム（Ｉｎ）、テルル（Ｔｅ）、鉛（Ｐｂ）、ガリウム（Ｇａ）、ヒ素（Ａｓ）、アルミニウム（Ａｌ）、等の元素を有する量子ドット材料を用いてもよい。 Examples of materials that can be used for the organic compound include fluorescent materials and phosphorescent materials. Examples of materials that can be used for the quantum dots include colloidal quantum dot materials, alloy type quantum dot materials, core / shell type quantum dot materials, and core type quantum dot materials. Alternatively, a material including an element group of Group 12 and Group 16, Group 13 and Group 15, or Group 14 and Group 16 may be used. Alternatively, cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As ), A quantum dot material having an element such as aluminum (Al) may be used.
　また、上述の有機化合物、及び無機化合物としては、例えば、蒸着法（真空蒸着法を含む）、液滴吐出法（インクジェット法ともいう）、塗布法、グラビア印刷法等の方法を用いて形成することができる。また、ＥＬ層７８６としては、低分子材料、中分子材料（オリゴマー、デンドリマーを含む）、または高分子材料を含んでも良い。 As the above-described organic compound and inorganic compound, for example, a deposition method (including a vacuum deposition method), a droplet discharge method (also referred to as an inkjet method), a coating method, a gravure printing method, or the like is used. be able to. Further, the EL layer 786 may include a low molecular material, a medium molecular material (including an oligomer and a dendrimer), or a high molecular material.
　ここで、液滴吐出法を用いてＥＬ層７８６を形成する方法について、図３９を用いて説明する。図３９（Ａ）乃至図３９（Ｄ）は、ＥＬ層７８６の作製方法を説明する断面図である。 Here, a method for forming the EL layer 786 using a droplet discharge method will be described with reference to FIGS. FIG. 39A to FIG. 39D are cross-sectional views illustrating a method for manufacturing the EL layer 786.
　まず、平坦化絶縁膜７７０上に導電膜７７２が形成され、導電膜７７２の一部を覆うように絶縁膜７３０が形成される（図３９（Ａ）参照）。 First, a conductive film 772 is formed over the planarization insulating film 770, and an insulating film 730 is formed so as to cover part of the conductive film 772 (see FIG. 39A).
　次に、絶縁膜７３０の開口である導電膜７７２の露出部に、液滴吐出装置７８３より液滴７８４を吐出し、組成物を含む層７８５を形成する。液滴７８４は、溶媒を含む組成物であり、導電膜７７２上に付着する（図３９（Ｂ）参照）。 Next, a droplet 784 is discharged from a droplet discharge device 783 to an exposed portion of the conductive film 772 which is an opening of the insulating film 730, so that a layer 785 containing a composition is formed. The droplet 784 is a composition including a solvent and is attached to the conductive film 772 (see FIG. 39B).
　なお、液滴７８４を吐出する工程を減圧下で行ってもよい。 Note that the step of discharging the droplet 784 may be performed under reduced pressure.
　次に、組成物を含む層７８５より溶媒を除去し、固化することによってＥＬ層７８６を形成する（図３９（Ｃ）参照）。 Next, an EL layer 786 is formed by removing the solvent from the layer 785 containing the composition and solidifying the layer (see FIG. 39C).
　なお、溶媒の除去方法としては、乾燥工程または加熱工程を行えばよい。 In addition, what is necessary is just to perform a drying process or a heating process as a removal method of a solvent.
　次に、ＥＬ層７８６上に導電膜７８８を形成し、発光素子７８２を形成する（図３９（Ｄ）参照）。 Next, a conductive film 788 is formed over the EL layer 786, so that the light-emitting element 782 is formed (see FIG. 39D).
　このようにＥＬ層７８６を液滴吐出法で行うと、選択的に組成物を吐出することができるため、材料のロスを削減することができる。また、形状を加工するためのリソグラフィ工程なども必要ないために工程も簡略化することができ、低コスト化が達成できる。 When the EL layer 786 is thus subjected to the droplet discharge method, the composition can be selectively discharged, so that material loss can be reduced. In addition, since a lithography process or the like for processing the shape is not necessary, the process can be simplified and cost reduction can be achieved.
　なお、上記説明した液滴吐出法とは、組成物の吐出口を有するノズル、あるいは１つ又は複数のノズルを有するヘッド等の液滴を吐出する手段を有するものの総称とする。 The droplet discharge method described above is a general term for a device having means for discharging droplets such as a nozzle having a composition discharge port or a head having one or a plurality of nozzles.
　次に、液滴吐出法に用いる液滴吐出装置について、図４０を用いて説明する。図４０は、液滴吐出装置１４００を説明する概念図である。 Next, a droplet discharge apparatus used for the droplet discharge method will be described with reference to FIG. FIG. 40 is a conceptual diagram for explaining the droplet discharge device 1400.
　液滴吐出装置１４００は、液滴吐出手段１４０３を有する。また、液滴吐出手段１４０３は、ヘッド１４０５と、ヘッド１４１２とを有する。 The droplet discharge device 1400 has droplet discharge means 1403. The droplet discharge unit 1403 includes a head 1405 and a head 1412.
　ヘッド１４０５、及びヘッド１４１２は制御手段１４０７に接続され、それがコンピュータ１４１０で制御することにより予めプログラミングされたパターンに描画することができる。 The head 1405 and the head 1412 are connected to the control means 1407, and can be drawn in a pre-programmed pattern by being controlled by the computer 1410.
　また、描画するタイミングとしては、例えば、基板１４０２上に形成されたマーカー１４１１を基準に行えば良い。あるいは、基板１４０２の外縁を基準にして基準点を確定させても良い。ここでは、マーカー１４１１を撮像手段１４０４で検出し、画像処理手段１４０９にてデジタル信号に変換したものをコンピュータ１４１０で認識して制御信号を発生させて制御手段１４０７に送る。 Further, the drawing timing may be performed with reference to the marker 1411 formed on the substrate 1402, for example. Alternatively, the reference point may be determined based on the outer edge of the substrate 1402. Here, the marker 1411 is detected by the image pickup means 1404, the digital signal converted by the image processing means 1409 is recognized by the computer 1410, a control signal is generated and sent to the control means 1407.
　撮像手段１４０４としては、電荷結合素子（ＣＣＤ）や相補型金属酸化物半導体（ＣＭＯＳ）を利用したイメージセンサなどを用いることができる。なお、基板１４０２上に形成されるべきパターンの情報は記憶媒体１４０８に格納されたものであり、この情報を基にして制御手段１４０７に制御信号を送り、液滴吐出手段１４０３の個々のヘッド１４０５、ヘッド１４１２を個別に制御することができる。吐出する材料は、材料供給源１４１３、材料供給源１４１４より配管を通してヘッド１４０５、ヘッド１４１２にそれぞれ供給される。 As the imaging means 1404, an image sensor using a charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS) can be used. Information on the pattern to be formed on the substrate 1402 is stored in the storage medium 1408. Based on this information, a control signal is sent to the control means 1407, and the individual heads 1405 of the droplet discharge means 1403 are sent. The heads 1412 can be individually controlled. The material to be discharged is supplied from the material supply source 1413 and the material supply source 1414 to the head 1405 and the head 1412 through piping.
　ヘッド１４０５の内部は、点線１４０６が示すように液状の材料を充填する空間と、吐出口であるノズルを有する構造となっている。図示しないが、ヘッド１４１２もヘッド１４０５と同様な内部構造を有する。ヘッド１４０５とヘッド１４１２のノズルを異なるサイズで設けると、異なる材料を異なる幅で同時に描画することができる。一つのヘッドで、複数種の発光材料などをそれぞれ吐出し、描画することができ、広領域に描画する場合は、スループットを向上させるため複数のノズルより同材料を同時に吐出し、描画することができる。大型基板を用いる場合、ヘッド１４０５、ヘッド１４１２は基板上を、図４０中に示すＸ、Ｙ、Ｚの矢印の方向に自在に走査し、描画する領域を自由に設定することができ、同じパターンを一枚の基板に複数描画することができる。 The interior of the head 1405 has a structure having a space filled with a liquid material as indicated by a dotted line 1406 and a nozzle that is a discharge port. Although not shown, the head 1412 has the same internal structure as the head 1405. When the nozzles of the head 1405 and the head 1412 are provided in different sizes, different materials can be drawn simultaneously with different widths. A single head can discharge and draw multiple types of light emitting materials, and when drawing over a wide area, the same material can be simultaneously discharged and drawn from multiple nozzles to improve throughput. it can. In the case of using a large substrate, the head 1405 and the head 1412 can freely scan on the substrate in the directions of arrows X, Y, and Z shown in FIG. Can be drawn on a single substrate.
　また、組成物を吐出する工程は、減圧下で行ってもよい。吐出時に基板を加熱しておいてもよい。組成物を吐出後、乾燥と焼成の一方又は両方の工程を行う。乾燥と焼成の工程は、両工程とも加熱処理の工程であるが、その目的、温度と時間が異なるものである。乾燥の工程、焼成の工程は、常圧下又は減圧下で、レーザ光の照射や瞬間熱アニール、加熱炉などにより行う。なお、この加熱処理を行うタイミング、加熱処理の回数は特に限定されない。乾燥と焼成の工程を良好に行うためには、そのときの温度は、基板の材質及び組成物の性質に依存する。 Further, the step of discharging the composition may be performed under reduced pressure. The substrate may be heated at the time of discharge. After discharging the composition, one or both steps of drying and baking are performed. The drying and firing steps are both heat treatment steps, but their purpose, temperature and time are different. The drying process and the firing process are performed under normal pressure or reduced pressure by laser light irradiation, rapid thermal annealing, a heating furnace, or the like. Note that the timing of performing this heat treatment and the number of heat treatments are not particularly limited. In order to satisfactorily perform the drying and firing steps, the temperature at that time depends on the material of the substrate and the properties of the composition.
　以上のように、液滴吐出装置を用いてＥＬ層７８６を作製することができる。 As described above, the EL layer 786 can be manufactured using a droplet discharge device.
　再び、図３８に示す表示装置７００の説明に戻る。 Returning again to the description of the display device 700 shown in FIG.
　また、図３８に示す表示装置７００には、平坦化絶縁膜７７０及び導電膜７７２上に絶縁膜７３０が設けられる。絶縁膜７３０は、導電膜７７２の一部を覆う。なお、発光素子７８２はトップエミッション構造である。したがって、導電膜７８８は透光性を有し、ＥＬ層７８６が発する光を透過する。なお、本実施の形態においては、トップエミッション構造について、例示するが、これに限定されない。例えば、導電膜７７２側に光を射出するボトムエミッション構造や、導電膜７７２及び導電膜７８８の双方に光を射出するデュアルエミッション構造にも適用することができる。 38, an insulating film 730 is provided over the planarization insulating film 770 and the conductive film 772. In the display device 700 illustrated in FIG. The insulating film 730 covers part of the conductive film 772. Note that the light-emitting element 782 has a top emission structure. Therefore, the conductive film 788 has a light-transmitting property and transmits light emitted from the EL layer 786. In the present embodiment, the top emission structure is illustrated, but is not limited thereto. For example, a bottom emission structure in which light is emitted to the conductive film 772 side or a dual emission structure in which light is emitted to both the conductive film 772 and the conductive film 788 can be used.
　また、発光素子７８２と重なる位置に、着色膜７３６が設けられ、絶縁膜７３０と重なる位置、引き回し配線部７１１、及びソースドライバ回路部７０４に遮光膜７３８が設けられている。また、着色膜７３６及び遮光膜７３８は、絶縁膜７３４で覆われている。また、発光素子７８２と絶縁膜７３４の間は封止膜７３２で充填されている。なお、図３８に示す表示装置７００においては、着色膜７３６を設ける構成について例示したが、これに限定されない。例えば、ＥＬ層７８６を塗り分けにより形成する場合においては、着色膜７３６を設けない構成としてもよい。 Further, a coloring film 736 is provided at a position overlapping with the light emitting element 782, and a light shielding film 738 is provided at a position overlapping with the insulating film 730, the lead wiring portion 711, and the source driver circuit portion 704. Further, the coloring film 736 and the light shielding film 738 are covered with an insulating film 734. A space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. Note that in the display device 700 illustrated in FIG. 38, the structure in which the colored film 736 is provided is illustrated, but the present invention is not limited to this. For example, in the case where the EL layer 786 is formed by separate coating, the coloring film 736 may not be provided.
［４−４．表示装置に入出力装置を設ける構成例］
　また、図３７及び図３８に示す表示装置７００に入出力装置を設けてもよい。当該入出力装置としては、例えば、タッチパネル等が挙げられる。 [4-4. Configuration example in which input / output device is provided in display device]
In addition, an input / output device may be provided in the display device 700 illustrated in FIGS. Examples of the input / output device include a touch panel.
　図３７に示す表示装置７００にタッチパネル７９１を設ける構成を図４１に、図３８に示す表示装置７００にタッチパネル７９１を設ける構成を図４２に、それぞれ示す。 37 shows a configuration in which the touch panel 791 is provided in the display device 700 shown in FIG. 37, and FIG. 42 shows a configuration in which the touch panel 791 is provided in the display device 700 shown in FIG.
　図４１は図３７に示す表示装置７００にタッチパネル７９１を設ける構成の断面図であり、図４２は図３８に示す表示装置７００にタッチパネル７９１を設ける構成の断面図である。 41 is a cross-sectional view of a configuration in which the touch panel 791 is provided on the display device 700 shown in FIG. 37, and FIG. 42 is a cross-sectional view of a configuration in which the touch panel 791 is provided on the display device 700 shown in FIG.
　まず、図４１及び図４２に示すタッチパネル７９１について、以下説明を行う。 First, the touch panel 791 shown in FIGS. 41 and 42 will be described below.
　図４１及び図４２に示すタッチパネル７９１は、基板７０５と着色膜７３６との間に設けられる、所謂インセル型のタッチパネルである。タッチパネル７９１は、遮光膜７３８、及び着色膜７３６を形成する前に、基板７０５側に形成すればよい。 A touch panel 791 shown in FIGS. 41 and 42 is a so-called in-cell type touch panel provided between the substrate 705 and the colored film 736. The touch panel 791 may be formed on the substrate 705 side before the light shielding film 738 and the coloring film 736 are formed.
　なお、タッチパネル７９１は、遮光膜７３８と、絶縁膜７９２と、電極７９３と、電極７９４と、絶縁膜７９５と、電極７９６と、絶縁膜７９７と、を有する。例えば、指やスタイラスなどの被検知体が近接することで、電極７９３と、電極７９４との相互容量の変化を検知することができる。 Note that the touch panel 791 includes a light-blocking film 738, an insulating film 792, an electrode 793, an electrode 794, an insulating film 795, an electrode 796, and an insulating film 797. For example, a change in mutual capacitance between the electrode 793 and the electrode 794 can be detected when a detection target such as a finger or a stylus comes close.
　また、図４１及び図４２に示すトランジスタ７５０の上方においては、電極７９３と、電極７９４との交差部を明示している。電極７９６は、絶縁膜７９５に設けられた開口部を介して、電極７９４を挟む２つの電極７９３と電気的に接続されている。なお、図４１及び図４２においては、電極７９６が設けられる領域を画素部７０２に設ける構成を例示したが、これに限定されず、例えば、ソースドライバ回路部７０４に形成してもよい。 Further, above the transistor 750 shown in FIG. 41 and FIG. 42, the intersection of the electrode 793 and the electrode 794 is clearly shown. The electrode 796 is electrically connected to two electrodes 793 sandwiching the electrode 794 through an opening provided in the insulating film 795. 41 and FIG. 42 exemplify the configuration in which the region where the electrode 796 is provided is provided in the pixel portion 702, but the present invention is not limited to this. For example, the region may be formed in the source driver circuit portion 704.
　電極７９３及び電極７９４は、遮光膜７３８と重なる領域に設けられる。また、図４１に示すように、電極７９３は、発光素子７８２と重ならないように設けられると好ましい。また、図４２に示すように、電極７９３は、液晶素子７７５と重ならないように設けられると好ましい。別言すると、電極７９３は、発光素子７８２及び液晶素子７７５と重なる領域に開口部を有する。すなわち、電極７９３はメッシュ形状を有する。このような構成とすることで、電極７９３は、発光素子７８２が射出する光を遮らない構成とすることができる。または、電極７９３は、液晶素子７７５を透過する光を遮らない構成とすることができる。したがって、タッチパネル７９１を配置することによる輝度の低下が極めて少ないため、視認性が高く、且つ消費電力が低減された表示装置を実現できる。なお、電極７９４も同様の構成とすればよい。 The electrode 793 and the electrode 794 are provided in a region overlapping with the light shielding film 738. As shown in FIG. 41, the electrode 793 is preferably provided so as not to overlap with the light-emitting element 782. As shown in FIG. 42, the electrode 793 is preferably provided so as not to overlap with the liquid crystal element 775. In other words, the electrode 793 has an opening in a region overlapping with the light-emitting element 782 and the liquid crystal element 775. That is, the electrode 793 has a mesh shape. With such a structure, the electrode 793 can be configured not to block light emitted from the light-emitting element 782. Alternatively, the electrode 793 can have a structure that does not block light transmitted through the liquid crystal element 775. Therefore, since the reduction in luminance due to the arrangement of the touch panel 791 is extremely small, a display device with high visibility and low power consumption can be realized. Note that the electrode 794 may have a similar structure.
　また、電極７９３及び電極７９４が発光素子７８２と重ならないため、電極７９３及び電極７９４には、可視光の透過率が低い金属材料を用いることができる。または、電極７９３及び電極７９４が液晶素子７７５と重ならないため、電極７９３及び電極７９４には、可視光の透過率が低い金属材料を用いることができる。 In addition, since the electrode 793 and the electrode 794 do not overlap with the light-emitting element 782, a metal material with low visible light transmittance can be used for the electrode 793 and the electrode 794. Alternatively, since the electrode 793 and the electrode 794 do not overlap with the liquid crystal element 775, a metal material with low visible light transmittance can be used for the electrode 793 and the electrode 794.
　そのため、可視光の透過率が高い酸化物材料を用いた電極と比較して、電極７９３及び電極７９４の抵抗を低くすることが可能となり、タッチパネルのセンサ感度を向上させることができる。 Therefore, the resistance of the electrode 793 and the electrode 794 can be reduced as compared with an electrode using an oxide material having a high visible light transmittance, and the sensor sensitivity of the touch panel can be improved.
　例えば、電極７９３、７９４、７９６には、導電性のナノワイヤを用いてもよい。当該ナノワイヤは、直径の平均値が１ｎｍ以上１００ｎｍ以下、好ましくは５ｎｍ以上５０ｎｍ以下、より好ましくは５ｎｍ以上２５ｎｍ以下の大きさとすればよい。また、上記ナノワイヤとしては、Ａｇナノワイヤ、Ｃｕナノワイヤ、またはＡｌナノワイヤ等の金属ナノワイヤ、あるいは、カーボンナノチューブなどを用いればよい。例えば、電極６６４、６６５、６６７のいずれか一つあるいは全部にＡｇナノワイヤを用いる場合、可視光における光透過率を８９％以上、シート抵抗値を４０Ω／□以上１００Ω／□以下とすることができる。 For example, conductive nanowires may be used for the electrodes 793, 794, and 796. The nanowire may have an average diameter of 1 nm to 100 nm, preferably 5 nm to 50 nm, more preferably 5 nm to 25 nm. Moreover, as said nanowire, metal nanowires, such as Ag nanowire, Cu nanowire, or Al nanowire, or a carbon nanotube etc. may be used. For example, when an Ag nanowire is used for any one or all of the electrodes 664, 665, and 667, the light transmittance in visible light can be 89% or more, and the sheet resistance value can be 40Ω / □ or more and 100Ω / □ or less. .
　また、図４１及び図４２においては、インセル型のタッチパネルの構成について例示したが、これに限定されない。例えば、表示装置７００上に形成する、所謂オンセル型のタッチパネルや、表示装置７００に貼り合わせて用いる、所謂アウトセル型のタッチパネルとしてもよい。 41 and 42 illustrate the configuration of the in-cell type touch panel, but the present invention is not limited to this. For example, a so-called on-cell touch panel formed over the display device 700 or a so-called out-cell touch panel used by being attached to the display device 700 may be used.
　このように、本発明の一態様の表示装置は、様々な形態のタッチパネルと組み合わせて用いることができる。 As described above, the display device of one embodiment of the present invention can be used in combination with various forms of touch panels.
　本実施の形態は、少なくともその一部を本明細書中に記載する他の実施の形態と適宜組み合わせて実施することができる。 Note that at least part of this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate.
（実施の形態５）
　本実施の形態では、本発明の一態様の半導体装置を有する表示装置について、図４３を用いて説明を行う。 (Embodiment 5)
In this embodiment, a display device including the semiconductor device of one embodiment of the present invention will be described with reference to FIGS.
［５．表示装置の回路構成］
　図４３（Ａ）に示す表示装置は、表示素子の画素を有する領域（以下、画素部５０２という）と、画素部５０２の外側に配置され、画素を駆動するための回路を有する回路部（以下、駆動回路部５０４という）と、素子の保護機能を有する回路（以下、保護回路５０６という）と、端子部５０７と、を有する。なお、保護回路５０６は、設けない構成としてもよい。 [5. Circuit configuration of display device]
A display device illustrated in FIG. 43A includes a region having a pixel of a display element (hereinafter referred to as a pixel portion 502) and a circuit portion (hereinafter referred to as a pixel portion 502) which is disposed outside the pixel portion 502 and has a circuit for driving the pixel. , A driver circuit portion 504), a circuit having a function of protecting an element (hereinafter referred to as a protection circuit 506), and a terminal portion 507. Note that the protection circuit 506 may be omitted.
　駆動回路部５０４の一部、または全部は、画素部５０２と同一基板上に形成されていることが望ましい。これにより、部品数や端子数を減らすことが出来る。駆動回路部５０４の一部、または全部が、画素部５０２と同一基板上に形成されていない場合には、駆動回路部５０４の一部、または全部は、ＣＯＧやＴＡＢ（Ｔａｐｅ　Ａｕｔｏｍａｔｅｄ　Ｂｏｎｄｉｎｇ）によって、実装することができる。 It is desirable that part or all of the drive circuit portion 504 is formed on the same substrate as the pixel portion 502. Thereby, the number of parts and the number of terminals can be reduced. When part or all of the driver circuit portion 504 is not formed over the same substrate as the pixel portion 502, part or all of the driver circuit portion 504 is formed by COG or TAB (Tape Automated Bonding). Can be implemented.
　画素部５０２は、Ｘ行（Ｘは２以上の自然数）Ｙ列（Ｙは２以上の自然数）に配置された複数の表示素子を駆動するための回路（以下、画素回路５０１という）を有し、駆動回路部５０４は、画素を選択する信号（走査信号）を出力する回路（以下、ゲートドライバ５０４ａという）、画素の表示素子を駆動するための信号（データ信号）を供給するための回路（以下、ソースドライバ５０４ｂ）などの駆動回路を有する。 The pixel portion 502 includes a circuit (hereinafter referred to as a pixel circuit 501) for driving a plurality of display elements arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The driver circuit portion 504 outputs a signal for selecting a pixel (scanning signal) (hereinafter referred to as a gate driver 504a) and a circuit for supplying a signal (data signal) for driving a display element of the pixel (a data signal). Hereinafter, it has a drive circuit such as a source driver 504b).
　ゲートドライバ５０４ａは、シフトレジスタ等を有する。ゲートドライバ５０４ａは、端子部５０７を介して、シフトレジスタを駆動するための信号が入力され、信号を出力する。例えば、ゲートドライバ５０４ａは、スタートパルス信号、クロック信号等が入力され、パルス信号を出力する。ゲートドライバ５０４ａは、走査信号が与えられる配線（以下、走査線ＧＬ＿１乃至ＧＬ＿Ｘという）の電位を制御する機能を有する。なお、ゲートドライバ５０４ａを複数設け、複数のゲートドライバ５０４ａにより、走査線ＧＬ＿１乃至ＧＬ＿Ｘを分割して制御してもよい。または、ゲートドライバ５０４ａは、初期化信号を供給することができる機能を有する。ただし、これに限定されず、ゲートドライバ５０４ａは、別の信号を供給することも可能である。 The gate driver 504a has a shift register and the like. The gate driver 504a receives a signal for driving the shift register via the terminal portion 507, and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, and the like and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of a wiring to which a scan signal is supplied (hereinafter referred to as scan lines GL_1 to GL_X). Note that a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of supplying an initialization signal. However, the present invention is not limited to this, and the gate driver 504a can supply another signal.
　ソースドライバ５０４ｂは、シフトレジスタ等を有する。ソースドライバ５０４ｂは、端子部５０７を介して、シフトレジスタを駆動するための信号の他、データ信号の元となる信号（画像信号）が入力される。ソースドライバ５０４ｂは、画像信号を元に画素回路５０１に書き込むデータ信号を生成する機能を有する。また、ソースドライバ５０４ｂは、スタートパルス、クロック信号等が入力されて得られるパルス信号に従って、データ信号の出力を制御する機能を有する。また、ソースドライバ５０４ｂは、データ信号が与えられる配線（以下、データ線ＤＬ＿１乃至ＤＬ＿Ｙという）の電位を制御する機能を有する。または、ソースドライバ５０４ｂは、初期化信号を供給することができる機能を有する。ただし、これに限定されず、ソースドライバ５０４ｂは、別の信号を供給することも可能である。 The source driver 504b has a shift register and the like. In addition to a signal for driving the shift register, the source driver 504b receives a signal (image signal) as a source of a data signal through the terminal portion 507. The source driver 504b has a function of generating a data signal to be written in the pixel circuit 501 based on the image signal. In addition, the source driver 504b has a function of controlling output of a data signal in accordance with a pulse signal obtained by inputting a start pulse, a clock signal, or the like. The source driver 504b has a function of controlling the potential of a wiring to which a data signal is supplied (hereinafter referred to as data lines DL_1 to DL_Y). Alternatively, the source driver 504b has a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b can supply another signal.
　ソースドライバ５０４ｂは、例えば複数のアナログスイッチなどを用いて構成される。ソースドライバ５０４ｂは、複数のアナログスイッチを順次オン状態にすることにより、画像信号を時分割した信号をデータ信号として出力できる。また、シフトレジスタなどを用いてソースドライバ５０４ｂを構成してもよい。 The source driver 504b is configured using a plurality of analog switches, for example. The source driver 504b can output a signal obtained by time-dividing the image signal as a data signal by sequentially turning on the plurality of analog switches. Further, the source driver 504b may be configured using a shift register or the like.
　複数の画素回路５０１のそれぞれは、走査信号が与えられる複数の走査線ＧＬの一つを介してパルス信号が入力され、データ信号が与えられる複数のデータ線ＤＬの一つを介してデータ信号が入力される。また、複数の画素回路５０１のそれぞれは、ゲートドライバ５０４ａによりデータ信号のデータの書き込み及び保持が制御される。例えば、ｍ行ｎ列目の画素回路５０１は、走査線ＧＬ＿ｍ（ｍはＸ以下の自然数）を介してゲートドライバ５０４ａからパルス信号が入力され、走査線ＧＬ＿ｍの電位に応じてデータ線ＤＬ＿ｎ（ｎはＹ以下の自然数）を介してソースドライバ５０４ｂからデータ信号が入力される。 Each of the plurality of pixel circuits 501 receives a pulse signal through one of the plurality of scanning lines GL to which the scanning signal is applied, and receives the data signal through one of the plurality of data lines DL to which the data signal is applied. Entered. In each of the plurality of pixel circuits 501, writing and holding of data signals are controlled by the gate driver 504a. For example, the pixel circuit 501 in the m-th row and the n-th column receives a pulse signal from the gate driver 504a through the scanning line GL_m (m is a natural number equal to or less than X), and the data line DL_n (n Is a natural number less than or equal to Y), a data signal is input from the source driver 504b.
　図４３（Ａ）に示す保護回路５０６は、例えば、ゲートドライバ５０４ａと画素回路５０１の間の配線である走査線ＧＬに接続される。または、保護回路５０６は、ソースドライバ５０４ｂと画素回路５０１の間の配線であるデータ線ＤＬに接続される。または、保護回路５０６は、ゲートドライバ５０４ａと端子部５０７との間の配線に接続することができる。または、保護回路５０６は、ソースドライバ５０４ｂと端子部５０７との間の配線に接続することができる。なお、端子部５０７は、外部の回路から表示装置に電源及び制御信号、及び画像信号を入力するための端子が設けられた部分をいう。 43A is connected to, for example, the scanning line GL that is a wiring between the gate driver 504a and the pixel circuit 501. The protection circuit 506 illustrated in FIG. Alternatively, the protection circuit 506 is connected to a data line DL that is a wiring between the source driver 504 b and the pixel circuit 501. Alternatively, the protection circuit 506 can be connected to a wiring between the gate driver 504 a and the terminal portion 507. Alternatively, the protection circuit 506 can be connected to a wiring between the source driver 504 b and the terminal portion 507. Note that the terminal portion 507 is a portion where a terminal for inputting a power supply, a control signal, and an image signal from an external circuit to the display device is provided.
　保護回路５０６は、自身が接続する配線に一定の範囲外の電位が与えられたときに、該配線と別の配線とを導通状態にする回路である。 The protection circuit 506 is a circuit that brings the wiring and another wiring into a conductive state when a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected.
　図４３（Ａ）に示すように、画素部５０２と駆動回路部５０４にそれぞれ保護回路５０６を設けることにより、ＥＳＤ（Ｅｌｅｃｔｒｏ　Ｓｔａｔｉｃ　Ｄｉｓｃｈａｒｇｅ：静電気放電）などにより発生する過電流に対する表示装置の耐性を高めることができる。ただし、保護回路５０６の構成はこれに限定されず、例えば、ゲートドライバ５０４ａに保護回路５０６を接続した構成、またはソースドライバ５０４ｂに保護回路５０６を接続した構成とすることもできる。あるいは、端子部５０７に保護回路５０６を接続した構成とすることもできる。 As shown in FIG. 43A, by providing a protection circuit 506 in each of the pixel portion 502 and the driver circuit portion 504, resistance of the display device to an overcurrent generated by ESD (Electro Static Discharge) is increased. be able to. However, the configuration of the protection circuit 506 is not limited thereto, and for example, a configuration in which the protection circuit 506 is connected to the gate driver 504a or a configuration in which the protection circuit 506 is connected to the source driver 504b may be employed. Alternatively, the protection circuit 506 may be connected to the terminal portion 507.
　また、図４３（Ａ）においては、ゲートドライバ５０４ａとソースドライバ５０４ｂによって駆動回路部５０４を形成している例を示しているが、この構成に限定されない。例えば、ゲートドライバ５０４ａのみを形成し、別途用意されたソースドライバ回路が形成された基板（例えば、単結晶半導体膜、多結晶半導体膜で形成された駆動回路基板）を実装する構成としても良い。 FIG. 43A illustrates an example in which the driver circuit portion 504 is formed using the gate driver 504a and the source driver 504b; however, the present invention is not limited to this structure. For example, only the gate driver 504a may be formed, and a substrate on which a separately prepared source driver circuit is formed (for example, a driver circuit substrate formed using a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted.
　また、図４３（Ａ）に示す複数の画素回路５０１は、例えば、図４３（Ｂ）に示す構成とすることができる。 In addition, the plurality of pixel circuits 501 illustrated in FIG. 43A can have a structure illustrated in FIG. 43B, for example.
　図４３（Ｂ）に示す画素回路５０１は、液晶素子５７０と、トランジスタ５５０と、容量素子５６０と、を有する。トランジスタ５５０に先の実施の形態に示すトランジスタを適用することができる。 43B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The pixel circuit 501 illustrated in FIG. The transistor described in the above embodiment can be applied to the transistor 550.
　液晶素子５７０の一対の電極の一方の電位は、画素回路５０１の仕様に応じて適宜設定される。液晶素子５７０は、書き込まれるデータにより配向状態が設定される。なお、複数の画素回路５０１のそれぞれが有する液晶素子５７０の一対の電極の一方に共通の電位（コモン電位）を与えてもよい。また、各行の画素回路５０１の液晶素子５７０の一対の電極の一方に異なる電位を与えてもよい。 One potential of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specification of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by written data. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Further, a different potential may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 in each row.
　例えば、液晶素子５７０を備える表示装置の駆動方法としては、ＴＮモード、ＳＴＮモード、ＶＡモード、ＡＳＭ（Ａｘｉａｌｌｙ　Ｓｙｍｍｅｔｒｉｃ　Ａｌｉｇｎｅｄ　Ｍｉｃｒｏ−ｃｅｌｌ）モード、ＯＣＢ（Ｏｐｔｉｃａｌｌｙ　Ｃｏｍｐｅｎｓａｔｅｄ　Ｂｉｒｅｆｒｉｎｇｅｎｃｅ）モード、ＦＬＣ（Ｆｅｒｒｏｅｌｅｃｔｒｉｃ　Ｌｉｑｕｉｄ　Ｃｒｙｓｔａｌ）モード、ＡＦＬＣ（ＡｎｔｉＦｅｒｒｏｅｌｅｃｔｒｉｃ　Ｌｉｑｕｉｄ　Ｃｒｙｓｔａｌ）モード、ＭＶＡモード、ＰＶＡ（Ｐａｔｔｅｒｎｅｄ　Ｖｅｒｔｉｃａｌ　Ａｌｉｇｎｍｅｎｔ）モード、ＩＰＳモード、ＦＦＳモード、又はＴＢＡ（Ｔｒａｎｓｖｅｒｓｅ　Ｂｅｎｄ　Ａｌｉｇｎｍｅｎｔ）モードなどを用いてもよい。また、表示装置の駆動方法としては、上述した駆動方法の他、ＥＣＢ（Ｅｌｅｃｔｒｉｃａｌｌｙ　Ｃｏｎｔｒｏｌｌｅｄ　Ｂｉｒｅｆｒｉｎｇｅｎｃｅ）モード、ＰＤＬＣ（ＰｏｌｙｍｅｒＤｉｓｐｅｒｓｅｄ　Ｌｉｑｕｉｄ　Ｃｒｙｓｔａｌ）モード、ＰＮＬＣ（Ｐｏｌｙｍｅｒ　Ｎｅｔｗｏｒｋ　Ｌｉｑｕｉｄ　Ｃｒｙｓｔａｌ）モード、ゲストホストモードなどがある。ただし、これに限定されず、液晶素子及びその駆動方式として様々なものを用いることができる。 For example, as a driving method of a display device including the liquid crystal element 570, a TN mode, an STN mode, a VA mode, an ASM (axially aligned micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, and an FLC (Frequential) mode. AFLC (Anti Ferroelectric Liquid Crystal) mode, MVA mode, PVA (Patterned Vertical Alignment) mode, IPS mode, FFS mode, TBA (Transverse Bend Alignment) mode, etc. may be used. In addition to the above-described driving methods, there are ECB (Electrically Controlled Birefringence) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid mode), and other driving methods for the display device. However, the present invention is not limited to this, and various liquid crystal elements and driving methods thereof can be used.
　ｍ行ｎ列目の画素回路５０１において、トランジスタ５５０のソース電極またはドレイン電極の一方は、データ線ＤＬ＿ｎに電気的に接続され、他方は液晶素子５７０の一対の電極の他方に電気的に接続される。また、トランジスタ５５０のゲート電極は、走査線ＧＬ＿ｍに電気的に接続される。トランジスタ５５０は、オン状態またはオフ状態になることにより、データ信号のデータの書き込みを制御する機能を有する。 In the pixel circuit 501 in the m-th row and the n-th column, one of the source electrode and the drain electrode of the transistor 550 is electrically connected to the data line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The In addition, the gate electrode of the transistor 550 is electrically connected to the scan line GL_m. The transistor 550 has a function of controlling data writing of the data signal by being turned on or off.
　容量素子５６０の一対の電極の一方は、電位が供給される配線（以下、電位供給線ＶＬ）に電気的に接続され、他方は、液晶素子５７０の一対の電極の他方に電気的に接続される。なお、電位供給線ＶＬの電位の値は、画素回路５０１の仕様に応じて適宜設定される。容量素子５６０は、書き込まれたデータを保持する保持容量としての機能を有する。 One of the pair of electrodes of the capacitor 560 is electrically connected to a wiring to which a potential is supplied (hereinafter, potential supply line VL), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The Note that the value of the potential of the potential supply line VL is appropriately set according to the specifications of the pixel circuit 501. The capacitor 560 functions as a storage capacitor for storing written data.
　例えば、図４３（Ｂ）の画素回路５０１を有する表示装置では、例えば、図４３（Ａ）に示すゲートドライバ５０４ａにより各行の画素回路５０１を順次選択し、トランジスタ５５０をオン状態にしてデータ信号のデータを書き込む。 For example, in the display device including the pixel circuit 501 in FIG. 43B, the pixel circuits 501 in each row are sequentially selected by the gate driver 504a illustrated in FIG. Write data.
　データが書き込まれた画素回路５０１は、トランジスタ５５０がオフ状態になることで保持状態になる。これを行毎に順次行うことにより、画像を表示できる。 The pixel circuit 501 in which data is written is in a holding state when the transistor 550 is turned off. By sequentially performing this for each row, an image can be displayed.
　また、図４３（Ａ）に示す複数の画素回路５０１は、例えば、図４３（Ｃ）に示す構成とすることができる。 In addition, the plurality of pixel circuits 501 illustrated in FIG. 43A can have a structure illustrated in FIG. 43C, for example.
　また、図４３（Ｃ）に示す画素回路５０１は、トランジスタ５５２、５５４と、容量素子５６２と、発光素子５７２と、を有する。トランジスタ５５２及びトランジスタ５５４のいずれか一方または双方に先の実施の形態に示すトランジスタを適用することができる。 In addition, the pixel circuit 501 illustrated in FIG. 43C includes transistors 552 and 554, a capacitor 562, and a light-emitting element 572. The transistor described in any of the above embodiments can be applied to one or both of the transistor 552 and the transistor 554.
　トランジスタ５５２のソース電極及びドレイン電極の一方は、データ信号が与えられる配線（以下、信号線ＤＬ＿ｎという）に電気的に接続される。さらに、トランジスタ５５２のゲート電極は、ゲート信号が与えられる配線（以下、走査線ＧＬ＿ｍという）に電気的に接続される。 One of the source electrode and the drain electrode of the transistor 552 is electrically connected to a wiring to which a data signal is supplied (hereinafter referred to as a signal line DL_n). Further, the gate electrode of the transistor 552 is electrically connected to a wiring to which a gate signal is supplied (hereinafter referred to as a scanning line GL_m).
　トランジスタ５５２は、オン状態またはオフ状態になることにより、データ信号のデータの書き込みを制御する機能を有する。 The transistor 552 has a function of controlling data writing of the data signal by being turned on or off.
　容量素子５６２の一対の電極の一方は、電位が与えられる配線（以下、電位供給線ＶＬ＿ａという）に電気的に接続され、他方は、トランジスタ５５２のソース電極及びドレイン電極の他方に電気的に接続される。 One of the pair of electrodes of the capacitor 562 is electrically connected to a wiring to which a potential is applied (hereinafter referred to as a potential supply line VL_a), and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 552. Is done.
　容量素子５６２は、書き込まれたデータを保持する保持容量としての機能を有する。 The capacitor element 562 functions as a storage capacitor for storing written data.
　トランジスタ５５４のソース電極及びドレイン電極の一方は、電位供給線ＶＬ＿ａに電気的に接続される。さらに、トランジスタ５５４のゲート電極は、トランジスタ５５２のソース電極及びドレイン電極の他方に電気的に接続される。 One of the source electrode and the drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. Further, the gate electrode of the transistor 554 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.
　発光素子５７２のアノード及びカソードの一方は、電位供給線ＶＬ＿ｂに電気的に接続され、他方は、トランジスタ５５４のソース電極及びドレイン電極の他方に電気的に接続される。 One of an anode and a cathode of the light-emitting element 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554.
　発光素子５７２としては、例えば有機エレクトロルミネセンス素子（有機ＥＬ素子ともいう）などを用いることができる。ただし、発光素子５７２としては、これに限定されず、無機材料からなる無機ＥＬ素子を用いても良い。 As the light-emitting element 572, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, the light-emitting element 572 is not limited thereto, and an inorganic EL element made of an inorganic material may be used.
　なお、電位供給線ＶＬ＿ａ及び電位供給線ＶＬ＿ｂの一方には、高電源電位ＶＤＤが与えられ、他方には、低電源電位ＶＳＳが与えられる。 Note that one of the potential supply line VL_a and the potential supply line VL_b is supplied with the high power supply potential VDD, and the other is supplied with the low power supply potential VSS.
　図４３（Ｃ）の画素回路５０１を有する表示装置では、例えば、図４３（Ａ）に示すゲートドライバ５０４ａにより各行の画素回路５０１を順次選択し、トランジスタ５５２をオン状態にしてデータ信号のデータを書き込む。 In the display device including the pixel circuit 501 in FIG. 43C, for example, the pixel circuits 501 in each row are sequentially selected by the gate driver 504a illustrated in FIG. Write.
　データが書き込まれた画素回路５０１は、トランジスタ５５２がオフ状態になることで保持状態になる。さらに、書き込まれたデータ信号の電位に応じてトランジスタ５５４のソース電極とドレイン電極の間に流れる電流量が制御され、発光素子５７２は、流れる電流量に応じた輝度で発光する。これを行毎に順次行うことにより、画像を表示できる。 The pixel circuit 501 in which data is written is in a holding state when the transistor 552 is turned off. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled in accordance with the potential of the written data signal, and the light-emitting element 572 emits light with luminance corresponding to the amount of flowing current. By sequentially performing this for each row, an image can be displayed.
　本実施の形態は、少なくともその一部を本明細書中に記載する他の実施の形態と適宜組み合わせて実施することができる。 Note that at least part of this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate.
（実施の形態６）
　本実施の形態では、上述の実施の形態で説明したトランジスタの適用可能な回路構成の一例について、図４４乃至図４７を用いて説明する。 (Embodiment 6)
In this embodiment, an example of a circuit configuration to which the transistor described in any of the above embodiments can be applied will be described with reference to FIGS.
［６．インバータ回路の構成例］
　図４４（Ａ）には、駆動回路が有するシフトレジスタやバッファ等に適用することができるインバータの回路図を示す。インバータ８００は、入力端子ＩＮに与える信号の論理を反転した信号を出力端子ＯＵＴに出力する。インバータ８００は、複数のＯＳトランジスタを有する。信号ＳＢＧは、ＯＳトランジスタの電気特性を切り替えることができる信号である。 [6. Inverter circuit configuration example]
FIG. 44A is a circuit diagram of an inverter that can be applied to a shift register, a buffer, or the like included in a driver circuit. The inverter 800 outputs a signal obtained by inverting the logic of the signal applied to the input terminal IN to the output terminal OUT. The inverter 800 includes a plurality of OS transistors. The signal SBG is a signal that can switch the electrical characteristics of the OS transistor.
　図４４（Ｂ）は、インバータ８００の一例である。インバータ８００は、ＯＳトランジスタ８１０、およびＯＳトランジスタ８２０を有する。インバータ８００は、ｎチャネル型トランジスタのみで作製することができるため、ＣＭＯＳ（Ｃｏｍｐｌｅｍｅｎｔａｒｙ　Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）でインバータ（ＣＭＯＳインバータ）を作製する場合と比較して、低コストで作製することが可能である。 FIG. 44B is an example of the inverter 800. The inverter 800 includes an OS transistor 810 and an OS transistor 820. Since the inverter 800 can be manufactured using only an n-channel transistor, it can be manufactured at a lower cost than a case where an inverter (CMOS inverter) is manufactured using a CMOS (Complementary Metal Oxide Semiconductor).
　なお、ＯＳトランジスタを有するインバータ８００は、Ｓｉトランジスタで構成されるＣＭＯＳ上に配置することもできる。インバータ８００は、ＣＭＯＳの回路に重ねて配置できるため、インバータ８００を追加する分の回路面積の増加を抑えることができる。 Note that the inverter 800 having an OS transistor can also be arranged on a CMOS composed of Si transistors. Since the inverter 800 can be arranged so as to overlap with a CMOS circuit, an increase in circuit area corresponding to the addition of the inverter 800 can be suppressed.
　ＯＳトランジスタ８１０、８２０は、フロントゲートとして機能する第１ゲートと、バックゲートとして機能する第２ゲートと、ソースまたはドレインの一方として機能する第１端子と、ソースまたはドレインの他方として機能する第２端子とを有する。 The OS transistors 810 and 820 include a first gate that functions as a front gate, a second gate that functions as a back gate, a first terminal that functions as one of a source and a drain, and a second gate that functions as the other of a source and a drain. Terminal.
　ＯＳトランジスタ８１０の第１ゲートは、第２端子に接続される。ＯＳトランジスタ８１０の第２ゲートは、信号ＳＢＧを供給する配線に接続される。ＯＳトランジスタ８１０の第１端子は、電圧ＶＤＤを与える配線に接続される。ＯＳトランジスタ８１０の第２端子は、出力端子ＯＵＴに接続される。 The first gate of the OS transistor 810 is connected to the second terminal. A second gate of the OS transistor 810 is connected to a wiring for supplying the signal SBG . A first terminal of the OS transistor 810 is connected to a wiring that supplies the voltage VDD. The second terminal of the OS transistor 810 is connected to the output terminal OUT.
　ＯＳトランジスタ８２０の第１ゲートは、入力端子ＩＮに接続される。ＯＳトランジスタ８２０の第２ゲートは、入力端子ＩＮに接続される。ＯＳトランジスタ８２０の第１端子は、出力端子ＯＵＴに接続される。ＯＳトランジスタ８２０の第２端子は、電圧ＶＳＳを与える配線に接続される。 The first gate of the OS transistor 820 is connected to the input terminal IN. A second gate of the OS transistor 820 is connected to the input terminal IN. The first terminal of the OS transistor 820 is connected to the output terminal OUT. A second terminal of the OS transistor 820 is connected to a wiring that supplies the voltage VSS.
　図４４（Ｃ）は、インバータ８００の動作を説明するためのタイミングチャートである。図４４（Ｃ）のタイミングチャートでは、入力端子ＩＮの信号波形、出力端子ＯＵＴの信号波形、信号ＳＢＧの信号波形、およびＯＳトランジスタ８１０のしきい値電圧の変化について示している。 FIG. 44C is a timing chart for explaining the operation of the inverter 800. The timing chart in FIG. 44C shows changes in the signal waveform of the input terminal IN, the signal waveform of the output terminal OUT, the signal waveform of the signal SBG, and the threshold voltage of the OS transistor 810.
　信号ＳＢＧをＯＳトランジスタ８１０の第２ゲートに与えることで、ＯＳトランジスタ８１０のしきい値電圧を制御することができる。 By supplying the signal SBG to the second gate of the OS transistor 810, the threshold voltage of the OS transistor 810 can be controlled.
　信号ＳＢＧは、しきい値電圧をマイナスシフトさせるための電圧ＶＢＧ＿Ａ、しきい値電圧をプラスシフトさせるための電圧ＶＢＧ＿Ｂを有する。第２ゲートに電圧ＶＢＧ＿Ａを与えることで、ＯＳトランジスタ８１０はしきい値電圧ＶＴＨ＿Ａにマイナスシフトさせることができる。また、第２ゲートに電圧ＶＢＧ＿Ｂを与えることで、ＯＳトランジスタ８１０は、しきい値電圧ＶＴＨ＿Ｂにプラスシフトさせることができる。 Signal S BG has a voltage V BG_B for shifted in the positive voltage V BG_A, the threshold voltage for negative shift the threshold voltage. By applying the voltage V BG_A to the second gate, the OS transistor 810 can be negatively shifted to the threshold voltage V TH_A . Further, by applying the voltage VBG_B to the second gate, the OS transistor 810 can be positively shifted to the threshold voltage VTH_B .
　前述の説明を可視化するために、図４５（Ａ）には、トランジスタの電気特性の一つである、Ｉｄ−Ｖｇカーブを示す。 In order to visualize the above description, FIG. 45A shows an Id-Vg curve which is one of the electrical characteristics of the transistor.
　上述したＯＳトランジスタ８１０の電気特性は、第２ゲートの電圧を電圧ＶＢＧ＿Ａのように大きくすることで、図４５（Ａ）中の破線８４０で表される曲線にシフトさせることができる。また、上述したＯＳトランジスタ８１０の電気特性は、第２ゲートの電圧を電圧ＶＢＧ＿Ｂのように小さくすることで、図４５（Ａ）中の実線８４１で表される曲線にシフトさせることができる。図４５（Ａ）に示すように、ＯＳトランジスタ８１０は、信号ＳＢＧを電圧ＶＢＧ＿Ａあるいは電圧ＶＢＧ＿Ｂというように切り替えることで、しきい値電圧をプラスシフトあるいはマイナスシフトさせることができる。 The above-described electrical characteristics of the OS transistor 810 can be shifted to a curve represented by a broken line 840 in FIG. 45A by increasing the voltage of the second gate as the voltage V BG_A . The above-described electrical characteristics of the OS transistor 810 can be shifted to a curve represented by a solid line 841 in FIG. 45A by reducing the voltage of the second gate as the voltage V BG_B . As shown in FIG. 45 (A), OS transistor 810, by switching the signal S BG and so the voltage V BG_A or voltage V BG_B, can be shifted in the positive or negative shift of the threshold voltage.
　しきい値電圧をしきい値電圧ＶＴＨ＿Ｂにプラスシフトさせることで、ＯＳトランジスタ８１０は電流が流れにくい状態とすることができる。図４５（Ｂ）には、この状態を可視化して示す。 By positively shifting the threshold voltage to the threshold voltage VTH_B , the OS transistor 810 can be in a state in which current does not easily flow. FIG. 45B visualizes this state.
　図４５（Ｂ）に図示するように、ＯＳトランジスタ８１０に流れる電流ＩＢを極めて小さくすることができる。そのため、入力端子ＩＮに与える信号がハイレベルでＯＳトランジスタ８２０はオン状態（ＯＮ）のとき、出力端子ＯＵＴの電圧を急峻に下降させることができる。 As shown in FIG. 45 (B), it can be extremely small current I B flowing through the OS transistor 810. Therefore, when the signal applied to the input terminal IN is at a high level and the OS transistor 820 is in an on state (ON), the voltage at the output terminal OUT can be sharply decreased.
　図４５（Ｂ）に図示したように、ＯＳトランジスタ８１０に流れる電流が流れにくい状態とすることができるため、図４４（Ｃ）に示すタイミングチャートにおける出力端子の信号波形８３１を急峻に変化させることができる。電圧ＶＤＤを与える配線と、電圧ＶＳＳを与える配線との間に流れる貫通電流を少なくすることができるため、低消費電力での動作を行うことができる。 As shown in FIG. 45B, since the current flowing through the OS transistor 810 can be hardly flown, the signal waveform 831 at the output terminal in the timing chart shown in FIG. Can do. Since the through current flowing between the wiring for applying the voltage VDD and the wiring for supplying the voltage VSS can be reduced, an operation with low power consumption can be performed.
　また、しきい値電圧をしきい値電圧ＶＴＨ＿Ａにマイナスシフトさせることで、ＯＳトランジスタ８１０は電流が流れやすい状態とすることができる。図４５（Ｃ）には、この状態を可視化して示す。図４５（Ｃ）に図示するように、このとき流れる電流ＩＡを少なくとも電流ＩＢよりも大きくすることができる。そのため、入力端子ＩＮに与える信号がローレベルでＯＳトランジスタ８２０はオフ状態（ＯＦＦ）のとき、出力端子ＯＵＴの電圧を急峻に上昇させることができる。図４５（Ｃ）に図示したように、ＯＳトランジスタ８１０に流れる電流が流れやすい状態とすることができるため、図４４（Ｃ）に示すタイミングチャートにおける出力端子の信号波形８３２を急峻に変化させることができる。 Further , by shifting the threshold voltage to the threshold voltage VTH_A minus, the OS transistor 810 can be in a state in which current easily flows. FIG. 45C visualizes this state. As shown in FIG. 45 (C), it can be larger than at least the current I B of the current I A flowing at this time. Therefore, when the signal supplied to the input terminal IN is at a low level and the OS transistor 820 is in an off state (OFF), the voltage of the output terminal OUT can be rapidly increased. As shown in FIG. 45C, since the current flowing through the OS transistor 810 can easily flow, the signal waveform 832 at the output terminal in the timing chart shown in FIG. Can do.
　なお、信号ＳＢＧによるＯＳトランジスタ８１０のしきい値電圧の制御は、ＯＳトランジスタ８２０の状態が切り替わる以前、すなわち時刻Ｔ１やＴ２よりも前に行うことが好ましい。例えば、図４４（Ｃ）に図示するように、入力端子ＩＮに与える信号がハイレベルに切り替わる時刻Ｔ１よりも前に、しきい値電圧ＶＴＨ＿Ａから、しきい値電圧ＶＴＨ＿ＢにＯＳトランジスタ８１０のしきい値電圧を切り替えることが好ましい。また、図４４（Ｃ）に図示するように、入力端子ＩＮに与える信号がローレベルに切り替わる時刻Ｔ２よりも前に、しきい値電圧ＶＴＨ＿Ｂからしきい値電圧ＶＴＨ＿ＡにＯＳトランジスタ８１０のしきい値電圧を切り替えることが好ましい。 The control of the threshold voltage of the OS transistor 810 by the signal S BG previously the state of the OS transistor 820 is switched, i.e. it is preferably performed before a time T1 and T2. For example, as illustrated in FIG. 44C , the threshold voltage V TH_A is changed from the threshold voltage V TH_A to the threshold voltage V TH_B before the time T1 when the signal applied to the input terminal IN switches to the high level. It is preferable to switch the threshold voltage. As shown in FIG. 44C , the OS transistor 810 is switched from the threshold voltage V TH_B to the threshold voltage V TH_A before the time T2 when the signal applied to the input terminal IN is switched to the low level. It is preferable to switch the threshold voltage.
　なお、図４４（Ｃ）のタイミングチャートでは、入力端子ＩＮに与える信号に応じて信号ＳＢＧを切り替える構成を示したが、別の構成としてもよい。例えば、しきい値電圧を制御するための電圧は、フローティング状態としたＯＳトランジスタ８１０の第２ゲートに保持させる構成としてもよい。当該構成を実現可能な回路構成の一例について、図４６（Ａ）に示す。 Note that although the structure in which the signal SBG is switched in accordance with the signal applied to the input terminal IN is illustrated in the timing chart in FIG. 44C , another structure may be employed. For example, the voltage for controlling the threshold voltage may be held in the second gate of the OS transistor 810 in a floating state. An example of a circuit configuration that can realize this configuration is illustrated in FIG.
　図４６（Ａ）では、図４４（Ｂ）で示した回路構成に加えて、ＯＳトランジスタ８５０を有する。ＯＳトランジスタ８５０の第１端子は、ＯＳトランジスタ８１０の第２ゲートに接続される。またＯＳトランジスタ８５０の第２端子は、電圧ＶＢＧ＿Ｂ（あるいは電圧ＶＢＧ＿Ａ）を与える配線に接続される。ＯＳトランジスタ８５０の第１ゲートは、信号ＳＦを与える配線に接続される。ＯＳトランジスタ８５０の第２ゲートは、電圧ＶＢＧ＿Ｂ（あるいは電圧ＶＢＧ＿Ａ）を与える配線に接続される。 46A includes an OS transistor 850 in addition to the circuit configuration illustrated in FIG. The first terminal of the OS transistor 850 is connected to the second gate of the OS transistor 810. The second terminal of the OS transistor 850 is connected to a wiring for applying the voltage V BG_B (or voltage V BG_A ). The first gate of the OS transistor 850 is connected to a wiring for providing signal S F. A second gate of the OS transistor 850 is connected to a wiring that supplies the voltage V BG_B (or the voltage V BG_A ).
　図４６（Ａ）の動作について、図４６（Ｂ）のタイミングチャートを用いて説明する。 The operation in FIG. 46A will be described with reference to the timing chart in FIG.
　ＯＳトランジスタ８１０のしきい値電圧を制御するための電圧は、入力端子ＩＮに与える信号がハイレベルに切り替わる時刻Ｔ３よりも前に、ＯＳトランジスタ８１０の第２ゲートに与える構成とする。信号ＳＦをハイレベルとしてＯＳトランジスタ８５０をオン状態とし、ノードＮＢＧにしきい値電圧を制御するための電圧ＶＢＧ＿Ｂを与える。 The voltage for controlling the threshold voltage of the OS transistor 810 is applied to the second gate of the OS transistor 810 before the time T3 when the signal applied to the input terminal IN switches to the high level. The OS transistor 850 is turned on the signal S F to the high level, providing a voltage V BG_B for controlling a threshold voltage in the node N BG.
　ノードＮＢＧが電圧ＶＢＧ＿Ｂとなった後は、ＯＳトランジスタ８５０をオフ状態とする。ＯＳトランジスタ８５０は、オフ電流が極めて小さいため、オフ状態にし続けることで、一旦ノードＮＢＧに保持させたしきい値電圧ＶＢＧ＿Ｂを保持することができる。そのため、ＯＳトランジスタ８５０の第２ゲートに電圧ＶＢＧ＿Ｂを与える動作の回数が減るため、電圧ＶＢＧ＿Ｂの書き換えに要する分の消費電力を小さくすることができる。 After the node N BG becomes voltage V BG_B is turned off the OS transistor 850. Since the off-state current of the OS transistor 850 is extremely small, the threshold voltage V BG_B once held at the node N BG can be held by continuing the off state. Therefore, the number of operations for applying the voltage V BG_B to the second gate of the OS transistor 850 is reduced, so that power consumption required for rewriting the voltage V BG_B can be reduced.
　なお、図４４（Ｂ）及び図４６（Ａ）の回路構成では、ＯＳトランジスタ８１０の第２ゲートに与える電圧を外部からの制御によって与える構成について示したが、別の構成としてもよい。例えば、しきい値電圧を制御するための電圧を、入力端子ＩＮに与える信号を基に生成し、ＯＳトランジスタ８１０の第２ゲートに与える構成としてもよい。当該構成を実現可能な回路構成の一例について、図４７（Ａ）に示す。 Note that in the circuit configurations in FIGS. 44B and 46A, a configuration in which the voltage applied to the second gate of the OS transistor 810 is given by external control is shown, but another configuration may be used. For example, a voltage for controlling the threshold voltage may be generated based on a signal supplied to the input terminal IN and supplied to the second gate of the OS transistor 810. FIG. 47A illustrates an example of a circuit configuration that can realize this configuration.
　図４７（Ａ）では、図４４（Ｂ）で示した回路構成において、入力端子ＩＮとＯＳトランジスタ８１０の第２ゲートとの間にＣＭＯＳインバータ８６０を有する。ＣＭＯＳインバータ８６０の入力端子は、入力端子ＩＮに接続される。ＣＭＯＳインバータ８６０の出力端子は、ＯＳトランジスタ８１０の第２ゲートに接続される。 47A, in the circuit configuration shown in FIG. 44B, a CMOS inverter 860 is provided between the input terminal IN and the second gate of the OS transistor 810. In FIG. The input terminal of the CMOS inverter 860 is connected to the input terminal IN. The output terminal of the CMOS inverter 860 is connected to the second gate of the OS transistor 810.
　図４７（Ａ）の動作について、図４７（Ｂ）のタイミングチャートを用いて説明する。図４７（Ｂ）のタイミングチャートでは、入力端子ＩＮの信号波形、出力端子ＯＵＴの信号波形、ＣＭＯＳインバータ８６０の出力波形ＩＮ＿Ｂ、及びＯＳトランジスタ８１０のしきい値電圧の変化について示している。 The operation in FIG. 47A will be described with reference to the timing chart in FIG. The timing chart in FIG. 47B shows changes in the signal waveform of the input terminal IN, the signal waveform of the output terminal OUT, the output waveform IN_B of the CMOS inverter 860, and the threshold voltage of the OS transistor 810.
　入力端子ＩＮに与える信号の論理を反転した信号である出力波形ＩＮ＿Ｂは、ＯＳトランジスタ８１０のしきい値電圧を制御する信号とすることができる。したがって、図４５（Ａ）乃至図４５（Ｃ）で説明したように、ＯＳトランジスタ８１０のしきい値電圧を制御できる。例えば、図４７（Ｂ）における時刻Ｔ４となるとき、入力端子ＩＮに与える信号がハイレベルでＯＳトランジスタ８２０はオン状態となる。このとき、出力波形ＩＮ＿Ｂはローレベルとなる。そのため、ＯＳトランジスタ８１０は電流が流れにくい状態とすることができ、出力端子ＯＵＴの電圧の上昇を急峻に下降させることができる。 The output waveform IN_B, which is a signal obtained by inverting the logic of the signal applied to the input terminal IN, can be a signal for controlling the threshold voltage of the OS transistor 810. Therefore, as described with reference to FIGS. 45A to 45C, the threshold voltage of the OS transistor 810 can be controlled. For example, at time T4 in FIG. 47B, the signal applied to the input terminal IN is at a high level and the OS transistor 820 is turned on. At this time, the output waveform IN_B is at a low level. Therefore, the OS transistor 810 can be set in a state in which current does not easily flow, and the voltage increase at the output terminal OUT can be sharply decreased.
　また、図４７（Ｂ）における時刻Ｔ５となるとき、入力端子ＩＮに与える信号がローレベルでＯＳトランジスタ８２０はオフ状態となる。このとき、出力波形ＩＮ＿Ｂはハイレベルとなる。そのため、ＯＳトランジスタ８１０は電流が流れやすい状態とすることができ、出力端子ＯＵＴの電圧を急峻に上昇させることができる。 Further, at time T5 in FIG. 47B, the signal applied to the input terminal IN is at a low level, so that the OS transistor 820 is turned off. At this time, the output waveform IN_B is at a high level. Therefore, the OS transistor 810 can be in a state in which current easily flows, and the voltage of the output terminal OUT can be rapidly increased.
　以上説明したように本実施の形態の構成では、ＯＳトランジスタを有するインバータにおける、バックゲートの電圧を入力端子ＩＮの信号の論理にしたがって切り替える。当該構成とすることで、ＯＳトランジスタのしきい値電圧を制御することができる。入力端子ＩＮに与える信号によってＯＳトランジスタのしきい値電圧を制御することで、出力端子ＯＵＴの電圧を急峻に変化させることができる。また、電源電圧を与える配線間の貫通電流を小さくすることができる。そのため、低消費電力化を図ることができる。 As described above, in the configuration of the present embodiment, the voltage of the back gate in the inverter having the OS transistor is switched in accordance with the signal logic of the input terminal IN. With this structure, the threshold voltage of the OS transistor can be controlled. By controlling the threshold voltage of the OS transistor by a signal applied to the input terminal IN, the voltage of the output terminal OUT can be changed abruptly. In addition, the through current between the wirings supplying the power supply voltage can be reduced. Therefore, low power consumption can be achieved.
　本実施の形態は、少なくともその一部を本明細書中に記載する他の実施の形態と適宜組み合わせて実施することができる。 Note that at least part of this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate.
（実施の形態７）
　本実施の形態では、上述の実施の形態で説明した酸化物半導体を有するトランジスタ（ＯＳトランジスタ）を、複数の回路に用いる半導体装置の一例について、図４８乃至図５１を用いて説明する。 (Embodiment 7)
In this embodiment, an example of a semiconductor device in which the transistor including an oxide semiconductor (OS transistor) described in any of the above embodiments is used for a plurality of circuits will be described with reference to FIGS.
［７．半導体装置の回路構成例］
　図４８（Ａ）は、半導体装置９００のブロック図である。半導体装置９００は、電源回路９０１、回路９０２、電圧生成回路９０３、回路９０４、電圧生成回路９０５および回路９０６を有する。 [7. Example of circuit configuration of semiconductor device]
FIG. 48A is a block diagram of the semiconductor device 900. The semiconductor device 900 includes a power supply circuit 901, a circuit 902, a voltage generation circuit 903, a circuit 904, a voltage generation circuit 905, and a circuit 906.
　電源回路９０１は、基準となる電圧ＶＯＲＧを生成する回路である。電圧ＶＯＲＧは、単一の電圧ではなく、複数の電圧でもよい。電圧ＶＯＲＧは、半導体装置９００の外部から与えられる電圧Ｖ０を基に生成することができる。半導体装置９００は、外部から与えられる単一の電源電圧を基に電圧ＶＯＲＧを生成できる。そのため半導体装置９００は、外部から電源電圧を複数与えることなく動作することができる。 The power supply circuit 901 is a circuit that generates a reference voltage V ORG . The voltage V ORG may be a plurality of voltages instead of a single voltage. The voltage V ORG can be generated based on the voltage V 0 given from the outside of the semiconductor device 900. The semiconductor device 900 can generate the voltage V ORG based on a single power supply voltage given from the outside. Therefore, the semiconductor device 900 can operate without applying a plurality of power supply voltages from the outside.
　回路９０２、９０４および９０６は、異なる電源電圧で動作する回路である。例えば回路９０２の電源電圧は、電圧ＶＯＲＧと電圧ＶＳＳ（ＶＯＲＧ＞ＶＳＳ）とを基に印加される電圧である。また、例えば回路９０４の電源電圧は、電圧ＶＰＯＧと電圧ＶＳＳ（ＶＰＯＧ＞ＶＯＲＧ）とを基に印加される電圧である。また、例えば回路９０６の電源電圧は、電圧ＶＯＲＧと電圧ＶＳＳと電圧ＶＮＥＧ（ＶＯＲＧ＞ＶＳＳ＞ＶＮＥＧ）とを基に印加される電圧である。なお電圧ＶＳＳは、グラウンド電位（ＧＮＤ）と等電位とすれば、電源回路９０１で生成する電圧の種類を削減できる。 The circuits 902, 904, and 906 are circuits that operate with different power supply voltages. For example, the power supply voltage of the circuit 902 is a voltage applied based on the voltage V ORG and the voltage V SS (V ORG > V SS ). For example, the power supply voltage of the circuit 904 is a voltage applied based on the voltage V POG and the voltage V SS (V POG > V ORG ). For example, the power supply voltage of the circuit 906 is a voltage applied based on the voltage V ORG , the voltage V SS, and the voltage V NEG (V ORG > V SS > V NEG ). Note that if the voltage VSS is equal to the ground potential (GND), the types of voltages generated by the power supply circuit 901 can be reduced.
　電圧生成回路９０３は、電圧ＶＰＯＧを生成する回路である。電圧生成回路９０３は、電源回路９０１から与えられる電圧ＶＯＲＧを基に電圧ＶＰＯＧを生成できる。そのため、回路９０４を有する半導体装置９００は、外部から与えられる単一の電源電圧を基に動作することができる。 The voltage generation circuit 903 is a circuit that generates the voltage V POG . The voltage generation circuit 903 can generate the voltage V POG based on the voltage V ORG supplied from the power supply circuit 901. Therefore, the semiconductor device 900 including the circuit 904 can operate based on a single power supply voltage supplied from the outside.
　電圧生成回路９０５は、電圧ＶＮＥＧを生成する回路である。電圧生成回路９０５は、電源回路９０１から与えられる電圧ＶＯＲＧを基に電圧ＶＮＥＧを生成できる。そのため、回路９０６を有する半導体装置９００は、外部から与えられる単一の電源電圧を基に動作することができる。 The voltage generation circuit 905 is a circuit that generates a voltage V NEG . The voltage generation circuit 905 can generate the voltage V NEG based on the voltage V ORG supplied from the power supply circuit 901. Therefore, the semiconductor device 900 including the circuit 906 can operate based on a single power supply voltage given from the outside.
　図４８（Ｂ）は電圧ＶＰＯＧで動作する回路９０４の一例、図４８（Ｃ）は回路９０４を動作させるための信号の波形の一例である。 FIG. 48B illustrates an example of a circuit 904 that operates at the voltage V POG , and FIG. 48C illustrates an example of a waveform of a signal for operating the circuit 904.
　図４８（Ｂ）では、トランジスタ９１１を示している。トランジスタ９１１のゲートに与える信号は、例えば、電圧ＶＰＯＧと電圧ＶＳＳを基に生成される。当該信号は、トランジスタ９１１を導通状態とする動作時に電圧ＶＰＯＧ、非導通状態とする動作時に電圧ＶＳＳとする。電圧ＶＰＯＧは、図４８（Ｃ）に図示するように、電圧ＶＯＲＧより大きい。そのため、トランジスタ９１１は、ソース（Ｓ）とドレイン（Ｄ）との間をより確実に導通状態にできる。その結果、回路９０４は、誤動作が低減された回路とすることができる。 In FIG. 48B, the transistor 911 is illustrated. Signal applied to the gate of the transistor 911 is generated, for example, based on the voltage V POG and voltage V SS. The signal is a voltage V SS during operation of the conductive state of transistor 911 voltage V POG, during operation of the non-conductive state. The voltage V POG is larger than the voltage V ORG as illustrated in FIG. Therefore, the transistor 911 can be more reliably connected between the source (S) and the drain (D). As a result, the circuit 904 can be a circuit in which malfunctions are reduced.
　図４８（Ｄ）は電圧ＶＮＥＧで動作する回路９０６の一例、図４８（Ｅ）は回路９０６を動作させるための信号の波形の一例である。 FIG. 48D illustrates an example of a circuit 906 that operates at the voltage V NEG , and FIG. 48E illustrates an example of a waveform of a signal for operating the circuit 906.
　図４８（Ｄ）では、バックゲートを有するトランジスタ９１２を示している。トランジスタ９１２のゲートに与える信号は、例えば、電圧ＶＯＲＧと電圧ＶＳＳを基にして生成される。当該信号は、トランジスタ９１２を導通状態とする動作時に電圧ＶＯＲＧ、非導通状態とする動作時に電圧ＶＳＳを基に生成される。また、トランジスタ９１２のバックゲートに与える信号は、電圧ＶＮＥＧを基に生成される。電圧ＶＮＥＧは、図４８（Ｅ）に図示するように、電圧ＶＳＳ（ＧＮＤ）より小さい。そのため、トランジスタ９１２の閾値電圧は、プラスシフトするように制御することができる。そのため、トランジスタ９１２をより確実に非導通状態とすることができ、ソース（Ｓ）とドレイン（Ｄ）との間を流れる電流を小さくできる。その結果、回路９０６は、誤動作が低減され、且つ低消費電力化が図られた回路とすることができる。 FIG. 48D illustrates a transistor 912 having a back gate. Signal applied to the gate of the transistor 912, for example, generated based on the voltage V ORG and the voltage V SS. The signal voltage V ORG during operation of the conductive state of transistor 912, is generated based on the voltage V SS during operation of a non-conductive state. Further, a signal given to the back gate of the transistor 912 is generated based on the voltage V NEG . The voltage V NEG is smaller than the voltage V SS (GND) as illustrated in FIG. Therefore, the threshold voltage of the transistor 912 can be controlled to shift positively. Therefore, the transistor 912 can be more reliably turned off, and the current flowing between the source (S) and the drain (D) can be reduced. As a result, the circuit 906 can be a circuit in which malfunctions are reduced and power consumption is reduced.
　なお、電圧ＶＮＥＧは、トランジスタ９１２のバックゲートに直接与える構成としてもよい。あるいは、電圧ＶＯＲＧと電圧ＶＮＥＧを基に、トランジスタ９１２のゲートに与える信号を生成し、当該信号をトランジスタ９１２のバックゲートに与える構成としてもよい。 Note that the voltage V NEG may be directly applied to the back gate of the transistor 912. Alternatively, a signal to be supplied to the gate of the transistor 912 may be generated based on the voltage V ORG and the voltage V NEG and the signal may be supplied to the back gate of the transistor 912.
　また図４９（Ａ）（Ｂ）には、図４８（Ｄ）（Ｅ）の変形例を示す。 49 (A) and 49 (B) show modified examples of FIGS. 48 (D) and 48 (E).
　図４９（Ａ）に示す回路図では、電圧生成回路９０５と、回路９０６と、の間に制御回路９２１によって導通状態が制御できるトランジスタ９２２を示す。トランジスタ９２２は、ｎチャネル型のＯＳトランジスタとする。制御回路９２１が出力する制御信号ＳＢＧは、トランジスタ９２２の導通状態を制御する信号である。また回路９０６が有するトランジスタ９１２Ａ、９１２Ｂは、トランジスタ９２２と同じＯＳトランジスタである。 In the circuit diagram illustrated in FIG. 49A, a transistor 922 whose conduction state can be controlled by the control circuit 921 is illustrated between the voltage generation circuit 905 and the circuit 906. The transistor 922 is an n-channel OS transistor. Control signal S BG control circuit 921 is output a signal for controlling the conduction state of the transistor 922. In addition, transistors 912A and 912B included in the circuit 906 are OS transistors which are the same as the transistor 922.
　図４９（Ｂ）のタイミングチャートには、制御信号ＳＢＧの電位の変化を示し、トランジスタ９１２Ａ、９１２Ｂのバックゲートの電位の状態をノードＮＢＧの電位の変化で示す。制御信号ＳＢＧがハイレベルのときにトランジスタ９２２が導通状態となり、ノードＮＢＧが電圧ＶＮＥＧとなる。その後、制御信号ＳＢＧがローレベルのときにノードＮＢＧが電気的にフローティングとなる。トランジスタ９２２は、ＯＳトランジスタであるため、オフ電流が小さい。そのため、ノードＮＢＧが電気的にフローティングであっても、一旦与えた電圧ＶＮＥＧを保持することができる。 The timing chart of FIG. 49 (B), the control signal indicates a change in the potential of the S BG, transistor 912A, indicated by a change in the potential of the state nodes N BG back gate potential of 912B. Control signal S BG is transistor 922 in a conducting state at the high level, the node N BG becomes voltage V NEG. Thereafter, when the control signal SBG is at a low level, the node NBG becomes electrically floating. Since the transistor 922 is an OS transistor, the off-state current is small. Therefore, even if the node NBG is electrically floating, the voltage V NEG once applied can be held.
　また、図５０（Ａ）には、上述した電圧生成回路９０３に適用可能な回路構成の一例を示す。図５０（Ａ）に示す電圧生成回路９０３は、ダイオードＤ１乃至Ｄ５、キャパシタＣ１乃至Ｃ５、およびインバータＩＮＶを有する５段のチャージポンプである。クロック信号ＣＬＫは、キャパシタＣ１乃至Ｃ５に直接、あるいはインバータＩＮＶを介して与えられる。インバータＩＮＶの電源電圧を、電圧ＶＯＲＧと電圧ＶＳＳとを基に印加される電圧とすると、クロック信号ＣＬＫを与えることによって、電圧ＶＯＲＧの５倍の正電圧に昇圧された電圧ＶＰＯＧを得ることができる。なお、ダイオードＤ１乃至Ｄ５の順方向電圧は０Ｖとしている。また、チャージポンプの段数を変更することで、所望の電圧ＶＰＯＧを得ることができる。 FIG. 50A illustrates an example of a circuit configuration which can be applied to the voltage generation circuit 903 described above. A voltage generation circuit 903 illustrated in FIG. 50A is a five-stage charge pump including diodes D1 to D5, capacitors C1 to C5, and an inverter INV. The clock signal CLK is supplied to the capacitors C1 to C5 directly or via the inverter INV. Assuming that the power supply voltage of the inverter INV is a voltage applied based on the voltage V ORG and the voltage V SS , the voltage V POG boosted to a positive voltage five times the voltage V ORG is given by applying the clock signal CLK. Obtainable. The forward voltage of the diodes D1 to D5 is 0V. Further, by changing the number of stages of the charge pump, it is possible to obtain a desired voltage V POG.
　また、図５０（Ｂ）には、上述した電圧生成回路９０５に適用可能な回路構成の一例を示す。図５０（Ｂ）に示す電圧生成回路９０５は、ダイオードＤ１乃至Ｄ５、キャパシタＣ１乃至Ｃ５、およびインバータＩＮＶを有する４段のチャージポンプである。クロック信号ＣＬＫは、キャパシタＣ１乃至Ｃ５に直接、あるいはインバータＩＮＶを介して与えられる。インバータＩＮＶの電源電圧を、電圧ＶＯＲＧと電圧ＶＳＳとを基に印加される電圧とすると、クロック信号ＣＬＫを与えることによって、グラウンド、すなわち電圧ＶＳＳから電圧ＶＯＲＧの４倍の負電圧に降圧された電圧ＶＮＥＧを得ることができる。なお、ダイオードＤ１乃至Ｄ５の順方向電圧は０Ｖとしている。また、チャージポンプの段数を変更することで、所望の電圧ＶＮＥＧを得ることができる。 FIG. 50B illustrates an example of a circuit configuration which can be applied to the voltage generation circuit 905 described above. A voltage generation circuit 905 illustrated in FIG. 50B is a four-stage charge pump including diodes D1 to D5, capacitors C1 to C5, and an inverter INV. The clock signal CLK is supplied to the capacitors C1 to C5 directly or via the inverter INV. When the power supply voltage of the inverter INV is a voltage applied based on the voltage V ORG and the voltage V SS , by supplying the clock signal CLK, the ground, that is, the negative voltage that is four times the voltage V ORG from the voltage V SS is obtained. The stepped down voltage V NEG can be obtained. The forward voltage of the diodes D1 to D5 is 0V. Further, the desired voltage V NEG can be obtained by changing the number of stages of the charge pump.
　なお、上述した電圧生成回路９０３の回路構成は、図５０（Ａ）で示す回路図の構成に限らない。例えば、電圧生成回路９０３の変形例を図５１（Ａ）乃至図５１（Ｃ）に示す。なお、電圧生成回路９０３の変形例は、図５１（Ａ）乃至図５１（Ｃ）に示す電圧生成回路９０３Ａ乃至９０３Ｃにおいて、各配線に与える電圧を変更すること、あるいは素子の配置を変更することで実現可能である。 Note that the circuit configuration of the voltage generation circuit 903 described above is not limited to the configuration of the circuit diagram illustrated in FIG. For example, modification examples of the voltage generation circuit 903 are illustrated in FIGS. Note that a modification example of the voltage generation circuit 903 includes changing the voltage applied to each wiring or changing the arrangement of elements in the voltage generation circuits 903A to 903C illustrated in FIGS. It is feasible.
　図５１（Ａ）に示す電圧生成回路９０３Ａは、トランジスタＭ１乃至Ｍ１０、キャパシタＣ１１乃至Ｃ１４、およびインバータＩＮＶ１を有する。クロック信号ＣＬＫは、トランジスタＭ１乃至Ｍ１０のゲートに直接、あるいはインバータＩＮＶ１を介して与えられる。クロック信号ＣＬＫを与えることによって、電圧ＶＯＲＧの４倍の正電圧に昇圧された電圧ＶＰＯＧを得ることができる。なお、段数を変更することで、所望の電圧ＶＰＯＧを得ることができる。図５１（Ａ）に示す電圧生成回路９０３Ａは、トランジスタＭ１乃至Ｍ１０をＯＳトランジスタとすることでオフ電流を小さくでき、キャパシタＣ１１乃至Ｃ１４に保持した電荷の漏れを抑制できる。そのため、効率的に電圧ＶＯＲＧから電圧ＶＰＯＧへの昇圧を図ることができる。 A voltage generation circuit 903A illustrated in FIG. 51A includes transistors M1 to M10, capacitors C11 to C14, and an inverter INV1. The clock signal CLK is supplied directly to the gates of the transistors M1 to M10 or via the inverter INV1. By providing the clock signal CLK, it is possible to obtain a voltage V POG that is boosted to a positive voltage that is four times the voltage V ORG . Note that a desired voltage V POG can be obtained by changing the number of stages. The voltage generation circuit 903A illustrated in FIG. 51A can reduce off-state current by using the transistors M1 to M10 as OS transistors, and can suppress leakage of charges held in the capacitors C11 to C14. Therefore, the voltage V ORG can be efficiently boosted from the voltage V POG .
　また、図５１（Ｂ）に示す電圧生成回路９０３Ｂは、トランジスタＭ１１乃至Ｍ１４、キャパシタＣ１５、Ｃ１６、およびインバータＩＮＶ２を有する。クロック信号ＣＬＫは、トランジスタＭ１１乃至Ｍ１４のゲートに直接、あるいはインバータＩＮＶ２を介して与えられる。クロック信号ＣＬＫを与えることによって、電圧ＶＯＲＧの２倍の正電圧に昇圧された電圧ＶＰＯＧを得ることができる。図５１（Ｂ）に示す電圧生成回路９０３Ｂは、トランジスタＭ１１乃至Ｍ１４をＯＳトランジスタとすることでオフ電流を小さくでき、キャパシタＣ１５、Ｃ１６に保持した電荷の漏れを抑制できる。そのため、効率的に電圧ＶＯＲＧから電圧ＶＰＯＧへの昇圧を図ることができる。 A voltage generation circuit 903B illustrated in FIG. 51B includes transistors M11 to M14, capacitors C15 and C16, and an inverter INV2. The clock signal CLK is supplied directly to the gates of the transistors M11 to M14 or via the inverter INV2. By providing the clock signal CLK, it is possible to obtain a voltage V POG that is boosted to a positive voltage that is twice the voltage V ORG . The voltage generation circuit 903B illustrated in FIG. 51B can reduce off-state current by using the transistors M11 to M14 as OS transistors, and can suppress leakage of charges held in the capacitors C15 and C16. Therefore, the voltage V ORG can be efficiently boosted from the voltage V POG .
　また、図５１（Ｃ）に示す電圧生成回路９０３Ｃは、インダクタＩｎｄ１、トランジスタＭ１５、ダイオードＤ６、およびキャパシタＣ１７を有する。トランジスタＭ１５は、制御信号ＥＮによって、導通状態が制御される。制御信号ＥＮによって、電圧ＶＯＲＧが昇圧された電圧ＶＰＯＧを得ることができる。図５１（Ｃ）に示す電圧生成回路９０３Ｃは、インダクタＩｎｄ１を用いて電圧の昇圧を行うため、変換効率の高い電圧の昇圧を行うことができる。 A voltage generation circuit 903C illustrated in FIG. 51C includes an inductor Ind1, a transistor M15, a diode D6, and a capacitor C17. The conduction state of the transistor M15 is controlled by the control signal EN. A voltage V POG obtained by boosting the voltage V ORG can be obtained by the control signal EN. Since the voltage generation circuit 903C illustrated in FIG. 51C uses the inductor Ind1 to increase the voltage, the voltage generation circuit 903C can increase the voltage with high conversion efficiency.
　以上説明したように本実施の形態の構成では、半導体装置が有する回路に必要な電圧を内部で生成することができる。そのため半導体装置は、外部から与える電源電圧の数を削減できる。 As described above, in the configuration of this embodiment, a voltage necessary for a circuit included in the semiconductor device can be generated internally. Therefore, the semiconductor device can reduce the number of power supply voltages given from the outside.
　本実施の形態は、少なくともその一部を本明細書中に記載する他の実施の形態と適宜組み合わせて実施することができる。 Note that at least part of this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate.
（実施の形態８）
　本実施の形態では、本発明の一態様の半導体装置を有する表示モジュール及び電子機器について、図５２乃至図５５を用いて説明を行う。 (Embodiment 8)
In this embodiment, a display module and an electronic device each including the semiconductor device of one embodiment of the present invention will be described with reference to FIGS.
［８−１．表示モジュール］
　図５２に示す表示モジュール７０００は、上部カバー７００１と下部カバー７００２との間に、ＦＰＣ７００３に接続されたタッチパネル７００４、ＦＰＣ７００５に接続された表示パネル７００６、バックライト７００７、フレーム７００９、プリント基板７０１０、バッテリ７０１１を有する。 [8-1. Display module]
A display module 7000 shown in FIG. 52 includes a touch panel 7004 connected to the FPC 7003, a display panel 7006 connected to the FPC 7005, a backlight 7007, a frame 7009, a printed circuit board 7010, a battery, between an upper cover 7001 and a lower cover 7002. 7011.
　本発明の一態様の半導体装置は、例えば、表示パネル７００６に用いることができる。 The semiconductor device of one embodiment of the present invention can be used for the display panel 7006, for example.
　上部カバー７００１及び下部カバー７００２は、タッチパネル７００４及び表示パネル７００６のサイズに合わせて、形状や寸法を適宜変更することができる。 The shape and dimensions of the upper cover 7001 and the lower cover 7002 can be changed as appropriate in accordance with the sizes of the touch panel 7004 and the display panel 7006.
　タッチパネル７００４は、抵抗膜方式または静電容量方式のタッチパネルを表示パネル７００６に重畳して用いることができる。また、表示パネル７００６の対向基板（封止基板）に、タッチパネル機能を持たせるようにすることも可能である。また、表示パネル７００６の各画素内に光センサを設け、光学式のタッチパネルとすることも可能である。 As the touch panel 7004, a resistive film type or capacitive type touch panel can be used by being superimposed on the display panel 7006. In addition, the counter substrate (sealing substrate) of the display panel 7006 can have a touch panel function. In addition, an optical sensor can be provided in each pixel of the display panel 7006 to form an optical touch panel.
　バックライト７００７は、光源７００８を有する。なお、図５２において、バックライト７００７上に光源７００８を配置する構成について例示したが、これに限定さない。例えば、バックライト７００７の端部に光源７００８を配置し、さらに光拡散板を用いる構成としてもよい。なお、有機ＥＬ素子等の自発光型の発光素子を用いる場合、または反射型パネル等の場合においては、バックライト７００７を設けない構成としてもよい。 The backlight 7007 has a light source 7008. Note that although FIG. 52 illustrates the configuration in which the light source 7008 is provided over the backlight 7007, the present invention is not limited to this. For example, the light source 7008 may be disposed at the end of the backlight 7007 and a light diffusing plate may be used. Note that in the case of using a self-luminous light emitting element such as an organic EL element or in the case of a reflective panel or the like, the backlight 7007 may not be provided.
　フレーム７００９は、表示パネル７００６の保護機能の他、プリント基板７０１０の動作により発生する電磁波を遮断するための電磁シールドとしての機能を有する。またフレーム７００９は、放熱板としての機能を有していてもよい。 The frame 7009 has a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed circuit board 7010 in addition to the protective function of the display panel 7006. The frame 7009 may have a function as a heat sink.
　プリント基板７０１０は、電源回路、ビデオ信号及びクロック信号を出力するための信号処理回路を有する。電源回路に電力を供給する電源としては、外部の商用電源であっても良いし、別途設けたバッテリ７０１１による電源であってもよい。バッテリ７０１１は、商用電源を用いる場合には、省略可能である。 The printed circuit board 7010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal. The power source for supplying power to the power supply circuit may be an external commercial power source or a power source using a battery 7011 provided separately. The battery 7011 can be omitted when a commercial power source is used.
　また、表示モジュール７０００は、偏光板、位相差板、プリズムシートなどの部材を追加して設けてもよい。 Further, the display module 7000 may be additionally provided with a member such as a polarizing plate, a phase difference plate, and a prism sheet.
［８−２．電子機器１］
　次に、図５３（Ａ）乃至図５３（Ｅ）に電子機器の一例を示す。 [8-2. Electronic device 1]
Next, FIGS. 53A to 53E illustrate examples of electronic devices.
　図５３（Ａ）は、ファインダー８１００を取り付けた状態のカメラ８０００の外観を示す図である。 FIG. 53 (A) is a diagram showing the appearance of the camera 8000 with the viewfinder 8100 attached.
　カメラ８０００は、筐体８００１、表示部８００２、操作ボタン８００３、シャッターボタン８００４等を有する。またカメラ８０００には、着脱可能なレンズ８００６が取り付けられている。 The camera 8000 includes a housing 8001, a display portion 8002, operation buttons 8003, a shutter button 8004, and the like. The camera 8000 is attached with a detachable lens 8006.
　ここではカメラ８０００として、レンズ８００６を筐体８００１から取り外して交換することが可能な構成としたが、レンズ８００６と筐体が一体となっていてもよい。 Here, the camera 8000 is configured such that the lens 8006 can be removed from the housing 8001 and replaced, but the lens 8006 and the housing may be integrated.
　カメラ８０００は、シャッターボタン８００４を押すことにより、撮像することができる。また、表示部８００２はタッチパネルとしての機能を有し、表示部８００２をタッチすることにより撮像することも可能である。 The camera 8000 can take an image by pressing a shutter button 8004. In addition, the display portion 8002 has a function as a touch panel and can capture an image by touching the display portion 8002.
　カメラ８０００の筐体８００１は、電極を有するマウントを有し、ファインダー８１００のほか、ストロボ装置等を接続することができる。 The housing 8001 of the camera 8000 has a mount having electrodes, and can be connected to a stroboscope or the like in addition to the finder 8100.
　ファインダー８１００は、筐体８１０１、表示部８１０２、ボタン８１０３等を有する。 The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.
　筐体８１０１は、カメラ８０００のマウントと係合するマウントを有しており、ファインダー８１００をカメラ８０００に取り付けることができる。また当該マウントには電極を有し、当該電極を介してカメラ８０００から受信した映像等を表示部８１０２に表示させることができる。 The housing 8101 has a mount that engages with the mount of the camera 8000, and the finder 8100 can be attached to the camera 8000. In addition, the mount includes an electrode, and an image received from the camera 8000 via the electrode can be displayed on the display portion 8102.
　ボタン８１０３は、電源ボタンとしての機能を有する。ボタン８１０３により、表示部８１０２の表示のオン・オフを切り替えることができる。 The button 8103 has a function as a power button. A button 8103 can be used to switch display on the display portion 8102 on and off.
　カメラ８０００の表示部８００２、及びファインダー８１００の表示部８１０２に、本発明の一態様の表示装置を適用することができる。 The display device of one embodiment of the present invention can be applied to the display portion 8002 of the camera 8000 and the display portion 8102 of the finder 8100.
　なお、図５３（Ａ）では、カメラ８０００とファインダー８１００とを別の電子機器とし、これらを脱着可能な構成としたが、カメラ８０００の筐体８００１に、表示装置を備えるファインダーが内蔵されていてもよい。 Note that in FIG. 53A, the camera 8000 and the viewfinder 8100 are separate electronic devices and can be attached to and detached from each other. However, a finder including a display device is incorporated in the housing 8001 of the camera 8000. Also good.
　図５３（Ｂ）は、ヘッドマウントディスプレイ８２００の外観を示す図である。 FIG. 53 (B) is a diagram showing the appearance of the head mounted display 8200.
　ヘッドマウントディスプレイ８２００は、装着部８２０１、レンズ８２０２、本体８２０３、表示部８２０４、ケーブル８２０５等を有している。また装着部８２０１には、バッテリ８２０６が内蔵されている。 The head mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, a cable 8205, and the like. In addition, a battery 8206 is built in the mounting portion 8201.
　ケーブル８２０５は、バッテリ８２０６から本体８２０３に電力を供給する。本体８２０３は無線受信機等を備え、受信した画像データ等の映像情報を表示部８２０４に表示させることができる。また、本体８２０３に設けられたカメラで使用者の眼球やまぶたの動きを捉え、その情報をもとに使用者の視点の座標を算出することにより、使用者の視点を入力手段として用いることができる。 The cable 8205 supplies power from the battery 8206 to the main body 8203. The main body 8203 includes a wireless receiver and the like, and can display video information such as received image data on the display portion 8204. In addition, it is possible to use the user's viewpoint as an input unit by capturing the movement of the user's eyeball or eyelid with a camera provided in the main body 8203 and calculating the coordinates of the user's viewpoint based on the information. it can.
　また、装着部８２０１には、使用者に触れる位置に複数の電極が設けられていてもよい。本体８２０３は使用者の眼球の動きに伴って電極に流れる電流を検知することにより、使用者の視点を認識する機能を有していてもよい。また、当該電極に流れる電流を検知することにより、使用者の脈拍をモニタする機能を有していてもよい。また、装着部８２０１には、温度センサ、圧力センサ、加速度センサ等の各種センサを有していてもよく、使用者の生体情報を表示部８２０４に表示する機能を有していてもよい。また、使用者の頭部の動きなどを検出し、表示部８２０４に表示する映像をその動きに合わせて変化させてもよい。 In addition, the mounting portion 8201 may be provided with a plurality of electrodes at positions where the user touches the mounting portion 8201. The main body 8203 may have a function of recognizing the user's viewpoint by detecting a current flowing through the electrode in accordance with the movement of the user's eyeball. Moreover, you may have a function which monitors a user's pulse by detecting the electric current which flows into the said electrode. The mounting portion 8201 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display portion 8204. Further, the movement of the user's head or the like may be detected, and the video displayed on the display unit 8204 may be changed in accordance with the movement.
　表示部８２０４に、本発明の一態様の表示装置を適用することができる。 The display device of one embodiment of the present invention can be applied to the display portion 8204.
　図５３（Ｃ）（Ｄ）（Ｅ）は、ヘッドマウントディスプレイ８３００の外観を示す図である。ヘッドマウントディスプレイ８３００は、筐体８３０１と、表示部８３０２と、バンド状の固定具８３０４と、一対のレンズ８３０５と、を有する。 53C, 53D, and 53E are views showing the appearance of the head mounted display 8300. FIG. The head mounted display 8300 includes a housing 8301, a display portion 8302, a band-shaped fixture 8304, and a pair of lenses 8305.
　使用者は、レンズ８３０５を通して、表示部８３０２の表示を視認することができる。なお、表示部８３０２を湾曲して配置させると好適である。表示部８３０２を湾曲して配置することで、使用者が高い臨場感を感じることができる。なお、本実施の形態においては、表示部８３０２を１つ設ける構成について例示したが、これに限定されず、例えば、表示部８３０２を２つ設ける構成としてもよい。この場合、使用者の片方の目に１つの表示部が配置されるような構成とすると、視差を用いた３次元表示等を行うことも可能となる。 The user can visually recognize the display on the display portion 8302 through the lens 8305. Note that the display portion 8302 is preferably arranged curved. By arranging the display portion 8302 to be curved, the user can feel a high sense of realism. Note that although a structure in which one display portion 8302 is provided is described in this embodiment mode, the present invention is not limited thereto, and for example, a structure in which two display portions 8302 are provided may be employed. In this case, if one display unit is arranged in one eye of the user, three-dimensional display using parallax or the like can be performed.
　なお、表示部８３０２に、本発明の一態様の表示装置を適用することができる。本発明の一態様の半導体装置を有する表示装置は、極めて精細度が高いため、図５３（Ｅ）のようにレンズ８３０５を用いて拡大したとしても、使用者に画素が視認されることなく、より現実感の高い映像を表示することができる。 Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. Since the display device including the semiconductor device of one embodiment of the present invention has extremely high definition, the pixel is not visually recognized by the user even when the display device is enlarged using the lens 8305 as illustrated in FIG. More realistic video can be displayed.
［８−３．電子機器２］
　次に、図５３（Ａ）乃至図５３（Ｅ）に示す電子機器と、異なる電子機器の一例を図５４（Ａ）乃至図５４（Ｇ）に示す。 [8-3. Electronic device 2]
Next, examples of electronic devices that are different from the electronic devices illustrated in FIGS. 53A to 53E are illustrated in FIGS. 54A to 54G.
　図５４（Ａ）乃至図５４（Ｇ）に示す電子機器は、篋体９０００、表示部９００１、スピーカ９００３、操作キー９００５（電源スイッチ、又は操作スイッチを含む）、接続端子９００６、センサ９００７（力、変位、位置、速度、加速度、角速度、回転数、距離、光、液、磁気、温度、化学物質、音声、時間、硬度、電場、電流、電圧、電力、放射線、流量、湿度、傾度、振動、におい又は赤外線を測定する機能を含むもの）、マイクロフォン９００８、等を有する。 54A to 54G includes a housing 9000, a display portion 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (force , Displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration , Including a function of measuring odor or infrared light), a microphone 9008, and the like.
　図５４（Ａ）乃至図５４（Ｇ）に示す電子機器は、様々な機能を有する。例えば、様々な情報（静止画、動画、テキスト画像など）を表示部に表示する機能、タッチパネル機能、カレンダー、日付または時刻などを表示する機能、様々なソフトウェア（プログラム）によって処理を制御する機能、無線通信機能、無線通信機能を用いて様々なコンピュータネットワークに接続する機能、無線通信機能を用いて様々なデータの送信または受信を行う機能、記録媒体に記録されているプログラムまたはデータを読み出して表示部に表示する機能、等を有することができる。なお、図５４（Ａ）乃至図５４（Ｇ）に示す電子機器が有することのできる機能はこれらに限定されず、様々な機能を有することができる。また、図５４（Ａ）乃至図５４（Ｇ）には図示していないが、電子機器には、複数の表示部を有する構成としてもよい。また、該電子機器にカメラ等を設け、静止画を撮影する機能、動画を撮影する機能、撮影した画像を記録媒体（外部またはカメラに内蔵）に保存する機能、撮影した画像を表示部に表示する機能、等を有していてもよい。 The electronic devices illustrated in FIGS. 54A to 54G have various functions. For example, a function for displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function for displaying a calendar, date or time, a function for controlling processing by various software (programs), Wireless communication function, function for connecting to various computer networks using the wireless communication function, function for transmitting or receiving various data using the wireless communication function, and reading and displaying the program or data recorded on the recording medium It can have a function of displaying on the section. Note that the functions of the electronic devices illustrated in FIGS. 54A to 54G are not limited to these, and can have various functions. Although not illustrated in FIGS. 54A to 54G, the electronic device may have a plurality of display portions. In addition, the electronic device is equipped with a camera, etc., to capture still images, to capture moving images, to store captured images on a recording medium (externally or built into the camera), and to display captured images on the display unit And the like.
　図５４（Ａ）乃至図５４（Ｇ）に示す電子機器の詳細について、以下説明を行う。 Details of the electronic devices shown in FIGS. 54A to 54G will be described below.
　図５４（Ａ）は、テレビジョン装置９１００を示す斜視図である。テレビジョン装置９１００は、表示部９００１を大画面、例えば、５０インチ以上、または１００インチ以上の表示部９００１を組み込むことが可能である。 FIG. 54A is a perspective view showing the television device 9100. FIG. The television device 9100 can incorporate the display portion 9001 with a large screen, for example, a display portion 9001 with a size of 50 inches or more, or 100 inches or more.
　図５４（Ｂ）は、携帯情報端末９１０１を示す斜視図である。携帯情報端末９１０１は、例えば電話機、手帳又は情報閲覧装置等から選ばれた一つ又は複数の機能を有する。具体的には、スマートフォンとして用いることができる。なお、携帯情報端末９１０１は、スピーカ９００３、接続端子９００６、センサ９００７等を設けてもよい。また、携帯情報端末９１０１は、文字や画像情報をその複数の面に表示することができる。例えば、３つの操作ボタン９０５０（操作アイコンまたは単にアイコンともいう）を表示部９００１の一の面に表示することができる。また、破線の矩形で示す情報９０５１を表示部９００１の他の面に表示することができる。なお、情報９０５１の一例としては、電子メールやＳＮＳ（ソーシャル・ネットワーキング・サービス）や電話などの着信を知らせる表示、電子メールやＳＮＳなどの題名、電子メールやＳＮＳなどの送信者名、日時、時刻、バッテリの残量、アンテナ受信の強度などがある。または、情報９０５１が表示されている位置に、情報９０５１の代わりに、操作ボタン９０５０などを表示してもよい。 FIG. 54B is a perspective view showing the portable information terminal 9101. The portable information terminal 9101 has one or a plurality of functions selected from, for example, a telephone, a notebook, an information browsing device, or the like. Specifically, it can be used as a smartphone. Note that the portable information terminal 9101 may include a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. Further, the portable information terminal 9101 can display characters and image information on the plurality of surfaces. For example, three operation buttons 9050 (also referred to as operation icons or simply icons) can be displayed on one surface of the display portion 9001. Further, information 9051 indicated by a broken-line rectangle can be displayed on another surface of the display portion 9001. As an example of the information 9051, a display that notifies an incoming call such as an e-mail, SNS (social networking service) or a telephone, a title such as an e-mail or SNS, a sender name such as an e-mail or SNS, a date, a time , Battery level, antenna reception strength and so on. Alternatively, an operation button 9050 or the like may be displayed instead of the information 9051 at a position where the information 9051 is displayed.
　図５４（Ｃ）は、携帯情報端末９１０２を示す斜視図である。携帯情報端末９１０２は、表示部９００１の３面以上に情報を表示する機能を有する。ここでは、情報９０５２、情報９０５３、情報９０５４がそれぞれ異なる面に表示されている例を示す。例えば、携帯情報端末９１０２の使用者は、洋服の胸ポケットに携帯情報端末９１０２を収納した状態で、その表示（ここでは情報９０５３）を確認することができる。具体的には、着信した電話の発信者の電話番号又は氏名等を、携帯情報端末９１０２の上方から観察できる位置に表示する。使用者は、携帯情報端末９１０２をポケットから取り出すことなく、表示を確認し、電話を受けるか否かを判断できる。 FIG. 54C is a perspective view showing the portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more surfaces of the display portion 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different planes. For example, the user of the portable information terminal 9102 can check the display (information 9053 here) in a state where the portable information terminal 9102 is stored in the chest pocket of clothes. Specifically, the telephone number or name of the caller of the incoming call is displayed at a position where it can be observed from above portable information terminal 9102. The user can check the display and determine whether to receive a call without taking out the portable information terminal 9102 from the pocket.
　図５４（Ｄ）は、腕時計型の携帯情報端末９２００を示す斜視図である。携帯情報端末９２００は、移動電話、電子メール、文章閲覧及び作成、音楽再生、インターネット通信、コンピュータゲームなどの種々のアプリケーションを実行することができる。また、表示部９００１はその表示面が湾曲して設けられ、湾曲した表示面に沿って表示を行うことができる。また、携帯情報端末９２００は、通信規格された近距離無線通信を実行することが可能である。例えば無線通信可能なヘッドセットと相互通信することによって、ハンズフリーで通話することもできる。また、携帯情報端末９２００は、接続端子９００６を有し、他の情報端末とコネクターを介して直接データのやりとりを行うことができる。また接続端子９００６を介して充電を行うこともできる。なお、充電動作は接続端子９００６を介さずに無線給電により行ってもよい。 FIG. 54D is a perspective view showing a wristwatch-type portable information terminal 9200. FIG. The portable information terminal 9200 can execute various applications such as a mobile phone, electronic mail, text browsing and creation, music playback, Internet communication, and computer games. Further, the display portion 9001 is provided with a curved display surface, and can perform display along the curved display surface. In addition, the portable information terminal 9200 can execute short-range wireless communication with a communication standard. For example, it is possible to talk hands-free by communicating with a headset capable of wireless communication. In addition, the portable information terminal 9200 includes a connection terminal 9006 and can directly exchange data with other information terminals via a connector. Charging can also be performed through the connection terminal 9006. Note that the charging operation may be performed by wireless power feeding without using the connection terminal 9006.
　図５４（Ｅ）（Ｆ）（Ｇ）は、折り畳み可能な携帯情報端末９２０１を示す斜視図である。また、図５４（Ｅ）が携帯情報端末９２０１を展開した状態の斜視図であり、図５４（Ｆ）が携帯情報端末９２０１を展開した状態または折り畳んだ状態の一方から他方に変化する途中の状態の斜視図であり、図５４（Ｇ）が携帯情報端末９２０１を折り畳んだ状態の斜視図である。携帯情報端末９２０１は、折り畳んだ状態では可搬性に優れ、展開した状態では、継ぎ目のない広い表示領域により表示の一覧性に優れる。携帯情報端末９２０１が有する表示部９００１は、ヒンジ９０５５によって連結された３つの筐体９０００に支持されている。ヒンジ９０５５を介して２つの筐体９０００間を屈曲させることにより、携帯情報端末９２０１を展開した状態から折りたたんだ状態に可逆的に変形させることができる。例えば、携帯情報端末９２０１は、曲率半径１ｍｍ以上１５０ｍｍ以下で曲げることができる。 54E, 54F, and 54G are perspective views showing a foldable portable information terminal 9201. FIG. FIG. 54E is a perspective view of a state in which the portable information terminal 9201 is expanded, and FIG. 54F is a state in the middle of changing from one of the expanded state or the folded state of the portable information terminal 9201 to the other. FIG. 54G is a perspective view of the portable information terminal 9201 folded. The portable information terminal 9201 is excellent in portability in the folded state, and in the expanded state, the portable information terminal 9201 is excellent in display listability due to a seamless wide display area. A display portion 9001 included in the portable information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. By bending between the two housings 9000 via the hinge 9055, the portable information terminal 9201 can be reversibly deformed from the expanded state to the folded state. For example, the portable information terminal 9201 can be bent with a curvature radius of 1 mm to 150 mm.
　次に、図５３（Ａ）乃至図５３（Ｅ）に示す電子機器、及び図５４（Ａ）乃至図５４（Ｇ）に示す電子機器と異なる電子機器の一例を図５５（Ａ）（Ｂ）に示す。図５５（Ａ）（Ｂ）は、複数の表示パネルを有する表示装置の斜視図である。なお、図５５（Ａ）は、複数の表示パネルが巻き取られた形態の斜視図であり、図５５（Ｂ）は、複数の表示パネルが展開された状態の斜視図である。 Next, examples of the electronic device illustrated in FIGS. 53A to 53E and the electronic device different from the electronic devices illustrated in FIGS. 54A to 54G are illustrated in FIGS. Shown in 55A and 55B are perspective views of a display device having a plurality of display panels. FIG. 55A is a perspective view of a form in which a plurality of display panels are wound, and FIG. 55B is a perspective view of a state in which the plurality of display panels are developed.
　図５５（Ａ）（Ｂ）に示す表示装置９５００は、複数の表示パネル９５０１と、軸部９５１１と、軸受部９５１２と、を有する。また、複数の表示パネル９５０１は、表示領域９５０２と、透光性を有する領域９５０３と、を有する。 55A and 55B includes a plurality of display panels 9501, a shaft portion 9511, and a bearing portion 9512. The plurality of display panels 9501 each include a display region 9502 and a region 9503 having a light-transmitting property.
　また、複数の表示パネル９５０１は、可撓性を有する。また、隣接する２つの表示パネル９５０１は、それらの一部が互いに重なるように設けられる。例えば、隣接する２つの表示パネル９５０１の透光性を有する領域９５０３を重ね合わせることができる。複数の表示パネル９５０１を用いることで、大画面の表示装置とすることができる。また、使用状況に応じて、表示パネル９５０１を巻き取ることが可能であるため、汎用性に優れた表示装置とすることができる。 In addition, the plurality of display panels 9501 have flexibility. Further, two adjacent display panels 9501 are provided so that a part of them overlap each other. For example, a light-transmitting region 9503 of two adjacent display panels 9501 can be overlapped. By using a plurality of display panels 9501, a large-screen display device can be obtained. In addition, since the display panel 9501 can be taken up depending on the use state, a display device with excellent versatility can be obtained.
　また、図５５（Ａ）（Ｂ）においては、表示領域９５０２が隣接する表示パネル９５０１で離間する状態を図示しているが、これに限定されず、例えば、隣接する表示パネル９５０１の表示領域９５０２を隙間なく重ねあわせることで、連続した表示領域９５０２としてもよい。 FIGS. 55A and 55B illustrate a state in which the display area 9502 is separated by the adjacent display panel 9501, but is not limited to this. For example, the display area 9502 of the adjacent display panel 9501 is displayed. The display area 9502 may be a continuous display area by overlapping them with no gap.
　本実施の形態において述べた電子機器は、何らかの情報を表示するための表示部を有することを特徴とする。ただし、本発明の一態様の半導体装置は、表示部を有さない電子機器にも適用することができる。 The electronic device described in this embodiment has a display portion for displaying some information. Note that the semiconductor device of one embodiment of the present invention can also be applied to an electronic device that does not include a display portion.
　本実施の形態は、少なくともその一部を本明細書中に記載する他の実施の形態と適宜組み合わせて実施することができる。 Note that at least part of this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate.
１００　　トランジスタ
１００Ａ　　トランジスタ
１００Ｂ　　トランジスタ
１００Ｃ　　トランジスタ
１００Ｄ　　トランジスタ
１００Ｅ　　トランジスタ
１００Ｆ　　トランジスタ
１００Ｇ　　トランジスタ
１００Ｈ　　トランジスタ
１００Ｊ　　トランジスタ
１００Ｋ　　トランジスタ
１０２　　基板
１０４　　絶縁膜
１０６　　導電膜
１０８　　酸化物半導体膜
１０８＿１　　酸化物半導体膜
１０８＿２　　酸化物半導体膜
１０８＿３　　酸化物半導体膜
１０８ｄ　　ドレイン領域
１０８ｆ　　領域
１０８ｉ　　チャネル領域
１０８ｓ　　ソース領域
１１０　　絶縁膜
１１２　　導電膜
１１２＿１　　導電膜
１１２＿２　　導電膜
１１４　　絶縁膜
１１６　　絶縁膜
１１８　　絶縁膜
１２０ａ　　導電膜
１２０ｂ　　導電膜
１２２　　絶縁膜
１４１ａ　　開口部
１４１ｂ　　開口部
１４３　　開口部
３００Ａ　　トランジスタ
３００Ｂ　　トランジスタ
３００Ｃ　　トランジスタ
３００Ｄ　　トランジスタ
３００Ｅ　　トランジスタ
３００Ｆ　　トランジスタ
３００Ｇ　　トランジスタ
３０２　　基板
３０４　　導電膜
３０６　　絶縁膜
３０７　　絶縁膜
３０８　　酸化物半導体膜
３０８＿１　　酸化物半導体膜
３０８＿２　　酸化物半導体膜
３０８＿３　　酸化物半導体膜
３１２ａ　　導電膜
３１２ｂ　　導電膜
３１２ｃ　　導電膜
３１４　　絶縁膜
３１６　　絶縁膜
３１８　　絶縁膜
３２０ａ　　導電膜
３２０ｂ　　導電膜
３４１ａ　　開口部
３４１ｂ　　開口部
３４２ａ　　開口部
３４２ｂ　　開口部
３４２ｃ　　開口部
３５１　　開口部
３５２ａ　　開口部
３５２ｂ　　開口部
５０１　　画素回路
５０２　　画素部
５０４　　駆動回路部
５０４ａ　　ゲートドライバ
５０４ｂ　　ソースドライバ
５０６　　保護回路
５０７　　端子部
５５０　　トランジスタ
５５２　　トランジスタ
５５４　　トランジスタ
５６０　　容量素子
５６２　　容量素子
５７０　　液晶素子
５７２　　発光素子
６６４　　電極
６６５　　電極
６６７　　電極
７００　　表示装置
７０１　　基板
７０２　　画素部
７０４　　ソースドライバ回路部
７０５　　基板
７０６　　ゲートドライバ回路部
７０８　　ＦＰＣ端子部
７１０　　信号線
７１１　　配線部
７１２　　シール材
７１６　　ＦＰＣ
７３０　　絶縁膜
７３２　　封止膜
７３４　　絶縁膜
７３６　　着色膜
７３８　　遮光膜
７５０　　トランジスタ
７５２　　トランジスタ
７６０　　接続電極
７７０　　平坦化絶縁膜
７７２　　導電膜
７７３　　絶縁膜
７７４　　導電膜
７７５　　液晶素子
７７６　　液晶層
７７８　　構造体
７８０　　異方性導電膜
７８２　　発光素子
７８３　　液滴吐出装置
７８４　　液滴
７８５　　層
７８６　　ＥＬ層
７８８　　導電膜
７９０　　容量素子
７９１　　タッチパネル
７９２　　絶縁膜
７９３　　電極
７９４　　電極
７９５　　絶縁膜
７９６　　電極
７９７　　絶縁膜
８００　　インバータ
８１０　　ＯＳトランジスタ
８２０　　ＯＳトランジスタ
８３１　　信号波形
８３２　　信号波形
８４０　　破線
８４１　　実線
８５０　　ＯＳトランジスタ
８６０　　ＣＭＯＳインバータ
９００　　半導体装置
９０１　　電源回路
９０２　　回路
９０３　　電圧生成回路
９０３Ａ　　電圧生成回路
９０３Ｂ　　電圧生成回路
９０３Ｃ　　電圧生成回路
９０４　　回路
９０５　　電圧生成回路
９０６　　回路
９１１　　トランジスタ
９１２　　トランジスタ
９１２Ａ　　トランジスタ
９１２Ｂ　　トランジスタ
９２１　　制御回路
９２２　　トランジスタ
１４００　　液滴吐出装置
１４０２　　基板
１４０３　　液滴吐出手段
１４０４　　撮像手段
１４０５　　ヘッド
１４０６　　点線
１４０７　　制御手段
１４０８　　記憶媒体
１４０９　　画像処理手段
１４１０　　コンピュータ
１４１１　　マーカー
１４１２　　ヘッド
１４１３　　材料供給源
１４１４　　材料供給源
７０００　　表示モジュール
７００１　　上部カバー
７００２　　下部カバー
７００３　　ＦＰＣ
７００４　　タッチパネル
７００５　　ＦＰＣ
７００６　　表示パネル
７００７　　バックライト
７００８　　光源
７００９　　フレーム
７０１０　　プリント基板
７０１１　　バッテリ
８０００　　カメラ
８００１　　筐体
８００２　　表示部
８００３　　操作ボタン
８００４　　シャッターボタン
８００６　　レンズ
８１００　　ファインダー
８１０１　　筐体
８１０２　　表示部
８１０３　　ボタン
８２００　　ヘッドマウントディスプレイ
８２０１　　装着部
８２０２　　レンズ
８２０３　　本体
８２０４　　表示部
８２０５　　ケーブル
８２０６　　バッテリ
８３００　　ヘッドマウントディスプレイ
８３０１　　筐体
８３０２　　表示部
８３０４　　固定具
８３０５　　レンズ
９０００　　筐体
９００１　　表示部
９００３　　スピーカ
９００５　　操作キー
９００６　　接続端子
９００７　　センサ
９００８　　マイクロフォン
９０５０　　操作ボタン
９０５１　　情報
９０５２　　情報
９０５３　　情報
９０５４　　情報
９０５５　　ヒンジ
９１００　　テレビジョン装置
９１０１　　携帯情報端末
９１０２　　携帯情報端末
９２００　　携帯情報端末
９２０１　　携帯情報端末
９５００　　表示装置
９５０１　　表示パネル
９５０２　　表示領域
９５０３　　領域
９５１１　　軸部
９５１２　　軸受部 100 Transistor 100A Transistor 100B Transistor 100C Transistor 100D Transistor 100E Transistor 100F Transistor 100G Transistor 100H Transistor 100J Transistor 100K Transistor 102 Substrate 104 Insulating film 106 Conductive film 108 Oxide semiconductor film 108_1 Oxide semiconductor film 108_2 Oxide semiconductor film 108_3 Oxide semiconductor film 108d drain region 108f region 108i channel region 108s source region 110 insulating film 112 conductive film 112_1 conductive film 112_2 conductive film 114 insulating film 116 insulating film 118 insulating film 120a conductive film 120b conductive film 122 insulating film 141a opening 141b opening 143 opening 300A Transistor 300B G Transistor 300C transistor 300D transistor 300E transistor 300F transistor 300G transistor 302 substrate 304 conductive film 306 insulating film 307 insulating film 308 oxide semiconductor film 308_1 oxide semiconductor film 308_2 oxide semiconductor film 308_3 oxide semiconductor film 312a conductive film 312b conductive film 312c conductive Film 314 Insulating film 316 Insulating film 318 Insulating film 320a Conductive film 320b Conductive film 341a Opening 341b Opening 342a Opening 342b Opening 342c Opening 351 Opening 352a Opening 352b Opening 501 Pixel circuit 502 Pixel part 504 Drive circuit part 504a Gate driver 504b Source driver 506 Protection circuit 507 Terminal portion 550 Transistor 552 Transistor 55 Transistor 560 Capacitor 562 Capacitor 570 Liquid crystal element 572 Light-emitting element 664 Electrode 665 Electrode 667 Electrode 700 Display device 701 Substrate 702 Pixel unit 704 Source driver circuit unit 705 Substrate 706 Gate driver circuit unit 708 FPC terminal unit 710 Signal line 711 Wiring unit 712 Seal material 716 FPC
730 Insulating film 732 Sealing film 734 Insulating film 736 Colored film 738 Light shielding film 750 Transistor 752 Transistor 760 Connection electrode 770 Flattening insulating film 772 Conductive film 773 Insulating film 774 Conductive film 775 Liquid crystal element 776 Liquid crystal layer 778 Structure 780 Anisotropy Conductive film 782 Light emitting element 783 Droplet discharge device 784 Droplet 785 Layer 786 EL layer 788 Conductive film 790 Capacitance element 791 Touch panel 792 Insulating film 793 Electrode 794 Electrode 795 Insulating film 796 Electrode 797 Insulating film 800 Inverter 810 OS transistor 820 OS transistor 831 Signal waveform 832 Signal waveform 840 Broken line 841 Solid line 850 OS transistor 860 CMOS inverter 900 Semiconductor device 901 Power supply circuit 902 Circuit 903 Voltage generation circuit 90 A voltage generation circuit 903B voltage generation circuit 903C voltage generation circuit 904 circuit 905 voltage generation circuit 906 circuit 911 transistor 912 transistor 912A transistor 912B transistor 921 control circuit 922 transistor 1400 droplet ejection device 1402 substrate 1403 droplet ejection unit 1404 imaging unit 1405 head 1406 Dotted line 1407 Control means 1408 Storage medium 1409 Image processing means 1410 Computer 1411 Marker 1412 Head 1413 Material supply source 1414 Material supply source 7000 Display module 7001 Upper cover 7002 Lower cover 7003 FPC
7004 touch panel 7005 FPC
7006 Display panel 7007 Backlight 7008 Light source 7009 Frame 7010 Printed circuit board 7011 Battery 8000 Camera 8001 Housing 8002 Display unit 8003 Operation button 8004 Shutter button 8006 Lens 8100 Viewfinder 8101 Housing 8102 Display unit 8103 Button 8200 Head mounted display 8201 Mounting unit 8202 Lens 8203 Body 8204 Display unit 8205 Cable 8206 Battery 8206 Head mounted display 8301 Housing 8302 Display unit 8304 Fixing tool 8305 Lens 9000 Housing 9001 Display unit 9003 Speaker 9005 Operation key 9006 Connection terminal 9007 Sensor 9008 Microphone 9050 Operation button 9051 Information 9052 Information Information 9053 Information 9054 Information 9055 Hinge 9100 Television apparatus 9101 Portable information terminal 9102 Portable information terminal 9200 Portable information terminal 9201 Portable information terminal 9500 Display device 9501 Display panel 9502 Display area 9503 Area 9511 Shaft part 9512 Bearing part

Claims (8)

  1. 　インジウム、Ｍ（Ｍは、Ａｌ、Ｇａ、Ｙ、またはＳｎ）、及び亜鉛を含む金属酸化物膜であって、
    　膜面に垂直な方向におけるＸ線回折において、結晶構造に起因した回折強度のピークが観測される領域を有し、
    　１０ｎｍ以上５０ｎｍ以下の厚さに薄片化し、プローブ径を５０ｎｍ以上とした、断面に垂直な方向における電子線回折において、リング状の回折パターンと、前記リング状の回折パターンと重なる位置に２つの第１のスポットと、を有する第１の電子線回折パターンが観測され、且つプローブ径を０．３ｎｍ以上５ｎｍ以下とした電子線回折において、前記第１のスポットと、円周方向に分布する複数の第２のスポットと、を有する第２の電子線回折パターンが観測される領域を有する、
    　金属酸化物膜。     A metal oxide film containing indium, M (M is Al, Ga, Y, or Sn), and zinc,
    In the X-ray diffraction in the direction perpendicular to the film surface, it has a region where a peak of diffraction intensity due to the crystal structure is observed,
    In the electron beam diffraction in the direction perpendicular to the cross section, which is sliced to a thickness of 10 nm or more and 50 nm or less and the probe diameter is 50 nm or more, two ring-shaped diffraction patterns and two positions overlapping with the ring-shaped diffraction pattern In an electron beam diffraction in which a first electron beam diffraction pattern having one spot is observed and the probe diameter is 0.3 nm or more and 5 nm or less, the first spot and a plurality of spots distributed in the circumferential direction are used. A second spot, and a region where a second electron diffraction pattern is observed.
    Metal oxide film.
  2. 　請求項１において、
    　２つの前記第１のスポットは、中心に対して対称に観測され、
    　前記第１のスポットの最も輝度の高い点と、中心とを通る第１の直線と、膜面の法線方向との間の角度が０度以上１０度以下である領域を有する、
    　金属酸化物膜。     In claim 1,
    The two first spots are observed symmetrically with respect to the center;
    A region in which an angle between the highest brightness point of the first spot, the first straight line passing through the center, and the normal direction of the film surface is 0 degree or more and 10 degrees or less;
    Metal oxide film.
  3. 　請求項２において、
    　前記第１の電子線回折パターンにおいて、前記第１の直線と直交する第２の直線と前記リング状の回折パターンとの交点における、前記リング状の回折パターンの輝度が、前記第１のスポットの輝度よりも小さい領域を有する、
    　金属酸化物膜。     In claim 2,
    In the first electron beam diffraction pattern, the luminance of the ring-shaped diffraction pattern at the intersection of the second straight line orthogonal to the first straight line and the ring-shaped diffraction pattern is the first spot. Having an area smaller than the brightness,
    Metal oxide film.
  4. 　請求項３において、
    　前記第１のスポットの輝度は、前記第２の直線と前記リング状の回折パターンとの交点における前記リング状の回折パターンの輝度に対して、１倍よりも大きく、１０倍以下である領域を有する、
    　金属酸化物膜。     In claim 3,
    An area where the luminance of the first spot is greater than 1 and less than or equal to 10 times the luminance of the ring-shaped diffraction pattern at the intersection of the second straight line and the ring-shaped diffraction pattern. Have
    Metal oxide film.
  5. 　請求項１乃至請求項４のいずれか一において、
    　断面の透過電子顕微鏡像において、ｃ軸の方向と膜面の方向との間の角度が１０度以下である結晶部が存在する部分を除いた部分の面積の割合が、２５％以上１００未満である領域を有する、
    　金属酸化物膜。     In any one of Claims 1 thru | or 4,
    In the transmission electron microscopic image of the cross section, the area ratio of the portion excluding the portion where the crystal portion where the angle between the c-axis direction and the film surface direction is 10 degrees or less exists is 25% or more and less than 100 Have a certain area,
    Metal oxide film.
  6. 　請求項１乃至請求項４のいずれか一において、
    　断面のＴＥＭ像に対して高速フーリエ変換した第１の像に対して、周期性を示す範囲を残すマスク処理を施した後に逆フーリエ変換した第２の像において、元の像から残存した像を差し引いた面積の割合が、２５％以上１００未満である領域を有する、
    　金属酸化物膜。     In any one of Claims 1 thru | or 4,
    In the second image obtained by performing the inverse Fourier transform on the first image obtained by performing fast Fourier transform on the cross-sectional TEM image and performing the mask processing that leaves the range showing the periodicity, an image remaining from the original image is obtained. The area ratio after subtraction has a region that is 25% or more and less than 100.
    Metal oxide film.
  7. 　請求項１乃至請求項４のいずれか一において、
    　前記第１のスポットは、円周方向に広がった形状を有し、
    　前記第１のスポットの円周方向の２つの端部のそれぞれと、電子線回折パターンの中心とを通る２つの直線の角度が、４５度以内である、
    　金属酸化物膜。     In any one of Claims 1 thru | or 4,
    The first spot has a shape spreading in the circumferential direction,
    The angle of two straight lines passing through each of the two circumferential ends of the first spot and the center of the electron beam diffraction pattern is within 45 degrees.
    Metal oxide film.
  8. 　半導体層と、ゲート絶縁層と、ゲートと、を有する半導体装置であって、
    　前記半導体層は、請求項１乃至請求項４のうちいずれか一に記載の金属酸化物膜を含む、
    　半導体装置。     A semiconductor device having a semiconductor layer, a gate insulating layer, and a gate,
    The semiconductor layer includes the metal oxide film according to any one of claims 1 to 4.
    Semiconductor device.
PCT/IB2016/057594 2015-12-24 2016-12-14 Metal oxide film and semiconductor device WO2017109642A1 (en)

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JP2015109427A (en) * 2013-10-22 2015-06-11 株式会社半導体エネルギー研究所 Oxide semiconductor film manufacturing method
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JP2014143404A (en) * 2012-12-25 2014-08-07 Semiconductor Energy Lab Co Ltd Resistance element, display device, and electronic apparatus
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