WO2017096689A1 - 显示面板与栅极驱动架构 - Google Patents

显示面板与栅极驱动架构 Download PDF

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Publication number
WO2017096689A1
WO2017096689A1 PCT/CN2016/070304 CN2016070304W WO2017096689A1 WO 2017096689 A1 WO2017096689 A1 WO 2017096689A1 CN 2016070304 W CN2016070304 W CN 2016070304W WO 2017096689 A1 WO2017096689 A1 WO 2017096689A1
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WIPO (PCT)
Prior art keywords
numbered
odd
gate film
film flip
chips
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Ceased
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PCT/CN2016/070304
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English (en)
French (fr)
Inventor
黄笑宇
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/907,304 priority Critical patent/US20170169786A1/en
Publication of WO2017096689A1 publication Critical patent/WO2017096689A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0281—Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation

Definitions

  • the present patent application relates to a display panel and a gate driving architecture, particularly for a thin film transistor liquid crystal display (Thin Film) Transistor Liquid Crystal Display, TFT-LCD) display panel and gate drive architecture.
  • Thin Film Thin Film Transistor Liquid Crystal Display
  • Thin film transistor liquid crystal display (Thin Film Transistor Liquid Crystal Display, TFT-LCD) is the main variety of current flat panel displays.
  • the main driving principle of TFT-LCD as shown in Figure 1, the system board 1 will R/G/B tri-color compression signal, control signal and power through the wire and printed circuit board 10 (Print The connectors on the Circuit Board, PCB) are connected, and the PCB board 10 is covered by a source film (Source-Chip on Film, The S-COF 11 and the Gate-Chip on Film (G-COF) 12 are connected to the display region 13, so that the LCD obtains the required power and signals.
  • a source film Source film
  • S-COF 11 and the Gate-Chip on Film (G-COF) 12 are connected to the display region 13, so that the LCD obtains the required power and signals.
  • the signal transmission between the source film flip chip 11 and the gate film flip chip 12 and between the different gate film flip chips is completed through the layout of the fan-out region 14 .
  • the routing space of the fan-side fan-out area is decreasing day by day, the layout routing difficulty is increasing, and the line width is also shrinking. Therefore, it is required to reduce the trace density of the fan-out area.
  • the gate drive architecture is required to reduce the trace density of the fan-out area.
  • the gate film in the conventional single-side driving structure is flipped and arranged on both sides of the display panel.
  • the output of the odd-numbered gate film flip-chip is used as the starting signal of the even-numbered gate film flip-chip to reduce the trace density in the fan-out area.
  • An embodiment of the present patent application provides a display panel having a display area, a plurality of sequentially arranged odd-numbered and even-numbered scan lines in the display area, and non-display areas on both sides of the display area.
  • the panel includes a plurality of odd-numbered gate film flip-chips disposed on a first side of the non-display area, each of the odd-numbered gate film flip-chips having an individual corresponding to each of the odd-numbered scan lines a plurality of odd-numbered scan output channels; and a plurality of even-numbered gate film flip-chips disposed on the second side of the opposite sides of the first side on the non-display area, each of the even-numbered gates
  • the film flip chip has a plurality of even-numbered scan output channels respectively corresponding to each of the even-numbered scan lines; wherein the first odd-numbered gate film of the plurality of odd-numbered gate film flip-chips is over-crystallized according to The first start signal sequentially drives each of the odd-numbered scan output channels, and in the
  • the odd-numbered gate film flip-chips other than the first odd-numbered gate film flip-chip in the plurality of odd-numbered gate film flip-chips sequentially drive each odd-numbered stage according to another scan driving signal. Scan the output channel.
  • the other even-numbered gate film flip-chips other than the first even-numbered gate film flip-chip in the plurality of even-numbered gate film flip-chips sequentially drive each even-numbered stage according to another scan driving signal. Scan the output channel.
  • each of the odd-numbered scanning output channels of the plurality of odd-numbered gate film flip-chips and the even-numbered scanning output channels of the plurality of odd-numbered gate thin films are driven to be interleaved with each other. drive.
  • the first start signal comprises an initial pulse vertical signal (start pulse vertical) Signal, STV), the initial pulse vertical signal is used as an enable signal for each picture refresh of the odd-numbered gate film flip-chip.
  • start pulse vertical start pulse vertical
  • the patent application provides a gate driving structure capable of reducing the trace density of the fan-out area, increasing the wiring space and reducing the difficulty of the routing, thereby improving product quality and enhancing product competitiveness.
  • FIG. 1 is a schematic structural view of a conventional gate driving panel
  • FIG. 2 is a schematic structural diagram of a gate driving panel according to an embodiment of the present patent application.
  • Figure 3 is a detailed schematic view of Figure 2;
  • FIG. 4 is a waveform diagram of the scan output channel of the gate film of FIG. 3 in the operation of the display panel.
  • FIG. 3 is a schematic structural diagram of a gate driving panel according to an embodiment of the present application.
  • FIG. 3 is a schematic structural view of FIG. 2 .
  • the display panel 2 has a display area 20 and a plurality of layers in the display area 20 .
  • the panel 2 includes a plurality of odd-numbered gates a pole film flip chip 210 disposed on the first side 201 of the non-display area 21, each of the odd-numbered gate film flip chips 210 having a plurality of odd-numbered scans individually corresponding to each of the odd-numbered scan lines An output channel Ch_O; and a plurality of even-numbered gate film flip-chips 210' disposed on the non-display area 21 on the opposite sides of the first side 201 of the second side 202, each of the even-numbered gates
  • the film flip chip 210' has an individual corresponding to each of the even-numbered sweeps A plurality of scan lines of even-numbered stage output channel Ch_E.
  • the first odd-numbered gate film flip chip 210_1 of the plurality of odd-numbered gate film flip-chips 210 sequentially drives each of the odd-numbered scan output channels according to a first start signal STV.
  • Ch_O and in the first odd-numbered gate film flip chip 210_1, the first odd-numbered scan output channel passes Ch_O_1 through the first odd-numbered scan line GL1 to output a scan drive signal S_Gate1 to the plurality of even-numbered gates a first even-numbered gate film flip-chip 210_1 ′ of the ultra-thin film flip-chip 210 ′, the scan driving signal S_Gate1 is used as a second start signal S_ini of the first even-numbered gate film flip-chip, Each of the even-numbered scan output channels Ch_E is driven sequentially.
  • odd-numbered gate-film flip-chips 210 other than the first odd-numbered gate film flip-chip 210_1 of the plurality of odd-numbered gate film flip-chips 210 are sequentially aligned according to another scan driving signal STV'.
  • Each odd-level scan output channel Ch_O is driven.
  • the other even-numbered gate film flip chip 210' except the first even-numbered gate film flip-chip 210_1' of the plurality of even-numbered gate film flip-chips 210' is in accordance with another scan driving signal S_ini' phase
  • each even-numbered scanning output channel Ch_E is driven in sequence.
  • each odd-numbered scanning output channel Ch_O of the plurality of odd-numbered gate film flip chips 210 and each even-numbered scanning output channel Ch_E of the plurality of odd-numbered gate film flip-chips 210' are driven The way is to drive each other in a staggered manner.
  • the first start signal comprises a start pulse vertical signal (start pulse vertical signal, STV), the initial pulse vertical signal is used as an enable signal for each picture refresh of the odd-numbered gate film flip chip 210, and for the gate film flip chip, each picture is only required once.
  • start pulse vertical signal start pulse vertical signal
  • the output scan driving signal S_Gate1 is connected to the first even level
  • the gate film flip chip 210_1 ′ serves as the second start signal S_ini of the second side 202 and starts from the second output of the first odd gate film flip chip 210_1 , and the output signal thereof only serves as the turn-on signal of the gate.
  • the even-numbered gate film is no longer connected to the second side 202.
  • the PCB After a picture refresh is completed, the PCB generates a next first start signal, which is transmitted to the first odd gate film flip chip 210_1, that is, each picture, the first side 201 and the second side 202 only have one The first start signal STV and the second start signal S_ini.
  • the scan output signal S_Gate1 outputted by the first odd-numbered gate film flip chip 210_1 is used as the second start signal S_ini of the first even-numbered gate film flip chip 210_1'.
  • a start signal STV is a start signal of the first odd-numbered gate film flip chip 210_1
  • S_Gate1 is a gate film flip chip 210_1'
  • the second start signal S_ini, and the first even-numbered gate film flip chip 210_1' output scan drive signal is S_Gate2.
  • FIG. 4 is a waveform diagram of the scan output channel of the gate film of FIG. 3 in the operation of the display panel, wherein the first odd-numbered scan output channel Ch_O_1 in the first odd-numbered gate film flip chip 210_1 corresponds to The first odd-numbered scan line GL1, the first even-numbered scan output channel Ch_E_1 of the first even-numbered gate film flip-chip 210_1' corresponds to the next even-numbered scan line GL2 of the first odd-numbered scan line GL1, And sequentially, the second odd-numbered scanning output channel Ch_O_2 in the gate film flip chip 210_1 corresponds to the odd-numbered scanning line GL3, and the second even-numbered scanning output channel Ch_E_2 of the first even-numbered gate film flip-chip 210_1' It will correspond to the next even-numbered scanning line GL4 of the odd-numbered scanning line GL3.
  • This patent application is combined with a specific gate film flip-chip output timing to finally realize the function of gate film flipping, and expands the single-sided trace space to two sides, increasing the wiring space and reducing the difficulty of routing, thereby enhancing the product. Quality and enhance product competitiveness.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种显示面板（2），所述显示面板（2）具有一显示区域（20）、在所述显示区域（20）的多条依序排列的奇数级与偶数级扫描线（GL1，GL3；GL2，GL4）、以及位于所述显示区域（20）两侧的非显示区域（21），并包括多个奇数级栅极薄膜覆晶（210），设置于所述非显示区域（21）的第一侧（201），每一所述奇数级栅极薄膜覆晶（210）具有分别对应于每一所述奇数级扫描线（GL1，GL3）的多个奇数级扫描输出通道（CH_O）；以及多个偶数级栅极薄膜覆晶（210'），设置于所述非显示区域（21）上所述第一侧（201）的相对异侧之第二侧（202），每一所述偶数级栅极薄膜覆晶（210'）具有分别对应于每一所述偶数级扫描线（GL2，GL4）的多个偶数级扫描输出通道（CH_E）。

Description

显示面板与栅极驱动架构 技术领域
本专利申请涉及一种显示面板与栅极驱动架构，特别是用于薄膜晶体管液晶显示器（Thin Film Transistor Liquid Crystal Display, TFT-LCD）的显示面板与栅极驱动架构。
 背景技术
薄膜晶体管液晶显示器（Thin Film Transistor Liquid Crystal Display, TFT-LCD）是当前平板显示的主要品种。TFT-LCD主要驱动原理，如图1所示，系统主板1将R/G/B三色压缩信号、控制信号及动力通过线材与印刷电路板10(Print Circuit Board, PCB)上的连接器相连接，PCB板10通过源极薄膜覆晶（Source-Chip on Film, S-COF）11和栅极薄膜覆晶（Gate-Chip on Film, G-COF）12与显示区13连接，从而使得LCD获得所需的电源、信号。
其中，源极薄膜覆晶11与栅极薄膜覆晶12之间，以及不同栅极薄膜覆晶之间的信号传输都是通过扇出区14的布局走线完成的。随着显示面板的窄边框需求渐增，栅极侧扇出区的走线空间日趋减少，布局走线难度日益增大，线宽也不断缩小，因此需要提出降低了扇出区的走线密度的栅极驱动架构。
 技术问题
本专利申请为增加栅极侧扇出区的走线空间，将传统单侧驱动架构中的栅极薄膜覆晶，排在显示面板的两侧。并利用多个奇数级栅极薄膜覆晶的输出，作为偶数级栅极薄膜覆晶的启始信号，达到减少扇出区走线密度的目的。
 技术解决方案
本专利申请一实施例提出了一种显示面板，具有一显示区域、在所述显示区域的多条依序排列的奇数级与偶数级扫描线、以及位于所述显示区域两侧的非显示区域，所述面板包括多个奇数级栅极薄膜覆晶，设置于所述非显示区域的第一侧，每一所述奇数级栅极薄膜覆晶具有个别对应于每一所述奇数级扫描线的多个奇数级扫描输出通道；以及多个偶数级栅极薄膜覆晶，设置于所述非显示区域上所述第一侧的相对异侧之第二侧，每一所述偶数级栅极薄膜覆晶具有个别对应于每一所述偶数级扫描线的多个偶数级扫描输出通道；其中，所述多个奇数级栅极薄膜覆晶中的第一奇数级栅极薄膜覆晶依据一第一启始信号依序驱动每一所述奇数级扫描输出通道，并且在所述第一奇数级栅极薄膜覆晶中，第一奇数级扫描输出通道通过第一奇数级扫描线将一扫描驱动信号输出至所述多个偶数级栅极薄膜覆晶的一第一偶数级栅极薄膜覆晶，使所述扫描驱动信号作为所述第一偶数级栅极薄膜覆晶的一第二启始信号，以依序驱动每一所述偶数级扫描输出通道。
较优选地，所述多个奇数级栅极薄膜覆晶中第一奇数级栅极薄膜覆晶以外的其余奇数级栅极薄膜覆晶依据另一扫描驱动信号相对应依序驱动每一奇数级扫描输出通道。
较优选地，所述多个偶数级栅极薄膜覆晶中第一偶数级栅极薄膜覆晶以外的其余偶数级栅极薄膜覆晶依据另一扫描驱动信号相对应依序驱动每一偶数级扫描输出通道。
较优选地，所述多个奇数级栅极薄膜覆晶的每一奇数级扫描输出通道与所述多个奇数级栅极薄膜覆晶的每一偶数级扫描输出信道的驱动方式为互相间隔交错驱动。
较优选地，所述第一启始信号包括初始脉冲垂直信号(start pulse vertical signal, STV)，所述初始脉冲垂直信号作为所述奇数级栅极薄膜覆晶的每个画面刷新的启动信号。
 有益效果
本专利申请提供一种可以降低了扇出区的走线密度的栅极驱动架构，增加走线空间，降低走线难度，从而提升产品品质，提升产品竞争力。
附图说明
图1是传统栅极驱动面板的架构示意图；
图2是依据本专利申请一实施例的栅极驱动面板的架构示意图；
图3是图2的细部架构示意图；以及
图4是图3的栅极薄膜覆晶的扫描输出通道在显示面板工作中的波形图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本专利申请可用以实施的特定实施例。本专利申请所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本专利申请，而非用以限制本专利申请。
本专利申请为增加栅极侧扇出区的走线空间，将传统单侧驱动架构中的栅极薄膜覆晶，排布在面板的两侧，请参照图2与图3，图2是依据本专利申请一实施例的栅极驱动面板的架构示意图，图3是图2的细部架构示意图，如图2所示，显示面板2具有一显示区域20、在所述显示区域20的多条依序排列的奇数级与偶数级扫描线(如奇数级扫描线GL1与偶数极扫描线GL2)、以及位于所述显示区域20两侧的非显示区域21，所述面板2包括多个奇数级栅极薄膜覆晶210，设置于所述非显示区域21的第一侧201，每一所述奇数级栅极薄膜覆晶210具有个别对应于每一所述奇数级扫描线的多个奇数级扫描输出通道Ch_O；以及多个偶数级栅极薄膜覆晶210’，设置于所述非显示区域21上所述第一侧201的相对异侧之第二侧202，每一所述偶数级栅极薄膜覆晶210’具有个别对应于每一所述偶数级扫描线的多个偶数级扫描输出通道Ch_E。
如图3所示，所述多个奇数级栅极薄膜覆晶210中的第一奇数级栅极薄膜覆晶210_1依据一第一启始信号STV依序驱动每一所述奇数级扫描输出通道Ch_O，并且在所述第一奇数级栅极薄膜覆晶210_1中，第一奇数级扫描输出通道通Ch_O_1过第一奇数级扫描线GL1将一扫描驱动信号S_Gate1输出至所述多个偶数级栅极薄膜覆晶210’的一第一偶数级栅极薄膜覆晶210_1’，使所述扫描驱动信号S_Gate1作为所述第一偶数级栅极薄膜覆晶的一第二启始信号S_ini，以依序驱动每一所述偶数级扫描输出通道Ch_E。
较优选地，所述多个奇数级栅极薄膜覆晶210中第一奇数级栅极薄膜覆晶210_1以外的其余奇数级栅极薄膜覆晶210依据另一扫描驱动信号STV’相对应依序驱动每一奇数级扫描输出通道Ch_O。
较优选地，所述多个偶数级栅极薄膜覆晶210’中第一偶数级栅极薄膜覆晶210_1’以外的其余偶数级栅极薄膜覆晶210’依据另一扫描驱动信号S_ini’相对应依序驱动每一偶数级扫描输出通道Ch_E。
较优选地，所述多个奇数级栅极薄膜覆晶210的每一奇数级扫描输出通道Ch_O与所述多个奇数级栅极薄膜覆晶210’的每一偶数级扫描输出信道Ch_E的驱动方式为互相间隔交错驱动。
较优选地，所述第一启始信号包括初始脉冲垂直信号(start pulse vertical signal, STV)，所述初始脉冲垂直信号作为所述奇数级栅极薄膜覆晶210的每个画面刷新的启动信号，对于栅极薄膜覆晶来说，每个画面仅需要一次。其中，当第一启始信号STV传输至第一奇数栅极薄膜覆晶210_1，第一奇数栅极薄膜覆晶210_1接收到STV后，输出的所述扫描驱动信号S_Gate1会连接至第一偶数级栅极薄膜覆晶210_1’作为第二侧202的第二启始信号S_ini，且从第一奇数栅极薄膜覆晶210_1的第二路输出开始，其输出信号仅作为栅极的开启信号，而不会再连接至第二侧202的偶数级栅极薄膜覆晶。待一个画面刷新完成后，PCB会产生下一个第一启始信号，传输至所述第一奇数栅极薄膜覆晶210_1，即每个画面，第一侧201和第二侧202仅会有一个第一启始信号STV与第二启始信号S_ini。
也就是说，利用第一奇数级栅极薄膜覆晶210_1输出的扫描输出信号S_Gate1，作为第一偶数级栅极薄膜覆晶210_1’的第二启始信号S_ini，从图3可看出，第一启始信号STV为第一奇数级栅极薄膜覆晶210_1的启始信号，第一奇数级栅极薄膜覆晶210_1输出的扫描驱动信号S_Gate1；而S_Gate1作为栅极薄膜覆晶210_1’的第二启始信号S_ini，而第一偶数级栅极薄膜覆晶210_1’输出扫描驱动信号为S_Gate2。
图4是图3的栅极薄膜覆晶的扫描输出通道在显示面板工作中的波形图，其中，第一奇数级栅极薄膜覆晶210_1中的所述第一奇数级扫描输出通道Ch_O_1对应于第一奇数级扫描线GL1，则第一偶数级栅极薄膜覆晶210_1’的第一偶数级扫描输出通道Ch_E_1会对应于所述第一奇数级扫描线GL1的下一条偶数级扫描线GL2，并依序地，栅极薄膜覆晶210_1中的第二奇数级扫描输出通道Ch_O_2对应于奇数级扫描线GL3，而第一偶数级栅极薄膜覆晶210_1’的第二偶数级扫描输出通道Ch_E_2会对应于所述奇数级扫描线GL3的下一条偶数级扫描线GL4。
本专利申请搭配特定的栅极薄膜覆晶输出时序，最终实现栅极薄膜覆晶的功能，并且将单侧的走线空间拓展为双侧，增加走线空间，降低走线难度，从而提升产品品质，提升产品竞争力。
综上所述，虽然本专利申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本专利申请，本领域的普通技术人员，在不脱离本专利申请的精神和范围内，均可作各种更动与润饰，因此本专利申请的保护范围以权利要求界定的范围为准。

Claims (11)

  1. 一种显示面板，具有一显示区域、在所述显示区域的多条依序排列的奇数级与偶数级扫描线、以及位于所述显示区域两侧的非显示区域，所述显示面板包括：
    多个奇数级栅极薄膜覆晶，设置于所述非显示区域的第一侧，每一所述奇数级栅极薄膜覆晶具有个别对应于每一所述奇数级扫描线的多个奇数级扫描输出通道；以及
    多个偶数级栅极薄膜覆晶，设置于所述非显示区域上所述第一侧的相对异侧之第二侧，每一所述偶数级栅极薄膜覆晶具有个别对应于每一所述偶数级扫描线的多个偶数级扫描输出通道；
    其中，所述多个奇数级栅极薄膜覆晶中的第一奇数级栅极薄膜覆晶依据一第一启始信号依序驱动每一所述奇数级扫描输出通道，并且在所述第一奇数级栅极薄膜覆晶中，第一奇数级扫描输出通道通过第一奇数级扫描线将一扫描驱动信号输出至所述多个偶数级栅极薄膜覆晶的一第一偶数级栅极薄膜覆晶，使所述扫描驱动信号作为所述第一偶数级栅极薄膜覆晶的一第二启始信号，以依序驱动每一所述偶数级扫描输出通道；所述第一启始信号包括初始脉冲垂直信号。
  2. 一种显示面板，具有一显示区域、在所述显示区域的多条依序排列的奇数级与偶数级扫描线、以及位于所述显示区域两侧的非显示区域，所述显示面板包括：
    多个奇数级栅极薄膜覆晶，设置于所述非显示区域的第一侧，每一所述奇数级栅极薄膜覆晶具有个别对应于每一所述奇数级扫描线的多个奇数级扫描输出通道；以及
    多个偶数级栅极薄膜覆晶，设置于所述非显示区域上所述第一侧的相对异侧之第二侧，每一所述偶数级栅极薄膜覆晶具有个别对应于每一所述偶数级扫描线的多个偶数级扫描输出通道；
    其中，所述多个奇数级栅极薄膜覆晶中的第一奇数级栅极薄膜覆晶依据一第一启始信号依序驱动每一所述奇数级扫描输出通道，并且在所述第一奇数级栅极薄膜覆晶中，第一奇数级扫描输出通道通过第一奇数级扫描线将一扫描驱动信号输出至所述多个偶数级栅极薄膜覆晶的一第一偶数级栅极薄膜覆晶，使所述扫描驱动信号作为所述第一偶数级栅极薄膜覆晶的一第二启始信号，以依序驱动每一所述偶数级扫描输出通道。
  3. 如权利要求2所述的显示面板，其中，所述多个奇数级栅极薄膜覆晶中第一奇数级栅极薄膜覆晶以外的其余奇数级栅极薄膜覆晶依据另一扫描驱动信号相对应依序驱动每一奇数级扫描输出通道。
  4. 如权利要求2所述的显示面板，其中，所述多个偶数级栅极薄膜覆晶中第一偶数级栅极薄膜覆晶以外的其余偶数级栅极薄膜覆晶依据另一扫描驱动信号相对应依序驱动每一偶数级扫描输出通道。
  5. 如权利要求2所述的显示面板，其中，所述多个奇数级栅极薄膜覆晶的每一奇数级扫描输出通道与所述多个奇数级栅极薄膜覆晶的每一偶数级扫描输出信道的驱动方式为互相间隔交错驱动。
  6. 如权利要求2所述的显示面板，其中，所述第一启始信号包括初始脉冲垂直信号，所述初始脉冲垂直信号作为所述奇数级栅极薄膜覆晶的每个画面刷新的启动信号。
  7. 一种栅极驱动架构，位于一显示面板中，所述显示面板具有多条依序排列的奇数级与偶数级扫描线，所述栅极驱动架构包括：
    多个奇数级栅极薄膜覆晶，设置于所述显示面板的第一侧中，每一所述奇数级栅极薄膜覆晶具有个别对应于每一所述奇数级扫描线的多个奇数级扫描输出通道；以及
    多个偶数级栅极薄膜覆晶，设置于所述显示面板中所述第一侧的相对异侧的第二侧，每一所述偶数级栅极薄膜覆晶具有个别对应于每一所述偶数级扫描线的多个偶数级扫描输出通道；
    其中，所述多个奇数级栅极薄膜覆晶中的第一奇数级栅极薄膜覆晶依据一第一启始信号依序驱动每一所述奇数级扫描输出通道，并且在所述第一奇数级栅极薄膜覆晶中，第一奇数级扫描输出通道通过第一奇数级扫描线将一扫描驱动信号输出至所述多个偶数级栅极薄膜覆晶的一第一偶数级栅极薄膜覆晶，使所述扫描驱动信号作为所述第一偶数级栅极薄膜覆晶的一第二启始信号，以依序驱动每一所述偶数级扫描输出通道。
  8. 如权利要求7所述的栅极驱动架构，其中，所述多个奇数级栅极薄膜覆晶中第一奇数级栅极薄膜覆晶以外的其余奇数级栅极薄膜覆晶依据另一扫描驱动信号相对应依序驱动每一奇数级扫描输出通道。
  9. 如权利要求7所述的栅极驱动架构，其中，所述多个偶数级栅极薄膜覆晶中第一偶数级栅极薄膜覆晶以外的其余偶数级栅极薄膜覆晶依据另一扫描驱动信号相对应依序驱动每一偶数级扫描输出通道。
  10. 如权利要求7所述的栅极驱动架构，其中，所述多个奇数级栅极薄膜覆晶的每一奇数级扫描输出通道与所述多个奇数级栅极薄膜覆晶的每一偶数级扫描输出信道的驱动方式为互相间隔交错驱动。
  11. 如权利要求7所述的栅极驱动架构，其中，所述第一启始信号包括初始脉冲垂直信号，所述初始脉冲垂直信号作为所述奇数级栅极薄膜覆晶的每个画面刷新的启动信号。
PCT/CN2016/070304 2015-12-11 2016-01-06 显示面板与栅极驱动架构 Ceased WO2017096689A1 (zh)

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