WO2017096503A1 - 具有延迟偏差检测和校准功能的数模转换器 - Google Patents

具有延迟偏差检测和校准功能的数模转换器 Download PDF

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WO2017096503A1
WO2017096503A1 PCT/CN2015/096535 CN2015096535W WO2017096503A1 WO 2017096503 A1 WO2017096503 A1 WO 2017096503A1 CN 2015096535 W CN2015096535 W CN 2015096535W WO 2017096503 A1 WO2017096503 A1 WO 2017096503A1
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signal
output
path
input
delay
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PCT/CN2015/096535
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English (en)
French (fr)
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周磊
吴旦昱
黄银坤
武锦
金智
刘新宇
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中国科学院微电子研究所
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Publication of WO2017096503A1 publication Critical patent/WO2017096503A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing

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  • the present invention relates to the field of electronic circuit technologies, and in particular, to a digital-to-analog converter having a delay deviation detection and calibration function.
  • a digital-to-analog converter is a circuit that converts a digital signal into an analog signal.
  • the use of high-speed, high-performance DAC chips not only greatly simplifies the system structure, but also increases the flexibility and portability of system design. For this reason, in many fields, high-speed, high-performance DAC chips are gradually replacing traditional analog circuits, becoming a new research hotspot in system solutions. These applications include broadband wireless communications, broadband cable data services, and fiber-optic communications. In the above applications, the performance of high-speed DAC chips, especially dynamic performance, is a key factor in determining system performance.
  • the dynamic performance of the DAC measures the spectral quality of the chip's output signal.
  • the main indicators include spurious-free dynamic range (SFDR), third-order intermodulation (IM3), and signal-to-noise-distortion ratio (SNDR).
  • a tree structure is adopted in the DAC output signal path and the clock path, so that the timings at which the clock reaches the last stage D flip-flop are the same, and the delays of the respective current switches to the output contacts are consistent.
  • the disadvantage of this method is that it significantly increases the complexity of the layout, increases the parasitic capacitance, may limit the increase of the clock frequency, and cause the high frequency performance of the DAC to decrease; in addition, this method cannot eliminate the last stage D flip-flop. And the delay deviation caused by the transistor threshold voltage mismatch in the current switch;
  • this technology eliminates the correlation between various non-ideal effects and DAC input data, thereby improving SFDR.
  • the main disadvantage of this method is that the output signal can only be a return-to-zero code, which limits the application field.
  • this method essentially converts harmonic distortion into noise, and the signal-to-noise ratio does not improve.
  • the present invention provides a digital to analog converter having a delay offset detection and calibration function.
  • the digital-to-analog converter of the present invention having delay deviation detection and calibration functions includes a switch matrix 4, a path module, a delay deviation detecting circuit 7, and a state machine 8.
  • the switch matrix 4 includes: N+1 input ports and N+1 output ports, and under the control of the strobe signal, one of the input ports is connected to one of the output ports, N ⁇ 1.
  • the path module includes N data paths and one redundant path. The data path and the redundant path have the same structure, and each includes a delay control unit, and for each path, and the input end thereof is connected to the switch matrix.
  • An output port has two outputs connected to the input of the delay deviation detecting circuit and the output of the digital-to-analog converter.
  • the signal to be compared at the front end of the delay deviation detecting circuit 7 is connected to the calibration signal output terminal common to the N+1 paths, and the reference signal input is input to the second reference signal for obtaining a delay deviation between the signal to be compared and the reference signal.
  • the back end of the state machine 8 is connected to the delay deviation detecting circuit, and the front end thereof is connected to the switch matrix and the path module for outputting the strobe signal to the switch matrix and the path module; and generating the delay by using the delay difference of the delay deviation detecting circuit output.
  • the control signal is sent to the delay control unit in the path to be calibrated, and the output signal of the path to be calibrated is finally aligned with the second reference signal on the time axis by multiple iterations of feedback.
  • the variation of the delay deviation caused by the temperature drift or the change of the working environment can also be calibrated in time, so that the DAC can maintain high performance for a long time and stably;
  • the delay deviation detecting circuit only needs to obtain information with large or small delay, and the linearity requirement for the delay deviation detecting circuit is low, and the circuit is easy to implement.
  • FIG. 1 is a block diagram showing the structure of a digital-to-analog converter having a delay deviation detecting and calibration function according to an embodiment of the present invention
  • FIG. 2 is a schematic structural view of a current switching unit in the digital-to-analog converter shown in FIG. 1;
  • FIG. 3 is a schematic structural view of a delay deviation detecting circuit in the digital-to-analog converter shown in FIG. 1.
  • the invention adopts a feedback adjustment method to add a redundant path, thereby realizing the delay deviation detection and calibration of the digital-to-analog converter.
  • a digital to analog converter having a delay offset detection and calibration function is provided.
  • the digital-to-analog converter with delay deviation detection and calibration function in this embodiment includes:
  • Switch matrix (MUX Array) 4 including: N+1 input ports, N+1 outputs Port, under the control of the strobe signal, one of the input ports can be connected to one of the output ports, N ⁇ 1;
  • the path module includes N data paths and one redundant path.
  • the data path and the redundant path have the same structure, and each includes a delay control unit.
  • the input end is connected to an output in the switch matrix.
  • a port having two outputs connected to an output of the delay deviation detecting circuit and an output of the digital to analog converter;
  • the delay deviation detecting circuit 7 has a signal input to be compared at a front end thereof connected to a calibration signal output terminal (CalP/CalN) common to the N+1 paths, and a reference signal input inputting a second reference signal REF 2 for obtaining a signal to be compared and a delay deviation between the second reference signals REF 2 ;
  • the state machine 8 has a back end connected to the delay deviation detecting circuit, and its front end is connected to the switch matrix and N+1 paths for:
  • the signal corresponding to the path to be calibrated is input to the redundant path, and the reference signal is input to the path to be calibrated.
  • the signal outputted by the redundant path is output to the output end of the digital-to-analog converter as an output signal of the data path to be calibrated, and the signal outputted by the path to be calibrated is output to the delay deviation detecting circuit;
  • a redundant path is added to the channel module, and the redundant path has the same circuit structure as other data paths; in the calibration process, the input end of the path to be calibrated is connected to the reference signal through the switch matrix, The output signal of the path is compared with the reference signal to obtain a delay difference between the two, and the calibration is completed; the input end of the redundant channel is connected to the input signal corresponding to the path to be calibrated through the switch matrix, and the output end of the path is connected to The output of the digital-to-analog converter; during this process, other paths remain in normal operation; after that, the path to be calibrated is interchanged with one of the original data paths, and the output signal of the new path to be calibrated is compared with the reference signal, Redundant paths work in place of this path.
  • the data switch path can be calibrated in turn, Until all channel delays are aligned with the reference signal.
  • the total number of current switches connected to the output node remains the same, and the digital-to-analog converter output signal remains operational and will not be interrupted by the calibration process.
  • the delay deviation of the redundant channel itself can also be calibrated during the calibration process.
  • the channel is the channel to be calibrated, and its input terminal is connected to the reference signal through the switch matrix, and the output signal is output to the delay deviation detecting circuit for comparison with the reference signal to obtain a delay between the two. Poor and complete calibration; other paths remain functional during this process.
  • the digital-to-analog converter of the present embodiment processes the signal to be calibrated by the redundant path by calibrating the path to be calibrated by adding the same redundant path as the normal data path.
  • the normal operation of the digital-to-analog converter needs to be interrupted, which greatly facilitates the calibration of the digital-to-analog converter path.
  • the switch matrix 4 has (N+1) input ports I REF , I 0 ⁇ I N-1 ; and (N+1) output ports O REF , O 0 ⁇ O N-1 .
  • Switch matrix wherein, the first reference signal REF 1 is input to the input port I REF , the data signals B 0 BB N N-1 are input to the input ports I 0 ⁇ I N-1 ; the redundant path is connected to the output port O REF , N data paths Connect to output port O 0 ⁇ O N-1 .
  • the strobe signal Cal ⁇ N-1:0, REF> input at the control port can output an input port input signal to any non-conflicting output port under the control of the signal.
  • the input port I REF is associated with the output port O REF without calibration, and the input ports I 0 to I N-1 are respectively associated with the output ports O 0 to O N- The corresponding port in 1 corresponds.
  • the input port I n is connected to the output port O REF under the control of the strobe signal Cal ⁇ N-1:0, REF>, so that the data signal B n passes through the redundant path. Processing is performed; the input port I REF is connected to the output port O n , and the reference signal REF1 is processed through the calibration path to enter a subsequent delay deviation detecting circuit.
  • the path module there are N data paths and one redundant path. Among them, the functions of the data path and the redundant path are different, but the structure is the same.
  • each path includes a Re-Sampling DFF 3, a Digital-controlled Delay-line 2, and a Current Switch 1.
  • DFF REF DFF REF
  • DFF 0 DFF 1 , DFF 2 , ..., DFF n , ..., DFF N-3 , DFF N-2 , DFF N-1
  • Td REF N+1 digitally controlled delay lines
  • Td REF Td 0 , Td 1 , Td 2 , ..., Td n , ..., Td N-3 , Td N-2 , Td N-1
  • CS REF CS 0 , CS 1 , CS 2 , ..., CS n , ..., CS N-3 , CS N-2 , CS N-1 ).
  • the method includes: a resampling D flip-flop 3 for aligning a signal outputted by a corresponding output port (O n ) on the switch matrix to a sampling clock; 2.
  • the signal for re-sampling the output of the D flip-flop 3 is delayed according to the delay control signal (Dly n ) input by the state machine 8; the current switch unit 1 is connected to the output end of the digital control delay line, and the output is output.
  • the terminals are respectively connected to the output of the digital-to-analog converter or the input of the delay deviation detecting circuit, and the current signal generated by the unit current source is output to the digital-to-analog converter under the control of the strobe signal (Cal n ) corresponding to the path.
  • the function of the resampling D flip-flop 3 is to realign the signal output from the corresponding output port on the switch matrix to the sampling clock.
  • other alignment circuits such as latches and RS flip-flops can be used.
  • the numerical control delay line 2 is used for control, and the delay value of the numerical control delay line is controlled by the state machine 8 according to the delay deviation given by the delay deviation detecting circuit 7, and the signal passing through the path is delayed-adjusted.
  • the function of the digitally controlled delay line can also be implemented by an analog delay cell.
  • the analog delay unit can achieve continuous adjustment, the fluctuation of the control voltage (or current) will increase the jitter of the output signal (jitter). ).
  • the advantage of using a digitally controlled delay line is that smaller jitter can be achieved, avoiding the degradation of the DAC signal-to-noise ratio (SNR).
  • N+1 digitally controlled delay lines - Td REF , Td 0 , Td 1 , Td 2 , ..., Td n , ..., Td N-3 , Td N-2 , Td N-1 are respectively output by the state machine
  • the main function of the current switching unit 1 is to output the current signal generated by the unit current source to the corresponding node according to the input digital signal and the calibration control signal.
  • the current switching unit adopts an NMOS current switch structure, compared to a PMOS current switch junction. Structure, which has a faster switching speed, and its schematic diagram of the circuit is shown in Figure 2.
  • differential logic is used in each circuit switching unit, that is, the output of the circuit switching unit to the digital-to-analog converter is two differential signals -OP, ON, and the same, the output is
  • the delay deviation detection circuit is also two differential signals -CP, CN.
  • the method includes:
  • the first NMOS transistor N1 and the second NMOS transistor N2 are connected in common with a current source, and the gates of the two are respectively connected to the input differential signals -DP n and DN n ;
  • the third NMOS transistor N3 and the fourth NMOS transistor N4 are connected in common to the drain of the first NMOS transistor N1, and the gates of the two are respectively connected to the Cal n and The drain output signal CN of the third NMOS transistor N3 and the drain output signal of the fourth NMOS transistor N4 are ON;
  • a fifth NMOS transistor N5 and a sixth NMOS transistor N6 the sources of which are commonly connected to the drain of the second NMOS transistor N2, the gates of which are respectively connected to Cal n and
  • the sixth NMOS transistor N6 outputs a signal CP, and the drain output signal OP of the fifth NMOS transistor N5;
  • Cal n and They are the strobe signal corresponding to the nth path in the path module and its negative signal.
  • the differential signal pair -OP and ON are output to the digital-to-analog converter output, and the differential signal pair -CP and CN are output to the delay deviation detecting circuit.
  • the main difficulty is the design of the delay detection circuit with high sensitivity.
  • the traditional solution is to use a phase detector.
  • the difference in delay between the two input signals detected in the present invention is on the order of sub-ps, which is difficult to implement with conventional phase detector units.
  • the delay deviation should be less than 0.1 ps in order to achieve 12-bit resolution accuracy.
  • the resolution of the delay deviation detection circuit needs to be less than 0.1 ps.
  • TDA time difference amplifier
  • TDC time data converter
  • the front and rear stage circuits are isolated, and the input signal needs to be buffer amplified.
  • the differential signal pair -CP and CN are passed through the first buffer amplifier 5 and then connected to the delay deviation detecting circuit.
  • the signal input to be compared is 7 and the second reference signal REF 2 is passed through the second buffer amplifier 6 and is connected to the reference signal input of the delay deviation detecting circuit 7.
  • the first buffer amplifier 5 and the second buffer amplifier 6 the function and arrangement of the first buffer amplifier 5 and the second buffer amplifier 6 will be clear, and will not be described in detail herein.
  • the delay deviation detecting circuit 7 includes a time difference amplifier (TDA) 9 and a time data converter (TDC) 10.
  • TDA time difference amplifier
  • TDC time data converter
  • the signal to be compared and the second reference signal are respectively input to the input of the time difference amplifier
  • the output of the time difference amplifier is connected to the input of the time data converter
  • the output of the time data converter is connected to the state machine.
  • the time difference amplifier is used to amplify a delay deviation of the signal to be compared and the second reference signal.
  • Time data converter 10 is used to achieve quantization of the delay offset.
  • the time difference amplifier is used to amplify the delay deviation of the signal to be compared and the reference signal.
  • FIG. 3 shows a specific implementation method of a time difference amplifier based on an RS flip-flop and an exclusive OR gate.
  • NAND1/NAND2 and NAND3/NAND4 respectively constitute first and second RS flip-flops
  • the set end of the first RS flip-flop - S1 is connected to the output end of the first inverter INV1, and the reset end - R1 is connected to the second input end of the time difference amplifier, and the positive and negative output terminals of the flip-flop are respectively connected to the first difference
  • the two inputs of the OR gate XOR1, which are simultaneously connected to the capacitive element, and the magnitude of the capacitance affects the gain of the time difference amplifier
  • the set end of the second RS flip-flop - S2 is connected to the second input end of the time difference amplifier, and the reset end - R1 is connected to the output end of the second inverter INV2, and the positive and negative output terminals of the flip-flop are respectively connected to the second different
  • the input end of the first inverter INV1 is connected to the first input end of the time difference amplifier, and the signal to be compared is input;
  • the input end of the second inverter INV2 is connected to the second input end of the time difference amplifier, and the second reference signal is input;
  • the input terminals of the first XOR gate XOR1/XOR2 are respectively connected to the positive and negative output terminals of the first and second RS flip-flops, and the output end thereof is the output end of the time difference amplifier.
  • the time difference amplifier For the time difference amplifier, if the time difference of the input signal is small, when the rising edge of the signal comes, the flip-flop will enter the metastable state, and the time when the flip-flop exits the metastable state depends on the input signal. The size of the time difference. The output signal of the TDA is flipped in turn at the moment of exiting the metastable state, and the amplification of the delay deviation is realized.
  • the time difference amplifier can resolve delay differences below 0.1 ps to meet the requirements of the system.
  • the time data converter 10 is for quantizing the delay offset in the form of an analog signal to obtain a delay offset (T 0 -T i ) in the form of a digital signal.
  • a delay offset T 0 -T i
  • Figure 3 shows a basic implementation of a time data converter.
  • the requirement for the number of quantization bits is not high, and the complexity of the circuit and the convergence speed of the calibration algorithm can be used, and a 4-bit quantizer can be used.
  • the state machine 8 has a back end connected to the delay deviation detecting circuit, and its front end is connected to the switch matrix and N+1 paths for:
  • the digital-to-analog converter of the embodiment adopts a feedback adjustment mode, and the delay deviation detecting circuit only needs to obtain information with a large or small delay, and the linearity requirement for the delay deviation detecting circuit is low, and the circuit is easy to implement. Greatly reduce the difficulty of circuit design.
  • the data signal and the reference signal for calibration (square wave signal) are connected in common to the switch matrix (MUX Array) 4; the switch matrix is under the control of the calibration strobe signal (Cal ⁇ N-1:0, REF>) Adjusting the order of the output signals, feeding the reference signal to the channel to be calibrated, and connecting the input signal of the channel to be calibrated to the redundant channel;
  • the digital control delay line 2 and the current switching unit 1 of the path to be calibrated After the reference signal REF1 passes through the resampling D flip-flop 3, the digital control delay line 2 and the current switching unit 1 of the path to be calibrated, it is connected to an input terminal of the delay deviation detecting circuit 7 through the first buffer amplifier 5, and the second reference The signal REF 2 is connected to the other input of the delay deviation detecting circuit through the second buffer amplifier 6, and the second reference signal REF 2 is generated by the first reference signal REF 1 through the delay circuit;
  • the delay deviation detecting circuit 7 compares the delay deviations of the two input signals and quantizes the value of the deviation. Thereafter, the state machine 8 adjusts the numerical control delay line according to the magnitude of the delay deviation, and detects the magnitude of the delay deviation again after the adjustment is completed, and repeats it repeatedly until the detection circuit cannot detect the delay deviation or is less than the set threshold value;
  • the path is interchanged with one of the original data paths, and the new path to be calibrated is calibrated, and the new path to be calibrated is replaced by the redundant path.
  • the data switching paths can be calibrated in sequence until all channel delays are aligned with the second reference signal REF 2 .
  • the output delays of all current switching units are aligned with the second reference signal REF 2 .
  • the process of calibrating the channel switching is completed in one clock cycle to ensure the normal output of the DAC, and the calibration process does not need to interrupt the normal operation of the system.
  • the digital-to-analog converter of the present embodiment can not only calibrate the general delay deviation, but also can perform the delay variation caused by the temperature drift or the change of the working environment, and the delay deviation caused by the inconsistent length of the interconnection line. Detection and calibration greatly improve the performance of the digital-to-analog converter.
  • MOS transistors can be replaced with BJT transistors
  • D flip-flops can be replaced by latches or RS flip-flops
  • the present invention adopts a feedback adjustment method, which requires low linearity for the delay deviation detecting circuit and is easy to implement, and the delay deviation caused by the inconsistent length of the interconnect line can also be detected and calibrated.
  • the invention adds a redundant path, and does not need to interrupt the normal operation of the DAC during the calibration process, and the delay deviation caused by the temperature drift or the working environment change can also be calibrated in time, so that the DAC remains stable for a long time. Performance work has a good prospect of promotion and application.

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Abstract

一种具有延迟偏差检测和校准功能的数模转换器，该数模转换器增加了一路结构与正常数据通路相同的冗余通路，在对待校准通路进行校准时，由冗余通路对待校准通路的信号进行处理，从而不需要中断数模转换器的正常工作，极大方便了数模转换器通路的校准。此外，该数模转换器采用反馈调节的方式，对于延迟偏差检测电路（7）的线性度要求较低，易于电路实现，并且还能够校准由温度漂移或工作环境变化所造成的延迟偏差变化及由互连线的长度不一致造成的延迟偏差。

Description

具有延迟偏差检测和校准功能的数模转换器 技术领域
本发明涉及电子电路技术领域，尤其涉及一种具有延迟偏差检测和校准功能的数模转换器。
背景技术
数模转换器(DAC)是将数字信号转换成模拟信号的电路。在通信系统应用中，采用高速、高性能DAC芯片不仅使得系统结构大大简化，同时提高了系统设计的灵活性和可移植性。正是这个原因，在许多领域，高速、高性能DAC芯片正逐步取代传统模拟电路，成为系统解决方案中新的研究热点。这些应用领域包括宽带无线通信、有线电缆宽带数据服务、光纤通信等。在上述应用领域中，高速DAC芯片的性能，尤其是动态性能，是决定系统性能的关键因素。
DAC的动态性能(dynamic performance)衡量的是芯片输出信号的频谱质量，主要指标包括无杂散动态范围(SFDR)、三阶交调(IM3)、信号与噪声失真比(SNDR)等。
近年来，随着微电子工艺的发展以及电路设计技术的进步，采样率达到GSps(Sample-per-second)的高速电流舵型(high speed current steering)DAC芯片受到越来越多关注。
对于高速电流舵型DAC芯片而言，通常其动态性能受到以下几个方面因素的影响，包括：电流源失配(mismatch-of-current-sources)、与数据相关的输出阻抗变化(data-dependent-output-resistance-variation)、与数据相关的延迟偏差(data-dependent-delay-variation)等。上述影响因素中，第一个因素(电流源失配)和第二个因素(与数据相关的输出阻抗变化)，已经有成熟的解决方案。对于第三个因素，目前尚无较好的解决方案。延迟偏差是指，由于版图或者晶体管开关速度不一致，所造成的DAC的各个电流开关单元到达输出接点的延迟不同的现象。
对于数据相关的延迟偏差，目前主要有以下几种解决思路：
1、在DAC输出信号路径和时钟路径中采用树形结构，使得时钟到达最后一级D触发器的时刻一致，以及各个电流开关到输出接点的延迟一致。 这种方法的缺点在于显著增加了版图的复杂度，寄生电容增大，可能限制时钟频率的提高，并引起DAC的高频性能的降低；另外，这种方法也不能消除最后一级D触发器以及电流开关中，由于晶体管阈值电压失配所引起延迟偏差；
2、采用数字随机归零技术，这种技术消除了各种非理想效应与DAC输入数据的相关性，从而提高SFDR。这种方法的主要缺点在于，输出信号只能为归零码，限制了应用领域；其次，这种方法本质是将谐波失真转换成噪声，信噪比并不会改善。
发明内容
(一)要解决的技术问题
鉴于上述技术问题，本发明提供了一种具有延迟偏差检测和校准功能的数模转换器。
(二)技术方案
本发明具有延迟偏差检测和校准功能的数模转换器包括：开关矩阵4、通路模块、延迟偏差检测电路7和状态机8。其中：开关矩阵4包括：N+1个输入端口和N+1个输出端口，其在选通信号的控制下，将其中之一的输入端口与其中之一的输出端口连通，N≥1。通路模块，包括N条数据通路和1条冗余通路，数据通路和冗余通路的结构相同，均包括一延迟控制单元，且对于每一条通路而言，且其输入端连接至开关矩阵中的一输出端口，其两个输出端分别连接至延迟偏差检测电路的输入端和数模转换器的输出端。延迟偏差检测电路7前端的待比较信号入口连接至N+1条通路共同的校准信号输出端，参考信号入口输入第二参考信号，用于获得待比较信号与参考信号之间的延迟偏差。状态机8后端连接至延迟偏差检测电路，其前端连接至开关矩阵和通路模块，用于：输出选通信号至开关矩阵和通路模块；并利用延迟偏差检测电路输出的延迟差，生成延时控制信号，并将该延时控制信号发送至待校准通路中的延迟控制单元，通过多次迭代反馈，最终使该待校准通路的输出信号与第二参考信号在时间轴上对准。
(三)有益效果
从上述技术方案可以看出，本发明具有延迟偏差检测和校准功能的数模转换器具有以下有益效果：
(1)增加了一路结构与正常数据通路相同的冗余通路，在对待校准通路进行校准时，由冗余通路对待校准通路进行的信号进行处理，从而不需要中断数模转换器的正常工作，极大方便了数模转换器通路的校准；
(2)由温度漂移或工作环境变化所造成的延迟偏差变化，也能及时被校准，从而使DAC长期稳定的保持高性能工作；
(3)由互连线的长度不一致造成的延迟偏差也能被检测和校准，因此在版图设计时，可以按照最短路径互联的原则，从而减小寄生电容，有助于提高时钟频率，实现更高的DAC采样率；
(4)采用反馈调节的方式，延迟偏差检测电路只需要获得延迟偏大或偏小的信息，对于延迟偏差检测电路的线性度要求较低，易于电路实现。
附图说明
图1为根据本发明实施例具有延迟偏差检测和校准功能的数模转换器的结构示意图；
图2为图1所示数模转换器中电流开关单元的结构示意图；
图3为图1所示数模转换器中延迟偏差检测电路的结构示意图。
【符号说明】
1-电流开关单元；          2-数控延时线；
3-重采样D触发器；         4-开关矩阵；
5-第一缓冲放大器；        6-第二缓冲放大器；
7-延迟偏差检测电路        8-状态机；
9-时间差放大器；          10-时间数据转换器。
具体实施方式
本发明采用反馈调节的方式，增加了一路冗余通路，从而实现了数模转换器的延迟偏差检测和校准。
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明进一步详细说明。
在本发明的一个示例性实施例中，提供了一种具有延迟偏差检测和校准功能的数模转换器。请参照图1，本实施例具有延迟偏差检测和校准功能的数模转换器包括：
开关矩阵(MUX Array)4，包括：N+1个输入端口、N+1个输出端 口，其在选通信号的控制下，可将其中之一的输入端口与其中之一的输出端口连通，N≥1；
通路模块，包括N条数据通路和1条冗余通路，数据通路和冗余通路的结构相同，均包括一延迟控制单元，对于每一条通路而言，其输入端连接至开关矩阵中的一输出端口，其两个输出端连接至延迟偏差检测电路的输出端和数模转换器的输出端；
延迟偏差检测电路7，其前端的待比较信号入口连接至N+1条通路共同的校准信号输出端(CalP/CalN)，参考信号入口输入第二参考信号REF2，用于获得待比较信号与第二参考信号REF2之间的延迟偏差；
状态机8，其后端连接至延迟偏差检测电路，其前端连接至开关矩阵和N+1条通路，用于：
(1)输出选通信号Cal<N-1：0，REF>至开关矩阵和N+1条通路，其中，
在开关矩阵中，将待校准通路对应的信号输入冗余通路，将参考信号输入待校准通路，
在N+1条通路的输出端，冗余通路输出的信号作为待校准数据通路的输出信号输出至数模转换器的输出端，待校准通路输出的信号被输出至延迟偏差检测电路；
(2)利用延迟偏差检测电路输出的延迟差，生成延时控制信号，并将该延时控制信号发送至待校准通路中的延迟控制单元，通过多次迭代反馈，最终使该待校准通路的输出信号与第二参考信号在时间轴上对准；
(3)在完成该待校准通路的校准之后，进行下一待校准通路的校准。
可见，本发明中，在通道模块增加了一路冗余通路，该冗余通路与其他的数据通路具有相同的电路结构；在校准过程中，待校准通路的输入端通过开关矩阵连接到参考信号，该通路的输出信号与参考信号进行比较，获得两者之间的延迟差，并完成校准；冗余通道的输入端通过开关矩阵连接到待校准通路对应的输入信号，该通路的输出端连接到数模转换器的输出端；在此过程中其他通路保持正常工作；之后，待校准通路与原数据通路中的一路互换，将新的待校准通路的输出信号与参考信号进行比较校准，由冗余通路代替该通路工作。类似的，可依次对数据开关通路进行校准， 直到所有通道延迟都与参考信号对齐。在校准过程中，连接到输出节点的电流开关总数目保持不变，数模转换器输出信号保持正常工作，不会因为校准过程而中断。
需要说明的是，在校准过程中冗余通道自身的延迟偏差也可被校准。在进行冗余通道自身校准时，该通道即为待校准通道，其输入端通过开关矩阵连接到参考信号，输出信号被输出至延迟偏差检测电路与参考信号进行比较，获得两者之间的延迟差，并完成校准；在此过程中其他通路保持正常工作。
由上述分析可知，本实施例数模转换器通过增加了一路结构与正常数据通路相同的冗余通路，在对待校准通路进行校准时，由冗余通路对待校准通路进行的信号进行处理，从而不需要中断数模转换器的正常工作，极大方便了数模转换器通路的校准。
请参照图1，开关矩阵4是一具有(N+1)个输入端口IREF、I0～IN-1；以及(N+1)个输出端口OREF、O0～ON-1，的开关矩阵。其中，第一参考信号REF1输入至输入端口IREF，数据信号B0～BN-1输入至输入端口I0～IN-1；冗余通路连接至输出端口OREF，N条数据通路连接至输出端口O0～ON-1。在控制端口输入的选通信号Cal<N-1：0，REF>，在该信号的控制下，可将一输入端口输入的信号输出至任一不冲突的输出端口。
在本实施例中，为简便起见，在未进行校准的情况下，将输入端口IREF与输出端口OREF对应，将输入端口I0～IN-1分别与输出端口O0～ON-1中的相应端口对应。在对第n条通路进行校准时，在选通信号Cal<N-1：0，REF>的控制下，将输入端口In与输出端口OREF相连通，使数据信号Bn通过冗余通路进行处理；将输入端口IREF与输出端口On相连通，使参考信号REF1经由校准通路进行处理，进入后续的延迟偏差检测电路。
可以理解的是，本实施例仅给出了一种简便的，易于实现的开关矩阵实现方式。本领域技术人员也可以采用其他的开关矩阵控制方式，此处不对其进行限制。
在通路模块中，包括N条数据通路和1条冗余通路。其中，数据通路和冗余通路的功能虽然不同，但其结构相同。
请参照图1，每一通路包括：重采样D触发器(Re-Sampling DFF)3、 数控延迟线(Digital-controlled Delay-line)2和电流开关单元(Current Switch)1。对于整个通路模块来讲，其包括：N+1个重采样D触发器(DFFREF、DFF0、DFF1、DFF2、……、DFFn、……、DFFN-3、DFFN-2、DFFN-1)；N+1个数控延迟线(TdREF、Td0、Td1、Td2、……、Tdn、……、TdN-3、TdN-2、TdN-1)；以及N+1个电流开关单元(CSREF、CS0、CS1、CS2、……、CSn、……、CSN-3、CSN-2、CSN-1)。
以所述通路模块中的第n条通路为例，其包括：重采样D触发器3，其用于将开关矩阵上相应输出端口(On)输出的信号对齐至采样时钟；数控延时线2，用于将重采样D触发器3的输出的信号按照状态机8输入的延时控制信号(Dlyn)进行延时；电流开关单元1，其输入端连接数控延迟线的输出端，输出端分别连接至数模转换器输出端或延迟偏差检测电路输入端，其在该条通路对应的选通信号(Caln)的控制下，将单位电流源产生的电流信号输出至数模转换器输出端口或延迟偏差检测模块的输入端口。其中，n＝0，1，……，N-1。
在一条通路中，重采样D触发器3的作用主要是将开关矩阵上相应输出端口输出的信号重新对齐到采样时钟。除了采用D触发器之外，还可以采用锁存器、RS触发器等其他的对齐电路。
本实施例中，采用数控延迟线2进行控制，在由状态机8根据延迟偏差检测电路7给出的延迟偏差大小控制数控延迟线的延迟值，对通过通路的信号进行延迟调节。
需要说明的是，数控延迟线的功能也可以采用模拟延迟单元(Analog Delay Cell)实现，虽然模拟延迟单元可以实现连续的调节，但控制电压(或电流)的波动将增加输出信号的抖动(jitter)。采用数控延迟线的好处是可以获得更小的抖动，避免DAC信噪比(SNR)的恶化。其中，N+1个数控延迟线-TdREF、Td0、Td1、Td2、……、Tdn、……、TdN-3、TdN-2、TdN-1分别由状态机输出的相应的延迟控制信号DlyREF、Dly0、Dly1、Dly2、……、Dlyn、……、DlyN-3、DlyN-2、DlyN-1，即Dly<N-1：0，REF>控制。
在一条通路中，电流开关单元1的主要作用是根据输入数字信号和校准控制信号，将单位电流源产生的电流信号输出到对应的节点。本实施例中，电流开关单元采用NMOS电流开关结构，相比于PMOS电流开关结 构，其具有更快的开关速度，其电路原理示意图请参照图2。
需要说明的是，为了提高电路的抗干扰性，在每一个电路开关单元采用差分逻辑，即电路开关单元输出至数模转换器输出端为两路差分信号-OP、ON，同样，其输出至延迟偏差检测电路的也为两路差分信号-CP、CN。
请参照图2，以第n条通路中的电流开关单元为例，其包括：
第一NMOS管N1和第二NMOS管N2，两者的源极共同连接电流源，两者的栅极分别连接到输入差分信号-DPn和DNn；
第三NMOS管N3和第四NMOS管N4，两者的源极共同连接至第一NMOS管N1的漏极，两者的栅极分别连接至Caln和
Figure PCTCN2015096535-appb-000001
第三NMOS管N3的漏极输出信号CN，第四NMOS管N4的漏极输出信号ON；
第五NMOS管N5和第六NMOS管N6，两者的源极共同连接至第二NMOS管N2的漏极，两者的栅极分别连接至Caln和
Figure PCTCN2015096535-appb-000002
第六NMOS管N6输出信号CP，第五NMOS管N5的漏极输出信号OP；
其中，Caln和
Figure PCTCN2015096535-appb-000003
分别为通路模块中第n条通路对应的选通信号及其负信号。差分信号对-OP和ON被输出至数模转换器输出端，差分信号对-CP和CN被输出至延迟偏差检测电路。
在校准电路的设计中，主要难点是与高灵敏度的延迟偏差检测电路设计。要鉴别两个存在相位差异的方波信号，传统的解决方案是采用鉴相器。然而，在本发明中进行检测的两个输入信号延迟差为亚ps量级，传统的鉴相器单元很难实现。例如，对于采样率达到4GSps的DAC芯片，为了达到12bit的分辨率精度，其延迟偏差应小于0.1ps。达到为了达到较高的调节精度，延迟偏差检测电路的分辨率需要小于0.1ps。为了克服上述困难，一个可行的方案是采用时间差放大器(TDA)和时间数据转换器(TDC)实现高灵敏度的延迟偏差检测。借助于时间差放大器(TDA)，先将延迟偏差tdi放大至K*tdi，其中K为时间差放大器增益，而后再送到时间数据转换器(TDC)中，对放大后的延迟偏差进行量化，从而降低了对TDC分辨率的要求。
需要说明的是，为了提高延迟偏差检测电路7的检测精度，隔离前后级电路，需要对输入信号进行缓冲放大，差分信号对-CP和CN经过第一 缓冲放大器5后被接入延迟偏差检测电路7的待比较信号入口，而第二参考信号REF2经过第二缓冲放大器6后被接入延迟偏差检测电路7的参考信号入口。关于第一缓冲放大器5和第二缓冲放大器6，本领域技术人员应当清楚其功能和设置方式，此处不再详细说明。
请参照图3，延迟偏差检测电路7包括：时间差放大器(TDA)9和时间数据转换器(TDC)10。其中，待比较信号和第二参考信号分别输入时间差放大器的输入端，时间差放大器的输出端连通至时间数据转换器的输入端，而时间数据转换器的输出端连接到状态机。时间差放大器用于放大待比较信号与第二参考信号的延迟偏差。时间数据转换器10用于实现延迟偏差的量化。
时间差放大器用于放大待比较信号与参考信号的延迟偏差。请继续参照图3，图中给出了一种基于RS触发器和异或门的时间差放大器具体实现方法。
与非门NAND1/NAND2与NAND3/NAND4分别构成第一、第二RS触发器；
第一RS触发器的置位端～S1与第一反相器INV1的输出端相连，复位端～R1连接时间差放大器的第二个输入端，该触发器的正负输出端分别连接第一异或门XOR1的两个输入端，该端口同时连接到电容元件，电容值的大小影响时间差放大器的增益；
第二RS触发器的置位端～S2与时间差放大器的第二个输入端相连，复位端～R1连接第二反相器INV2的输出端，该触发器的正负输出端分别连接第二异或门XOR2的两个输入端，该端口同时连接到电容元件，电容值的大小影响时间差放大器的增益；
第一反相器INV1的输入端连接时间差放大器的第一个输入端，输入待比较信号；第二反相器INV2的输入端连接时间差放大器的第二个输入端，输入第二参考信号；
第一异或门XOR1/XOR2的输入端分别与第一、第二RS触发器的正负输出端相连，其输出端为时间差放大器的输出端。
对于该时间差放大器，如果输入信号的时间差很小，当信号的上升沿到来时，触发器将进入亚稳态，触发器退出亚稳态的时间取决于输入信号 时间差的大小。TDA的输出信号在退出亚稳态的时刻依次翻转，实现延迟偏差的放大。该时间差放大器可分辨低于0.1ps的延迟差，满足本系统的要求。
时间数据转换器10用于将模拟信号形式的延迟偏差量化，得到数字信号形式的延迟偏差(T0～Ti)。请继续参照图3，图中给出了一种时间数据转换器的基本实现方法。在本实施案例中，由于校准系统采用反馈调节的方法，对量化位数的要求并不高，兼顾电路的复杂度和校准算法的收敛速度，可采用4bit的量化器。
状态机8，其后端连接至延迟偏差检测电路，其前端连接至开关矩阵和N+1条通路，用于：
(1)输出选通信号Cal<N-1：0，REF>至开关矩阵和N+1条通路，其中，在开关矩阵中，将待校准通路对应的信号输入冗余通路，将参考信号输入待校准通路，在N+1条通路的输出端，冗余通路输出的信号作为待校准数据通路的输出信号输出至数模转换器的输出端，待校准通路输出的信号被输出至延迟偏差检测电路；
(2)利用延迟偏差检测电路输出的延迟差，生成延时控制信号，并将该延时控制信号发送至待校准通路中的延迟控制单元，通过多次迭代反馈，最终使该待校准通路的输出信号与第二参考信号在时间轴上对准；
(3)在完成该待校准通路的校准之后，进行下一待校准通路的校准。
由上述分析可知，本实施例数模转换器采用反馈调节的方式，延迟偏差检测电路只需要获得延迟偏大或偏小的信息，对于延迟偏差检测电路的线性度要求较低，易于电路实现，极大的降低了电路设计的难度。
以下介绍本实施例数模转换器的具体工作过程：
(1)数据信号和用于校准的参考信号(方波信号)共同连接到开关矩阵(MUX Array)4；开关矩阵在校准选通信号(Cal＜N-1：0，REF＞)的控制下，调整输出信号的顺序，将参考信号输送到需要校准的通道，同时将待校准通道的输入信号连接到冗余通道；
(2)待校准通路的原输入信号经过开关矩阵连接到冗余通道，其输出信号连接到数模转换器输出端口；在这个过程中，除了待校准通道和冗余通道外的其他数据通道，保持正常工作模式，其输出信号均连接到数模 转换器输出端口；
(3)参考信号REF1经过待校准通路的重采样D触发器3、数控延迟线2和电流开关单元1后，通过第一缓冲放大器5连接到延迟偏差检测电路7的一个输入端，第二参考信号REF2通过第二缓冲放大器6连接到延迟偏差检测电路的另一个输入端，该第二参考信号REF2由第一参考信号REF1经过延时电路产生；
(4)延迟偏差检测电路7对比两个输入信号的延迟偏差，并对偏差的值进行量化。之后，状态机8根据延迟偏差的大小调节数控延迟线，并在完成调节后再次检测延迟偏差的大小，反复多次，直到检测电路无法检出延迟偏差或小于设定的门限值；
(5)待检测通道校准完成后，该通路与原数据通路中的一路互换，对新的待校准通路进行校准，由冗余通路代替新的待校准通路工作。类似的，可依次对数据开关通路进行校准，直到所有通道延迟都与第二参考信号REF2对齐。在各个通道依次完成校准后，所有电流开关单元的输出延迟均与第二参考信号REF2对齐。校准通道切换的过程在一个时钟周期内完成，以保证DAC正常输出，校准过程不需要中断系统正常工作。
由上述分析可知，本实施例数模转换器不仅能校准一般的延迟偏差，而且对由温度漂移或工作环境变化所造成的延迟偏差变化、由互连线的长度不一致造成的延迟偏差同样能够进行检测和校准，从而极大的提升了数模转换器的性能。
至此，已经结合附图对本实施例进行了详细描述。依据以上描述，本领域技术人员应当对本发明具有延迟偏差检测和校准功能的数模转换器有了清楚的认识。
需要说明的是，在附图或说明书正文中，未绘示或描述的实现方式，均为所属技术领域中普通技术人员所知的形式，并未进行详细说明。此外，上述对各元件和方法的定义并不仅限于实施例中提到的各种具体结构、形状或方式，本领域普通技术人员可对其进行简单地更改或替换，例如：
(1)MOS晶体管可以用BJT晶体管代替；
(2)D触发器可以用锁存器或RS触发器来代替；
(3)关于时间差放大器与时间数据转换器，本领域技术人员可以根 据需要选择其他的结构；
(4)本文可提供包含特定值的参数的示范，但这些参数无需确切等于相应的值，而是可在可接受的误差容限或设计约束内近似于相应值。
综上所述，本发明采用反馈调节的方式，对于延迟偏差检测电路的线性度要求较低，易于电路实现，同时由互连线的长度不一致造成的延迟偏差也能被检测和校准，此外，本发明增加了一路冗余通路，在校准的过程中不需要中断DAC的正常工作，由温度漂移或工作环境变化所造成的延迟偏差变化，也能及时被校准，从而使DAC长期稳定的保持高性能工作，具有较好的推广应用前景。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种具有延迟偏差检测和校准功能的数模转换器，其特征在于，包括：开关矩阵(4)、通路模块、延迟偏差检测电路(7)和状态机(8)，其中：
    开关矩阵(4)包括：N+1个输入端口和N+1个输出端口，其在选通信号的控制下，将其中之一的输入端口与其中之一的输出端口连通，N≥1；
    通路模块，包括N条数据通路和1条冗余通路，数据通路和冗余通路的结构相同，均包括一延迟控制单元，且对于每一条通路而言，且其输入端连接至开关矩阵中的一输出端口，其两个输出端分别连接至延迟偏差检测电路的输入端和数模转换器的输出端；
    延迟偏差检测电路(7)，其前端的待比较信号入口连接至N+1条通路共同的校准信号输出端，参考信号入口输入第二参考信号，用于获得待比较信号与参考信号之间的延迟偏差；
    状态机(8)，其后端连接至延迟偏差检测电路，其前端连接至开关矩阵和通路模块，用于：输出选通信号至开关矩阵和通路模块；并利用延迟偏差检测电路输出的延迟差，生成延时控制信号，并将该延时控制信号发送至待校准通路中的延迟控制单元，通过多次迭代反馈，最终使该待校准通路的输出信号与第二参考信号在时间轴上对准。
  2. 根据权利要求1所述的数模转换器，其特征在于：所述状态机输出选通信号至开关矩阵和通路模块；
    所述开关矩阵在选通信号的控制下，将待校准通路对应的信号输入冗余通路，将第一参考信号输入待校准通路；
    所述通路模块在选通信号的控制下完成如下操作：将冗余通路输出的信号代替待校准数据通路的输出信号输出至数模转换器的输出端，将待校准通路输出的信号被输出至延迟偏差检测电路。
  3. 根据权利要求2所述的数模转换器，其特征在于：
    所述开关矩阵(4)具有N+1个输入端口IREF、I0～IN-1；以及N+1个输出端口OREF、O0～ON-1，其中，第一参考信号(REF1)输入至输入端口IREF，数据信号B0～BN-1输入至输入端口I0～IN-1；冗余通路连接至输出端口 OREF，N条数据通路连接至输出端口O0～ON-1；
    其中，在控制端口输入的选通信号Cal<N-1：0，REF>的控制下，可将一输入端口输入的信号输出至任一不冲突的输出端口。
  4. 根据权利要求3所述的数模转换器，其特征在于：
    在未进行校准的情况下，将输入端口IREF与输出端口OREF对应，将输入端口I0～IN-1分别与输出端口O0～ON-1中的相应端口对应；
    在对第n条通路进行校准时，在选通信号Cal<N-1：0，REF>的控制下，将输入端口In与输出端口OREF相连通，使数据信号Bn通过冗余通路进行处理，并输出至数模转换器的输出端；将输入端口IREF与输出端口On相连通，使第一参考信号(REF1)经由待校准通路进入后续的延迟偏差检测电路；
    其中，n＝0，1，……，N-1。
  5. 根据权利要求1所述的数模转换器，其特征在于，所述通路模块中，数据通路和冗余通路中的延时控制单元为数控延时线；
    对于所述通路模块中的第n条通路，其包括：
    对齐电路，用于将开关矩阵上相应输出端口(On)输出的信号对齐至采样时钟；
    所述数控延时线，用于将对齐电路输出的信号按照状态机(8)输入的延时控制信号(Dlyn)进行延时；
    电流开关单元，其输入端连接数控延迟线的输出端，输出端分别连接至数模转换器输出端或延迟偏差检测电路输入端，其在该条通路对应的选通信号(Caln)的控制下，将单位电流源产生的电流信号输出至数模转换器输出端口或延迟偏差检测模块的输入端口；
    其中，n＝0，1，……，N-1。
  6. 根据权利要求5所述的数模转换器，其特征在于，所述对齐电路为重采样D触发器、锁存器或RS触发器。
  7. 根据权利要求5所述的数模转换器，其特征在于，所述电流开关单元包括：
    第一NMOS管(N1)和第二NMOS管(N2)，两者的源极共同连接电流源，两者的栅极分别连接到输入差分信号-DPn和DNn；
    第三NMOS管(N3)和第四NMOS管(N4)，两者的源极共同连接至第一NMOS管(N1)的漏极，两者的栅极分别连接至选通信号-Caln和
    Figure PCTCN2015096535-appb-100001
    第三NMOS管(N3)的漏极输出信号CN，第四NMOS管(N4)的漏极输出信号ON；
    第五NMOS管(N5)和第六NMOS管(N6)，两者的源极共同连接至第二NMOS管(N2)的漏极，两者的栅极分别连接至选通信号-Caln和
    Figure PCTCN2015096535-appb-100002
    第六NMOS管(N6)输出信号CP，第五NMOS管(N5)的漏极输出信号OP；
    其中，Caln和
    Figure PCTCN2015096535-appb-100003
    分别为通路模块中第n条通路对应的选通信号及其负信号，差分信号对-OP和ON被输出至数模转换器输出端，差分信号对-CP和CN被输出至延迟偏差检测电路。
  8. 根据权利要求1至7中任一项所述的数模转换器，其特征在于，所述延迟偏差检测模块包括：
    时间差放大器(9)，其前端的待比较信号入口连接至N+I条通路共同的校准信号输出端，输入待比较信号；参考信号入口输入第二参考信号，用于放大待比较信号与第二参考信号的延迟偏差；
    时间数据转换器(10)，其前端连接至时间差放大器(9)，其后端连接至状态机(8)，用于实现延迟偏差的量化，并把量化后的延迟偏差发送至状态机；
    其中，所述第二参考信号由第一参考信号经过延时产生。
  9. 根据权利要求8所述的数模转换器，其特征在于，所述时间差放大器(9)包括：
    第一反相器(INV1)和第二反相器(INV2)，两者的输入端分别输入待比较信号和第二参考信号；
    第一RS触发器，其置位端(～S1)与第一反相器(INV1)的输出端相连接，其复位端(～R1)输入第二参考信号；
    第二RS触发器，其置位端(～S1)输入第二参考信号，其复位端(～R1)与第二反相器(INV2)的输出端相连接；
    第一异或门(XOR1)，其两输入端分别与第一RS触发器的正、负输出端相连，其输出端作为时间差放大器的第一输出端；
    第二异或门(XOR2)，其两输入端分别与第二RS触发器的正、负输出端相连，其输出端作为时间差放大器的第二输出端。
  10. 根据权利要求1至7中任一项所述的数模转换器，其特征在于，
    所述状态机(8)，还用于在完成当前待校准通路的校准之后，进行下一待校准通路的校准。
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