WO2017088229A1 - 显示面板与阵列栅极驱动电路 - Google Patents

显示面板与阵列栅极驱动电路 Download PDF

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Publication number
WO2017088229A1
WO2017088229A1 PCT/CN2015/098768 CN2015098768W WO2017088229A1 WO 2017088229 A1 WO2017088229 A1 WO 2017088229A1 CN 2015098768 W CN2015098768 W CN 2015098768W WO 2017088229 A1 WO2017088229 A1 WO 2017088229A1
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Prior art keywords
thin film
gate
film transistor
output
output end
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English (en)
French (fr)
Inventor
黄笑宇
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/906,374 priority Critical patent/US9779683B2/en
Publication of WO2017088229A1 publication Critical patent/WO2017088229A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed

Definitions

  • the present invention relates to a display panel and an array gate driving circuit, particularly for a thin film transistor liquid crystal display (Thin Film) Transistor Liquid Crystal Display (TFT-LCD) display panel and array gate drive circuit.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the gate drive chip is integrated in the array substrate.
  • the display panel 1 includes a display area 10 , a fan-out area 11 , and a source-chip on film (Source-Chip On Film, S-COF) 12, a printed circuit board (PCB) 13, an array gate driving circuit is disposed between the display area and the fan-out area.
  • S-COF Source-Chip On Film
  • PCB printed circuit board
  • Gate drive of a conventional liquid crystal panel (gate The driver scans the gate of the thin film transistor (TFT) and charges the pixel electrode through the data line.
  • the liquid crystal rotates under the action of the electric field of the pixel to rotate the light for display.
  • the long charging time results in a long liquid crystal response time, which exacerbates the crosstalk phenomenon between the pixel electrodes.
  • Fan out area on the gate side of the conventional array gate drive circuit of the present invention (Fan Out Area) Add additional logic cells to achieve precharge between adjacent gate lines to increase high pixel charging speed.
  • An embodiment of the invention provides a display panel having a display area and a fan-out area, and an array of gate drives (Gate On Array, a GOA) circuit, comprising: a multi-stage pre-charging module, configured to connect an output end of two adjacent gates of the array gate driving circuit to adjacent two gates of the display area respectively in the fan-out area a line output, the pre-charging module of each stage includes a first thin film transistor, a source and a gate of the first thin film transistor are connected to a first output end of the gate, and a drain is connected to a first gate line output; a second thin film transistor, a gate of the second thin film transistor is connected to the first output end of the gate, and a drain is connected to the upper stage a pre-charging module; a third thin film transistor, a gate of the third thin film transistor is connected to the first output end of the gate, and a drain is connected to the first gate line output; a fourth thin film transistor, a drain of the fourth thin film transistor is connected to
  • the first gate output terminal is at a high voltage level and the second gate output terminal is at a low voltage level
  • the first thin film transistor, the third thin film transistor, and the The fourth thin film transistor is turned on
  • the second thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are turned off
  • the first gate line output is The second gate line outputs are all high voltage levels.
  • the first gate output terminal is at a low voltage level and the second gate output terminal is at a high voltage level
  • the first thin film transistor, the third thin film transistor, and the The fourth thin film transistor is turned off
  • the second thin film transistor, the fifth thin film transistor, and the sixth thin film transistor are turned on
  • the first gate line output is a low voltage
  • the second gate line output is a high voltage level.
  • the first gate output end and the second gate output end are both at a low voltage level
  • the first thin film transistor, the third thin film transistor, and the fifth thin film transistor And the sixth thin film transistor is turned off, the second thin film transistor and the fourth thin film transistor are turned on, and the first gate line output and the second gate line
  • the outputs are all low voltage levels.
  • the invention realizes pre-charging in the array gate driving circuit architecture, accelerates the charging speed, shortens the liquid crystal response time, and reduces the crosstalk phenomenon between the pixel electrodes.
  • FIG. 1 is a schematic structural view of a conventional gate driving panel
  • FIG. 2 is a circuit diagram of a precharge module in accordance with an embodiment of the present invention.
  • FIG. 3 is a waveform diagram of a gate line signal in a precharge module in the embodiment of the present invention.
  • an embodiment of the present invention discloses a display panel 1 having a display area 10 and a fan-out area 11 and an array gate drive (Gate On Array, GOA) circuit (no icon), array gate drive circuit is disposed in display area 10 and fan-out area 11, including multi-stage pre-charging module 14 (not shown), and circuit diagram of pre-charging module 14 in FIG.
  • the output ends of the adjacent two gates in the array gate driving circuit are respectively connected to the adjacent two gate lines corresponding to the display area 10 in the fan-out area 11.
  • FIG. 2 is a circuit diagram of a pre-charging module 14 according to an embodiment of the present invention. As shown in FIG.
  • the pre-charging module 14 of each stage includes a first thin film transistor M1, and the first film.
  • a source and a gate of the transistor M1 are connected to a first output terminal G_OUT1 at the gate, a drain is connected to a first gate line output GL_OUT1, a second thin film transistor M2, the second film a gate of the transistor M2 is connected to the first output terminal G_OUT1 at the gate, a drain is connected to the pre-charging module (no icon) of the upper stage;
  • a third thin film transistor M3, the a gate of the third thin film transistor M3 is connected to the first output terminal G_OUT1 at the gate, a drain is connected to the first gate line output GL_OUT1, and a fourth thin film transistor M4, the first a drain of the fourth thin film transistor M4 is connected to a source of the third thin film transistor M3;
  • a gate is connected to a second output terminal G_OUT2 at the gate, and a source is connected to a second gate a line output
  • a gate of the sixth thin film transistor M6 is connected to the second output terminal G_OUT2 at the gate, and a drain is connected to the second gate line output GL_OUT2
  • a source is connected to the pre-charging module (no icon) of the next stage.
  • the first gate output terminal G_OUT1 is a high voltage level VH and the second gate output terminal G_OUT2 is a low voltage level VL
  • the first thin film transistor M1 and the third thin film transistor M3, and the fourth thin film transistor M4 is turned on
  • the second thin film transistor M2 the fifth thin film transistor M5, and the sixth thin film transistor M6 are turned off
  • the A gate line output GL_OUT1 and the second gate line output GL_OUT2 are both high voltage levels VH.
  • the first gate output terminal G_OUT1 When the first gate output terminal G_OUT1 is at a low voltage level VL and the second gate output terminal G_OUT2 is at a high voltage level VH, the first thin film transistor M1 and the third thin film transistor M3, And the fourth thin film transistor M4 is turned off, the second thin film transistor M2, the fifth thin film transistor M5, and the sixth thin film transistor M6 are turned on, and the first gate The pole line output GL_OUT1 is a low voltage level VL, and the second gate line output GL_OUT2 is a high voltage level VH.
  • the first gate output terminal G_OUT1 and the second gate output terminal G_OUT2 are both at a low voltage level VL, the first thin film transistor M1, the third thin film transistor M3, and the fifth film The transistor M5 and the sixth thin film transistor M6 are turned off, the second thin film transistor M2 and the fourth thin film transistor M4 are turned on, and the first gate line outputs GL_OUT1 and The second gate line output GL_OUT2 is a low voltage level VL.
  • FIG. 3 is a waveform diagram of a gate line signal in the pre-charging module 14 in the embodiment of the present invention.
  • the charging waveforms of GL_OUT1 and GL_OUT2 will partially overlap, that is, the second gate line will start charging before the charging of the first gate line is completed, so that the charging efficiency is improved, so that the present invention is in the array grid.
  • the pre-charging is realized in the pole drive circuit architecture, the charging speed is accelerated, the liquid crystal response time is shortened, and the crosstalk phenomenon between the pixel electrodes is reduced.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)

Abstract

一种显示面板（1），具有一显示区（10）与一扇出区（11），与一阵列栅极驱动电路，该阵列栅极驱动电路包括多级预充电模块（14），用于在该扇出区（11）将该阵列栅极驱动电路中相邻两栅极的输出端（G_OUT1、G_OUT2）分别连接于该显示区（10）对应的相邻两栅极线输出（GL_OUT1、GL_OUT2），每一级该预充电模块14包括一第一薄膜晶体管（M1）、一第二薄膜晶体管（M2）、一第三薄膜晶体管（M3）、一第四薄膜晶体管（M4）、一第五薄膜晶体管（M5）以及一第六薄膜晶体管（M6）。

Description

显示面板与阵列栅极驱动电路 技术领域
本案涉及一种显示面板与阵列栅极驱动电路，特别是用于薄膜晶体管液晶显示器（Thin Film Transistor Liquid Crystal Display, TFT-LCD）的显示面板与阵列栅极驱动电路。
 背景技术
传统的TFT-LCD显示面板使用GOA（Gate On Array，栅级驱动芯片集成于阵列基板）的基本架构如图1所示，显示面板1中包含显示区10、扇出区11、源极薄膜上芯片(Source-Chip On Film, S-COF)12、印刷电路板(Printed Circuit Board, PCB)13，阵列栅极驱动电路会被设置于显示区与扇出区之间。
传统液晶面板的栅极驱动(gate driver)扫描薄膜晶体管(TFT)的栅极，透过数据线给像素电极充电。液晶在像素电场的作用下发生旋转而旋光以进行显示。而长的充电时间导致长的液晶响应时间，让像素电极间的互扰(crosstalk)现象加重。
因此，需要提出新的显示面板与阵列栅极驱动电路，提高像素充电速度。
 技术问题
本发明在传统阵列栅极驱动电路中栅极侧的扇出区(Fan Out Area)增加额外逻辑单元，以实现相邻行的栅极线之间进行预充电(Precharge)，以提高高像素充电速度。
 技术解决方案
本发明的一实施例提出一种显示面板，具有一显示区与一扇出区，与一阵列栅极驱动(Gate On Array, GOA)电路，包括多级预充电模块，用于在所述扇出区将所述阵列栅极驱动电路中相邻两栅极的输出端分别连接于所述显示区对应的相邻两栅极线输出，每一级所述预充电模块包括一第一薄膜晶体管，所述第一薄膜晶体管的一源极与栅极连接于位于所述栅极的一第一输出端，一漏极连接于一第一栅极线输出；一第二薄膜晶体管，所述第二薄膜晶体管的一栅极连接于位于所述栅极的所述第一输出端，一漏极连接于上一级的所述预充电模块；一第三薄膜晶体管，所述第三薄膜晶体管的一栅极连接于位于所述栅极的所述第一输出端，一漏极连接于所述第一栅极线输出；一第四薄膜晶体管，所述第四薄膜晶体管的一漏级连接于于所述第三薄膜晶体管的一源极；一栅极连接于位于所述栅极的一第二输出端，一源极连接于一第二栅极线输出；一第五薄膜晶体管，所述第五薄膜晶体管的一栅极连接于位于所述栅极的所述第二输出端，一源极连接于所述第二输出端，一漏极连接于所述第二栅极线输出；以及一第六薄膜晶体管，所述第六薄膜晶体管的一栅极连接于位于所述栅极的所述第二输出端，一漏极连接于所述第二栅极线输出，一源极连接于下一级的所述预充电模块。
较佳地，当所述第一栅极输出端为高电压准位，所述第二栅极输出端为低电压准位时，所述第一薄膜晶体管、所述第三薄膜晶体管，与所述第四薄膜晶体管是被导通的，所述第二薄膜晶体管、所述第五薄膜晶体管，与所述第六薄膜晶体管是被关断的，且所述第一栅极线输出与所述第二栅极线输出都是高电压准位。
较佳地，当所述第一栅极输出端为低电压准位，所述第二栅极输出端为高电压准位时，所述第一薄膜晶体管、所述第三薄膜晶体管，与所述第四薄膜晶体管是被关断的，所述第二薄膜晶体管、所述第五薄膜晶体管，与所述第六薄膜晶体管是被导通的，且所述第一栅极线输出是低电压准位，所述第二栅极线输出是高电压准位。
较佳地，当所述第一栅极输出端与所述第二栅极输出端都为低电压准位时，所述第一薄膜晶体管、所述第三薄膜晶体管、所述第五薄膜晶体管，与所述第六薄膜晶体管是被关断的，所述第二薄膜晶体管与所述第四薄膜晶体管是被导通的，且所述第一栅极线输出与所述第二栅极线输出都是低电压准位。
 有益效果
本发明在阵列栅极驱动电路架构中实现预充电，加快充电速度，缩短液晶响应时间，减少像素电极间的互扰(crosstalk)现象。
 附图说明
图1是传统栅极驱动面板的架构示意图；
图2是依据本发明一实施例的预充电模块电路图；以及
图3是本发明所述实施例中的预充电模块中栅极线讯号波形图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
如图1的显示面板架构，本发明的一实施例揭露了一显示面板1，具有一显示区10与一扇出区11，与一阵列栅极驱动(Gate On Array, GOA)电路(无图标)，阵列栅极驱动电路被设置于显示区10与扇出区11，包括多级预充电模块14(无图示)，图2中有预充电模块14的电路图，用于在所述扇出区11将所述阵列栅极驱动电路中相邻两栅极的输出端分别连接于所述显示区10对应的相邻两栅极线输出。请参照图2，图2是依据本发明一实施例的预充电模块14的电路图，如图2所示，每一级所述预充电模块14包括一第一薄膜晶体管M1，所述第一薄膜晶体管M1的一源极与栅极连接于位于所述栅极的一第一输出端G_OUT1，一漏极连接于一第一栅极线输出GL_OUT1；一第二薄膜晶体管M2，所述第二薄膜晶体管M2的一栅极连接于位于所述栅极的所述第一输出端G_OUT1，一漏极连接于上一级的所述预充电模块(无图标)；一第三薄膜晶体管M3，所述第三薄膜晶体管M3的一栅极连接于位于所述栅极的所述第一输出端G_OUT1，一漏极连接于所述第一栅极线输出GL_OUT1；一第四薄膜晶体管M4，所述第四薄膜晶体管M4的一漏级连接于于所述第三薄膜晶体管M3的一源极；一栅极连接于位于所述栅极的一第二输出端G_OUT2，一源极连接于一第二栅极线输出GL_OUT2；一第五薄膜晶体管M5，所述第五薄膜晶体管M5的一栅极连接于位于所述栅极的所述第二输出端G_OUT2，一源极连接于所述第二输出端G_OUT2，一漏极连接于所述第二栅极线输出GL_OUT2；以及一第六薄膜晶体管M6，所述第六薄膜晶体管M6的一栅极连接于位于所述栅极的所述第二输出端G_OUT2，一漏极连接于所述第二栅极线输出GL_OUT2，一源极连接于下一级的所述预充电模块(无图标)。
其中，当所述第一栅极输出端G_OUT1为高电压准位VH，所述第二栅极输出端G_OUT2为低电压准位VL时，所述第一薄膜晶体管M1、所述第三薄膜晶体管M3，与所述第四薄膜晶体管M4是被导通的，所述第二薄膜晶体管M2、所述第五薄膜晶体管M5，与所述第六薄膜晶体管M6是被关断的，且所述第一栅极线输出GL_OUT1与所述第二栅极线输出GL_OUT2都是高电压准位VH。当所述第一栅极输出端G_OUT1为低电压准位VL，所述第二栅极输出端G_OUT2为高电压准位VH时，所述第一薄膜晶体管M1、所述第三薄膜晶体管M3，与所述第四薄膜晶体管M4是被关断的，所述第二薄膜晶体管M2、所述第五薄膜晶体管M5，与所述第六薄膜晶体管M6是被导通的，且所述第一栅极线输出GL_OUT1是低电压准位VL，所述第二栅极线输出GL_OUT2是高电压准位VH。当所述第一栅极输出端G_OUT1与所述第二栅极输出端G_OUT2都为低电压准位VL时，所述第一薄膜晶体管M1、所述第三薄膜晶体管M3、所述第五薄膜晶体管M5，与所述第六薄膜晶体管M6是被关断的，所述第二薄膜晶体管M2与所述第四薄膜晶体管M4是被导通的，且所述第一栅极线输出GL_OUT1与所述第二栅极线输出GL_OUT2都是低电压准位VL。
请参照图3，图3是本发明所述实施例中的预充电模块14中栅极线讯号波形图。如图3所示，分别是所述第一栅极线输出GL_OUT1与第二栅极线输出GL_OUT2的波形。如图3所示，在GL_OUT1与GL_OUT2的充电波形会部分重迭，也就是说第二栅极线会在第一栅极线充电完成前开始充电，让充电效率提高，让本发明在阵列栅极驱动电路架构中实现预充电，加快充电速度，缩短液晶响应时间，减少像素电极间的互扰(crosstalk)现象。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (9)

  1. 一种显示面板，具有一显示区与一扇出区，与一阵列栅极驱动(Gate On Array, GOA)电路，所述显示面板包括：
    多级预充电模块，用于在所述扇出区将所述阵列栅极驱动电路中相邻两栅极的输出端分别连接于所述显示区对应的相邻两栅极线输出，每一级所述预充电模块包括：
    一第一薄膜晶体管，所述第一薄膜晶体管的一源极与栅极连接于位于所述栅极的一第一输出端，一漏极连接于一第一栅极线输出；
    一第二薄膜晶体管，所述第二薄膜晶体管的一栅极连接于位于所述栅极的所述第一输出端，一漏极连接于上一级的所述预充电模块；
    一第三薄膜晶体管，所述第三薄膜晶体管的一栅极连接于位于所述栅极的所述第一输出端，一漏极连接于所述第一栅极线输出；
    一第四薄膜晶体管，所述第四薄膜晶体管的一漏级连接于于所述第三薄膜晶体管的一源极；一栅极连接于位于所述栅极的一第二输出端，一源极连接于一第二栅极线输出；
    一第五薄膜晶体管，所述第五薄膜晶体管的一栅极连接于位于所述栅极的所述第二输出端，一源极连接于所述第二输出端，一漏极连接于所述第二栅极线输出；以及
    一第六薄膜晶体管，所述第六薄膜晶体管的一栅极连接于位于所述栅极的所述第二输出端，一漏极连接于所述第二栅极线输出，一源极连接于下一级的所述预充电模块；
    其中，所述第一栅极输出端与所述第二栅极输出端的充电波形是部分重迭的。
  2. 一种显示面板，具有一显示区与一扇出区，与一阵列栅极驱动(Gate On Array, GOA)电路，所述显示面板包括：
    多级预充电模块，用于在所述扇出区将所述阵列栅极驱动电路中相邻两栅极的输出端分别连接于所述显示区对应的相邻两栅极线输出，每一级所述预充电模块包括：
    一第一薄膜晶体管，所述第一薄膜晶体管的一源极与栅极连接于位于所述栅极的一第一输出端，一漏极连接于一第一栅极线输出；
    一第二薄膜晶体管，所述第二薄膜晶体管的一栅极连接于位于所述栅极的所述第一输出端，一漏极连接于上一级的所述预充电模块；
    一第三薄膜晶体管，所述第三薄膜晶体管的一栅极连接于位于所述栅极的所述第一输出端，一漏极连接于所述第一栅极线输出；
    一第四薄膜晶体管，所述第四薄膜晶体管的一漏级连接于于所述第三薄膜晶体管的一源极；一栅极连接于位于所述栅极的一第二输出端，一源极连接于一第二栅极线输出；
    一第五薄膜晶体管，所述第五薄膜晶体管的一栅极连接于位于所述栅极的所述第二输出端，一源极连接于所述第二输出端，一漏极连接于所述第二栅极线输出；以及
    一第六薄膜晶体管，所述第六薄膜晶体管的一栅极连接于位于所述栅极的所述第二输出端，一漏极连接于所述第二栅极线输出，一源极连接于下一级的所述预充电模块。
  3. 如权利要求2所述的显示面板，其中，当所述第一栅极输出端为高电压准位，所述第二栅极输出端为低电压准位时，所述第一薄膜晶体管、所述第三薄膜晶体管，与所述第四薄膜晶体管是被导通的，所述第二薄膜晶体管、所述第五薄膜晶体管，与所述第六薄膜晶体管是被关断的，且所述第一栅极线输出与所述第二栅极线输出都是高电压准位。
  4. 如权利要求2所述的显示面板，其中，当所述第一栅极输出端为低电压准位，所述第二栅极输出端为高电压准位时，所述第一薄膜晶体管、所述第三薄膜晶体管，与所述第四薄膜晶体管是被关断的，所述第二薄膜晶体管、所述第五薄膜晶体管，与所述第六薄膜晶体管是被导通的，且所述第一栅极线输出是低电压准位，所述第二栅极线输出是高电压准位。
  5. 如权利要求2所述的显示面板，其中，当所述第一栅极输出端与所述第二栅极输出端都为低电压准位时，所述第一薄膜晶体管、所述第三薄膜晶体管、所述第五薄膜晶体管，与所述第六薄膜晶体管是被关断的，所述第二薄膜晶体管与所述第四薄膜晶体管是被导通的，且所述第一栅极线输出与所述第二栅极线输出都是低电压准位。
  6. 一种阵列栅极驱动电路，用于一显示设备中，所述显示设备具有一显示区与一扇出区，所述阵列栅极驱动电路包括：
    多级预充电模块，用于在所述扇出区将GOA电路中相邻两栅极的输出端分别连接于所述显示区对应的相邻两栅极线输出，每一级所述预充电模块包括：
    一第一薄膜晶体管，所述第一薄膜晶体管的一源极与栅极连接于位于所述栅极的一第一输出端，一漏极连接于一第一栅极线输出；
    一第二薄膜晶体管，所述第二薄膜晶体管的一栅极连接于位于所述栅极的所述第一输出端，一漏极连接于上一级的所述预充电模块；
    一第三薄膜晶体管，所述第三薄膜晶体管的一栅极连接于位于所述栅极的所述第一输出端，一漏极连接于所述第一栅极线输出；
    一第四薄膜晶体管，所述第四薄膜晶体管的一漏级连接于于所述第三薄膜晶体管的一源极；一栅极连接于位于所述栅极的一第二输出端，一源极连接于一第二栅极线输出；
    一第五薄膜晶体管，所述第五薄膜晶体管的一栅极连接于位于所述栅极的所述第二输出端，一源极连接于所述第二输出端，一漏极连接于所述第二栅极线输出；以及
    一第六薄膜晶体管，所述第六薄膜晶体管的一栅极连接于位于所述栅极的所述第二输出端，一漏极连接于所述第二栅极线输出，一源极连接于下一级的所述预充电模块。
  7. 如权利要求6所述的阵列栅极驱动电路，其中，当所述第一栅极输出端为高电压准位，所述第二栅极输出端为低电压准位时，所述第一薄膜晶体管、所述第三薄膜晶体管，与所述第四薄膜晶体管是被导通的，所述第二薄膜晶体管、所述第五薄膜晶体管，与所述第六薄膜晶体管是被关断的，且所述第一栅极线输出与所述第二栅极线输出都是高电压准位。
  8. 如权利要求6所述的阵列栅极驱动电路，其中，当所述第一栅极输出端为低电压准位，所述第二栅极输出端为高电压准位时，所述第一薄膜晶体管、所述第三薄膜晶体管，与所述第四薄膜晶体管是被关断的，所述第二薄膜晶体管、所述第五薄膜晶体管，与所述第六薄膜晶体管是被导通的，且所述第一栅极线输出是低电压准位，所述第二栅极线输出是高电压准位。
  9. 如权利要求6所述的阵列栅极驱动电路，其中，当所述第一栅极输出端与所述第二栅极输出端都为低电压准位时，所述第一薄膜晶体管、所述第三薄膜晶体管、所述第五薄膜晶体管，与所述第六薄膜晶体管是被关断的，所述第二薄膜晶体管与所述第四薄膜晶体管是被导通的，且所述第一栅极线输出与所述第二栅极线输出都是低电压准位。
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