WO2017088219A1 - 用于液晶面板的阵列基板及其制作方法 - Google Patents

用于液晶面板的阵列基板及其制作方法 Download PDF

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WO2017088219A1
WO2017088219A1 PCT/CN2015/097735 CN2015097735W WO2017088219A1 WO 2017088219 A1 WO2017088219 A1 WO 2017088219A1 CN 2015097735 W CN2015097735 W CN 2015097735W WO 2017088219 A1 WO2017088219 A1 WO 2017088219A1
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layer
trench
region
exposure
forming
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PCT/CN2015/097735
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English (en)
French (fr)
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王威
雨文驹
虞晓江
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武汉华星光电技术有限公司
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Publication of WO2017088219A1 publication Critical patent/WO2017088219A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the invention belongs to the field of liquid crystal display technology, and in particular to a low temperature polycrystalline silicon (LTPS) thin film transistor (TFT) array substrate for a liquid crystal panel and a manufacturing method thereof.
  • LTPS low temperature polycrystalline silicon
  • TFT thin film transistor
  • LCDs liquid crystal displays
  • amorphous silicon thin film transistors are widely used as switching elements of LCDs, but a-Si TFT LCDs are required to be thin, lightweight, high-definition, high in brightness, high in reliability, and low in power consumption. Other requirements are still limited.
  • Lower Temperature Polycrystal Silicon (LTPS) TFT LCD has obvious advantages in meeting the above requirements compared with a-Si TFT LCD.
  • a liquid crystal panel formed of a color filter substrate (abbreviated as CF substrate) and a low temperature polysilicon thin film transistor array substrate (abbreviated as Array substrate) is generally included.
  • the Array substrate usually has an organic flat layer, wherein the organic flat layer can serve as a planarization deposition surface of the pixel electrode on the one hand, and can isolate the low temperature polysilicon thin film transistor and the pixel electrode on the other hand to prevent the low temperature polysilicon thin film transistor and the pixel electrode. The electric fields between each other interfere with each other.
  • a trench is disposed in the organic flat layer, wherein a trench in the organic flat layer in the display region (AA region) can pass the pixel electrode deposited on the organic flat layer through the trench and the low temperature polysilicon film
  • the drain of the transistor is in contact; however, since the organic flat layer is thick, the material of the pixel electrode (such as indium tin oxide ITO) is easily left at the slope of the trench, thereby easily causing a leakage phenomenon, thereby affecting the liquid crystal panel. The quality of the display.
  • an object of the present invention is to provide an array substrate for a liquid crystal panel, comprising: a display area and an edge area surrounding the display area, the display area and the edge area Each having a planar layer having a first trench therein and a second trench recessed by a bottom of the first trench, wherein between the first trench and the second trench Has a step difference.
  • the second groove is located at an intermediate position of the bottom of the first groove.
  • a ratio of a depth of the first trench to a depth of the second trench is 4:1.
  • Another object of the present invention is to provide a method for fabricating an array substrate for a liquid crystal panel, the array substrate comprising: a display area and an edge area surrounding the display area, wherein the manufacturing method comprises: providing a Forming a low temperature polysilicon thin film transistor on the substrate of the display region, and sequentially forming a second insulating layer, a gate electrode, a third insulating layer and a second metal layer on the substrate of the edge region; forming a cover a flat layer of the low temperature polysilicon thin film transistor and the second metal layer; a first trench formed in the planar layer and a second trench recessed from a bottom of the first trench; wherein a second trench of the display region exposes a drain electrode of the low temperature polysilicon thin film transistor, a second trench in the edge region exposes the second metal layer; a passivation layer is formed over the planar layer; a pixel electrode is formed on the passivation layer of the display region and in the first trench and the second trench; wherein the pixel electrode contacts
  • the second groove is located at an intermediate position of the bottom of the first groove.
  • a ratio of a depth of the first trench to a depth of the second trench is 4:1.
  • a specific method of forming the first trench and the second trench in the planar layer includes: exposing the planar layer with an exposure mask to determine a first in the planar layer An exposure area; moving the exposure mask; wherein a moving distance of the exposure mask is smaller than a width of the first exposure area; exposing the flat layer again by using the exposure mask to Determining a second exposure region in the layer; wherein the first exposure region partially overlaps the second exposure region; developing the exposed flat layer to be in the first exposure region and the first The flat layer in the two exposed regions is removed, thereby forming the first trench and the second trench.
  • the manufacturing method further includes: a substrate in the display area and the low temperature polysilicon A light shielding layer is formed between the thin film transistors; wherein the light shielding layer is disposed opposite to the low temperature polysilicon thin film transistor.
  • the manufacturing method further includes: forming a first insulating layer between the light shielding layer and the low temperature polysilicon thin film transistor and between the substrate of the edge region and the second insulating layer; A first insulating layer between the light shielding layer and the low temperature polysilicon thin film transistor covers the light shielding layer.
  • the manufacturing method of the low-temperature polysilicon thin film transistor specifically includes: forming a polysilicon layer over the first insulating layer; forming a second insulating layer covering the polysilicon layer over the first insulating layer; Forming a gate electrode over the second insulating layer; forming a third insulating layer covering the gate electrode over the second insulating layer; forming a first layer in the third insulating layer and the second insulating layer a through hole and a second through hole; wherein the first through hole and the second through hole expose a surface of the polysilicon layer; and a source electrode and a drain electrode are formed on the third insulating layer; wherein The source electrode fills the first via and contacts a surface of the polysilicon layer, and the drain electrode fills the second via and contacts a surface of the polysilicon layer.
  • the present invention simultaneously forms two grooves having a step height difference in a flat layer located in a display region and an edge region by one movement of the exposure mask and double exposure of the flat layer before and after the movement.
  • the height of the inner wall of the trench is effectively reduced, and the material forming the pixel electrode in the edge region is prevented from remaining in the trench, and the display region can be prevented.
  • the pixel electrode is broken in the inner wall of the trench.
  • FIG. 1 is a top plan view of a low temperature polysilicon thin film transistor array substrate in accordance with an embodiment of the present invention
  • FIG. 2 is a cross-sectional view of an edge region of a low temperature polysilicon thin film transistor array substrate in accordance with an embodiment of the present invention
  • FIG. 3 is a first trench and a second formed in a planar layer in an edge region, in accordance with an embodiment of the present invention. Schematic diagram of the trench;
  • FIG. 4 is a cross-sectional view showing a display region of a low temperature polysilicon thin film transistor array substrate in accordance with an embodiment of the present invention
  • FIG. 5 is a schematic diagram of forming a first trench and a second trench in a planar layer in a display region, in accordance with an embodiment of the present invention.
  • FIG. 1 is a top plan view of a low temperature polysilicon thin film transistor array substrate in accordance with an embodiment of the present invention.
  • a low temperature polysilicon thin film transistor array substrate includes: a display area (ie, AA area) 1, an edge area 2 surrounding the display area 1, and a side of the display area 1 and located outside the edge area 2.
  • IC area 3 In the present embodiment, an organic flat layer is formed in both the edge region 2 and the display region 1, and a trench is formed in both the edge region 2 and the organic flat layer in the display region 1.
  • the trench in the organic planar layer in the display region 1 serves to electrically contact the drain of the low temperature polysilicon thin film transistor with the pixel electrode; and the trench in the organic planar layer in the edge region 2 serves to improve filling The firmness of the sealant.
  • FIG. 2 is a cross-sectional view of an edge region of a low temperature polysilicon thin film transistor array substrate in accordance with an embodiment of the present invention.
  • a substrate 101 is provided.
  • the substrate 101 may be a transparent glass substrate, but the present invention is not limited thereto.
  • the substrate 101 may be a transparent resin substrate.
  • a first insulating layer 103 is formed on the substrate 101 of the edge region 2.
  • the first insulating layer 103 is formed of silicon nitride and silicon oxide, but the present invention is not limited thereto.
  • a second insulating layer 105 is formed over the first insulating layer 103 of the edge region 2; wherein, in the present embodiment, the second insulating layer 105 is formed of silicon nitride and silicon oxide, but the present invention is not limited thereto.
  • a gate electrode 106 is formed over the second insulating layer 105 of the edge region 2.
  • the gate electrode 106 is formed of a conductive metal such as chromium, nickel or the like.
  • a third insulating layer 107 is formed on the gate electrode 106 of the edge region 2; wherein, in the present embodiment, the third insulating layer 107 is formed of silicon nitride and silicon oxide, but the present invention is not limited thereto.
  • a second metal layer 109 is formed over the third insulating layer 107 of the edge region 2.
  • the second metal layer 109 in the display region 1 forms the source electrode 109a and the drain electrode 109b.
  • the second metal layer 109 is formed of a conductive metal such as chromium, nickel or the like.
  • a flat layer 110 is formed over the second metal layer 109 of the edge region 2.
  • the flat layer 110 is formed of an organic material.
  • a first trench 111a and a second trench 111b recessed downward by the first trench 111a are formed in the flat layer 110 of the edge region 2.
  • the second trench 111b exposes the second metal layer 109.
  • a passivation layer 112 is formed on the planar layer 110 of the edge region 2. Therein, there is no passivation layer 112 in the first trench 111a and the second trench 111b. The formation of the first trench 111a and the second trench 111b in the planar layer 110 located in the edge region 2 will be described in detail below.
  • FIG 3 is a schematic diagram of forming a first trench and a second trench in a planar layer in an edge region, in accordance with an embodiment of the present invention.
  • the planarization layer 110 in the edge region 2 is exposed by the exposure mask 200 to determine the first exposure region in the planarization layer 110.
  • the exposure mask 200 is moved; wherein the moving distance of the exposure mask 200 is smaller than the width of the first exposure area A.
  • the exposure mask 200 is moved to the left, but the present invention is not limited thereto, and for example, the exposure mask 200 may be moved toward the right.
  • the flat layer 110 of the edge region 2 is again exposed by the exposure mask 200 to determine the second exposure region B in the flat layer 110 of the edge region 2; wherein, the first exposure region A and The second exposure regions B partially overlap, that is, the overlapping portions of the first exposure region A and the second exposure region B are double-exposed.
  • the flat layer 110 of the exposed edge region 2 is developed to remove the flat layer 110 of the edge region 2 of the first exposed region A and the second exposed region B.
  • the flat layer 110 in the edge region 2 of the overlapping region will be removed more than the flat layer 110 of the edge region 2 of the other regions.
  • the second trench 111b is recessed at the bottom of the formed first trench 111a.
  • a second groove 111b is recessed at an intermediate position of the bottom of the first groove 111a.
  • a first trench 111a and a second trench 111b having a step therebetween are formed in the flat layer 110 of the edge region 2; wherein the depth (or height) of the first trench 111a is the second
  • the ratio of the depth (or height) of the groove 111b is not less than 1:1 and not more than 5:1.
  • the ratio of the depth (or height) of the first trench 111a to the depth (or height) of the second trench 111b is 4:1.
  • the depth (or height) of the first trench 111a refers to the distance between the upper surface of the flat layer 110 and the step
  • the depth (or height) of the second trench 111b refers to the The distance between the step and the bottom of the second groove 111b.
  • the material forming the pixel electrode 113 (shown in FIG. 4) on the flat layer 110 in the edge region 2 is etched, since there is a height difference between the first trench 111a and the second trench 111b, The material forming the pixel electrode 113 in the first trench 111a and the second trench 111b can be etched clean, and leakage of electricity caused by the material remaining of the pixel electrode 113 is prevented from occurring.
  • FIG. 4 is a cross-sectional view of a display region of a low temperature polysilicon thin film transistor array substrate in accordance with an embodiment of the present invention.
  • the substrate 101 may be a transparent glass substrate, but the present invention is not limited thereto.
  • the substrate 101 may be a transparent resin substrate.
  • a light shielding layer 102 is formed on the substrate 101 of the display region 1.
  • the light shielding layer 102 is disposed opposite to the low temperature polysilicon thin film transistor to be formed, so that the light shielding layer 102 shields the channel of the low temperature polysilicon thin film transistor, thereby preventing leakage current of the low temperature polysilicon thin film transistor due to illumination.
  • the light shielding layer 102 is disposed opposite to the low temperature polysilicon thin film transistor. That is, the light shielding layer 102 completely blocks the low temperature polysilicon thin film transistor from the bottom up.
  • a first insulating layer 103 covering the light shielding layer 102 is formed on the substrate 101 of the display region 1. That is, the light shielding layer 102 is directly formed on the substrate 101 of the display region 1, the first insulating layer 103 is directly formed on the substrate 101 of the display region 1 and covers the light shielding layer 102, and the low temperature polysilicon thin film transistor is directly formed in the first An insulating layer 103.
  • the first insulating layer 103 is formed of silicon nitride and silicon oxide, but the present invention is not limited thereto. Thus, the first insulating layer 103 is simultaneously formed in the display region 1 and the edge region 2.
  • a polysilicon layer 104 is formed over the first insulating layer 103 of the display region 1; wherein the polysilicon layer 104 is used to form a carrier moving channel.
  • a second insulating layer 105 covering the polysilicon layer 104 is formed over the first insulating layer 103 of the display region 1; wherein, in the embodiment, the second insulating layer 105 is formed of silicon nitride and silicon oxide, but the present invention Not limited to this. Thus, the second insulating layer 105 is simultaneously formed in the display region 1 and the edge region 2.
  • a gate electrode 106 is formed over the second insulating layer 105 of the display region 1.
  • the gate electrode 106 is formed of a conductive metal such as chromium, nickel or the like.
  • the gate electrode 106 is simultaneously formed in the display region 1 and the edge region 2.
  • the third insulating layer 107 is formed of silicon nitride and silicon oxide, but the present invention is not limited thereto.
  • the third insulating layer 107 is simultaneously formed in the display region 1 and the edge region 2.
  • a first via hole 108a and a second via hole 108b are formed in the third insulating layer 107 of the display region 1 and the second insulating layer 105 of the display region 1; wherein the first via hole 108a and the second via hole 108b expose the polysilicon layer The surface of 104.
  • a source electrode 109a and a drain electrode 109b are formed over the third insulating layer 107 of the display region 1, where the second metal layer 109 deposited over the third insulating layer 107 of the display region 1 forms the source electrode 109a and the drain electrode 109b.
  • the source electrode 109a fills the first via hole 108a and contacts the surface of the polysilicon layer 104
  • the drain electrode 109b fills the second via hole 108b and contacts the surface of the polysilicon layer 104.
  • the second metal layer 109 is simultaneously formed in the display region 1 and the edge region 2.
  • the above is a specific formation process of the low temperature polysilicon thin film transistor according to an embodiment of the present invention.
  • the formation of the low temperature polysilicon thin film transistor array substrate according to the embodiment of the present invention will be described below.
  • a planarization layer 110 covering the source electrode 109a and the drain electrode 109b is formed over the third insulating layer 107 of the display region 1; wherein the planarization layer 110 is formed of an organic material.
  • the flat layer 110 is simultaneously formed in the display region 1 and the edge region 2.
  • a first trench 111a and a second trench 111b recessed downward from a bottom of the first trench 111a are formed in the flat layer 110 of the display region 1; wherein the second trench 111b exposes the drain electrode 109b of the low temperature polysilicon thin film transistor .
  • a passivation layer 112 is formed on the flat layer 110 of the display region 1. Therein, there is no passivation layer 112 in the first trench 111a and the second trench 111b.
  • a pixel electrode 113 is formed over the passivation layer 112 of the display region 1; wherein the pixel electrode 113 is formed in the first trench 111a and the second trench 111b, and is contacted by the first trench 111a and the second trench 111b
  • the pixel electrode 113 is formed of indium tin oxide ITO, but the present invention is not limited thereto. It should be understood that when the material forming the pixel electrode 113 is deposited, the material forming the pixel electrode 113 is also deposited on the flat layer 112 in the edge region 2, but when the pixel electrode 113 is formed, the flat layer 112 in the edge region 2 is required. Formation image of upper sediment The material of the element electrode 113 is etched away.
  • the above is the entire fabrication process of the low temperature polysilicon thin film transistor array substrate according to the embodiment of the present invention.
  • the formation process of the first trench 111a and the second trench 111b in the planar layer 110 in the display region 1 will be specifically described below.
  • FIG. 5 is a schematic diagram of forming a first trench and a second trench in a planar layer in a display region, in accordance with an embodiment of the present invention.
  • the flat layer 110 covering the source electrode 109a and the drain electrode 109b is formed over the third insulating layer 107 of the display region 1, the flat layer 110 is exposed by the exposure mask 200 to be determined in the flat layer 110.
  • First exposure area A is a part of the flat layer 110 covering the source electrode 109a and the drain electrode 109b.
  • the exposure mask 200 is moved; wherein the moving distance of the exposure mask 200 is smaller than the width of the first exposure area A.
  • the exposure mask 200 is moved to the left, but the present invention is not limited thereto, and for example, the exposure mask 200 may be moved toward the right.
  • the flat layer 110 of the display area 1 is again exposed by the exposure mask 200 to determine the second exposure area B in the flat layer 110 of the display area 1; wherein, the first exposure area A and The second exposure regions B partially overlap, that is, the overlapping portions of the first exposure region A and the second exposure region B are double-exposed.
  • the flat layer 110 of the exposed display region 1 is developed to remove the flat layer 110 of the display region 1 of the first exposed region A and the second exposed region B.
  • the flat layer 110 of the display region 1 in the overlapping region will be removed more than the flat layer 110 of the display region 1 of the other regions.
  • the bottom of the first trench 111a is recessed to form the second trench 111b.
  • the second groove 111b is recessed downward at an intermediate position of the bottom of the first groove 111a.
  • the first trench 111a and the second trench 111b having a step therebetween are formed in the flat layer 110; wherein the depth (or height) of the first trench 111a and the second trench 111b
  • the ratio of depth (or height) is not less than 1:1 and not more than 5:1.
  • the ratio of the depth (or height) of the first trench 111a to the depth (or height) of the second trench 111b is 4:1.
  • the depth (or height) of the first trench 111a refers to the distance between the upper surface of the flat layer 110 and the step
  • the depth (or height) of the second trench 111b refers to the The distance between the step and the bottom of the second groove 111b.
  • the pixel electrode 113 in the first trench 111a and the second trench 111b is less likely to be broken, thereby improving the yield of the product. .
  • two grooves having a step height difference are simultaneously formed in a flat layer located in the display region and the edge region by one movement of the exposure mask and double exposure of the flat layer before and after the movement, Compared with the single trench formed in the flat layer of the prior art, the height of the inner wall of the trench is effectively reduced, and the material forming the pixel electrode in the edge region is prevented from remaining in the trench, and the pixel in the display region can be prevented. The electrode is broken in the inner wall of the groove.

Abstract

一种用于液晶面板的阵列基板及制造方法，阵列包括：显示区（1）及围绕显示区（1）的边沿区（2），显示区（1）和边沿区（2）中具有平坦层（110），平坦层（110）中具有第一沟槽（111a）以及由第一沟槽（111a）的底部下凹的第二沟槽（111b），第一沟槽（111a）与第二沟槽（111b）之间具有台阶差。平坦层（110）中形成具有台阶高度差的两个沟槽（111a，111b），有效降低了沟槽内壁的高度，避免了边沿区（2）中形成像素电极的材料残留在沟槽内，同时防止显示区（1）中的像素电极（113）在沟槽内壁出现断线。

Description

用于液晶面板的阵列基板及其制作方法 技术领域
本发明属于液晶显示技术领域，具体地讲，涉及一种用于液晶面板的低温多晶硅(Lower Temperature Polycrystal Silicon，LTPS)薄膜晶体管(Thin Film Transistor，TFT)阵列基板及其制作方法。
背景技术
随着光电与半导体技术的演进，也带动了平板显示器(Flat Panel Display)的蓬勃发展，而在诸多平板显示器中，液晶显示器(Liquid Crystal Display，简称LCD)因具有高空间利用效率、低消耗功率、无辐射以及低电磁干扰等诸多优越特性，已成为市场的主流。
目前，作为LCD的开关元件而广泛采用的是非晶硅薄膜三极管(a-Si TFT)，但a-Si TFT LCD在满足薄型、轻量、高精细度、高亮度、高可靠性、低功耗等要求仍受到限制。低温多晶硅(Lower Temperature Polycrystal Silicon，LTPS)TFT LCD与a-Si TFT LCD相比，在满足上述要求方面，具有明显优势。
在现有的LTPS TFT LCD中，通常包括由彩色滤光片基板(简称CF基板)和低温多晶硅薄膜晶体管阵列基板(简称Array基板)对盒形成的液晶面板。Array基板上通常具有有机平坦层，其中，该有机平坦层一方面可以作为像素电极的平坦化沉积面，另一方面可以隔离低温多晶硅薄膜晶体管与像素电极，以防止低温多晶硅薄膜晶体管与像素电极之间的电场相互干扰。
通常，该有机平坦层中设置有沟槽，其中，位于显示区(AA区)内的有机平坦层中的沟槽可使沉积在该有机平坦层上的像素电极通过该沟槽与低温多晶硅薄膜晶体管的漏极接触；然而，由于该有机平坦层较厚，在该沟槽的斜坡处容易引起像素电极的材料(诸如氧化铟锡ITO)残留，从而容易造成漏电现象的发生，进而影响液晶面板的显示质量。
发明内容
为了解决上述现有技术存在的问题，本发明的目的在于提供一种用于液晶面板的阵列基板，包括：显示区及围绕所述显示区的边沿区，所述显示区和所述边沿区中均具有平坦层，所述平坦层中具有第一沟槽以及由所述第一沟槽的底部下凹的第二沟槽，其中，所述第一沟槽与所述第二沟槽之间具有台阶差。
进一步地，所述第二沟槽位于所述第一沟槽的底部的中间位置。
进一步地，所述第一沟槽的深度与所述第二沟槽的深度的比值为4:1。
本发明的另一目的还在于提供一种用于液晶面板的阵列基板的制作方法，所述阵列基板包括：显示区及围绕所述显示区的边沿区，其中，所述制作方法包括：提供一基板；在所述显示区的基板之上形成低温多晶硅薄膜晶体管，并且在所述边沿区的基板之上依次形成第二绝缘层、栅电极、第三绝缘层及第二金属层；形成覆盖所述低温多晶硅薄膜晶体管和所述第二金属层的平坦层；在所述平坦层中形成第一沟槽以及由所述第一沟槽的底部下凹的第二沟槽；其中，在所述显示区的第二沟槽露出所述低温多晶硅薄膜晶体管的漏电极，在所述边沿区的第二沟槽露出所述第二金属层；在所述平坦层之上形成钝化层；在所述显示区的钝化层上以及所述第一沟槽和所述第二沟槽中形成像素电极；其中，所述像素电极通过所述第一沟槽和所述第二沟槽接触所述低温多晶硅薄膜晶体管的漏电极。
进一步地，所述第二沟槽位于所述第一沟槽的底部的中间位置。
进一步地，所述第一沟槽的深度与所述第二沟槽的深度的比值为4:1。
进一步地，在所述平坦层中形成所述第一沟槽以及所述第二沟槽的具体方法包括：利用曝光光罩对所述平坦层进行曝光，以在所述平坦层中确定第一曝光区域；移动所述曝光光罩；其中，所述曝光光罩的移动距离小于所述第一曝光区域的宽度；利用所述曝光光罩再次对所述平坦层进行曝光，以在所述平坦层中确定第二曝光区域；其中，所述第一曝光区域与所述第二曝光区域部分重合；对曝光后的所述平坦层进行显影，以将处于所述第一曝光区域和所述第二曝光区域中的平坦层去除，从而形成所述第一沟槽以及所述第二沟槽。
进一步地，所述制作方法还包括：在所述显示区的基板与所述低温多晶硅 薄膜晶体管之间形成遮光层；其中，所述遮光层与所述低温多晶硅薄膜晶体管正相对设置。
进一步地，所述制作方法还包括：在所述遮光层与所述低温多晶硅薄膜晶体管之间以及在所述边沿区的基板与所述第二绝缘层之间形成第一绝缘层；其中，所述遮光层与所述低温多晶硅薄膜晶体管之间的第一绝缘层覆盖所述遮光层。
进一步地，所述低温多晶硅薄膜晶体管的制作方法具体包括：在所述第一绝缘层之上形成多晶硅层；在所述第一绝缘层之上形成覆盖所述多晶硅层的第二绝缘层；在所述第二绝缘层之上形成栅电极；在所述第二绝缘层之上形成覆盖所述栅电极的第三绝缘层；在所述第三绝缘层和所述第二绝缘层中形成第一通孔和第二通孔；其中，所述第一通孔和所述第二通孔露出所述多晶硅层的表面；在所述第三绝缘层之上形成源电极和漏电极；其中，所述源电极填充所述第一通孔并接触所述多晶硅层的表面，所述漏电极填充所述第二通孔并接触所述多晶硅层的表面。
本发明的有益效果：本发明通过对曝光光罩的一次移动以及移动前后对平坦层的两次曝光，在位于显示区和边沿区的平坦层中同时形成具有台阶高度差的两个沟槽，其与现有技术的平坦层中形成的单一沟槽相比，有效地降低了沟槽内壁的高度，避免了边沿区中形成像素电极的材料残留在沟槽内，同时能够防止显示区中的像素电极在沟槽内壁中出现断线的情况。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1是根据本发明的实施例的低温多晶硅薄膜晶体管阵列基板的俯视示意图；
图2是根据本发明的实施例的低温多晶硅薄膜晶体管阵列基板的边沿区的剖面图；
图3是根据本发明的实施例的在边沿区中的平坦层中形成第一沟槽和第二 沟槽的示意图；
图4是根据本发明的实施例的低温多晶硅薄膜晶体管阵列基板的显示区的剖面图；
图5是根据本发明的实施例的在显示区中的平坦层中形成第一沟槽和第二沟槽的示意图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。
在附图中，为了清楚器件，夸大了层和区域的厚度，相同的标号在整个说明书和附图中可用来表示相同的元件。
将理解的是，尽管在这里可使用术语“第一”、“第二”、“第三”等来描述各种元件，但是这些元件不应受这些术语的限制。这些术语仅用于将一个元件与另一个元件区分开来。
也将理解的是，在一层或元件被称为在或形成在另一层或基板“之上”或“上”时，它可以直接在或形成在该另一层或基板上，或者也可以存在中间层。
图1是根据本发明的实施例的低温多晶硅薄膜晶体管阵列基板的俯视示意图。
参照图1，根据本发明的实施例的低温多晶硅薄膜晶体管阵列基板包括：显示区(即AA区)1、围绕显示区1的边沿区2以及位于显示区1一侧且位于边沿区2以外的IC区3。在本实施例中，边沿区2和显示区1中均沉积形成有有机平坦层，位于边沿区2和显示区1中的有机平坦层中均形成有沟槽。其中，位于显示区1中的有机平坦层中的沟槽用于使低温多晶硅薄膜晶体管的漏极与像素电极电接触；而位于边沿区2中的有机平坦层中的沟槽用于提高填充在其中的框胶的牢固度。
以下首先对边沿区2中的有机平坦层的形成过程进行说明。
图2是根据本发明的实施例的低温多晶硅薄膜晶体管阵列基板的边沿区的剖面图。
参照图2，提供一基板101。在本实施例中，基板101可为透明的玻璃基板，但本发明并不限制于此，例如基板101也可为透明的树脂基板。
在边沿区2的基板101上形成第一绝缘层103。在本实施例中，第一绝缘层103由氮化硅和氧化硅形成，但本发明并不限制于此。
在边沿区2的第一绝缘层103之上形成第二绝缘层105；其中，在本实施例中，第二绝缘层105由氮化硅和氧化硅形成，但本发明并不限制于此。
在边沿区2的第二绝缘层105之上形成栅电极106。在本实施例中，栅电极106由导电金属形成，例如铬、镍等。
在边沿区2的栅电极106上形成第三绝缘层107；其中，在本实施例中，第三绝缘层107由氮化硅和氧化硅形成，但本发明并不限制于此。
在边沿区2的第三绝缘层107之上形成第二金属层109。其中，在显示区1中的第二金属层109形成源电极109a和漏电极109b。在本实施例中，第二金属层109由导电金属形成，例如铬、镍等。
在边沿区2的第二金属层109之上形成平坦层110。其中，平坦层110由有机材料形成。
在边沿区2的平坦层110中形成第一沟槽111a以及由第一沟槽111a向下凹陷的第二沟槽111b。其中，第二沟槽111b露出第二金属层109。
在边沿区2的平坦层110上形成钝化层112。其中，在第一沟槽111a和第二沟槽111b中没有钝化层112。以下将对位于边沿区2中的平坦层110中形成第一沟槽111a和第二沟槽111b进行详细说明。
图3是根据本发明的实施例的在边沿区中的平坦层中形成第一沟槽和第二沟槽的示意图。
参照图3，在边沿区2的第二金属层109之上形成平坦层110之后，利用曝光光罩200对边沿区2中的平坦层110进行曝光，以在平坦层110中确定第一曝光区域A。
移动曝光光罩200；其中，曝光光罩200的移动距离小于第一曝光区域A的宽度。在本实施例中，朝向左方移动曝光光罩200，但本发明并不限制于此，例如也可朝向右方移动曝光光罩200。
在曝光光罩200移动之后，利用曝光光罩200再次对边沿区2的平坦层110进行曝光，以在边沿区2的平坦层110中确定第二曝光区域B；其中，第一曝光区域A与第二曝光区域B部分重合，即，第一曝光区域A与第二曝光区域B的重合部分被两次曝光。
对曝光后的边沿区2的平坦层110进行显影，以将第一曝光区域A和第二曝光区域B的边沿区2的平坦层110去除。这里，由于第一曝光区域A与第二曝光区域B的重合部分被两次曝光，因此处于该重合区域的边沿区2的平坦层110将比其他区域的边沿区2的平坦层110去除的更多，从而在形成的第一沟槽111a的底部下凹形成第二沟槽111b。进一步地，第一沟槽111a的底部的中间位置下凹形成第二沟槽111b。
也就是说，在边沿区2的平坦层110中形成二者之间具有台阶的第一沟槽111a和第二沟槽111b；其中，第一沟槽111a的深度(或称高度)与第二沟槽111b的深度(或称高度)的比值不小于1:1且不大于5:1。优选地，在本实施例中，第一沟槽111a的深度(或称高度)与第二沟槽111b的深度(或称高度)的比值为4:1。这里，第一沟槽111a的深度(或称高度)指的是平坦层110的上表面与所述台阶之间的距离，而第二沟槽111b的深度(或称高度)指的是所述台阶与第二沟槽111b的底部之间的距离。
这样，当对边沿区2中的平坦层110上的形成像素电极113(图4所示)的材料进行刻蚀时，由于第一沟槽111a与第二沟槽111b之间具有高度差，因此可将第一沟槽111a和第二沟槽111b中的形成像素电极113的材料刻蚀干净，避免了形成像素电极113的材料残留而导致的漏电现象发生。
接着，对显示区1中的有机平坦层的形成过程进行说明。
图4是根据本发明的实施例的低温多晶硅薄膜晶体管阵列基板的显示区的剖面图。
参照图4，提供一基板101。在本实施例中，基板101可为透明的玻璃基板，但本发明并不限制于此，例如基板101也可为透明的树脂基板。
在显示区1的基板101上形成遮光层102。在本实施例中，遮光层102与将要形成的低温多晶硅薄膜晶体管相对设置，以使遮光层102对低温多晶硅薄膜晶体管的沟道进行遮光，从而防止低温多晶硅薄膜晶体管因光照而产生漏电流。
进一步地，遮光层102与低温多晶硅薄膜晶体管正相对设置。也就是说，从下向上看，遮光层102完全遮挡低温多晶硅薄膜晶体管。
在显示区1的基板101上形成覆盖遮光层102的第一绝缘层103。也就是说，遮光层102直接形成在显示区1的基板101上上，第一绝缘层103直接形成在显示区1的基板101上上并覆盖遮光层102，而低温多晶硅薄膜晶体管直接形成在第一绝缘层103上。在本实施例中，第一绝缘层103由氮化硅和氧化硅形成，但本发明并不限制于此。这样，第一绝缘层103同时形成在显示区1和边沿区2中。
以下参照图4对低温多晶硅薄膜晶体管的形成进行具体说明。
继续参照图4，在显示区1的第一绝缘层103之上形成多晶硅层104；其中，多晶硅层104用来形成载流子移动通道。
在显示区1的第一绝缘层103之上形成覆盖多晶硅层104的第二绝缘层105；其中，在本实施例中，第二绝缘层105由氮化硅和氧化硅形成，但本发明并不限制于此。这样，第二绝缘层105同时形成在显示区1和边沿区2中。
在显示区1的第二绝缘层105之上形成栅电极106。在本实施例中，栅电极106由导电金属形成，例如铬、镍等。这样，栅电极106同时形成在显示区1和边沿区2中。
在显示区1的第二绝缘层105之上形成覆盖栅电极106的第三绝缘层107； 其中，在本实施例中，第三绝缘层107由氮化硅和氧化硅形成，但本发明并不限制于此。这样，第三绝缘层107同时形成在显示区1和边沿区2中。
在显示区1的第三绝缘层107和显示区1的第二绝缘层105中形成第一通孔108a和第二通孔108b；其中，第一通孔108a和第二通孔108b露出多晶硅层104的表面。
在显示区1的第三绝缘层107之上形成源电极109a和漏电极109b，这里，沉积在显示区1的第三绝缘层107之上的第二金属层109形成源电极109a和漏电极109b；其中，源电极109a填充第一通孔108a并接触多晶硅层104的表面，漏电极109b填充第二通孔108b并接触多晶硅层104的表面。这样，第二金属层109同时形成在显示区1和边沿区2中。
以上为根据本发明的实施例的低温多晶硅薄膜晶体管的具体形成过程。以下继续对根据本发明的实施例的低温多晶硅薄膜晶体管阵列基板的形成进行说明。
继续参照图4，在显示区1的第三绝缘层107之上形成覆盖源电极109a和漏电极109b的平坦层110；其中，平坦层110由有机材料形成。这样，平坦层110同时形成在显示区1和边沿区2中。
在显示区1的平坦层110中形成第一沟槽111a以及由第一沟槽111a的底部向下凹陷的第二沟槽111b；其中，第二沟槽111b露出低温多晶硅薄膜晶体管的漏电极109b。
在显示区1的平坦层110上形成钝化层112。其中，在第一沟槽111a和第二沟槽111b中没有钝化层112。
在显示区1的钝化层112之上形成像素电极113；其中，像素电极113形成在第一沟槽111a和第二沟槽111b中，并通过第一沟槽111a和第二沟槽111b接触低温多晶硅薄膜晶体管的漏电极109b。在本实施例中，像素电极113由氧化铟锡ITO形成，但本发明并不限制于此。应当理解的是，沉积形成像素电极113的材料时，也在边沿区2中的平坦层112沉积形成像素电极113的材料，但是在形成像素电极113时，需要将边沿区2中的平坦层112上沉积的形成像 素电极113的材料刻蚀去除。
以上为根据本发明的实施例的低温多晶硅薄膜晶体管阵列基板的全部制作过程。以下将对位于显示区1中的平坦层110中的第一沟槽111a及第二沟槽111b的形成过程进行具体说明。
图5是根据本发明的实施例的在显示区中的平坦层中形成第一沟槽和第二沟槽的示意图。
参照图5，在显示区1的第三绝缘层107之上形成覆盖源电极109a和漏电极109b的平坦层110之后，利用曝光光罩200对平坦层110进行曝光，以在平坦层110中确定第一曝光区域A。
移动曝光光罩200；其中，曝光光罩200的移动距离小于第一曝光区域A的宽度。在本实施例中，朝向左方移动曝光光罩200，但本发明并不限制于此，例如也可朝向右方移动曝光光罩200。
在曝光光罩200移动之后，利用曝光光罩200再次对显示区1的平坦层110进行曝光，以在显示区1的平坦层110中确定第二曝光区域B；其中，第一曝光区域A与第二曝光区域B部分重合，即，第一曝光区域A与第二曝光区域B的重合部分被两次曝光。
对曝光后的显示区1的平坦层110进行显影，以将第一曝光区域A和第二曝光区域B的显示区1的平坦层110去除。这样，由于第一曝光区域A与第二曝光区域B的重合部分被两次曝光，因此处于该重合区域的显示区1的平坦层110将比其他区域的显示区1的平坦层110去除的更多，从而第一沟槽111a的底部下凹形成第二沟槽111b。
进一步地，在第一沟槽111a的底部的中间位置向下凹陷形成第二沟槽111b。
也就是说，在平坦层110中形成二者之间具有台阶的第一沟槽111a和第二沟槽111b；其中，第一沟槽111a的深度(或称高度)与第二沟槽111b的深度(或称高度)的比值不小于1:1且不大于5:1。优选地，在本实施例中，第一沟槽111a的深度(或称高度)与第二沟槽111b的深度(或称高度)的比值为 4:1。这里，第一沟槽111a的深度(或称高度)指的是平坦层110的上表面与所述台阶之间的距离，而第二沟槽111b的深度(或称高度)指的是所述台阶与第二沟槽111b的底部之间的距离。
这样，由于第一沟槽111a与第二沟槽111b之间具有台阶高度差，因此第一沟槽111a和第二沟槽111b中的像素电极113不易产生断线，从而提高了产品的良率。
根据本发明的实施例，通过对曝光光罩的一次移动以及移动前后对平坦层的两次曝光，在位于显示区和边沿区的平坦层中同时形成具有台阶高度差的两个沟槽，其与现有技术的平坦层中形成的单一沟槽相比，有效地降低了沟槽内壁的高度，避免了边沿区中形成像素电极的材料残留在沟槽内，同时能够防止显示区中的像素电极在沟槽内壁中出现断线的情况。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (13)

  1. 一种用于液晶面板的阵列基板，包括：显示区及围绕所述显示区的边沿区，所述显示区和所述边沿区中均具有平坦层，其中，所述平坦层中具有第一沟槽以及由所述第一沟槽的底部下凹的第二沟槽，其中，所述第一沟槽与所述第二沟槽之间具有台阶差。
  2. 根据权利要求1所述的阵列基板，其中，所述第二沟槽位于所述第一沟槽的底部的中间位置。
  3. 根据权利要求1所述的阵列基板，其中，所述第一沟槽的深度与所述第二沟槽的深度的比值为4:1。
  4. 根据权利要求2所述的阵列基板，其中，所述第一沟槽的深度与所述第二沟槽的深度的比值为4:1。
  5. 一种用于液晶面板的阵列基板的制作方法，所述阵列基板包括：显示区及围绕所述显示区的边沿区，其中，所述制作方法包括：
    提供一基板；
    在所述显示区的基板之上形成低温多晶硅薄膜晶体管，并且在所述边沿区的基板之上依次形成第二绝缘层、栅电极、第三绝缘层及第二金属层；
    形成覆盖所述低温多晶硅薄膜晶体管和所述第二金属层的平坦层；
    在所述平坦层中形成第一沟槽以及由所述第一沟槽的底部下凹的第二沟槽；其中，在所述显示区的第二沟槽露出所述低温多晶硅薄膜晶体管的漏电极，在所述边沿区的第二沟槽露出所述第二金属层；
    在所述平坦层之上形成钝化层；
    在所述显示区的钝化层上以及所述第一沟槽和所述第二沟槽中形成像素电极；其中，所述像素电极通过所述第一沟槽和所述第二沟槽接触所述低温多晶硅薄膜晶体管的漏电极。
  6. 根据权利要求5所述的制作方法，其中，所述第二沟槽位于所述第一沟槽的底部的中间位置。
  7. 根据权利要求6所述的制作方法，其中，所述第一沟槽的深度与所述第二沟槽的深度的比值为4:1。
  8. 根据权利要求5所述的制作方法，其中，在所述平坦层中形成所述第一沟槽以及所述第二沟槽的具体方法包括：
    利用曝光光罩对所述平坦层进行曝光，以在所述平坦层中确定第一曝光区域；
    移动所述曝光光罩；其中，所述曝光光罩的移动距离小于所述第一曝光区域的宽度；
    利用所述曝光光罩再次对所述平坦层进行曝光，以在所述平坦层中确定第二曝光区域；其中，所述第一曝光区域与所述第二曝光区域部分重合；
    对曝光后的所述平坦层进行显影，以将处于所述第一曝光区域和所述第二曝光区域中的平坦层去除，从而形成所述第一沟槽以及所述第二沟槽。
  9. 根据权利要求6所述的制作方法，其中，在所述平坦层中形成所述第一沟槽以及所述第二沟槽的具体方法包括：
    利用曝光光罩对所述平坦层进行曝光，以在所述平坦层中确定第一曝光区域；
    移动所述曝光光罩；其中，所述曝光光罩的移动距离小于所述第一曝光区域的宽度；
    利用所述曝光光罩再次对所述平坦层进行曝光，以在所述平坦层中确定第二曝光区域；其中，所述第一曝光区域与所述第二曝光区域部分重合；
    对曝光后的所述平坦层进行显影，以将处于所述第一曝光区域和所述第二曝光区域中的平坦层去除，从而形成所述第一沟槽以及所述第二沟槽。
  10. 根据权利要求7所述的制作方法，其中，在所述平坦层中形成所述第 一沟槽以及所述第二沟槽的具体方法包括：
    利用曝光光罩对所述平坦层进行曝光，以在所述平坦层中确定第一曝光区域；
    移动所述曝光光罩；其中，所述曝光光罩的移动距离小于所述第一曝光区域的宽度；
    利用所述曝光光罩再次对所述平坦层进行曝光，以在所述平坦层中确定第二曝光区域；其中，所述第一曝光区域与所述第二曝光区域部分重合；
    对曝光后的所述平坦层进行显影，以将处于所述第一曝光区域和所述第二曝光区域中的平坦层去除，从而形成所述第一沟槽以及所述第二沟槽。
  11. 根据权利要求5所述的制作方法，其中，所述制作方法还包括：在所述显示区的基板与所述低温多晶硅薄膜晶体管之间形成遮光层；其中，所述遮光层与所述低温多晶硅薄膜晶体管正相对设置。
  12. 根据权利要求11所述的制作方法，其中，所述制作方法还包括：在所述遮光层与所述低温多晶硅薄膜晶体管之间以及在所述边沿区的基板与所述第二绝缘层之间形成第一绝缘层；其中，所述遮光层与所述低温多晶硅薄膜晶体管之间的第一绝缘层覆盖所述遮光层。
  13. 根据权利要求12所述的制作方法，其中，所述低温多晶硅薄膜晶体管的制作方法具体包括：
    在所述第一绝缘层之上形成多晶硅层；
    在所述第一绝缘层之上形成覆盖所述多晶硅层的第二绝缘层；
    在所述第二绝缘层之上形成栅电极；
    在所述第二绝缘层之上形成覆盖所述栅电极的第三绝缘层；
    在所述第三绝缘层和所述第二绝缘层中形成第一通孔和第二通孔；其中，所述第一通孔和所述第二通孔露出所述多晶硅层的表面；
    在所述第三绝缘层之上形成源电极和漏电极；其中，所述源电极填充所述第一通孔并接触所述多晶硅层的表面，所述漏电极填充所述第二通孔并接触所述多晶硅层的表面。
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