WO2017084492A1 - 双结薄膜太阳能电池组件及其制作方法 - Google Patents

双结薄膜太阳能电池组件及其制作方法 Download PDF

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WO2017084492A1
WO2017084492A1 PCT/CN2016/104204 CN2016104204W WO2017084492A1 WO 2017084492 A1 WO2017084492 A1 WO 2017084492A1 CN 2016104204 W CN2016104204 W CN 2016104204W WO 2017084492 A1 WO2017084492 A1 WO 2017084492A1
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cell
battery
gaas
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顾世海
张庆钊
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北京汉能创昱科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0687—Multiple junction or tandem solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0725—Multiple junction or tandem solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/544—Solar cells from Group III-V materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a method for fabricating a III-V dual junction thin film battery assembly, and more particularly to a dual junction thin film solar cell module using polycrystalline germanium as a bottom cell, gallium arsenide as a top cell, and a method of fabricating the same .
  • GaAs solar cell technology Since the 1980s, GaAs solar cell technology has undergone several development stages from LPE to MOCVD, from homoepitaxial to heteroepitaxial, from single junction to multi-junction laminate structures, from LM structures to IMM structures. The pace of development is increasing and efficiency is increasing. At present, the highest efficiency has reached 28.8% (alta devices), three knots 44.4% (Sharp IMM), and the four-junction laboratory is close to 50% (Fhg-ISE).
  • the triple-junction GaAs cell of germanium substrate is the focus of research.
  • the research of double-junction GaAs battery is relatively rare.
  • the double-junction cell uses GaAs and InGaP as the bottom cell and the top-electric double junction cell, with low electrical and optical loss.
  • the tunnel junctions are connected.
  • the double junction must consider the band gap matching problem between the bottom cell and the top cell.
  • the optimal band gap is 1.23 eV and 1.97 eV, and the theoretical efficiency can reach 35.8%.
  • Double junction GaAs cells are typically GaAs as the substrate, GaAs and InGaP as the bottom and top cells respectively Junction battery, the cost of this double junction battery is higher than that of single junction GaAs battery.
  • the cost of epitaxy is almost twice that of single junction, but the efficiency is slightly higher than that of single junction. At present, the highest efficiency of single junction is 28.8%, and the maximum efficiency of double junction is 30.8. %, also need to use a large amount of indium as a raw material.
  • the thickness of the absorption layer of the double junction GaAs and GaInP is relatively large, resulting in an overall thickness of the battery of more than 10 ⁇ m.
  • the thickness of the flexible thin film battery is generally required to be between 1-10 ⁇ m, and such a double junction battery cannot achieve battery flexibility.
  • the present invention provides a double junction thin film solar cell module and a manufacturing method thereof.
  • the present invention provides a thin film interconnected solar cell module, a double junction thin film solar cell module, which is formed by connecting a plurality of battery cells in series, each of which includes a bottom cell and a top cell, and the bottom cell is provided a back metal electrode layer, the top cell is provided with a patterned front metal electrode layer, the bottom cell is a polycrystalline Ge bottom cell layer, the top cell is a GaAs cell, and the polycrystalline Ge bottom cell layer is An N-type diffusion layer, an N-type buffer layer, a tunnel junction N-type region, and a tunnel junction P-type region are sequentially grown between the top cells, and an anti-reflection layer is formed on the front metal electrode layer.
  • the buffer layer is an N-type InGaAs-GaAs graded buffer layer in which the proportion of indium is changed from 1% to 0%.
  • the GaAs cell is an AlGaAs back field, a P-type GaAs base region, an N-type AlGaAs emitter, an N-type AlGaInP window layer, and an N+-type GaAS front contact layer which are epitaxially grown in the tunnel junction P-type region,
  • the front metal electrode layer is on the front contact layer.
  • the window layer is exposed from the front contact layer, and a surface thereof is formed into a roughened structure.
  • the present invention also provides a method of fabricating a dual junction thin film solar cell, the method comprising the following steps:
  • Step one sequentially growing an InGaAs-GaAs graded first buffer layer for adjusting lattice matching and a sacrificial layer AlInAs matched with the polycrystalline germanium on the GaAs substrate;
  • Step two depositing a low-doped P-type polycrystalline germanium material layer on the surface of the sacrificial layer AlInAs to form a polycrystalline bottom cell layer;
  • Step 3 forming a diffusion layer, a tunnel junction and a top cell structure by epitaxial growth on the surface of the polycrystalline silicon bottom battery layer to form a double junction battery structure;
  • Step 4 separating the GaAs substrate from the double junction cell structure by selectively etching the sacrificial layer
  • Step 5 forming a back metal electrode layer on the back surface of the double junction battery structure, and forming a patterned front metal electrode layer on the front surface of the double junction battery structure;
  • Step six separating the double junction battery structure epitaxially grown above the polycrystalline germanium bottom battery layer into a plurality of independent battery cells
  • Step 7 forming an anti-reflection layer on the front metal electrode layer, and sequentially cutting the anti-reflection layer, the polycrystalline bottom cell layer, and a metal electrode layer on the back side, completely separating the battery cells;
  • step 8 the battery cells are connected in series and placed between the upper and lower flexible substrates for packaging to obtain a thin film battery assembly.
  • the InGaAs-GaAs graded first buffer layer for adjusting lattice matching and the sacrificial layer AlInAs matched with the polycrystalline germanium are sequentially grown on the GaAs substrate, and the specific method is:
  • the GaAs substrate temperature is raised to 700-750 ° C for 1-5 min; then the temperature is lowered to 630-670 ° C to start growing the epitaxial structure of the cell; the first buffer of the P-type InGaAs-GaAs gradient is grown on the surface of the P-type GaAs substrate.
  • the proportion of In gradually increases from 0 to 1%; a P-type InAlAs sacrificial layer is grown on the surface of the buffer layer, and the temperature is lowered to normal temperature.
  • a diffusion layer, a tunnel junction and a top cell structure are sequentially formed on the surface of the polycrystalline germanium bottom battery layer by epitaxial growth, and the specific method is: growing an N-type InGaP diffusion layer on the surface of the polycrystalline germanium bottom battery layer; A shallow diffusion PN junction is formed by diffusion of P element into the interior of the polycrystalline bottom cell layer at a high temperature; the diffusion layer InGaP is annealed in a PH 3 atmosphere; and the second buffer layer and the tunnel junction are sequentially grown under constant temperature conditions. The back field of the top cell, the base region, the emitter, the window layer and the front contact layer.
  • the separated batteries are connected in series by a copper foil, and then placed between the upper and lower PET films, and a thin film flexible battery module is formed by laminator packaging.
  • the present invention uses a GaAs substrate, polysilicon and GaAs as the double junction battery of the bottom cell and the top cell, respectively.
  • the forbidden band width of the polycrystalline germanium cell is 0.65 eV
  • the forbidden band width of the top cell GaAs is 1.4. eV, this combination is more conducive to segmenting the solar spectrum, forming a more reasonable current matching, and further capable of absorbing light with a wavelength in the range of 900-2000 nm, and the battery efficiency can reach 32%.
  • the manufacturing cost of the polycrystalline germanium battery of the invention is lower than that of the GaAs bottom battery. Since the thickness of the diffusion junction and the thickness of the bottom cell can be less than 1 micrometer, and the complicated battery structure does not need to be grown, only the high temperature diffusion can be performed. Forming the PN junction, the fabrication process is simple; at the same time, the price of the polycrystalline silicon as the bottom battery is lower than that of the GaAs as the bottom battery, and the battery only needs to use the indium of the material ratio ⁇ 1%, which can reduce the indium. The limitation of raw materials can greatly reduce the cost of battery manufacturing.
  • the front metal electrode layer and the back metal electrode layer of the battery are both plated.
  • the cost of the plating technique is lower, and the manufacturing cost can be further reduced.
  • the invention adds an annealing treatment technology to the battery manufacturing process, which can further improve the crystal quality of the tunnel junction and the top cell.
  • the top cell uses GaAs and AlGaAs materials to reduce the amount of indium raw materials used.
  • 1 is a schematic view showing an epitaxial structure of a polycrystalline Ge/GaAs double junction battery
  • FIG. 2 is a schematic view showing the structure of a battery of a polycrystalline Ge/GaAs double junction battery
  • FIG. 3 is a block diagram of the fabrication of a double junction thin film solar cell provided by the present invention.
  • the present invention provides a method for fabricating a dual-junction flexible thin film battery using polycrystalline Ge (germanium) as a bottom battery and GaAs (gallium arsenide) as a top battery. :
  • Step one sequentially growing a lattice-matched InGaAs graded first buffer layer 102 and a polycrystalline germanium lattice on the GaAs substrate 100 by epitaxial equipment such as MOCVD (Metal-organic Chemical Vapor DePosition metal organic compound chemical vapor deposition).
  • MOCVD Metal-organic Chemical Vapor DePosition metal organic compound chemical vapor deposition
  • the extension temperature is 630-670 ° C
  • the pressure is 50-100 torr, preferably the extension temperature is 650 ° C, and the pressure is 76 torr.
  • step two a low-doping P-type polycrystalline germanium material is deposited on the surface of the AlInAs sacrificial layer 104 by LPCVD (Low Pressure Chemical Vapor Deposition), and the thickness is about 1-3 ⁇ m to form a polycrystalline crucible.
  • Battery layer 106 a low-doping P-type polycrystalline germanium material is deposited on the surface of the AlInAs sacrificial layer 104 by LPCVD (Low Pressure Chemical Vapor Deposition), and the thickness is about 1-3 ⁇ m to form a polycrystalline crucible.
  • Battery layer 106 LiD
  • the present invention grows a polycrystalline germanium cell layer 106 on a lattice-matched AlInAs surface to enable the growth of high quality polycrystalline germanium and even small angle polysilicon.
  • the use of polycrystalline germanium as the bottom cell layer avoids complicated structural design. Compared with the GaAs bottom cell, the use of polycrystalline germanium as the bottom cell layer can greatly reduce the cost of the battery, and can absorb photons in the range of 900 nm to 1800 nm. Photoelectric conversion efficiency.
  • a double junction cell structure 127 is formed on the surface of the polycrystalline germanium cell layer 106 by epitaxially growing the diffusion layer 108, the tunnel junction and the top cell structure.
  • the epitaxial temperature was 630-670 ° C
  • the pressure was 50-100 torr
  • the epitaxial temperature was 650 ° C in the examples
  • the pressure was 76 torr.
  • the temperature is raised to 650 ° C, the N-type InGaP diffusion layer 108 is grown on the surface of the polycrystalline silicon substrate 106; the shallow diffusion PN junction is formed by diffusion of the P element into the polycrystalline bottom cell layer 106 at a high temperature;
  • the InGaP diffusion layer 108 is annealed in a PH 3 atmosphere to eliminate interface defects and ensure the crystal quality of the surface of the diffusion layer 108, which is favorable for further epitaxial growth to form a tunnel junction and a top cell; the temperature is lowered to 630-670 ° C under constant temperature conditions.
  • the second buffer layer 110, the tunnel junction, the back field 116 of the top cell, the base region 118, the emitter 120, the window layer 122 and the front contact layer 124 are sequentially grown to complete the growth of the epitaxial layer and then fall to normal temperature.
  • the invention adds an annealing treatment method, which can further improve the crystal quality of the tunnel junction and the top cell, and the top battery adopts GaAs and AlGaAs materials to reduce the use amount of the In (indium) raw material.
  • Step four separating the GaAs substrate 100 from the double junction cell structure 127 by selectively etching the sacrificial layer 104.
  • the GaAs substrate 100 is peeled off by an ELO (Epitaxy lift-off epitaxial lift-off) technique, and the GaAs substrate 100 after peeling can be reused after polishing, and the stripping solution is a HF solution of a certain temperature.
  • ELO epixy lift-off epitaxial lift-off
  • the battery device structure is fabricated.
  • the back metal electrode layer 300 is formed on the back surface of the double junction battery structure 127, and the patterned front metal electrode layer 200 is formed on the front surface of the double junction battery structure 127.
  • a metal layer is coated on the back surface of the battery by a full-surface plating technique to form a back metal electrode layer 300; a metal layer is plated on the front surface of the battery by a full-surface plating technique to form a front metal electrode layer 200, which is wet etched. The process removes part of the metal electrode layer to form a front patterned electrode structure.
  • the etching solution is a mixture of FeCl 3 and HCl;
  • the excess front contact layer 124 is removed to expose the window layer 122 and form a roughened structure on the surface of the window layer 122.
  • the purpose is to prevent the GaAs material of the front contact layer 124 from absorbing light, and the excess front contact layer 124 is removed at room temperature to form a rough surface.
  • the etchant is a mixture of NH 4 OH and H 2 O 2 .
  • step six the double junction cell structure 127 epitaxially grown above the polycrystalline germanium cell layer 106 is separated into a plurality of individual battery cells by a wet etching process.
  • the third device structure 125 at a specific location is completely separated by a wet etching process, and is etched to the polycrystalline bottom cell layer 106, the epitaxial structure is initially separated into a plurality of independent battery cells, and the third device structure 125 includes a diffusion layer 108.
  • step seven an anti-reflection layer 400 is formed on the front metal electrode layer 200, and then the anti-reflection layer 400, the polycrystalline bottom cell layer 106, and the back metal electrode layer 300 are sequentially cut, and the respective battery cells are completely separated.
  • PECVD Plasma Enhanced Chemical Vapor Deposition Plasma Enhanced Chemical Vapor Deposition
  • the electrode layer 300 completely separates the batteries.
  • step 8 the battery cells are placed in series and placed between the upper and lower flexible substrates to form a thin film battery assembly.
  • Adjacent batteries were connected in series with copper foil; each battery cell in series was placed between the upper and lower PET films, and packaged into a thin film flexible battery module using a laminator.
  • the structure of the obtained double junction thin film solar cell is shown in FIG. 2 .
  • the battery is formed by connecting a plurality of battery cells in series, each battery cell includes a bottom battery and a top battery, the bottom battery is provided with a back metal electrode layer 300, and the top battery is provided with a patterned front metal electrode layer 200, wherein
  • the bottom battery is a polycrystalline bottom battery layer 106
  • the top battery is a GaAs battery
  • an N-type diffusion layer 108, an N-type second buffer layer 110, and a tunnel junction are sequentially grown between the polycrystalline bottom battery layer 106 and the top battery.
  • the N-type region 112 and the tunnel junction P-type region 114 form an anti-reflection layer 400 on the front metal electrode layer 200.
  • the GaAs cell is an AlGaAs back field 116, a P-type GaAs base region 118, an N-type AlGaAs emitter 120, an N-type AlGaInP or AlGaAs window layer 122, and an N+ type GaAS front surface epitaxially grown in the tunnel junction P-type region 114.
  • the contact layer 124 has a front metal electrode layer 200 on the front contact layer 124.
  • the window layer 122 in the present invention is exposed from the front contact layer 124, and its surface forms a roughened structure.
  • the double junction cell structure 127 is epitaxially grown on the GaAs substrate 100 by an epitaxial device such as MOCVD. Its epitaxial temperature is 650 ° C and the pressure is 76 torr.
  • the temperature of the GaAs substrate 100 is first raised to 750 ° C for 3-5 min for cleaning the GaAs substrate 100 and forming a step plane for epitaxial growth. Then, the temperature is lowered to 650 ° C to start growing the epitaxial structure of the battery;
  • the first device structure 105 includes a GaAs substrate 100, a first buffer layer 102, and a sacrificial layer 104.
  • a polycrystalline Ge material is deposited on the surface of the sacrificial layer 104 using an LPCVD apparatus to form a polycrystalline underlayer battery layer 106.
  • Heating to 500-800 ° C, in this embodiment is 600-700 ° C; the growth chamber is passed through pure decane and diborane, controlling the flow ratio of pure decane and diborane, the growth chamber pressure is 1 ⁇ 200 torr, and the growth thickness is
  • the P-type polycrystalline bottom cell layer 106 of 1-5 ⁇ m has a doping concentration of 4E 17 .
  • the surface of the polycrystalline ruthenium bottom battery layer 106 is chemically polished, and the etching liquid is a mixed etching solution of hydrogen peroxide and sodium hydroxide, and is polished after polishing.
  • the polished second device 107 is placed in MOCVD, and the second device 107 includes a GaAs substrate 100, a first buffer layer 102, a sacrificial layer 104, and a polysilicon bottom cell layer 106.
  • the temperature was raised to 650 ° C, and an N-type In x Ga 1-x P diffusion layer 108 of 20 nm was grown on the surface of the second device 107, x ⁇ 0.5. Then, the temperature was raised to 750 ° C for 2 min, and then the temperature was lowered to 650 ° C, and annealing was performed in an atmosphere of pH 3 to improve the crystal quality of the surface of the diffusion layer 108.
  • a 20 nm N+ type GaAs tunnel junction N-type region 112 is grown on the surface of the second buffer layer 110.
  • a P-type Al x Ga 1-x As back field 116 of 40 nm was grown on the surface of the tunnel junction P-type region 114, x ⁇ 0.7.
  • a P-type GaAs base region 118 of 3000 nm is grown on the surface of the back field 116.
  • a 20 nm N + -type GaAs front contact layer 124 was grown on the surface of the window layer 122, and was dropped to normal temperature after the epitaxial growth was completed.
  • Substrate peeling The GaAs substrate 100 and the double junction cell structure 127 were separated by EV selective etching of the sacrificial layer 104 by ELO technique, and then the PET film was removed by heating.
  • a back surface metal electrode layer 300 is formed on the back surface of the polycrystalline silicon substrate layer 106 by an electroplating method, and the thickness of the electrode is 1-10 ⁇ m, and the material is selected from copper or copper-nickel alloy;
  • Front electrode The front side of the battery is cleaned, and a front metal electrode layer 200 is deposited on the surface of the front contact layer 124 by an electroplating process.
  • the thickness of the electrode is 1-10 ⁇ m, and the material is copper or copper-nickel alloy.
  • the unnecessary front metal electrode layer 200 is removed by a photolithography process and a wet process to form a patterned front metal electrode layer 200.
  • the etching liquid is 30% FeCl 3 + 4% HCl + H 2 O, and is etched at room temperature.
  • the non-electrode-covered front contact layer 124 is removed by a wet etching process to expose the window layer 122, and the surface of the window layer 122 is surface roughened, and the etching liquid is NH 4 OH and H. 2 O 2 mixture, corrosive at room temperature.
  • the third device structure 125 at a specific position is completely separated by a wet etching process, and is etched to the polycrystalline bottom cell layer 106 to separate the epitaxial structure into a plurality of independent battery cells, using different ratios.
  • the etching solution of the mixture of H 3 PO 4 and H 2 O 2 , the mixture of HC1 and C 2 H 6 O 2 is sequentially corroded in turn.
  • Anti-reflection layer A layer of MgF 2 or ZnS anti-reflection layer 400 was deposited on the front side of the cell by PECVD.

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Abstract

一种双结薄膜太阳能电池组件及其制作方法，太阳能电池组件由多个电池单元串联而成，每个电池单元包括底电池和顶电池，底电池上设有背面金属电极层（300），顶电池上设有图形化的正面金属电极层（200），底电池为多晶Ge底电池层（106），顶电池为GaAs电池，多晶Ge底电池层至顶电池之间依次生长有N型的扩散层（108）、N型的缓冲层、隧道结N型区（112）和隧道结P型区（114），在正面金属电极层上形成减反射层（400）。采用GaAs衬底（100）、多晶锗和GaAs分别作为底电池和顶电池的双结电池，首先，多晶锗底电池的禁带宽度是0.65eV，顶电池GaAs的禁带宽度是1.4eV，该组合更有利于分割太阳能光谱，形成比较合理的电流匹配，而且能够进一步吸收波长在900-2000nm范围内的光线，电池转化效率可达到32％(AM1.5)。

Description

双结薄膜太阳能电池组件及其制作方法
相关申请
本发明申请要求2015年11月20日申请的，申请号为201510811983.1，名称为“一种双结薄膜太阳能电池组件及其制作方法”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本发明涉及一种III-V族双结薄膜电池组件的制作方法，更具体地讲，涉及一种多晶锗作为底电池，砷化镓作为顶电池的双结薄膜太阳能电池组件及其制作方法。
背景技术
1954年世界上首次发现GaAs材料具有光伏效应，20世纪60年代，Gobat等研制了第1个掺锌GaAs太阳能电池，转化率仅为9％～10％，远低于27％的理论值。最早的单结晶体GaAs电池的做法和现在的单晶硅做法基本相同，但是作为直接禁带半导体，吸收层厚度只需要几个微米，晶体GaAs无疑是巨大的浪费。
20世纪70年代，IBM公司和前苏联Ioffe技术物理所等为代表的研究单位，采用LPE(液相外延)技术引入GaAlAs异质窗口层，降低了GaAs表面的复合速率，使GaAs太阳电池的效率达16％。不久，美国的HRL(Hughes Research Lab)及Spectrolab通过改进LPE技术使得电池的平均效率达到18％，并实现批量生产，开创了高效率砷化镓太阳电池的新时代。
从上世纪80年代后，GaAs太阳能电池技术经历了从LPE到MOCVD，从同质外延到异质外延，从单结到多结叠层结构，从LM结构到IMM结构等几个发展阶段，其发展速度日益加快，效率也不断提高。目前最高效率已达到单结28.8％(alta devices)，三结44.4％(Sharp IMM)，四结实验室最高接近50％(Fhg-ISE)
目前锗衬底的三结GaAs电池是研究的重点，双结GaAs电池的研究比较少，通常双结电池都采用GaAs和InGaP作为底电池和顶电的双结电池，用电学和光学低损耗的隧道结连接而成。双结必须要考虑底电池和顶电池的禁带宽度匹配问题，对于AM0来说，最佳的禁带宽度是1.23eV和1.97eV，理论效率可以达到35.8％。目前技术上比较可行的是采用晶格匹配的材料从而放宽了对禁带宽度Eg的要求，而且由于底电池的禁带宽度是1.42eV，顶电池是1.9eV左右，两者的差值只有0.48eV左右，并且底电池的禁带宽度过大，不能吸收900nm以上波长的光线、最终的是造成底电池的光生电流密度小于顶电池的电流密度，导致二者的光生电流不匹配，会严重降低了电池的内量子效率。
双结GaAs电池通常都是GaAs作为衬底、GaAs和InGaP分别作为底电池和顶电池的双 结电池，这种双结电池成本比单结GaAs电池高，外延的成本几乎是单结的两倍，但效率比单结的稍微高一点，目前单结最高效率28.8％、双结最高效率30.8％，还需要使用大量的铟作为原材料。
另外，双结GaAs和GaInP的吸收层厚度都比较大，导致电池整体厚度大于10μm。而柔性薄膜电池的厚度一般要求在1-10μm之间，此类双结电池无法实现电池柔性。
发明内容
为了实现双结III-V族电池的柔性化，降低双结电池的制造成本，提高电池的发电效率，本发明提供了一种双结薄膜太阳能电池组件及其制作方法。
所采用技术方案如下所述：
一方面，本发明提供了一种薄膜互联太阳能电池组件，一种双结薄膜太阳能电池组件，由多个电池单元串联而成，每个电池单元包括底电池和顶电池，所述底电池上设有背面金属电极层，所述顶电池上设有图形化的正面金属电极层，所述底电池为多晶Ge底电池层，所述顶电池为GaAs电池，所述多晶Ge底电池层至所述顶电池之间依次生长有N型的扩散层、N型的缓冲层、隧道结N型区和隧道结P型区，所述正面金属电极层上形成减反射层。
所述缓冲层为N型的InGaAs-GaAs渐变缓冲层，其中铟的比例由1％渐变到0％。
所述GaAs电池为在所述隧道结P型区依次外延生长的AlGaAs背场、P型的GaAs基区、N型的AlGaAs发射极、N型的AlGaInP窗口层和N+型的GaAS正面接触层，所述正面金属电极层位于所述正面接触层上。
所述窗口层由所述正面接触层中外露，且其表面形成粗化结构。
另一方面，本发明还提供了一种双结薄膜太阳能电池的制作方法，所述方法包括如下步骤：
步骤一，在GaAs衬底上依次生长用于调节晶格匹配的InGaAs-GaAs渐变第一缓冲层和与多晶锗晶格匹配的牺牲层AlInAs；
步骤二，在牺牲层AlInAs表面沉积低掺杂P型多晶锗材料层，制得多晶锗底电池层；
步骤三，在多晶锗底电池层表面通过外延生长依次形成扩散层、隧道结和顶电池结构，形成双结电池结构；
步骤四，通过选择性腐蚀牺牲层的方法将GaAs衬底与双结电池结构分开；
步骤五，在双结电池结构的背面形成背面金属电极层，在双结电池结构的正面形成图形化的正面金属电极层；
步骤六，将位于多晶锗底电池层上方外延生长的双结电池结构分离成多个独立电池单元；
步骤七，在正面金属电极层上形成减反射层，并依次切割减反射层、多晶锗底电池层和 背面金属电极层，将各电池单元彻底分开；
步骤八，将各电池单元串联后置于上下两柔性衬底之间进行封装，制得薄膜电池组件。
所述步骤一中的在GaAs衬底上依次生长用于调节晶格匹配的InGaAs-GaAs渐变第一缓冲层和与多晶锗晶格匹配的牺牲层AlInAs，其具体方法是：
将GaAs衬底温度升高到700-750℃保持1-5min；然后降温至630-670℃开始生长电池外延结构；在P型的GaAs衬底表面上生长P型InGaAs-GaAs渐变的第一缓冲层，In的比例逐渐从0增加到1％；在缓冲层表面生长P型的InAlAs牺牲层，并降温至常温。
所述步骤三中的在多晶锗底电池层表面通过外延生长依次形成扩散层、隧道结和顶电池结构，其具体方法是：在多晶锗底电池层表面生长N型的InGaP扩散层；通过P元素在高温下向多晶锗底电池层内部进行扩散形成浅的扩散PN结；在PH3的氛围下对扩散层InGaP进行退火处理；在恒温条件下依次生长第二缓冲层、隧道结、顶电池的背场，基区，发射极、窗口层和正面接触层。
所述步骤五中在双结电池的正面接触层上通过电镀和湿法刻蚀方法形成图形化的正面金属电极层；然后去除未被正面金属电极层覆盖的正面接触层，露出窗口层并在窗口层表面形成粗化结构。
所述步骤八中的通过铜箔将分离后的各电池串联，然后置于上下两层PET薄膜之间，通过层压机封装形成薄膜柔性电池组件。
本发明相对于现有技术具有如下有益效果：
A.本发明采用GaAs衬底、多晶锗和GaAs分别作为底电池和顶电池的双结电池，首先，多晶锗底电池的禁带宽度是0.65eV，顶电池GaAs的禁带宽度是1.4eV，该组合更有利于分割太阳能光谱，形成比较合理的电流匹配，而且能够进一步吸收波长在900-2000nm范围内的光线，电池效率可达到32％。
B.本发明采用多晶锗底电池的制造成本比GaAs做底电池低，由于扩散结厚度、底电池的厚度可以小于1微米，且不需要生长复杂的电池结构，只需要通过高温扩散就能形成PN结，制作工艺简单；同时多晶锗作为底电池的价格也要比GaAs作为底电池价格低，且该电池仅缓冲层需要用到材料占比≤1％的铟，可以减少铟这种原材料的限制，因此可大大降低电池制造成本。
C.本发明中电池的正面金属电极层和背面金属电极层均采用电镀技术，以往蒸镀和溅射技术相比，电镀技术的成本更低，能够进一步的降低制造成本。
D.本发明在电池制作过程中加入了退火处理技术，能够进一步提高隧道结和顶电池的结晶质量，顶电池采用GaAs和AlGaAs材料可减少铟原材料的使用量。
附图说明
为了使本发明的内容更容易被清楚的理解，下面根据本发明的具体实施例并结合附图，对本发明作进一步详细的说明，其中
图1是多晶Ge/GaAs双结电池的外延结构示意图；
图2是多晶Ge/GaAs双结电池的电池结构示意图；
图3是本发明所提供的双结薄膜太阳能电池制作框图。
图中：100-GaAs衬底；102-第一缓冲层；104-牺牲层；106-多晶锗底电池层；108-扩散层；110-第二缓冲层；112-隧道结N型区；114-隧道结P型区；116-背场；118-基区；120-发射极；122-窗口层；124-正面接触层；105-第一器件结构；107-第二器件结构；125-第三器件结构；127-双结电池结构；200-正面金属电极层；300-背面金属电极层；400-减反射层。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。
结合图1、图2和图3所示，本发明提供一种多晶Ge(锗)作为底电池，GaAs(砷化镓)作为顶电池的双结柔性薄膜电池的制作方法，具体制作方法如下：
步骤一，采用MOCVD(Metal-organic Chemical Vapor DePosition金属有机化合物化学气相淀积)等外延设备在GaAs衬底100上依次生长调节晶格匹配的InGaAs渐变第一缓冲层102和与多晶锗晶格匹配的AlInAs牺牲层104；其中，In的含量最大值为1％。外延温度630-670℃，压力50-100torr，优选外延温度650℃，压力76torr。
步骤二，采用LPCVD(Low Pressure Chemical Vapor Deposition低压力化学气相沉积法)设备在AlInAs牺牲层104表面沉积一层低掺杂P型多晶锗材料，厚度在1-3μm左右，形成多晶锗底电池层106。
本发明在晶格匹配的AlInAs表面生长多晶锗底电池层106，以便能生长高质量的多晶锗，甚至能实现小角度多晶锗。其次采用多晶锗作为底电池层避免了复杂的结构设计，与采用GaAs底电池相比，采用多晶锗作为底电池层能够大大降低电池成本，还能够吸收900nm-1800nm范围内的光子，提高光电转化效率。
步骤三，在多晶锗底电池层106表面通过外延生长扩散层108、隧道结和顶电池结构，形成双结电池结构127。外延温度630-670℃，压力50-100torr，实施例中外延温度650℃，压力76torr。
具体地，升温到650℃，在多晶锗底电池层106表面生长N型的InGaP扩散层108；通过P元素在高温下向多晶锗底电池层106内部进行扩散形成浅的扩散PN结；在PH3的氛围 下对InGaP扩散层108进行退火处理，消除界面缺陷，保证扩散层108表面的晶体质量，有利于进一步外延生长形成隧道结和顶电池；降温到630-670℃，在恒温条件下依次生长第二缓冲层110、隧道结、顶电池的背场116，基区118，发射极120、窗口层122和正面接触层124，完成外延层的生长后降至常温。
本发明加入了退火处理方法，能够进一步提高隧道结和顶电池的结晶质量，顶电池采用GaAs和AlGaAs材料可减少In(铟)原材料的使用量。
步骤四，通过选择性腐蚀牺牲层104的方法将GaAs衬底100与双结电池结构127分开。
利用ELO(Epitaxy lift-off外延剥离)技术对GaAs衬底100进行剥离，剥离之后的GaAs衬底100经抛光之后可再次利用，剥离液采用一定温度的HF溶液。
步骤五，电池器件结构的制作，在双结电池结构127的背面形成背面金属电极层300，在双结电池结构127的正面形成图形化的正面金属电极层200。
具体地，采用整面电镀技术在电池背面镀一层金属层，形成背面金属电极层300；采用整面电镀技术在电池正面镀一层金属层，形成正面金属电极层200，通过湿法刻蚀工艺去除部分金属电极层，形成正面图形化的电极结构，金属层为铜电极层时蚀刻液为FeCl3和HCl的混合液；
去除多余的正面接触层124，露出窗口层122并在窗口层122表面形成粗化结构，目的是避免正面接触层124的GaAs材料吸收光线，常温腐蚀去除多余的正面接触层124，并形成表面粗化结构，蚀刻液为NH4OH和H2O2的混合物。
步骤六，采用湿法刻蚀工艺，将位于多晶锗底电池层106上方外延生长的双结电池结构127分离成多个独立电池单元。
采用湿法刻蚀工艺，将特定位置的第三器件结构125完全分离，一直腐蚀至多晶锗底电池层106，将外延结构初步分离成若干独立的电池单元，第三器件结构125包括扩散层108、第二缓冲层110、隧道结N型区112、隧道结P型区114、背场116、基区118、发射极120、窗口层122以及正面接触层124。
步骤七，在正面金属电极层200上形成减反射层400，然后依次切割减反射层400、多晶锗底电池层106和背面金属电极层300，将各电池单元彻底分开。
PECVD(Plasma Enhanced Chemical Vapor Deposition等离子体增强化学气相沉积法)在电池正面沉积一层MgF2或ZnS减反射层400；采用激光切割工艺切割减反射层400、多晶锗底电池层106和背面金属电极层300，将电池彻底分开。
步骤八，将各电池单元串联后置于上下两柔性衬底之间封装，制得薄膜电池组件。
将相邻的电池用铜箔进行串联；将串联好的的各电池单元放置在上下两层PET薄膜之间，采用层压机封装成薄膜柔性电池组件。
所制得的双结薄膜太阳能电池结构如图2所示。
其中的电池是由多个电池单元串联而成，每个电池单元包括底电池和顶电池，底电池上设有背面金属电极层300，顶电池上设有图形化的正面金属电极层200，其中底电池为多晶锗底电池层106，顶电池为GaAs电池，多晶锗底电池层106至顶电池之间依次生长有N型的扩散层108、N型的第二缓冲层110、隧道结N型区112和隧道结P型区114，正面金属电极层200上形成减反射层400。GaAs电池为在隧道结P型区114依次外延生长的AlGaAs背场116、P型的GaAs基区118、N型的AlGaAs发射极120、N型的AlGaInP或者AlGaAs窗口层122和N+型的GaAS正面接触层124，正面金属电极层200位于正面接触层124上。
本发明中的窗口层122由正面接触层124中外露，且其表面形成粗化结构。
以下通过具体实施例来说明双结薄膜电池的制作方法，如图1所示。
一、第一次外延生长电池结构
用MOCVD等外延设备在GaAs衬底100上外延生长双结电池结构127。其外延温度650℃，压力76torr。
(1)先将GaAs衬底100的温度升高到750℃保持3-5min，用于清洁GaAs衬底100和形成外延生长的台阶平面。然后降温到650℃开始生长电池外延结构；
(2)在P型的GaAs衬底100表面上生长一层50nm的P型的InGaAs渐变第一缓冲层102，In的比例逐渐从0增加到1％；
(3)在第一缓冲层102表面生长20nm的P型的InxAl1-xAs牺牲层104，x约1％。降至常温，将第一器件结构105从MOCVD中取出。第一器件结构105包括GaAs衬底100、第一缓冲层102和牺牲层104。
二、多晶锗底电池层的制备
(1)采用LPCVD设备在牺牲层104表面沉积一层多晶Ge材料，形成多晶锗底电池层106。加热至500～800℃，本实施例中为600-700℃；生长室通入纯锗烷和乙硼烷，控制纯锗烷和乙硼烷流量比，生长室压强1～200torr，生长厚度为1-5μm的P型多晶锗底电池层106，掺杂浓度4E17。
(2)采用化学抛光多晶锗底电池层106的表面，腐蚀液为过氧化氢和氢氧化钠混合腐蚀液，抛光后进行清洗。
三、第二次外延生长
(1)将抛光后的第二器件107放入到MOCVD中，第二器件107包括GaAs衬底100、第一缓冲层102、牺牲层104和多晶锗底电池层106。
升温到650℃，在第二器件107的表面生长20nm的N型的InxGa1-xP扩散层108，x≈0.5。然后升温到750℃保持2min，再降温到650℃，在PH3的氛围下进行退火，提高扩散层108表面的晶体质量。
(2)在扩散层108的表面生长20nm的500nm的N型的InGaAs-GaAs渐变第二缓冲层110，铟的比例逐渐从1％减少到0％。
(3)在第二缓冲层110的表面生长20nm的N+型的GaAs隧道结N型区112。
(4)在隧道结N型区112的表面生长20nm的P+型的AlxGa1-xAs隧道结P型区114，x≈0.7。
(5)在隧道结P型区114的表面生长40nm的P型的AlxGa1-xAs背场116，x≈0.7。
(6)在背场116的表面生长3000nm的P型的GaAs基区118。
(7)在基区118的表面生长50nm的N型的AlxGa1-xAs发射极120，x≈0.3。
(8)在发射极120的表面生长20nm的N型的(AlxGa1-x)yIn1-yP窗口层122，x≈0.7、y≈0.5。
(9)在窗口层122的表面生长20nm的N+型的GaAs正面接触层124，外延生长结束后降至常温。
四、衬底剥离
(1)正面层压：用压敏粘合剂PSA将外延Wafer正面键合到PET薄膜表面，在紫外光的条件下，加热到50℃，层压5min。
(2)衬底剥离：采用ELO技术，采用HF选择性腐蚀牺牲层104，将GaAs衬底100和双结电池结构127分开，然后加热去除PET薄膜。
五、双面金属电极层结构制作
(1)背面电极：采用电镀方法在多晶锗底电池层106的背表面形成背面金属电极层300，采用整面电镀，电极的厚度是1-10μm，材料选择铜或者铜镍合金；
(2)正面电极：清洗电池正面，采用电镀工艺，在正面接触层124表面沉积正面金属电极层200，电极的厚度是1-10μm，材料选择铜或者铜镍合金。
采用光刻工艺和湿法工艺，去除不需要的正面金属电极层200，形成图形化的正面金属电极层200，蚀刻液为30％FeCl3+4％HCl+H2O，常温蚀刻。
(3)去除正面接触层：采用湿法刻蚀工艺，将非电极覆盖的正面接触层124去除，露出窗口层122，并且窗口层122表面形成表面粗化结构，蚀刻液为NH4OH和H2O2的混合物，常温下腐蚀。
六、电池分离和镀前反射层
(1)湿法分离：采用湿法刻蚀工艺，将特定位置的第三器件结构125完全分离，一直腐蚀至多晶锗底电池层106，将外延结构分离成若干独立的电池单元，采用不同比例的H3PO4和H2O2混合液、HC1和C2H6O2混合液等腐蚀液，轮流依次腐蚀。
(2)减反射层：采用PECVD在电池正面沉积一层MgF2或ZnS减反射层400。
(3)激光分离:采用激光切割工艺，切割减反射层400、多晶锗底电池层106和背面金属电极层300，将电池彻底分开。
七、电池组件制作
(1)电池间串联：将相邻的电池用铜箔进行串联。
(2)层压：将串联好的的电池放置在上下两层PET之间，采用层压机封装成薄膜柔性电池组件。
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本发明的保护范围之中。

Claims (9)

  1. 一种双结薄膜太阳能电池组件，由多个电池单元串联而成，每个电池单元包括底电池和顶电池，所述底电池上设有背面金属电极层，所述顶电池上设有图形化的正面金属电极层，其特征在于，所述底电池为多晶Ge底电池层，所述顶电池为GaAs电池，所述多晶Ge底电池层至所述顶电池之间依次生长有N型的扩散层、N型的缓冲层、隧道结N型区和隧道结P型区，所述正面金属电极层上形成减反射层。
  2. 根据权利要求1所述的双结薄膜太阳能电池组件，其特征在于，所述缓冲层为N型的InGaAs-GaAs渐变缓冲层，其中铟的比例由1％渐变到0％。
  3. 根据权利要求1所述的双结薄膜太阳能电池组件，其特征在于，所述GaAs电池为在所述隧道结P型区依次外延生长的AlGaAs背场、P型的GaAs基区、N型的AlGaAs发射极、N型的AlGaInP或者AlGaAs窗口层和N+型的GaAs正面接触层，所述正面金属电极层位于所述正面接触层上。
  4. 根据权利要求3所述的双结薄膜太阳能电池组件，其特征在于，所述窗口层由所述正面接触层中外露，且其表面形成粗化结构。
  5. 一种双结薄膜太阳能电池组件的制作方法，其特征在于，所述方法包括如下步骤：
    步骤一，在GaAs衬底上依次生长用于调节晶格匹配的InGaAs-GaAs渐变第一缓冲层和与多晶锗晶格匹配的AlInAs牺牲层；
    步骤二，在所述AlInAs牺牲层表面沉积低掺杂P型多晶锗材料层，制得多晶锗底电池层；
    步骤三，在所述多晶锗底电池层表面通过外延生长依次形成扩散层、隧道结和顶电池结构，形成双结电池结构；
    步骤四，通过选择性腐蚀所述AlInAs牺牲层的方法将所述GaAs衬底与所述双结电池结构分开；
    步骤五，在所述双结电池结构的背面形成背面金属电极层，在所述双结电池结构的正面形成图形化的正面金属电极层；
    步骤六，将位于所述多晶锗底电池层上方外延生长的所述双结电池结构分离成多个独立电池单元；
    步骤七，在所述正面金属电极层上形成减反射层，并依次切割所述减反射层、所述多晶锗底电池层和所述背面金属电极层，将各电池单元彻底分开；
    步骤八，将所述各电池单元串联后置于上下两柔性衬底之间进行封装，制得薄膜电池组件。
  6. 根据权利要求5所述的双结薄膜太阳能电池组件的制作方法，其特征在于，所述步骤 一中的在所述GaAs衬底上依次生长用于调节晶格匹配的所述InGaAs-GaAs渐变第一缓冲层和与多晶锗晶格匹配的所述AlInAs牺牲层，其具体方法是：
    将所述GaAs衬底温度升高到700-750℃保持1-5min；然后降温至630-670℃开始生长电池外延结构；在P型的所述GaAs衬底表面上生长P型的所述InGaAs-GaAs渐变的第一缓冲层，In的比例逐渐从0增加到1％；在所述InGaAs-GaAs渐变第一缓冲层表面生长P型的所述InAlAs牺牲层，并降温至常温。
  7. 根据权利要求5所述的双结薄膜太阳能电池组件的制作方法，其特征在于，所述步骤三中的在所述多晶锗底电池层表面通过外延生长依次形成所述扩散层、隧道结和顶电池结构，其具体方法是：在所述多晶锗底电池层表面生长N型的InGaP扩散层；通过P元素在高温下向所述多晶锗底电池层内部进行扩散形成浅的扩散PN结；在PH3的氛围下对所述InGaP扩散层进行退火处理；在恒温条件下依次生长第二缓冲层、所述隧道结、顶电池的背场、基区、发射极、窗口层和正面接触层。
  8. 根据权利要求7所述的双结薄膜太阳能电池组件的制作方法，其特征在于，所述步骤五中在所述双结电池结构的所述正面接触层上通过电镀和湿法刻蚀方法形成所述图形化的正面金属电极层；然后去除未被所述正面金属电极层覆盖的所述正面接触层，露出所述窗口层并在所述窗口层表面形成粗化结构。
  9. 根据权利要求8所述的双结薄膜太阳能电池组件的制作方法，其特征在于，所述步骤八中通过铜箔将分离后的所述各电池单元串联，然后置于上下两层PET薄膜之间，通过层压机封装形成薄膜柔性电池组件。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110491964A (zh) * 2019-07-25 2019-11-22 中山德华芯片技术有限公司 一种柔性双面太阳能电池及其制备方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112713205A (zh) * 2021-03-29 2021-04-27 南昌凯迅光电有限公司 一种高抗辐照三结砷化镓太阳电池及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101345268A (zh) * 2007-07-13 2009-01-14 晶元光电股份有限公司 具有结合结构的半导体光电元件
CN101459204A (zh) * 2007-12-13 2009-06-17 昂科公司 反项变质多结太阳能电池中的指数掺杂层
CN104091849A (zh) * 2014-07-29 2014-10-08 天津三安光电有限公司 多结太阳能电池及其制备方法
CN104428908A (zh) * 2012-04-12 2015-03-18 阿聚尔斯佩西太阳能有限责任公司 太阳能电池堆叠

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1177375C (zh) * 2003-01-14 2004-11-24 河北科技大学 一种太阳能转换多结极联光电池
CN101499493A (zh) * 2009-02-23 2009-08-05 东南大学 一种三结太阳能电池
TWI425643B (zh) * 2009-03-31 2014-02-01 Sony Corp 固態攝像裝置及其製造方法、攝像裝置和抗反射結構之製造方法
CN101651169B (zh) * 2009-07-07 2011-04-20 扬州乾照光电有限公司 一种高效太阳电池的制备方法
US9076915B2 (en) * 2010-03-08 2015-07-07 Alliance For Sustainable Energy, Llc Boron, bismuth co-doping of gallium arsenide and other compounds for photonic and heterojunction bipolar transistor devices
CN102244114A (zh) * 2011-06-22 2011-11-16 厦门市三安光电科技有限公司 一种高倍聚光多结太阳能电池及其制备方法
CN102790120B (zh) * 2012-07-19 2015-04-01 中国科学院苏州纳米技术与纳米仿生研究所 GaInP/GaAs/Ge三结级联太阳能电池及其制备方法
CN104241416B (zh) * 2014-09-18 2017-01-25 瑞德兴阳新能源技术有限公司 一种含量子阱结构的三结太阳能电池

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101345268A (zh) * 2007-07-13 2009-01-14 晶元光电股份有限公司 具有结合结构的半导体光电元件
CN101459204A (zh) * 2007-12-13 2009-06-17 昂科公司 反项变质多结太阳能电池中的指数掺杂层
CN104428908A (zh) * 2012-04-12 2015-03-18 阿聚尔斯佩西太阳能有限责任公司 太阳能电池堆叠
CN104091849A (zh) * 2014-07-29 2014-10-08 天津三安光电有限公司 多结太阳能电池及其制备方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110491964A (zh) * 2019-07-25 2019-11-22 中山德华芯片技术有限公司 一种柔性双面太阳能电池及其制备方法

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