WO2017084024A1 - 低密度奇偶校验码的译码方法和译码器 - Google Patents

低密度奇偶校验码的译码方法和译码器 Download PDF

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WO2017084024A1
WO2017084024A1 PCT/CN2015/094783 CN2015094783W WO2017084024A1 WO 2017084024 A1 WO2017084024 A1 WO 2017084024A1 CN 2015094783 W CN2015094783 W CN 2015094783W WO 2017084024 A1 WO2017084024 A1 WO 2017084024A1
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ldpc
code
decoder
decoding
ldpc code
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PCT/CN2015/094783
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English (en)
French (fr)
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范嘉旗
司小书
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华为技术有限公司
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Priority to EP15908521.6A priority Critical patent/EP3364578B1/en
Priority to PCT/CN2015/094783 priority patent/WO2017084024A1/zh
Priority to CN201580002347.2A priority patent/CN107534511B/zh
Publication of WO2017084024A1 publication Critical patent/WO2017084024A1/zh
Priority to US15/982,503 priority patent/US10484009B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
    • H03M13/1117—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule
    • H03M13/112—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule with correction functions for the min-sum rule, e.g. using an offset or a scaling factor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
    • H03M13/1117—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using approximations for check node processing, e.g. an outgoing message is depending on the signs and the minimum over the magnitudes of all incoming messages according to the min-sum rule

Definitions

  • Embodiments of the present invention relate to the field of codecs and, more particularly, to a decoding method and a decoder for a Low Density Parity Check Code (LDPC).
  • LDPC Low Density Parity Check Code
  • the low density parity check code is a packet error correction code with a sparse check matrix, which is suitable for almost all channels. Because the performance of LDPC code is close to Shannon limit, it has the characteristics of simple description, simple implementation, easy theoretical analysis and research, simple decoding and parallel operation, suitable for hardware implementation. It has become a research hotspot in the field of communication in recent years.
  • a decoder supports multiple code lengths at the same time.
  • an LDPC decoder supports three LDPC code lengths of long code, medium code and short code.
  • Existing LDPC decoders are designed with the longest code length, for example, LDPC codes of various code lengths (56, 180, 360) are decoded by an LDPC decoder of 360 code length.
  • the LDPC decoder of this design decodes LDPC codes of different code lengths, so the degree of parallelism is different and the processing performance is different. For example, for a long code, the processing performance is high, but the resources used are large, and the timing is difficult; for the short code, the degree of parallelism is low, the processing performance is low, and the trafficability requirement cannot be met.
  • Embodiments of the present invention provide a decoding method and a decoder for an LDPC code, which can flexibly control the parallelism of decoding of an LDPC code.
  • a method of decoding an LDPC code is provided, the method being performed by a decoder of length d.
  • the decoder performs a packet operation, that is, groups the shift codes according to the length of the decoder. Specifically, the decoder obtains the t*m group LDPC subcode F according to the shift code E and the length d of the decoder. 1 , F 2 ,..., F tm-1 , F tm , wherein E j is divided into m groups, and among them m represents the (s-1)th+1th line to the sd line of E j , among them, Indicates an up rounding operation.
  • the decoder decodes the m sets of LDPC subcodes to obtain the decoding result of the LDPC code C.
  • the cyclically shifted LDPC code may be grouped according to the length of the decoder, and then the block code is decoded to obtain the decoding result of the LDPC code, so that the length of the decoder is not limited to the system.
  • the maximum code length of the supported LDPC code so that the decoding parallelism of the LDPC code can be flexibly controlled. For example, the decoding resource of the larger LDPC code can be reduced, and the processing performance of the smaller LDPC code can be improved. Can achieve a better balance of decoding performance and resources.
  • the embodiment of the present invention only needs a decoder with a length d, which can reduce the resources and computational complexity occupied by a single decoder, so that it can be flexibly applied to a resource-constrained scenario.
  • the decoder length d of the embodiment of the present invention is less than 360.
  • such a decoder has a low length and is not limited to the longest LDPC code length supported by the system, and thus is more suitable for a resource-limited scenario. .
  • the decoder obtains the decoding result of the LDPC code C when the m group LDPC subcode is decoded, and the decoder obtains the LDPC sub
  • the code corresponds to a Log Likelihood Ratio (LLR) value G 1 , G 2 , ..., G tm-1 , G tm .
  • the decoder can then update the variable nodes column by column according to the row update matrix to obtain a column update matrix.
  • the decoder can perform decision and check on the column update matrix to obtain the decoding result of the LDPC code C.
  • the decoder of the embodiment of the present invention can perform a row update operation on the grouped LDPC subcodes in the row update process, thereby implementing decoding of the longer length LDPC code by the decoder of a smaller length. process.
  • the LDPC code C is a Quasi-Cyclic Low Density Parity Check Code (QC-LDPC), Where l is the expansion factor of the QC-LDPC code.
  • QC-LDPC Quasi-Cyclic Low Density Parity Check Code
  • the QC-LDPC code is segmented, and the degree of parallelism of decoding can be flexibly controlled. At the same time, the decoding can be conveniently performed to reduce the decoding complexity.
  • d is 60 or 180.
  • the decoder when the decoder decodes the m group LDPC subcode to obtain the decoding result of the LDPC code C, the decoder may The m-group LDPC subcode is decoded by using a Min-sum decoding algorithm to obtain a decoding result of the LDPC code C.
  • a decoder for an LDPC code having a length d, and the decoder comprises: a segmentation unit, an arrangement unit, a shift unit, a packet unit, and a decoding unit.
  • Grouping unit performs packetization operation, i.e., the length decoder in accordance with the shift code packet, in particular, the packet group unit to obtain t * m sub LDPC codes according to the length F 1 d and the shift code decoder E, F 2 ,..., F tm-1 , F tm , where E j is divided into m groups, and among them m represents E j of (s-1) d + 1 to row line sd,
  • the decoding unit decodes the m sets of LDPC subcodes to obtain the decoding result of the LDPC code C.
  • the cyclically shifted LDPC code may be grouped according to the length of the decoder, and then the block code is decoded to obtain the decoding result of the LDPC code, so that the length of the decoder is not limited to the system.
  • the maximum code length of the supported LDPC code so that the decoding parallelism of the LDPC code can be flexibly controlled. For example, the decoding resource of the larger LDPC code can be reduced, and the processing performance of the smaller LDPC code can be improved. Can achieve a better balance of decoding performance and resources.
  • the embodiment of the present invention only needs a decoder with a length d, which can reduce the resources and computational complexity occupied by a single decoder, so that it can be flexibly applied to a resource-constrained scenario.
  • the decoder length d of the embodiment of the present invention is less than 360.
  • such a decoder has a low length and is not limited to the longest LDPC code length supported by the system, and thus is more suitable for a resource-limited scenario. .
  • the respective units of the decoder of the second aspect can also refer to the corresponding steps of the method in the first aspect, and will not be repeated here.
  • a method of decoding an LDPC code is provided, the method being performed by a decoder of length d.
  • the matrix E ⁇ E 1 , E 2 , ..., E t-1 , E t ⁇ , where t is equal to the number of rows of the target check matrix.
  • the decoder decodes the m sets of LDPC subcodes to obtain the decoding result of the LDPC code C.
  • the initialization check matrix may be grouped according to the length of the decoder, and then the block code is decoded to obtain the decoding result of the LDPC code.
  • the length of the decoder is not limited to the maximum code length of the LDPC code supported by the system, so that the degree of parallelism of decoding of the LDPC code can be flexibly controlled.
  • the decoding resource of a large LDPC code can be reduced. Improving the processing performance of a smaller LDPC code can achieve a better balance between decoding performance and resources.
  • the embodiment of the present invention only needs a decoder with a length d, which can reduce the resources and computational complexity occupied by a single decoder, so that it can be flexibly applied to a resource-constrained scenario.
  • the decoder length d of the embodiment of the present invention is less than 360.
  • such a decoder has a low length and is not limited to the longest LDPC code length supported by the system, and thus is more suitable for a resource-limited scenario. .
  • the decoder of the embodiment of the present invention can perform a row update operation on the grouped LDPC subcodes in the row update process, thereby implementing decoding of the longer length LDPC code by the decoder of a smaller length. process.
  • the embodiment of the present invention is substantially the same as the embodiment of the first aspect.
  • the decoder performs the transposition operation, the rotation operation, and the LLR value operation.
  • the initialization check matrix in the embodiment of the present invention may be followed by the same steps as the embodiment of the present invention, so that the decoding result of the LDPC code can be obtained.
  • a decoder for an LDPC code having a length d, and the decoder comprises: a segmentation unit, an initialization unit, a packet unit, and a decoding unit.
  • packetization operation i.e. length decoder in accordance with a parity check matrix of the initialization packet, in particular, a decoder to obtain t * m sub-group LDPC codes according to the length d F 1 and the initialization code decoder, F 2 , ..., F tm-1 , F tm , where E j ,
  • the decoding unit decodes the m sets of LDPC subcodes to obtain the decoding result of the LDPC code C.
  • the initialization check matrix may be grouped according to the length of the decoder, and then the block code is decoded to obtain the decoding result of the LDPC code.
  • the length of the decoder is not limited to the maximum code length of the LDPC code supported by the system, so that the degree of parallelism of decoding of the LDPC code can be flexibly controlled.
  • the decoding resource of a large LDPC code can be reduced. Improving the processing performance of a smaller LDPC code can achieve a better balance between decoding performance and resources.
  • the embodiment of the present invention only needs a decoder with a length d, which can reduce the resources and computational complexity occupied by a single decoder, so that it can be flexibly applied to a resource-constrained scenario.
  • the decoder length d of the embodiment of the present invention is less than 360.
  • such a decoder has a low length and is not limited to the longest LDPC code length supported by the system, and thus is more suitable for a resource-limited scenario. .
  • the respective units of the decoder of the fourth aspect can refer to the corresponding steps of the method in the third aspect, and will not be repeated here.
  • a communication device comprising the decoder of the second aspect or the decoder of the fourth aspect.
  • the communication device in the embodiment of the present invention may include a plurality of the above decoders, wherein the lengths of the decoders may be the same or different.
  • the decoders may be 60 in length and the other one or more decoders may be 180 in length.
  • the communication device includes a plurality of decoders, which can improve the decoding parallelism of the communication device.
  • FIG. 1 is a schematic flowchart of a decoding method of an LDPC code.
  • FIG. 2 is a schematic block diagram of a decoding method of an LDPC code.
  • FIG. 3 is a schematic block diagram showing the structure of a QC-LDPC code base matrix according to an embodiment of the present invention.
  • FIG. 4 is a schematic block diagram showing the structure of an element matrix of a QC-LDPC code base matrix according to an embodiment of the present invention.
  • FIG. 5 is a schematic flowchart of a method for decoding an LDPC code according to another embodiment of the present invention.
  • FIG. 6 is a schematic block diagram of a decoding method of an LDPC code according to another embodiment of the present invention.
  • FIG. 7 is a schematic block diagram of a decoding method of an LDPC code according to another embodiment of the present invention.
  • FIG. 8 is a schematic block diagram of a decoding method of an LDPC code according to another embodiment of the present invention.
  • FIG. 9 is a schematic block diagram of a decoding method of an LDPC code according to another embodiment of the present invention.
  • FIG. 10 is a schematic block diagram of a decoding method of an LDPC code according to an embodiment of the present invention.
  • FIG. 11 is a schematic block diagram of a decoding method of an LDPC code according to another embodiment of the present invention.
  • Figure 12 is a schematic block diagram of a decoder of an LDPC code in accordance with one embodiment of the present invention.
  • Figure 13 is a schematic block diagram of a communication device in accordance with an embodiment of the present invention.
  • LDPC decoding can be divided into two categories: hard decision decoding and soft decision decoding.
  • the processing object of hard decision decoding is binary data, the amount of calculation data is small, but the decoding performance is very limited; the processing object of soft decision decoding is LLR value, and the amount of calculated data is much larger, but it has good decoding performance.
  • the method of soft decision decoding is mainly used. Therefore, embodiments of the present invention mainly discuss a method of using soft decision decoding.
  • the following takes the Min-sum decoding algorithm as an example, and describes the flow based on the Min-sum decoding algorithm in detail with reference to FIG. 1 and FIG.
  • the parity check matrix H of a particular LDPC is unique, its dimension is P*N; and H is a sparse matrix in which the majority of the elements have a value equal to zero and only a very small number of values equal to one.
  • soft information ie, codeword C
  • codeword C soft information
  • the codeword C includes 7 LLR values, wherein
  • the LLR value is defined as the probability that the current bit r i is equal to 0 divided by the probability equal to 1, and then the logarithm of the result.
  • the distribution of 1 in the check matrix H is shown in (b) of FIG. 2, the square of the dark background represents 1 and the square without background represents 0; according to the distribution position of the H matrix 1, the value of the variable node is initialized with the APP value.
  • the value of the position where the i-th column is 1 is ci.
  • the value of the first row of the first column is c1
  • the value of the third row of the fifth column is c5.
  • the check node Lr ji is updated row by row, as shown in (c) of FIG. 2; the point to be updated is removed, and the sign bits of other check nodes of the line are multiplied as the output sign bit of the current point; Point, take the minimum value of the absolute value of other check nodes as the absolute value of the output of the current point; update line by line until the 4 lines are updated.
  • the updating process is as shown in the formula (2), wherein R j/i represents the set of the column index not equal to i in the jth row, and Lr ji represents the value of the i-th column of the j-th row after the check matrix row is updated.
  • the value of column 1 of row 1 is Sign*Min(c3, c5); the value of column 2 of row 2 is Sign*Min(c4, c6).
  • ⁇ l ⁇ Cj/i Lr ji indicates that the point of the i-th column of the current j-th row is removed, and the values of the other variable nodes of the i-th column are added to obtain the updated value of the point of the i-th column of the j-th row.
  • the first to fourth rows are denoted by A, B, C, and D, respectively, and the column numbers are represented by numbers.
  • A1 indicates the first row and the first column after the column update.
  • the value of the point, C5 represents the value of the point in the fifth row and the fifth column.
  • the value of the first row and the first column A1 Sign*Min(c5, c7).
  • the total variable node value corresponding to column 1 is A1+C1+c1.
  • the first K (three) bits are output as the final output.
  • the check matrix of the QC-LDPC is determined by two parameters, a base matrix H1 and an expansion factor L.
  • Each element in the base matrix represents a square matrix of L*L, and the square matrix value is determined by the value of that element.
  • the values of the elements in the base matrix can be divided into two types, -1 and non-1.
  • -1 represents a zero matrix of L*L
  • a value other than -1, such as k represents a matrix obtained by dividing the unit matrix of L*L by a column vector by right shifting k times, then 0 represents an L*L
  • the unit matrix; 1 represents the matrix obtained by the unit matrix being rotated right by the column vector.
  • k ranges from -1, 0, 1, ..., L-1.
  • Figure 4 depicts the case where k is equal to the matrix content represented by the values of 0, 1, and 2. The case where k takes other values can be obtained by analogy. I will not repeat them here.
  • this type of check matrix H can be represented by the base matrix H1 and the expansion factor L.
  • H1 needs to be stored, compared to the manner in which the original check matrix H is generally stored. The amount of storage is greatly reduced. Therefore, in many scenarios, QC-LDPC is widely used.
  • each element represents a set of L*L data. Since each element of the QC-LDPC basis matrix is a zero matrix of L*L, or a unit matrix, or a shifted array of unit arrays, each base matrix element is only associated with a fixed L LLR data. And there is only one 1 per small row or small column, that is, only related to one LLR data. In order to facilitate the operation, the input LLR data is generally divided into multiple groups, and each group of L LLR data is cyclically shifted according to the value of each element of the base matrix, and then aligned and then operated.
  • an LDPC decoder supports a plurality of LDPC code lengths at the same time, for example, the three code lengths described above, although the performance of the long code L decoding traffic is high, a large amount of resources are consumed; and for the short code L, Parallelism and processing performance are low, less than one-sixth of the long code, which does not meet the traffic performance requirements.
  • the embodiment of the present invention provides a decoding method for an LDPC code, which solves the problem that the processing performance of multiple LDPC code lengths is inconsistent, the long code occupies more resources, and the short code processing performance is low.
  • FIG. 5 is a flowchart of a decoding method of an LDPC code according to an embodiment of the present invention.
  • the method of Figure 5 can be performed by a decoder of an LDPC code.
  • the decoder may be located in a receiving device of the LDPC code, for example by a processor in the receiving device, or by a dedicated LDPC code decoder in the receiving device.
  • the length of the LDPC code refers to the number of bits included in the LDPC code.
  • the LDPC code C refers to the original LDPC code that needs to be decoded.
  • the LDPC code may be a QC-LDPC code.
  • the segmentation may be performed according to the expansion factor of the base matrix of the QC-LDPC code.
  • Other LDPC codes can also be processed according to a similar segmentation method, and details are not described herein again.
  • each segment of the code after segmentation can be regarded as a matrix of 1*l, and any operation on the segmentation code can be regarded as a corresponding operation on the matrix of 1*l.
  • the decoder arranges the segmentation codes in columns, which can be regarded as a transposition operation on a 1*l matrix.
  • the result of the operation is a matrix of l*1, that is, the result of the operation can be regarded as k A matrix of l*1.
  • the target check matrix refers to the check matrix actually stored when the logic is implemented. For example, if the input of the decoder is a QC-LDPC code, then the target check matrix is the base matrix of the QC-LDPC code, and And the dimension of the base matrix is t*k, and the dimension of the corresponding original check matrix is (t*l)*(k*l).
  • the decoder obtains t*m group LDPC subcodes F 1 , F 2 , . . . , F tm-1 , F tm according to the shift code E and the length d of the decoder, wherein E j is divided into m groups, and among them m represents the (s-1)th+1th line to the sd line of E j ,
  • E j is Composed, in fact, E j can be viewed as a matrix, expressed as:
  • the decoder decodes the m group LDPC subcode to obtain a decoding result of the LDPC code C.
  • the cyclically shifted LDPC codes may be grouped according to the length of the decoder.
  • the block code is further decoded to obtain the decoding result of the LDPC code, so that the length of the decoder is not limited to the maximum code length of the LDPC code supported by the system, so that the decoding parallel degree of the LDPC code can be flexibly controlled. For example, the cost of decoding a large LDPC code can be reduced, the processing performance of a smaller LDPC code can be improved, and the decoding performance and resources can be better balanced.
  • the embodiment of the present invention only needs a decoder with a length d, which can reduce the resources and computational complexity occupied by a single decoder, so that it can be flexibly applied to a resource-constrained scenario.
  • the decoder length d of the embodiment of the present invention is less than 360.
  • such a decoder has a low length and is not limited to the longest LDPC code length supported by the system, and thus is more suitable for a resource-limited scenario. .
  • step 220 and step 230 may not be performed.
  • the decoder of the embodiment of the present invention can perform a row update operation on the grouped LDPC subcodes in the row update process, thereby implementing decoding of the longer length LDPC code by the decoder of a smaller length. process.
  • the decoder when the decoder decodes the m sets of LDPC subcodes, the m-group LDPC subcodes may be decoded by using a Min-sum decoding algorithm to obtain the translation of the LDPC code C. Code result.
  • Min-sum decoding algorithm is a commonly used algorithm for LDPC code decoding, but the present invention does not limit a specific decoding algorithm.
  • the code's expansion factor l 8 divides the QC-LDPC code into 10 segments, and the obtained segmentation code can be expressed as:
  • the QC-LDPC code is segmented, and the degree of parallelism of decoding can be flexibly controlled. At the same time, the decoding can be conveniently performed to reduce the decoding complexity.
  • the QC-LDPC code C can be regarded as a matrix of 1*80, each segment code is regarded as a matrix of 1*8, and FIG. 6 is segmentation of the QC-LDPC code. schematic diagram.
  • the base matrix of the QC-LDPC code is taken as an example of the base matrix shown in FIG. 3 .
  • the above segmentation codes are arranged in columns to obtain a transposition code as shown in FIG.
  • the transposed code is shifted according to the value of the corresponding element in the base matrix.
  • the value of the first column element shown in FIG. 8 is a result of cyclically shifting the elements of the first column of the segmentation code by the value 3 of the element in the first column of the first row in the base matrix. Similarly, similar operations are performed on other columns of the segmentation code.
  • the transposition codes are correspondingly shifted according to the corresponding elements in the second row, the third row and the fourth row in the base matrix, and a matrix as shown in FIG. 8 can be obtained.
  • the shift codes shown in FIG. 8 are grouped according to the length of the decoder. For example, when the length of the decoder is 4, the shift codes shown in FIG. 8 can be divided into 8 groups, that is, as shown in FIG. The groups of F 1 , F 2 , F 3 , F 4 , F 5 , F 6 , F 7 and F 8 are shown. That is to say, the QC-LDPC code can be divided into 8 groups of QC-LDPC subcodes.
  • Min-sum decoding algorithm may, F 2 group, F 3 group, F 4 group, F 5 group, F 6 group, and the order of the group F 7 F 8 groups sequentially decoded according to the group F 1
  • F 1 For a specific decoding method, reference may be made to the decoding method of the LDPC code described above in conjunction with FIGS. 1 and 2.
  • the previously obtained shift code can be directly used for check node update.
  • the element 3 of the first row and the first column in the base matrix represents a matrix obtained by cyclically shifting the unit matrix of 8*8 by the column vector by 3 times, as shown in FIG. 9(a), It is initialized, and the obtained matrix is as shown in (b) of FIG. 9.
  • the elements of the first row to the fourth row are sequentially a4, a5, a6, a7, and FIG.
  • the first four rows of element values of the first column of the shift code shown are also a4, a5, a6, a7, as can be seen, the shift The checksum update can be completed by performing the corresponding operation on the bit code.
  • the value of the base element of the matrix of four rows in the matrix can be obtained as shown in FIG. 8 32 * 10, during check node update, the group F 1 of the first check node update, i.e. for the 32 * The first four rows of the matrix of 10 are updated, and the check nodes are updated for the F 2 group, that is, the fifth row to the eighth row of the 32*10 matrix are updated. Similarly, the remaining sets of row updates are made. For specific processing, refer to step 105. To avoid repetition, details are not described herein. This completes the update of all check nodes, and the resulting matrix can be called a row update matrix.
  • variable node is updated according to the row update matrix to obtain a column update matrix.
  • step 106 For specific processing, refer to step 106. To avoid repetition, details are not described herein.
  • the total variable node value is calculated, the decision and the check are performed, and finally the decoding result can be obtained.
  • the decoding result can be obtained.
  • the embodiment of the present invention divides the LDPC code of length n into a multi-segment LDPC code of length l, arranges and cyclically shifts the segmented LDPC code, and groups the cyclically shifted LDPC codes. It is feasible and effective to decode the block code to obtain the decoding result of the LDPC code.
  • the embodiment of the present invention may group the cyclically shifted LDPC codes according to the length of the decoder, and then decode the block code to obtain the decoding result of the LDPC code, so that the length of the decoder is not affected. It is limited to the maximum code length of the LDPC code supported by the system, so that the decoding parallelism of the LDPC code can be flexibly controlled. For example, the decoding resource of the larger LDPC code can be reduced, and the smaller LDPC code can be improved. Processing performance enables a better balance of decoding performance and resources.
  • the embodiment of the present invention only needs a decoder with a length d, which can reduce the resources and computational complexity occupied by a single decoder, so that it can be flexibly applied to a resource-constrained scenario.
  • the decoder length d of the embodiment of the present invention is less than 360.
  • such a decoder has a low length and is not limited to the longest LDPC code length supported by the system, and thus is more suitable for a resource-limited scenario. .
  • d may be 60 or 180.
  • the long code can be divided into 6 groups, each group of 60 data, after processing 6 sets of data, the line update is completed; the middle code can be divided into 3 groups, each group of 60 data, after processing 6 sets of data , the line update is completed; Short codes are not grouped, still processed according to 56 data, and 4 data is wasted, the performance loss is very small, only 4/60, that is, one-twelfth.
  • the parallelism of an LDPC decoding module is only 60 at the maximum, the resources are also reduced, the timing is better, and the performance of the long, medium, and short codes is basically the same.
  • the code block received by the decoder includes only any two code lengths of the long, medium and short codes, it can also be decoded as described above. It should be understood that the three code lengths in DOCSIS 3.1 are taken as an example here. The present invention does not limit the LDPC codes of other code lengths and other specific parallel degrees. The specific operations may be processed according to requirements and available resources.
  • the degree of parallelism in the above example is only 60, the processing performance is low.
  • a plurality of decoders can be instantiated, and the processing capability is also doubled. That is to say, when at least two code blocks of the plurality of code blocks received by the decoder include LDPCs of multiple code lengths, multiple decoders may be used for decoding.
  • the decoder when at least two code blocks received by the decoder include a plurality of LDPCs of length n, two decoders, namely 1# and 2#, can be instantiated by using two lengths of 60.
  • the decoder forms a decoder of length 120, which can increase the parallelism of the LDPC decoding module to 120.
  • the resources will be doubled, the processing performance will be doubled.
  • the performance of the three medium-length lengths is basically the same.
  • FIG. 12 is a block diagram of a decoder of an LDPC code according to an embodiment of the present invention.
  • the decoder 400 of FIG. 12 includes a segmentation unit 410, an arrangement unit 420, a shift unit 430, a grouping unit 440, and a decoding unit 450.
  • the grouping unit 440 obtains t*m group LDPC subcodes F 1 , F 2 , . . .
  • the decoding unit 450 decodes the m sets of LDPC subcodes to obtain the decoding result of the LDPC code C.
  • the cyclically shifted LDPC code may be grouped according to the length of the decoder, and then the block code is decoded to obtain the decoding result of the LDPC code, so that the length of the decoder is not limited to the system.
  • the maximum code length of the supported LDPC code so that the decoding parallelism of the LDPC code can be flexibly controlled. For example, the decoding resource of the larger LDPC code can be reduced, and the processing performance of the smaller LDPC code can be improved. Can achieve a better balance of decoding performance and resources.
  • the embodiment of the present invention only needs a decoder with a length d, which can reduce the resources and computational complexity occupied by a single decoder, so that it can be flexibly applied to a resource-constrained scenario.
  • the decoder length d of the embodiment of the present invention is less than 360.
  • such a decoder has a low length and is not limited to the longest LDPC code length supported by the system, and thus is more suitable for a resource-limited scenario. .
  • the decoder may not include the segmentation unit 420 and the shift unit 430, but may include an initialization unit.
  • the matrix E ⁇ E 1 , E 2 , ..., E t-1 , E t ⁇ , where t is equal to the number of rows of the target check matrix.
  • the grouping unit 440 groups the initialization check matrix according to the length of the decoder to obtain a t*m group LDPC subcode, and further can be decoded by using the decoder of the embodiment of the present invention.
  • the decoding unit 450 is specifically configured to: obtain a log likelihood ratio LLR value G 1 , G 2 , . . . , G tm-1 , G tm corresponding to the LDPC subcode; according to the LLR value.
  • a log likelihood ratio LLR value G 1 , G 2 , . . . , G tm-1 , G tm corresponding to the LDPC subcode according to the LLR value.
  • check node update is performed to obtain a row update matrix
  • the variable node is updated column by column to obtain a column update matrix
  • the matrix performs decision and check to obtain the decoding result of the LDPC code C.
  • the decoder in the embodiment of the present invention may be implemented entirely by dedicated hardware, such as a dedicated chip, an integrated circuit, or other firmware; or may be implemented by a general-purpose processor and its instructions, and the instructions may be stored in the processor. Or stored in a separate memory. These forms are all within the scope of embodiments of the invention.
  • the LDPC code C is a quasi-cyclic low-density parity check code QC-LDPC, where l is an expansion factor of the QC-LDPC code.
  • d is 60 or 180.
  • the decoding unit 450 decodes the m group of the LDPC subcodes by using a Min-sum decoding algorithm to obtain a decoding result of the LDPC code C.
  • FIG. 13 is a schematic block diagram of a communication device in accordance with another embodiment of the present invention.
  • the communication device 600 of FIG. 13 can be used to implement the steps and methods in the foregoing method embodiments.
  • the communication device 600 can be applied to a base station or terminal in various communication systems.
  • the communication device 600 includes a transmitting circuit 602, a receiving circuit 603, a decoding processor 604, a processing unit 605, a memory 606, and an antenna 601.
  • Processing unit 605 controls the operation of device 600 and can be used to process signals.
  • the processing unit 605 may also be referred to as a CPU (Central Processing Unit).
  • Memory 606 can include read only memory and random access memory and provides instructions and data to processing unit 605.
  • a portion of memory 606 may also include non-volatile line random access memory (NVRAM).
  • the communication device 600 can embed or itself be a wireless communication device such as a mobile telephone, and can also include a carrier that houses the transmit circuitry 602 and the receive circuitry 603 to allow for data transmission between the device 60 and the remote location. And receiving. Transmit circuit 602 and receive circuit 603 can be coupled to antenna 601.
  • the various components of communication device 600 are coupled together by a bus system 609, which in addition to the data bus includes a power bus, a control bus, and a status signal bus. However, for clarity of description, various buses are labeled as bus system 609 in the figure.
  • Decoding processor 604 may be an integrated circuit chip with signal processing capabilities. In an implementation process, the steps of the above method may be completed by an integrated logic circuit of the hardware in the decoding processor 604 or an instruction in the form of software. These instructions can be implemented and controlled by processing unit 605.
  • the above decoding processor may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable Logic devices, discrete gates or transistor logic devices, discrete hardware components.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA off-the-shelf programmable gate array
  • the general purpose processor may be a microprocessor or the processor or any conventional processor, decoder or the like.
  • the steps of the method disclosed in the embodiments of the present invention may be directly implemented by the hardware decoding processor, or may be performed by a combination of hardware and software modules in the decoding processor.
  • the software module can be located in a conventional storage medium such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the storage medium is located in the memory 606, and the decoding processor 604 reads the information in the memory 606. The steps of the above method are completed in combination with the hardware.
  • memory 606 can store instructions that cause decoding processor 604 or processing unit 605 to perform the following process:
  • E j is divided into m groups, and among them m represents the (s-1)th+1th line to the sd line of E j ,
  • the m group LDPC subcode is decoded to obtain the decoding result of the LDPC code C.
  • the cyclically shifted LDPC code may be grouped according to the length of the decoder, and then the block code is decoded to obtain the decoding result of the LDPC code, so that the length of the decoder is not limited to the system.
  • the maximum code length of the supported LDPC code so that the decoding parallelism of the LDPC code can be flexibly controlled. For example, the decoding resource of the larger LDPC code can be reduced, and the processing performance of the smaller LDPC code can be improved. Can achieve a better balance of decoding performance and resources.
  • the embodiment of the present invention only needs a decoder with a length d, which can reduce the resources and computational complexity occupied by a single decoder, so that it can be flexibly applied to a resource-constrained scenario.
  • the decoder length d of the embodiment of the present invention is less than 360.
  • such a decoder has a low length and is not limited to the longest LDPC code length supported by the system, and thus is more suitable for a resource-limited scenario. .
  • Memory 606 can store instructions that cause decoding processor 604 or processing unit 605 to perform the respective steps of reference method 200, and are not repeated here.
  • system and “network” are used interchangeably herein.
  • the term “and/or” in this context is merely an association describing the associated object, indicating that there may be three relationships, for example, A and / or B, which may indicate that A exists separately, and both A and B exist, respectively. B these three situations.
  • the character "/" in this article generally indicates that the contextual object is an "or" relationship.
  • B corresponding to A means that B is associated with A, and B can be determined according to A.
  • determining B from A does not mean that B is only determined based on A, and that B can also be determined based on A and/or other information.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of cells is only a logical function division.
  • multiple units or components may be combined or integrated. Go to another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, or an electrical, mechanical or other form of connection.
  • the units described as separate components may or may not be physically separate, as a single
  • the components displayed by the meta may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiments of the present invention.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another.
  • a storage medium may be any available media that can be accessed by a computer.
  • computer readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage media or other magnetic storage device, or can be used for carrying or storing in the form of an instruction or data structure.
  • connection may suitably be a computer readable medium.
  • the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave
  • coaxial cable , fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, wireless, and microwave are included in the fixing of the associated media.
  • a disk and a disc include a compact disc (CD), a laser disc, a compact disc, a digital versatile disc (DVD), a floppy disk, and a Blu-ray disc, wherein the disc is usually magnetically copied, and the disc is The laser is used to optically replicate the data. Combinations of the above should also be included within the scope of the computer readable media.

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Abstract

本发明实施例提供了一种LDPC码的译码方法和译码器，该方法包括：译码器将长度为n的LDPC码C分为k个LDPC码D＝{D1，D2，...，Dk-1，Dk}；译码器将Di，i＝1，2，...，k-1，k按列进行排列，得到LDPC码D的转置码式I；根据目标校验矩阵中对应元素的值，对式II，i=1, 2,..., k-1, k按行进行循环移位，得到移位码E＝{E1，E2，...，Et-1，Et}，其中t等于目标校验矩阵的行数；译码器根据移位码E和译码器的长度d得到t*m组LDPC子码F1，F2，...，Ftm-1，Ftm，其中Ej分为m组，且式III，其中m=[l/d]；译码器对m组LDPC子码进行译码，以获取LDPC码C的译码结果。这样能够灵活地控制LDPC码的译码并行度，能够使译码性能和资源达到更佳平衡。

Description

低密度奇偶校验码的译码方法和译码器 技术领域
本发明实施例涉及编解码领域，并且更具体地，涉及低密度奇偶校验码(Low Density Parity Check Code，LDPC)的译码方法和译码器。
背景技术
低密度奇偶校验码是具有稀疏校验矩阵的分组纠错码，几乎适用于所有的信道。由于LDPC码的性能逼近香农(Shannon)限，具有描述和实现简单，易于进行理论分析和研究，译码简单且可实行并行操作，适合硬件实现等特点，近年来已经成为通信领域的研究热点。
LDPC码具有多种码长，例如DOCSIS 3.1协议中规定了三种码长，其中长码码长L＝360，中码码长L＝180，短码码长L＝56。一般而言，一个译码器要同时支持多种码长，例如，一个LDPC译码器同时要支持长码、中码和短码三种LDPC码长。现有的LDPC译码器是按照最长的码长设计的，例如以360码长的LDPC译码器来对各种码长(56、180、360)的LDPC码进行译码。这种设计的LDPC译码器在对不同码长的LDPC码进行译码时，由于运算使用的处理单元数目不同，因此并行度不同，处理性能不同。例如，对于长码，处理性能高，但使用的资源多，时序困难；对于短码，并行度较低，处理性能低，不能满足流量性要求。
发明内容
本发明实施例提供了一种LDPC码的译码方法和译码器，能够灵活控制LDPC码的译码并行度。
第一方面，提供了一种LDPC码的译码方法，该方法由长度为d的译码器执行。
首先，译码器执行分段操作，即译码器将长度为n的LDPC码C＝{c1,c2,c3,…,cn-1,cn}分为k个LDPC码D＝{D1,D2,…,Dk-1,Dk}，其中，Di＝{c(i-1)l+1,c(i-1)l+2,…,cil-1,cil}，i＝1,2,...,k-1,k，且Di的长度l＝n/k。
然后，译码器执行转置操作，即将Di，i＝1,2,...,k-1,k按列进行排列，得到LDPC码D的转置码
Figure PCTCN2015094783-appb-000001
其中，
Figure PCTCN2015094783-appb-000002
然后，译码器执行旋转操作(或者称为循环移位操作)，即根据目标校验矩阵中对应元素的值，对
Figure PCTCN2015094783-appb-000003
k按行进行循环移位，得到移位码E＝{E1,E2,…,Et-1,Et}，其中t等于目标校验矩阵的行数，且Ej，j＝1,2,...,t-1,t为根据目标校验矩阵中第j行的元素对DT移位的结果。
然后，译码器执行分组操作，即按照译码器的长度对移位码进行分组，具体地，译码器根据移位码E和译码器的长度d得到t*m组LDPC子码F1,F2,…,Ftm-1,Ftm，其中Ej分为m组，且
Figure PCTCN2015094783-appb-000004
其中
Figure PCTCN2015094783-appb-000005
m表示Ej的第(s-1)d+1行到sd行，
Figure PCTCN2015094783-appb-000006
其中，
Figure PCTCN2015094783-appb-000007
表示向上取整运算。
最后，译码器对m组LDPC子码进行译码，以获取LDPC码C的译码结果。
本发明实施例可按照译码器的长度对循环移位后的LDPC码进行分组，再对分组码进行译码，以获取LDPC码的译码结果，这样译码器的长度不受限于系统支持的LDPC码的最大码长，从而可以灵活地控制LDPC码的译码并行度，例如，可以减少l较大的LDPC码的耗费的译码资源，提高l较小的LDPC码的处理性能，能够使译码性能和资源达到更佳平衡。
另外，本发明实施例只需长度为d的译码器，可以降低单个译码器所占用的资源和计算复杂度，这样可以灵活地应用于资源受限的场景。一般而言，本发明实施例的译码器长度d小于360，显然，这样的译码器长度较低，也不必局限于系统支持的最长LDPC码长，因此更加适合于资源受限的场景。
译码器执行的上述分段操作、转置操作和循环移位操作可类似于现有的对应操作，因此本发明实施例可不做详细描述。
结合第一方面，在第一方面的第一种实现方式中，译码器在对m组LDPC子码进行译码以获取LDPC码C的译码结果时，译码器可获取与该LDPC子码对应的对数似然比(Log Likelihood Ratio，LLR)值G1,G2,…,Gtm-1,Gtm。然后译码器可根据LLR值，按照r＝1,2,...,tm-1,tm的顺序，进行校验节点更新，得到行更新矩阵。然后译码器可根据行更新矩阵，逐列更新变量节点，得到列更新矩阵。最后，译码器可对列更新矩阵进行判决和校验，以获取 LDPC码C的译码结果。
这样，本发明实施例的译码器可以在行更新过程中对分组后的LDPC子码分别进行行更新操作，从而实现以较小长度的译码器对较长长度的LDPC码进行译码的过程。
结合第一方面或其上述实现方式，在第一方面的第二种实现方式中，该LDPC码C为准循环低密度奇偶校验码(Quasi-Cyclic Low Density Parity Check Code，QC-LDPC)，其中，l为QC-LDPC码的膨胀因子。
按照QC-LDPC码的膨胀因子的大小对QC-LDPC码进行分段，可以灵活控制译码并行度，同时，可以方便地进行译码，降低译码复杂度。
结合第一方面或其上述实现方式，在第一方面的第三种实现方式中，d为60或180。
结合第一方面或其上述实现方式，在第一方面的第四种实现方式中，译码器在对m组LDPC子码进行译码以获取LDPC码C的译码结果时，译码器可采用最小和(Min-sum)译码算法对m组LDPC子码进行译码，以获取该LDPC码C的译码结果。
第二方面，提供了一种LDPC码的译码器，该译码器的长度为d，译码器包括：分段单元、排列单元、移位单元、分组单元和译码单元。
分段单元执行分段操作，即将长度为n的LDPC码C＝{c1,c2,c3,…,cn-1,cn}分为k个LDPC码D＝{D1,D2,…,Dk-1,Dk}，其中，Di＝{c(i-1)l+1,c(i-1)l+2,…,cil-1,cil}，i＝1,2,...,k-1,k，且Di的长度l＝n/k。
排列单元执行转置操作，即将Di,i＝1,2,...,k-1,k按列进行排列，得到LDPC码D的转置码
Figure PCTCN2015094783-appb-000008
其中，
Figure PCTCN2015094783-appb-000009
移位单元执行旋转操作(或者称为循环移位操作)，即根据目标校验矩阵中对应元素的值，对
Figure PCTCN2015094783-appb-000010
k按行进行循环移位，得到移位码E＝{E1,E2,…,Et-1,Et}，其中t等于目标校验矩阵的行数，且Ej，j＝1,2,...,t-1,t为根据目标校验矩阵中第j行的元素对DT移位的结果。
分组单元执行分组操作，即按照译码器的长度对移位码进行分组，具体地，分组单元根据移位码E和译码器的长度d得到t*m组LDPC子码F1,F2,…,Ftm-1,Ftm，其中Ej分为m组，且
Figure PCTCN2015094783-appb-000011
其中
Figure PCTCN2015094783-appb-000012
m表示Ej的第(s-1)d+1行到sd行，
Figure PCTCN2015094783-appb-000013
译码单元对m组LDPC子码进行译码，以获取LDPC码C的译码结果。
本发明实施例可按照译码器的长度对循环移位后的LDPC码进行分组，再对分组码进行译码，以获取LDPC码的译码结果，这样译码器的长度不受限于系统支持的LDPC码的最大码长，从而可以灵活地控制LDPC码的译码并行度，例如，可以减少l较大的LDPC码的耗费的译码资源，提高l较小的LDPC码的处理性能，能够使译码性能和资源达到更佳平衡。
另外，本发明实施例只需长度为d的译码器，可以降低单个译码器所占用的资源和计算复杂度，这样可以灵活地应用于资源受限的场景。一般而言，本发明实施例的译码器长度d小于360，显然，这样的译码器长度较低，也不必局限于系统支持的最长LDPC码长，因此更加适合于资源受限的场景。
第二方面的译码器的各个单元还可以参照第一方面中的方法的相应步骤，在此不再重复。
第三方面，提供一种LDPC码的译码方法，该方法由长度为d的译码器执行。
首先，译码器执行分段操作，即译码器将长度为n的LDPC码C＝{c1,c2,c3,…,cn-1,cn}分为k个LDPC码D＝{D1,D2,…,Dk-1,Dk}，其中，Di＝{c(i-1)l+1,c(i-1)l+2,…,cil-1,cil}，i＝1,2,...,k-1,k，且Di的长度为l＝n/k。
然后，译码器获取与LDPC码D对应的LLR值G＝{G1,G2,…,Gk-1,Gk}，并根据LLR值对目标校验矩阵进行初始化，得到初始化校验矩阵E＝{E1,E2,…,Et-1,Et}，其中t等于目标校验矩阵的行数。
然后，译码器执行分组操作，即按照译码器的长度对初始化校验矩阵进行分组，具体地，译码器根据初始化码和译码器的长度d得到t*m组LDPC子码F1,F2,…,Ftm-1,Ftm，其中Ej，j＝1,2,...,t-1,t分为m组，且
Figure PCTCN2015094783-appb-000014
其中
Figure PCTCN2015094783-appb-000015
m表示Ej的第(s-1)d+1行到sd行，
Figure PCTCN2015094783-appb-000016
其中，
Figure PCTCN2015094783-appb-000017
表示向上取整运算。
最后，译码器对m组LDPC子码进行译码，以获取LDPC码C的译码结果。
本发明实施例可以按照译码器的长度对初始化校验矩阵进行分组，再对分组码进行译码，以获取LDPC码的译码结果。这样译码器的长度不受限于系统支持的LDPC码的最大码长，从而可以灵活地控制LDPC码的译码并行度，例如，可以减少l较大的LDPC码的耗费的译码资源，提高l较小的LDPC码的处理性能，能够使译码性能和资源达到更佳平衡。
另外，本发明实施例只需长度为d的译码器，可以降低单个译码器所占用的资源和计算复杂度，这样可以灵活地应用于资源受限的场景。一般而言，本发明实施例的译码器长度d小于360，显然，这样的译码器长度较低，也不必局限于系统支持的最长LDPC码长，因此更加适合于资源受限的场景。
结合第三方面，在第三方面的第一种实现方式中，译码器在对m组LDPC子码进行译码以获取LDPC码C的译码结果时，译码器可根据m组LDPC子码，按照r＝1,2,...,tm-1,tm的顺序，进行校验节点更新，得到行更新矩阵。然后译码器可根据行更新矩阵，逐列更新变量节点，得到列更新矩阵。最后，译码器可对列更新矩阵进行判决和校验，以获取LDPC码C的译码结果。
这样，本发明实施例的译码器可以在行更新过程中对分组后的LDPC子码分别进行行更新操作，从而实现以较小长度的译码器对较长长度的LDPC码进行译码的过程。
需要说明的是，本发明实施例与第一方面的实施例本质上是相同的，在第一方面的实施例中，译码器进行转置操作、旋转操作和获取LLR值操作后，可以获得本发明实施例中的初始化校验矩阵，之后可以执行与本发明实施例相同的步骤，从而可以获取LDPC码的译码结果。
第三方面的方法的各个步骤还可以参照第一方面中的方法的相应步骤，在此不再重复。
第四方面，提供一种LDPC码的译码器，该译码器的长度为d，译码器包括：分段单元、初始化单元、分组单元和译码单元。
分段单元执行分段操作，即将长度为n的LDPC码C＝{c1,c2,c3,…,cn-1,cn}分为k个LDPC码D＝{D1,D2,…,Dk-1,Dk}，其中，Di＝{c(i-1)l+1,c(i-1)l+2,…,cil-1,cil}，i＝1,2,...,k-1,k，且Di的长度l＝n/k。
初始化单元，获取与LDP码D对应的LLR值G＝{G1,G2,…,Gk-1,Gk}，并根据LLR值对目标校验矩阵进行初始化，得到初始化校验矩阵E＝{E1,E2,…,Et-1,Et}，其中t等于目标校验矩阵的行数。
分组单元执行分组操作，即按照译码器的长度对初始化校验矩阵进行分组，具体地，译码器根据初始化码和译码器的长度d得到t*m组LDPC子码F1,F2,…,Ftm-1,Ftm，其中Ej，j＝1,2,...,t-1,t分为m组，且
Figure PCTCN2015094783-appb-000018
其中
Figure PCTCN2015094783-appb-000019
m表示Ej的第(s-1)d+1行到sd行，
Figure PCTCN2015094783-appb-000020
其中，
Figure PCTCN2015094783-appb-000021
表示向上取整运算。
译码单元对m组LDPC子码进行译码，以获取LDPC码C的译码结果。
本发明实施例可以按照译码器的长度对初始化校验矩阵进行分组，再对分组码进行译码，以获取LDPC码的译码结果。这样译码器的长度不受限于系统支持的LDPC码的最大码长，从而可以灵活地控制LDPC码的译码并行度，例如，可以减少l较大的LDPC码的耗费的译码资源，提高l较小的LDPC码的处理性能，能够使译码性能和资源达到更佳平衡。
另外，本发明实施例只需长度为d的译码器，可以降低单个译码器所占用的资源和计算复杂度，这样可以灵活地应用于资源受限的场景。一般而言，本发明实施例的译码器长度d小于360，显然，这样的译码器长度较低，也不必局限于系统支持的最长LDPC码长，因此更加适合于资源受限的场景。
第四方面的译码器的各个单元可以参照第三方面中的方法的相应步骤，在此不再重复。
第五方面，提供一种通信设备，包括上述第二方面的译码器或第四方面的译码器。
本发明实施例中的通信设备可以包括多个上述译码器，其中，这些译码器的长度可以相同或不同。例如，其中一个或多个译码器的长度可以为60，另外一个或多个译码器的长度可以为180。
通信设备内包括多个译码器，可以提高该通信设备的译码并行度。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是一种LDPC码的译码方法的示意性流程图。
图2是一种LDPC码的译码方法的示意性框图。
图3是根据本发明一个实施例的QC-LDPC码基矩阵的结构示意框图。
图4是根据本发明一个实施例的QC-LDPC码基矩阵的元素矩阵的结构示意框图。
图5是根据本发明另一实施例的LDPC码的译码方法的示意性流程图。
图6是根据本发明另一实施例的LDPC码的译码方法的示意性框图。
图7是根据本发明另一实施例的LDPC码的译码方法的示意性框图。
图8是根据本发明另一实施例的LDPC码的译码方法的示意性框图。
图9是根据本发明另一实施例的LDPC码的译码方法的示意性框图。
图10是根据本发明一个实施例的LDPC码的译码方法的示意性框图。
图11是根据本发明另一实施例的LDPC码的译码方法的示意性框图。
图12是根据本发明一个实施例的LDPC码的译码器的示意性框图。
图13是根据本发明实施例的通讯设备的示意性框图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
LDPC译码可以分为两大类：硬判决译码和软判决译码。硬判决译码的处理对象是二进制数据，计算数据量少，但译码性能很有限；软判决译码的处理对象是LLR值，计算数据量相比较大很多，但具有很好的译码性能，在实际应用中，主要使用软判决译码的方式。因此，本发明实施例主要讨论采用软判决译码的方法。
下面以Min-sum译码算法为例，结合图1和图2详细描述基于Min-sum译码算法流程。
具体而言，设LDPC参数为(N,K,P)，其中N表示码字码长，K表示信息码长，P表示编码后产生的校验码长，有如下关系P＝N-K。特定LDPC的校验矩阵H是唯一的，其维度为P*N；并且H是稀疏矩阵，其中大部分元素的值等于0，只有极少数值等于1。
设LDPC参数为(7,3,4)的码长N＝7，其中，信息码长K＝3，校验码长 P＝N-K＝4，校验矩阵H维度为4*7。
101，开始。
102，设置最大迭代次数Iter，初始化I＝0。
具体地，该最大迭代次数例如可以为3、5、10等，初始化迭代次数I＝0。
103，接收包括N个LLR值的LDPC码C。
例如，如图2中的(a)所示的软信息(即码字C)：
APP＝[c1 c2 c3 c4 c5 c6 c7]，
如图2中的图(a)所示，码字C包括7个LLR值，其中，
Figure PCTCN2015094783-appb-000022
LLR值定义为当前比特ri等于0的概率除以等于1的概率，然后对结果取对数。
104，利用C值初始化变量节点值。
校验矩阵H中1的分布如图2中的(b)所示，深色背景的方格代表1，没有背景的方格代表0；根据H矩阵1分布位置，用APP值初始化变量节点值Lqji，如公式(1)所示，其中，i是列索引，j是行索引，Lqji表示校验矩阵中第j行第i列的取值，Lci＝ci，i∈[1,7]。
Lqji＝Lci      (1)
例如，初始化后，第i列是1的位置的值均为ci。例如，第1列第1行的值为c1，第5列第3行的值为c5。
105，根据校验矩阵H，行更新校验节点。
逐行更新校验节点Lrji，如图2中的(c)所示；除去当前待更新的点，将本行其它校验节点的符号位相乘作为当前点的输出符号位；除出当前点，取其它校验节点绝对值的最小值作为当前点的输出绝对值；逐行更新，直到4行都更新完毕。更新过程如公式(2)所示，其中，Rj/i表示第j行中，列索引不等于i的集合，Lrji表示校验矩阵行更新后第j行第i列的取值，
Figure PCTCN2015094783-appb-000023
表示除去当前待更新的第j行第i列的点，将j行其它校验节点的符号位相乘得到的第j行第i列的点的符号位，
Figure PCTCN2015094783-appb-000024
表示除出当前j行第i列的点，取其它校验节点绝对值的最小值得到的当前点的绝对值。在图2中的(c)中用Sign*Min(*,*)表示上述行更新的结果。
Figure PCTCN2015094783-appb-000025
βjl＝||Lqjl||       (3)
例如，行更新后，第1行第1列的值为Sign*Min(c3,c5)；第2行第2列的值为Sign*Min(c4,c6)。
106，根据校验矩阵H，列更新变量节点。
逐列更新变量节点Lqji，如图2中的(d)所示；除去当前待更新的点，将本列其它变量节点的值相加得到当前点的更新值；更新过程如公式(4)所示，其中Cj/i表示第i列中，行索引不等于j的集合，Lqji表示校验矩阵列更新后第j行第i列的取值。Σl∈Cj/iLrji表示除去当前第j行第i列的的点，将i列其它变量节点的值相加得到第j行第i列的点的更新值。应理解，在图2中的(d)中，第1至第4行分别用A、B、C、D表示，列标用数字表示，例如，A1表示列更新后第1行第1列的点的取值，C5表示第3行第5列的点的取值。
Lqji＝Σl∈Cj/iLrji     (4)
例如，列更新后，第1行第1列的值A1＝Sign*Min(c5,c7)。
107，计算总的变量节点值，对其做硬判，得到C1
硬判决，过程如图2中的(e)所示；将每列所有变量节点值相加，再加上对应位置输入的LLR原始值，得到总的变量节点值LQi，根据其符号位判决成1或0；具体地，根据以下公式确定其判决值：
Figure PCTCN2015094783-appb-000026
LLR(ri)＜0  ri＝1
LLR(ri)＞0  ri＝0
其中，ri表示当前比特，这里，ri＝LQi。
LQi的计算过程如公式(5)所示，其中Ci表示第i列的索引集合，
Figure PCTCN2015094783-appb-000027
表示i列所有变量节点值之和。
Figure PCTCN2015094783-appb-000028
例如，第1列对应的总的变量节点值为A1+C1+c1。
108，判断I是否等于Iter。
具体地，判断I是否等于最大迭代次数Iter。如果判断结果为“是”(Y)即I＝Iter，则执行步骤111，如果判断结果为“否”(N)即I<Iter，则执行步骤109。
109，I＝I+1。
具体地，当I小于Iter时，使I的值增加1。
110，H*C1是否等于0。
根据硬判以后的码字C1与H矩阵进行校验，如果校验成功，即H*C1＝0，则迭代完成，执行步骤111，否则，H*C1不等于0，则如图2中的图(f)所示，在每列已经列更新的变量节点基础上，加上当前列对应的原始输入LLR值Lcji，作为更新后的变量节点值Lqji，如公式(6)所示。
Figure PCTCN2015094783-appb-000029
之后，返回迭代执行步骤105。
例如，下一次迭代之前第1行第1列的值更新为A1+c1。
111，取C1中前K个比特作为输出。
具体地，在达到最大迭代次数，或在校验成功以后，输出前K(三个)比特作为最后的输出结果。
112，结束。
由此可见，上述的译码算法中，当LDPC码长N较大时，在逻辑实现时，存储校验矩阵H就需要较多的存储单元，存储需求较大。因此，在LDPC应用中，QC-LDPC由于具有更小的存储需求而成为主要的类型。
具体地，QC-LDPC的校验矩阵由两个参数决定，基矩阵H1和膨胀因子L。图3描述了基矩阵H1的结构，其中膨胀因子L＝8。基矩阵中的每个元素代表着一个L*L的方阵，方阵值由该元素的值决定。根据示例中基矩阵的维度参数4*10(m＝4,n＝10)，及膨胀因子L＝8，可以得到原始校验矩阵H的维度为32*80(mL*nL)，进而得到LDPC的基本参数：N＝80，P＝32，K＝48。基矩阵中元素的值可以分为两种类型，-1和非-1。-1代表一个L*L的零矩阵；非-1的值，如k，它代表L*L的单位矩阵以列向量为单元循环右移k次后得到的矩阵，则0代表一个L*L的单位阵；1代表单位矩阵以列向量为单元循环右移一次得到的矩阵。k取值范围为-1、0、1、…、L-1。图4描述了k等于0、1和2值代表的矩阵内容的情形，k取其他值的情形以此类推能够得到， 此处不再赘述。
根据QC-LDPC的描述可知，这种类型的校验矩阵H可以由基矩阵H1和膨胀因子L表示，在逻辑实现时，只需要存储H1，相比较于一般存储原始校验矩阵H的方式，存储量极大减小。因此，现在很多场景中，QC-LDPC被广泛应用。
QC-LDPC的软判决译码方法与图1所示方法相同，只是其中每个元素代表一组L*L的数据。因为QC-LDPC基矩阵的每个元素是L*L的一个零矩阵，或一个单位阵，或者单位阵的移位阵，因此每个基矩阵元素都只和固定的L个LLR数据相关。而且每小行或者每小列都只有一个1，即只和一个LLR数据相关。为了运算方便，一般都将输入的LLR数据分成多组，每组L个LLR数据，根据基矩阵每个元素的值，将这L个LLR数据进行循环移位，对齐后进行运算。
基于上述的描述，可知如果L较大，例如DOCSIS 3.1协议中规定了三种码长，其中长码L＝360，则需要对360个LLR数据展开进行迭代运算，如果每个LLR数据的位宽为6比特，则需同时处理360*6＝2160个比特，因此LDPC译码需要耗费很多的硬件资源，并且很难满足时序要求；如果L较小，则并行度会降低，资源会减少，虽然时序会改善，但解码流量也会降低。
由此可见，当一个LDPC译码器同时要支持多种LDPC码长，例如上述描述的三种码长，虽然对于长码L解码流量性能高，但消耗了大量资源；而对于短码L，并行度和处理性能较低，不到长码的六分之一，不满足流量性能要求。
本发明实施例提供了一种LDPC码的译码方法，解决了上述技术下的对多种LDPC码长处理性能不一致，长码占用资源多、短码处理性能低的问题。下面结合具体例子进行详细描述。
图5是本发明一个实施例的LDPC码的译码方法的流程图。图5的方法可以由LDPC码的译码器执行。该译码器可以位于LDPC码的接收设备中，例如由接收设备中的处理器实现，或者由接收设备中的专用LDPC码译码器实现。
210，译码器将长度为n的LDPC码C＝{c1,c2,c3,…,cn-1,cn}分为k个LDPC码D＝{D1,D2,…,Dk-1,Dk}，其中，Di＝{c(i-1)l+1,c(i-1)l+2,…,cil-1,cil},i＝1,2,...,k-1,k，且Di的长度为l＝n/k。
LDPC码的长度是指LDPC码所包含的比特数。LDPC码C是指需要译码的原始LDPC码。
LDPC码C＝{c1,c2,c3,…,cn-1,cn}可以看作是一个序列，因此可以按照这个序列的先后顺序将LDPC码分为k段，每段长度为l，每段的l个比特按照其原来的顺序构成LDPC码Di，i＝1,2,...,k-1,k。
以n＝1080为例，将LDPC码分为3段，即k＝3，此时LDPC码可以表示为D＝{D1,D2,D3}，其中D1＝{c1,c2,…,c359,c360}，D2＝{c361,c2,…,c359,c720}，D3＝{c721,c2,…,c359,c1080}，D1、D2和D3的长度均为60，即均包括60个比特。
类似地，还可以将n＝1080的LDPC码分为6段，即k＝6，经分段后的LDPC码可表示为：
D＝{D1,D2,D3,D4,D5,D6}＝{{c1,c2,…,c179,c180},{c181,c182,…,c359,c360},{c361,c362,…,c539,c540},{c541,c542,…,c719,c720},{c721,c722,…,c899,c900},{c901,c902,…,c1079,c1080}}
对于其他的n值和/或k值，可以类似的得到LDPC码D＝{D1,D2,…,Dk-1,Dk}，在此不再赘述。
可选地，作为一个实施例，LDPC码可以是QC-LDPC码。在对QC-LDPC码进行分段时，可以按QC-LDPC码的基矩阵的膨胀因子进行分段。对于其它LDPC码也可以按照类似分段做法进行处理，在此不再赘述。
可以理解，进行分段后的每段码可以看作是一个1*l的矩阵，对分段码进行的任何操作都可以看作是对1*l的矩阵的相应的运算。
220，译码器将Di,i＝1,2,...,k-1,k按列进行排列，得到LDPC码D的转置码
Figure PCTCN2015094783-appb-000030
其中，
Figure PCTCN2015094783-appb-000031
Figure PCTCN2015094783-appb-000032
译码器将分段码按列进行排列，可以看作是对1*l的矩阵的转置运算，运算的结果是一个l*1的矩阵，也就是说运算的结果可以看作是k个l*1的矩阵。
230，根据目标校验矩阵中对应元素的值，对
Figure PCTCN2015094783-appb-000033
k按行进行循环移位，得到移位码E＝{E1,E2,…,Et-1,Et}，其中t等于目标校验矩阵的行数，且Ej，j＝1,2,...,t-1,t为根据目标校验矩阵中第j行的元素对DT移位的结果。
目标校验矩阵是指在逻辑实现时，实际存储的校验矩阵。例如，译码器的输入是QC-LDPC码，那么目标校验矩阵就是QC-LDPC码的基矩阵，并 且该基矩阵的维度为t*k，对应的原始校验矩阵的维度为(t*l)*(k*l)。
需要说明的是，E＝{E1,E2,…,Et-1,Et}仅表示E由E1,E2,…,Et-1,Et组成，实际上Ej可以看作是l*k的矩阵，E可以看作是(t*l)*k的矩阵，可以表示为：
Figure PCTCN2015094783-appb-000034
240，译码器根据移位码E和译码器的长度d得到t*m组LDPC子码F1,F2,…,Ftm-1,Ftm，其中Ej分为m组，且
Figure PCTCN2015094783-appb-000035
其中
Figure PCTCN2015094783-appb-000036
m表示Ej的第(s-1)d+1行到sd行，
Figure PCTCN2015094783-appb-000037
译码器将E1,E2,…,Et-1,Et均分为m组，例如译码器将Ej分为2组，即m＝2，具体地，将E1分为F1和F2两组，将E2分为F3和F4两组，类似地，直至将Et分为Ftm-1和Ftm两组，其中，
Figure PCTCN2015094783-appb-000038
也就是说E1的第一行至第d行构成的矩阵是F1组LDPC子码，E1的第d+1行至第2d行构成的矩阵是F2组LDPC子码，其余类似，在此不再详述。
需要说明的是，
Figure PCTCN2015094783-appb-000039
仅表示Ej由
Figure PCTCN2015094783-appb-000040
组成，实际上Ej可看作是矩阵的形式，表示为：
Figure PCTCN2015094783-appb-000041
250，译码器对m组LDPC子码进行译码，以获取LDPC码C的译码结果。
本发明实施例可按照译码器的长度对循环移位后的LDPC码进行分组， 再对分组码进行译码，以获取LDPC码的译码结果，这样译码器的长度不受限于系统支持的LDPC码的最大码长，从而可以灵活地控制LDPC码的译码并行度，例如，可以减少l较大的LDPC码的耗费的译码资源，提高l较小的LDPC码的处理性能，能够使译码性能和资源达到更佳平衡。
另外，本发明实施例只需长度为d的译码器，可以降低单个译码器所占用的资源和计算复杂度，这样可以灵活地应用于资源受限的场景。一般而言，本发明实施例的译码器长度d小于360，显然，这样的译码器长度较低，也不必局限于系统支持的最长LDPC码长，因此更加适合于资源受限的场景。
可替代地，在本发明的另一实施例中，可以不执行步骤220和步骤230。
在此情况下，当不执行步骤220和步骤230时，译码器需要执行以下初始化操作：译码器获取与LDPC分段码对应的LLR值G＝{G1,G2,…,Gk-1,Gk}，并根据LLR值对目标校验矩阵进行初始化，得到初始化校验矩阵E＝{E1,E2,…,Et-1,Et}，其中t等于目标校验矩阵的行数。然后，译码器执行分组操作，即按照译码器的长度对初始化校验矩阵进行分组，具体地，译码器根据初始化码和译码器的长度d得到步骤240所示的t*m组LDPC子码。最后，译码器可以根据步骤250的进行译码操作。
可选地，作为一个实施例，在步骤250中，可按照如下方式对m组LDPC子码进行译码：获取与LDPC子码对应的对数似然比LLR值G1,G2,…,Gtm-1,Gtm；根据LLR值，按照r＝1,2,...,tm-1,tm的顺序，进行校验节点更新，得到行更新矩阵；根据行更新矩阵，逐列更新变量节点，得到列更新矩阵；对列更新矩阵进行判决和校验，以获取LDPC码C的译码结果。
这样，本发明实施例的译码器可以在行更新过程中对分组后的LDPC子码分别进行行更新操作，从而实现以较小长度的译码器对较长长度的LDPC码进行译码的过程。
可选地，作为另一实施例，在译码器对m组LDPC子码进行译码时，可以采用Min-sum译码算法对m组LDPC子码进行译码，以获取LDPC码C的译码结果。
Min-sum译码算法是LDPC码译码时常用的算法，但本发明并不限定具体的译码算法。
下面将结合具体例子，详细描述本发明实施例的译码过程。图6至图9是码长n＝80的QC-LDPC码采用Min-sum译码算法的译码过程的示意图。
首先将QC-LDPC码C＝{c1,c2,c3,…,c79,c80}＝{a1,a2,a3,…,a79,a80}按照该QC-LDPC码的膨胀因子l＝8将该QC-LDPC码分为10段，得到的分段码可表示为：
D＝{D1,D2,D3,D4,D5,D6,D7,D8,D9,D10}＝{{c1,c2,…,c7,c8},{c9,c10,…,c15,c16},{c17,c18,…,c23,c24},{c25,c26,…,c31,c32},{c33,c34,…,c39,c40},{c41,c42,…,c47,c48},{c49,c50,…c55,c56},{c57,c58,…,c63,c64},{c65,c67,…,c71,c72},{c73,c74,…,c79,c80}}
按照QC-LDPC码的膨胀因子的大小对QC-LDPC码进行分段，可以灵活控制译码并行度，同时，可以方便地进行译码，降低译码复杂度。
在本发明实施例中，可以将QC-LDPC码C看作是1*80的矩阵，每段分段码看作是1*8的矩阵，图6为对该QC-LDPC码进行分段的示意图。
需要说明的是，本发明实施例以QC-LDPC码的基矩阵为图3所示的基矩阵为例进行说明。
将上述分段码按列进行排列，得到如图7所示的转置码。
然后按照前述图3所示的基矩阵，根据基矩阵中对应元素的值，对上述转置码进行移位。图8所示的第一列元素的值为按照基矩阵中第一行第一列的元素的值3，对分段码第一列的元素按行循环移位的结果。类似地，对分段码其他列进行相似操作。同时，根据基矩阵中第二行、第三行和第四行中对应的元素对转置码进行相应移位，可以得到如图8所示的矩阵。
根据译码器的长度对图8所示的移位码进行分组，例如，当译码器的长度为4时，可以将图8所示的移位码分为8组，即图8中所示的F1、F2、F3、F4、F5、F6、F7和F8组。也就是说，可以将QC-LDPC码分为8组QC-LDPC子码。
以Min-sum译码算法为例，可以按照F1组、F2组、F3组、F4组、F5组、F6组、F7组和F8组的顺序，依次进行译码，具体的译码法方法可参照前述结合图1和图2所阐述的LDPC码的译码方法。
需要说明的是，在进行行更新的时候，由于只需要知道检验节点所在的行的位置，并不需要知道它在哪一列，因此，可以直接使用之前得到的移位码进行校验节点更新。以基矩阵中第一行第一列的元素3为例，它代表8*8的单位矩阵以列向量为单位循环右移3次后得到的矩阵，如图9的(a)所示，对其进行初始化，得到的矩阵如图9的(b)所示，显然，这个8*8的矩阵中，第一行至第四行的元素依次是a4、a5、a6、a7，而图(8)所示的移位码的第一列的前四行元素值也依次是a4、a5、a6、a7，可以看出，对移 位码进行相应运算就可以完成校验节点更新。
具体地，根据基矩阵中四行元素的值可以得到如图8所示的32*10的矩阵，在进行校验节点更新时，先对F1组进行校验节点更新，即对这个32*10的矩阵中的前四行进行行更新，再对F2组进行校验节点更新，即对这个32*10的矩阵中的第五行至第八行进行行更新。类似地，进行剩余几组的行更新。具体处理过程可以参照步骤105，为避免重复，在此不再赘述。这样就完成了所有校验节点的更新，可以将得到的矩阵称为行更新矩阵。
根据行更新矩阵进行变量节点更新，得到列更新矩阵。具体处理过程可以参照步骤106，为避免重复，在此不再赘述。
根据列更新矩阵，计算总的变量节点值，进行判决和校验，最后可以得到译码结果。同样地，具体处理过程可以参照步骤107～112，为避免重复，在此不再赘述。
因此，本发明实施例通过将长度为n的LDPC码分为长为l的多段LDPC码，对分段后的LDPC码按列排列和循环移位，并对循环移位后的LDPC码进行分组，再对分组码进行译码，以获取LDPC码的译码结果的方案是可行和有效的。
一方面，本发明实施例可按照译码器的长度对循环移位后的LDPC码进行分组，再对分组码进行译码，以获取LDPC码的译码结果，这样译码器的长度不受限于系统支持的LDPC码的最大码长，从而可以灵活地控制LDPC码的译码并行度，例如，可以减少l较大的LDPC码的耗费的译码资源，提高l较小的LDPC码的处理性能，能够使译码性能和资源达到更佳平衡。
另一方面，本发明实施例只需长度为d的译码器，可以降低单个译码器所占用的资源和计算复杂度，这样可以灵活地应用于资源受限的场景。一般而言，本发明实施例的译码器长度d小于360，显然，这样的译码器长度较低，也不必局限于系统支持的最长LDPC码长，因此更加适合于资源受限的场景。
可选地，作为另一实施例，d可以为60或180。
以d为60来讲，在例如DOCSIS 3.1中，当译码器接收的码块包括长中短三种码长，即当译码器需要处理长中短等3种码长时，如图10所示，可以将长码分为6组，每组60个数据，处理完6组数据后，就完成了行更新；中码可以分为3组，每组60个数据，处理6组数据后，就完成了行更新； 短码不分组，仍然按照56个数据处理，浪费了4个数据，性能损失很小，只有4/60，即十二分之一。
这样，一个LDPC译码模块的并行度最大只有60，其资源也会减少，时序会更优，而且长中短码的性能基本一致。
显然，如果译码器接收的码块只包括长中短码中的任意两种码长时，也可按照上述方法进行译码。应理解，此处仅以DOCSIS 3.1中的三种码长为例进行说明，本发明对于其它码长的LDPC码和其它具体的并行度不作限定，具体操作时可根据需求和可用资源进行处理。
由于上例中并行度只有60，因此处理性能较低，当需要提高处理性能时，可以例化多个译码器，此时处理能力也成倍提高。也就是说，当译码器接收的多个码块中，有至少两个码块包括多种码长的LDPC时，可以采用多个译码器进行译码。
如图11所示，译码器接收的至少两个码块都包括多个长度为n的LDPC时，可以例化2个译码器即1#和2#，通过使用两个长度为60的译码器构成一个长度为120的译码器，可以使得LDPC译码模块的并行度可以提高到120。虽然资源会增加一倍，但是处理性能会提高一倍，此时，长中短三种码长的性能仍然保持基本一致。
图12是本发明一个实施例LDPC码的译码器的框图。图12的译码器400包括分段单元410、排列单元420、移位单元430、分组单元440和译码单元450。
具体地，分段单元410将长度为n的LDPC码C＝{c1,c2,c3,…,cn-1,cn}分为k个LDPC码D＝{D1,D2,…,Dk-1,Dk}，其中，Di＝{c(i-1)l+1,c(i-1)l+2,…,cil-1,cil}，i＝1,2,...,k-1,k且Di的长度为l＝n/k。排列单元420将Di,i＝1,2,...,k-1,k按列进行排列，得到LDPC码D的转置码
Figure PCTCN2015094783-appb-000042
其中，
Figure PCTCN2015094783-appb-000043
移位单元430根据目标校验矩阵中对应元素的值，对
Figure PCTCN2015094783-appb-000044
k按行进行循环移位，得到移位码E＝{E1,E2,…，Et-1,Et}，其中t等于目标校验矩阵的行数，且Ej，j＝1,2,...,t-1,t为根据目标校验矩阵中第j行的元素对DT移位的结果。分组单元440根据移位码E和译码器的长度d得到t*m组LDPC子码F1,F2,…,Ftm-1,Ftm，其中Ej分为m组，且
Figure PCTCN2015094783-appb-000045
其中
Figure PCTCN2015094783-appb-000046
m表示Ej的第(s-1)d+1行到sd行，
Figure PCTCN2015094783-appb-000047
译码单元450对m组LDPC子码进行译码，以获取LDPC码C的译码结果。
本发明实施例可按照译码器的长度对循环移位后的LDPC码进行分组，再对分组码进行译码，以获取LDPC码的译码结果，这样译码器的长度不受限于系统支持的LDPC码的最大码长，从而可以灵活地控制LDPC码的译码并行度，例如，可以减少l较大的LDPC码的耗费的译码资源，提高l较小的LDPC码的处理性能，能够使译码性能和资源达到更佳平衡。
另外，本发明实施例只需长度为d的译码器，可以降低单个译码器所占用的资源和计算复杂度，这样可以灵活地应用于资源受限的场景。一般而言，本发明实施例的译码器长度d小于360，显然，这样的译码器长度较低，也不必局限于系统支持的最长LDPC码长，因此更加适合于资源受限的场景。
可替代地，在本发明的另一实施例中，译码器可以不包括分段单元420和移位单元430，而可以包括初始化单元。具体地，初始化单元获取与LDPC分段码对应的LLR值G＝{G1,G2,…,Gk-1,Gk}，并根据LLR值对目标校验矩阵进行初始化，得到初始化校验矩阵E＝{E1,E2,…,Et-1,Et}，其中t等于目标校验矩阵的行数。此时，分组单元440按照译码器的长度对初始化校验矩阵进行分组，获得t*m组LDPC子码，进而可以应用本发明实施例的译码器进行译码。
可选地，作为一个实施例，译码单元450具体用于：获取与LDPC子码对应的对数似然比LLR值G1,G2,…,Gtm-1,Gtm；根据LLR值，按照r＝1,2,...,tm-1,tm的顺序，进行校验节点更新，得到行更新矩阵；根据行更新矩阵，逐列更新变量节点，得到列更新矩阵；对列更新矩阵进行判决和校验，以获取LDPC码C的译码结果。
应注意，本发明实施例中的译码器可以是完全由专用硬件实现，例如专用的芯片、集成电路或其他固件；也可以由通用处理器及其指令实现，该指令可以存储于处理器中或者存储于独立的存储器中。这些形式均落入本发明实施例的范围内。
可选地，作为另一实施例，LDPC码C为准循环低密度奇偶校验码QC-LDPC，其中，l为QC-LDPC码的膨胀因子。
可选地，作为另一实施例，d为60或180。
可选地，作为另一实施例，译码单元450采用Min-sum译码算法对m组所述LDPC子码进行译码，以获取所述LDPC码C的译码结果。
图13是本发明另一实施例的通讯设备的示意性框图。图13的通讯设备600可用于实现上述方法实施例中各步骤及方法。通讯设备600可应用于各种通信系统中的基站或者终端。图13的实施例中，通讯设备600包括发射电路602、接收电路603、译码处理器604、处理单元605，存储器606及天线601。处理单元605控制装置600的操作，并且可用于处理信号。处理单元605还可以称为CPU(Central Processing Unit，中央处理单元)。存储器606可以包括只读存储器和随机存取存储器，并向处理单元605提供指令和数据。存储器606的一部分还可以包括非易失行随机存取存储器(NVRAM)。具体的应用中，通讯设备600可以嵌入或者本身可以就是例如移动电话之类的无线通信设备，还可以包括容纳发射电路602和接收电路603的载体，以允许装置60和远程位置之间进行数据发射和接收。发射电路602和接收电路603可以耦合到天线601。通讯设备600的各个组件通过总线系统609耦合在一起，其中总线系统609除包括数据总线之外，还包括电源总线、控制总线和状态信号总线。但是为了清楚说明起见，在图中将各种总线都标为总线系统609。
上述本发明实施例揭示的方法可以应用于译码处理器604中，或者由译码处理器604实现。译码处理器604可能是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法的各步骤可以通过译码处理器604中的硬件的集成逻辑电路或者软件形式的指令完成。这些指令可以通过处理单元605以配合实现及控制。用于执行本发明实施例揭示的方法，上述的译码处理器可以是通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现成可编程门阵列(FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本发明实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器，译码器等。结合本发明实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器606，译码处理器604读取存储器606中的信息， 结合其硬件完成上述方法的步骤。
具体地，存储器606可存储使得译码处理器604或处理单元605执行以下过程的指令：
将长度为n的LDPC码C＝{c1,c2,c3,…,cn-1,cn}分为k个LDPC码D＝{D1,D2,…,Dk-1,Dk}，其中，Di＝{c(i-1)l+1,c(i-1)l+2,…,cil-1,cil}，i＝1,2,...,k-1,k，且Di的长度为l＝n/k；译码器将Di，i＝1,2,...,k-1,k按列进行排列，得到LDPC码D的转置码
Figure PCTCN2015094783-appb-000048
其中，
Figure PCTCN2015094783-appb-000049
根据目标校验矩阵中对应元素的值，对
Figure PCTCN2015094783-appb-000050
k按行进行循环移位，得到移位码E＝{E1,E2,…,Et-1,Et}，其中t等于目标校验矩阵的行数，且Ej，j＝1,2,...,t-1,t为根据目标校验矩阵中第j行的元素对DT移位的结果；根据移位码E和译码器的长度d得到t*m组LDPC子码F1,F2,…,Ftm-1,Ftm，其中Ej分为m组，且
Figure PCTCN2015094783-appb-000051
其中
Figure PCTCN2015094783-appb-000052
m表示Ej的第(s-1)d+1行到sd行，
Figure PCTCN2015094783-appb-000053
对m组LDPC子码进行译码，以获取LDPC码C的译码结果。
本发明实施例可按照译码器的长度对循环移位后的LDPC码进行分组，再对分组码进行译码，以获取LDPC码的译码结果，这样译码器的长度不受限于系统支持的LDPC码的最大码长，从而可以灵活地控制LDPC码的译码并行度，例如，可以减少l较大的LDPC码的耗费的译码资源，提高l较小的LDPC码的处理性能，能够使译码性能和资源达到更佳平衡。
另外，本发明实施例只需长度为d的译码器，可以降低单个译码器所占用的资源和计算复杂度，这样可以灵活地应用于资源受限的场景。一般而言，本发明实施例的译码器长度d小于360，显然，这样的译码器长度较低，也不必局限于系统支持的最长LDPC码长，因此更加适合于资源受限的场景。
存储器606可存储使得译码处理器604或处理单元605执行参照方法200的相应步骤的指令，在此不再重复。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本发明的至少一个实施例中。因 此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本发明的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本发明实施例的实施过程构成任何限定。
另外，本文中术语“系统”和“网络”在本文中常被可互换使用。本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
应理解，在本发明实施例中，“与A相应的B”表示B与A相关联，根据A可以确定B。但还应理解，根据A确定B并不意味着仅仅根据A确定B，还可以根据A和/或其它信息确定B。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、装置或单元的间接耦合或通信连接，也可以是电的，机械的或其它的形式连接。
作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单 元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本发明实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以是两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到本发明可以用硬件实现，或固件实现，或它们的组合方式来实现。当使用软件实现时，可以将上述功能存储在计算机可读介质中或作为计算机可读介质上的一个或多个指令或代码进行传输。计算机可读介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是计算机能够存取的任何可用介质。以此为例但不限于：计算机可读介质可以包括RAM、ROM、EEPROM、CD-ROM或其他光盘存储、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质。此外。任何连接可以适当的成为计算机可读介质。例如，如果软件是使用同轴电缆、光纤光缆、双绞线、数字用户线(DSL)或者诸如红外线、无线电和微波之类的无线技术从网站、服务器或者其他远程源传输的，那么同轴电缆、光纤光缆、双绞线、DSL或者诸如红外线、无线和微波之类的无线技术包括在所属介质的定影中。如本发明所使用的，盘(Disk)和碟(disc)包括压缩光碟(CD)、激光碟、光碟、数字通用光碟(DVD)、软盘和蓝光光碟，其中盘通常磁性的复制数据，而碟则用激光来光学的复制数据。上面的组合也应当包括在计算机可读介质的保护范围之内。
总之，以上所述仅为本发明技术方案的较佳实施例而已，并非用于限定本发明的保护范围。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种低密度奇偶校验LDPC码的译码方法，其特征在于，所述方法包括：
    译码器将长度为n的LDPC码C＝{c1,c2,c3,...,cn-1,cn}分为k个LDPC码D＝{D1,D2,...,Dk-1,Dk}，其中，Di＝{c(i-1)l+1,c(i-1)l+2,...,cil-1,cil},i＝1,2,...,k-1,k，且所述Di的长度l＝n/k；
    所述译码器将所述Di,i＝1,2,...,k-1,k按列进行排列，得到所述LDPC码D的转置码
    Figure PCTCN2015094783-appb-100001
    其中，
    Figure PCTCN2015094783-appb-100002
    i＝1,2,...,k-1,k；
    根据目标校验矩阵中对应元素的值，对所述
    Figure PCTCN2015094783-appb-100003
    i＝1,2,...,k-1,k按行进行循环移位，得到移位码E＝{E1,E2,...,Et-1,Et}，其中t等于所述目标校验矩阵的行数，且所述Ej，j＝1,2,...,t-1,t为根据所述目标校验矩阵中第j行的元素对所述DT移位的结果；
    所述译码器根据所述移位码E和所述译码器的长度d得到t*m组LDPC子码F1,F2,...,Ftm-1,Ftm，其中所述Ej分为m组，且
    Figure PCTCN2015094783-appb-100004
    其中
    Figure PCTCN2015094783-appb-100005
    s＝1,2,...,m-1,m表示所述Ej的第(s-1)d+1行到sd行，
    Figure PCTCN2015094783-appb-100006
    所述译码器对m组所述LDPC子码进行译码，以获取所述LDPC码C的译码结果。
  2. 根据权利要求1所述的方法，其特征在于，所述对m组所述LDPC子码进行译码，以获取所述LDPC码C的译码结果，包括：
    获取与所述LDPC子码对应的对数似然比LLR值G1,G2,...,Gtm-1,Gtm；
    根据所述LLR值，按照r＝1,2,...,tm-1,tm的顺序，进行校验节点更新，得到行更新矩阵；
    根据所述行更新矩阵，逐列更新变量节点，得到列更新矩阵；
    对所述列更新矩阵进行判决和校验，以获取所述LDPC码C的译码结果。
  3. 根据权利要求1或2所述的方法，其特征在于，所述LDPC码C为准循环低密度奇偶校验码QC-LDPC，其中，所述l为所述QC-LDPC码的膨 胀因子。
  4. 根据权利要求1至3中任一项所述的方法，其特征在于，所述d为60或180。
  5. 根据权利要求1至4中任一项所述的方法，其特征在于，所述对m组所述LDPC子码进行译码，以获取所述LDPC码C的译码结果，包括：
    采用最小和Min-sum译码算法对m组所述LDPC子码进行译码，以获取所述LDPC码C的译码结果。
  6. 一种低密度奇偶校验LDPC码的译码器，其特征在于，包括：
    分段单元，用于将长度为n的LDPC码C＝{c1,c2,c3,...,cn-1,cn}分为k个LDPC码D＝{D1,D2,...,Dk-1,Dk}，其中，Di＝{c(i-1)l+1,c(i-1)l+2,...,cil-1,cil}，i＝1,2,...,k-1,k且所述Di的长度为l＝n/k；
    排列单元，用于将所述Di,i＝1,2,...,k-1,k按列进行排列，得到所述LDPC码D的转置码
    Figure PCTCN2015094783-appb-100007
    其中，
    Figure PCTCN2015094783-appb-100008
    i＝1,2,...,k-1,k；
    移位单元，用于根据目标校验矩阵中对应元素的值，对所述
    Figure PCTCN2015094783-appb-100009
    i＝1,2,...,k-1,k按行进行循环移位，得到移位码E＝{E1,E2,...,Et-1,Et}，其中t等于所述目标校验矩阵的行数，且所述Ej，j＝1,2,...,t-1,t为根据所述目标校验矩阵中第j行的元素对所述DT移位的结果；
    分组单元，用于根据所述移位码E和所述译码器的长度d得到t*m组LDPC子码F1,F2,...,Ftm-1,Ftm，其中所述Ej分为m组，且
    Figure PCTCN2015094783-appb-100010
    其中
    Figure PCTCN2015094783-appb-100011
    s＝1,2,...,m-1,m表示所述Ej的第(s-1)d+1行到sd行，
    Figure PCTCN2015094783-appb-100012
    译码单元，用于对m组所述LDPC子码进行译码，以获取所述LDPC码C的译码结果。
  7. 根据权利要求6所述的译码器，其特征在于，所述译码单元具体用于：
    获取与所述LDPC子码对应的对数似然比LLR值G1,G2,...,Gtm-1,Gtm；
    根据所述LLR值，按照r＝1,2,...,tm-1,tm的顺序，进行校验节点更新， 得到行更新矩阵；
    根据所述行更新矩阵，逐列更新变量节点，得到列更新矩阵；
    对所述列更新矩阵进行判决和校验，以获取所述LDPC码C的译码结果。
  8. 根据权利要求6或7所述的译码器，其特征在于，所述LDPC码C为准循环低密度奇偶校验码QC-LDPC，其中，所述l为所述QC-LDPC码的膨胀因子。
  9. 根据权利要求6至8中任一项所述的译码器，其特征在于，所述d为60或180。
  10. 根据权利要求6至9中任一项所述的译码器，其特征在于，所述译码单元具体用于：
    采用最小和Min-sum译码算法对m组所述LDPC子码进行译码，以获取所述LDPC码C的译码结果。
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