WO2017045142A1 - Ldpc截短码的译码方法和译码设备 - Google Patents

Ldpc截短码的译码方法和译码设备 Download PDF

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Publication number
WO2017045142A1
WO2017045142A1 PCT/CN2015/089687 CN2015089687W WO2017045142A1 WO 2017045142 A1 WO2017045142 A1 WO 2017045142A1 CN 2015089687 W CN2015089687 W CN 2015089687W WO 2017045142 A1 WO2017045142 A1 WO 2017045142A1
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code
check matrix
decoding
target
column
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PCT/CN2015/089687
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English (en)
French (fr)
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司小书
范嘉旗
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华为技术有限公司
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Priority to PCT/CN2015/089687 priority Critical patent/WO2017045142A1/zh
Priority to CN201580080721.0A priority patent/CN107615666A/zh
Publication of WO2017045142A1 publication Critical patent/WO2017045142A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

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  • the embodiments of the present invention relate to the field of communications technologies, and in particular, to a decoding method and a decoding device for a low density parity check code LDPC truncation code.
  • the purpose of communication is to ensure the reliability, security and effectiveness of the delivered messages.
  • the validity and reliability are contradictory.
  • the reliability of the communication is achieved by adding certain redundant information, but the bandwidth of the system is wasted, that is, the effectiveness is reduced.
  • scholars have proposed an error correction coding scheme to resist the interference of channel noise on the transmitted information during transmission, and to ensure reliable transmission of information.
  • Shannon's limit is the minimum bit-to-noise ratio that error correction coding can perform for effective error correction.
  • the performance of error correction coding is determined by the degree of approaching the Shannon limit. .
  • the Turbo code was proposed and its performance was very close to the Shannon limit.
  • LDPC Low Density Parity Check Code
  • the longer the LDPC code length the better the decoding performance, but the long code length means that the logic implementation needs to occupy more resources, and because the LDPC decoding requires multiple iterations, the decoding module's throughput is caused.
  • the amount is very low. In practical applications, it is necessary to reduce the amount of data involved in decoding as much as possible, thereby reducing the resources occupied by the logic implementation and improving the decoding throughput.
  • LDPC truncation codes are widely adopted by many standards.
  • the information bits involved in the coding are less than the complete information code length, and the zero value is padded after the remaining data, so that the total data length is equal to the complete information code length.
  • the information code is then encoded to produce a check digit. Finally, the padded zero value is removed and the data and checksum sections are sent to the channel.
  • the conventional decoding method first fills a specific value to a truncated position, then decodes the complete codeword, and finally outputs only the decoded information portion (less than the complete information code length). .
  • the conventional LDPC truncated code decoding process is the same as the full code decoding process, and the processed data amount is also the same, but the output valid data length is short. In an extreme case, the effective data length of the output is 1, which causes the LDPC truncated code decoding.
  • the throughput is very low.
  • Embodiments of the present invention provide a decoding method and a decoding device for an LDPC truncation code, which can improve decoding throughput.
  • a decoding method for a low density parity check code LDPC truncation code comprising:
  • N' column is intercepted from the P*N original check matrix of the complete code corresponding to the truncation code as a P*N' target check matrix, wherein the N' column includes at least the K' information bits
  • the K' column of the original check matrix corresponding to the position in the complete code, and the last P column of the original check matrix, N is the length of the complete code length corresponding to the truncated code, and N' is the target check matrix
  • the truncated code is decoded according to the target check matrix to obtain K' decoded bits.
  • the truncating code is decoded according to the target check matrix to obtain K' decoding bits, including:
  • the truncation code is decoded using a minimum and Min-sum decoding algorithm to obtain K' decoding bits.
  • the P row N' column is intercepted from the P*N original check matrix of the complete code corresponding to the truncated code, and the P*N' target check matrix includes:
  • the truncation code is a quasi-cyclic low-density parity check code QC-LDPC truncation code, and the complete code corresponding to the QC-LDPC truncation code
  • the original base matrix of the P*N original check matrix has a dimension of P/L*N/L, and L is an expansion factor.
  • the P row N' column is intercepted from the P*N original check matrix of the complete code corresponding to the truncated code, and the P*N' target check matrix includes:
  • the decoding method when the K' is not When it is an integer multiple of L, before decoding the truncated code by using the minimum and Min-sum decoding algorithm according to the target check matrix, the decoding method further includes:
  • the truncation code is decoded by using a minimum and Min-sum decoding algorithm to obtain K' bits, including:
  • the target truncation code is decoded according to the target check matrix using a minimum and Min-sum decoding algorithm to obtain K' decoding bits.
  • a decoding apparatus for a low density parity check code LDPC truncation code comprising:
  • An intercepting unit configured to intercept a P row N′ column from a P*N original check matrix of the complete code corresponding to the truncated code, as a P*N′ target check matrix, where the N′ column includes at least the K The K' column of the original check matrix corresponding to the position of the information bits in the complete code, and the last P column of the original check matrix, where N is the length of the complete code length corresponding to the truncated code, N' is The length of the code length corresponding to the target truncation code, K'+P ⁇ N' ⁇ N;
  • the decoding unit decodes the truncated code according to the target check matrix to obtain K' decoded bits.
  • the decoding unit decodes the truncated code by using a minimum and Min-sum decoding algorithm to obtain K′ translations. Code bit.
  • the truncation code is a quasi-cyclic low-density parity check code QC-LDPC truncation code
  • the QC-LDPC truncation code The original base matrix of the corresponding P*N original check matrix of the complete code has a dimension of P/L*N/L, and L is an expansion factor.
  • the decoding device when the K' is not an integer multiple of L, the decoding device further includes:
  • the decoding unit is specifically configured to decode the target truncation code according to the target check matrix by using a minimum and Min-sum decoding algorithm to obtain K' decoding bits.
  • the embodiment of the present invention intercepts a target check matrix corresponding to the truncated code from an original check matrix of a complete code corresponding to the truncated code, and performs the truncation according to the target check matrix.
  • the short code is used for decoding. Since the embodiment of the present invention uses the target check matrix smaller than the original check matrix to decode the truncated code, the complete code is not required to be decoded, and the decoding throughput and decoding efficiency are improved.
  • 1 is a schematic block diagram of padding bits in a decoding method of an LDPC truncation code.
  • FIG. 2 is a schematic flow chart of a decoding method of an LDPC truncation code.
  • FIG. 3 is a schematic block diagram of a decoding method of an LDPC truncation code.
  • FIG. 4 is a schematic flowchart of a decoding method of an LDPC truncation code according to an embodiment of the present invention.
  • FIG. 5 is a schematic flowchart of a decoding method of an LDPC truncation code according to another embodiment of the present invention.
  • FIG. 6 is a schematic block diagram showing the structure of a QC-LDPC code base matrix according to an embodiment of the present invention.
  • FIG. 7 is a schematic block diagram showing the structure of an element matrix of a QC-LDPC code base matrix according to an embodiment of the present invention.
  • FIG. 8 is a schematic flowchart of a decoding method of an LDPC truncation code according to another embodiment of the present invention.
  • FIG. 9 is a schematic block diagram of a decoding apparatus of an LDPC truncation code according to an embodiment of the present invention.
  • FIG. 10 is a schematic block diagram of a decoding apparatus of an LDPC truncation code according to another embodiment of the present invention.
  • the technical solutions of the embodiments of the present invention may be applied to various communication systems, for example, may be applied to a digital communication system and an optical communication system, or the technical solution of the embodiments of the present invention may be applied to a wired communication system or a wireless communication system.
  • the embodiments of the present invention are not limited thereto.
  • the decoding device may be integrated as a module in any one of the receivers for decoding, or may be directly the following devices, including but not limited to wireless or wired signal receivers, having A computer or other device that functions as a signal receiver.
  • an LDPC truncated code decoding method is as follows. Before decoding, the truncated code needs to be filled into padding bits to form a complete code, and then decoded.
  • the parity check matrix H of a particular LDPC is unique, its dimension is P*N; and H is a sparse matrix in which the majority of the elements have a value equal to zero and only a very small number of values equal to one.
  • the information code length of the truncated code be K', which satisfies K' ⁇ K; when the LDPC code is used, the sender first fills K-K' zero bits after the K' information bits to form K information bits. Then, the K information bits are encoded by the check matrix H to obtain P check bits; before being transmitted to the channel, the padded K-K' zero bits need to be deleted, and only K'+P bits are transmitted.
  • LDPC decoding can be divided into two categories: hard decision decoding and soft decision decoding.
  • the processing object of hard decision decoding is binary data, and the amount of calculation data is small, but the decoding performance is very limited; the processing object of soft decision decoding is Log Likelihood Ratio (LLR) value, and the calculated data amount is compared. It is much larger, but has good decoding performance.
  • LLR Log Likelihood Ratio
  • the receiving end After receiving the K'+P LLR values, the receiving end needs to fill the K-K' specific LLR values to the position where the transmitting end code fills the zero bits to form a codeword with a total length of N; and then according to the check matrix H And the padded codeword is decoded; among them, there are many decoding algorithms, and the decoding process is described by taking the Min-sum decoding algorithm as an example.
  • codeword C includes 7 LLR values, where The three values c3 represent the filled LLR values, wherein The LLR value is defined as the probability that the current bit r i is equal to 0 divided by the probability equal to 1, and then the logarithm of the result.
  • the value of the position where the i-th column is 1 is ci.
  • the value of the first row of column 1 is c1
  • the value of the third row of column 5 is c5.
  • the value of column 1 of row 1 is Sign*Min(c3, c5); the value of column 2 of row 2 is Sign*Min(c4, c6).
  • variable node Lq ji is updated column by column, as shown in Fig. 3(d); the points to be updated are removed, and the values of other variable nodes in the column are added to obtain the updated value of the current point; the update process is as shown in formula (4).
  • C j / i represents the set in the i-th column, the row index is not equal to j, and Lq ji represents the value of the i-th column of the j-th row after the check matrix column is updated.
  • the first to fourth rows are respectively denoted by A, B, C, and D, and the column numbers are represented by numbers.
  • A1 represents the point of the first row and the first column after the column update.
  • Value represents the value of the point in the fifth row and fifth column.
  • the value of the first row and the first column A1 Sign*Min(c5, c7).
  • the total variable node value corresponding to column 1 is A1+C1+c1.
  • C 1 take front K 'bits as output.
  • the first K' (two) bits are output as the final output.
  • the LDPC truncated code decoding method in the prior art has the following drawbacks: the row and column update of each iteration needs to process the filled LLR value, which increases the decoding processing time and reduces the system throughput.
  • the above operations require additional logical resources to store the padded data, resulting in an increase in decoding resources.
  • the embodiment of the invention provides a simplified method for decoding LDPC truncated code, which solves the problem that the decoding throughput of the LDPC truncated code is low and the resources are occupied.
  • a detailed description will be given below in conjunction with specific examples.
  • FIG. 4 is a schematic flowchart of a decoding method of an LDPC truncation code according to an embodiment of the present invention.
  • the truncation code includes K' information bits and P parity bits.
  • the decoding method shown in FIG. 4 may be performed by a decoding device. Specifically, the decoding method includes:
  • N' column includes at least K' information bits in the complete
  • the K' column of the original check matrix corresponding to the position in the code, and the last P column of the original check matrix, N is the length of the complete code length corresponding to the truncation code, and N' is the code length corresponding to the target check matrix. Length, K'+P ⁇ N' ⁇ N;
  • the embodiment of the present invention intercepts the target check matrix corresponding to the truncated code from the original check matrix of the complete code corresponding to the truncated code, and decodes the truncated code according to the target check matrix, The embodiment of the invention decodes the truncated code by using a target check matrix smaller than the original check matrix, and does not need to decode the complete code, thereby improving the decoding throughput and improving the decoding efficiency.
  • the embodiment of the present invention since the embodiment of the present invention does not need to fill the truncated code into a complete code and then performs decoding, the truncation code is directly decoded after the original check matrix is intercepted, or only a small portion is filled. The bit is decoded again to improve the decoding efficiency.
  • the embodiment of the present invention reduces the update calculation of the filled LLR value, and improves the processing capability of the decoding module. At the same time, the embodiment of the invention reduces the storage of the filled LLR value and reduces the resources occupied by the logic implementation.
  • the complete check matrix may be intercepted according to the truncated code truncation position. Specifically, each bit of the complete code corresponds to one column of the P*N original check matrix, and the present invention
  • the target check matrix may be obtained according to the interception of the original check matrix corresponding to the position of the information bits in the truncated code corresponding to the information bits, wherein the target check matrix includes at least all the columns corresponding to the information bits and the check bits. Column, and the number of columns in the target check matrix is less than the number of columns in the original check matrix.
  • the target check matrix when the K' information bits of the truncated code are located in the first K' bits of the complete code, the target check matrix includes at least the first K' column of the original check matrix (the first K' column of the original check matrix) And the last P column (the last P column of the original parity check matrix). For example, when the K' information bits are located in the middle K' bits of the complete code, the target check matrix includes at least the corresponding intermediate K of the original check matrix.
  • the target check matrix includes at least a corresponding intermediate a column, a b column, and a rear P column of the original parity check matrix.
  • the target check matrix includes at least the first K' column and the last P column of the original check matrix, which will be described in detail as an example.
  • embodiments of the invention are not limited thereto.
  • the obtained K' decoding bits are the decoding bits corresponding to the K' information bits of the truncated code. That is, even if there are padding bits, the final output is only K' bits of decoding bits corresponding to the K' information bits of the truncation code, in other words, only the decoded information portion is finally output.
  • the truncation code can be decoded using a minimum and Min-sum decoding algorithm according to the target check matrix to obtain K' decoding bits.
  • Embodiments of the invention are not limited thereto.
  • the minimum and Min-sum decoding algorithm is used to decode the truncated code as an example. Description.
  • LLR if the LLR value corresponding to the current bit is less than zero, the probability that the current bit is 1 is large, and it is suitable to be judged as 1; on the contrary, if the LLR value is greater than zero, it is suitable to be judged as 0; and the LLR value is The larger the absolute value, the greater the probability of being judged as 1 or 0; if the LLR value is exactly equal to zero, indicating that the probability that the current bit is equal to 0 or 1 is equal, it is judged as 1 or 0 (indicating that an error has occurred, resulting in an error) code).
  • the K-K' zero values are first padded after the truncated information code, and then encoded.
  • the filled real bit is 0, so it is necessary to fill a positive large LLR value. The larger the LLR value is filled, the smaller the possibility that the position bit is inverted, and the better the decoding performance.
  • the value c3 filled in Fig. 3(a) is a positive maximum value, which means that the c3 value is much larger than other values, and the following analysis is performed:
  • the LLR value filled by the existing algorithm has a limited effect on the algorithm update; only when the filled c3 is small, after iteration, c3
  • the value of the location is updated to the minimum value
  • the update of other nodes can be affected.
  • the value of the location of c3 is already small, and the sign may even be reversed, resulting in a false positive, thereby reducing the decoding performance. Therefore, it can be seen that even if the filled LLR value has an effect on the iterative process, it is only a negative influence. So in the iterative process, the filled LLR does not have to participate in the update process.
  • the target check matrix corresponding to the truncated code is obtained by intercepting the original check matrix of the complete code corresponding to the truncated code, and the scheme for decoding the truncated code by using the target check matrix is Feasible and effective.
  • the original check matrix corresponding to the position of the K′ information bits in the complete code is intercepted from the P*N original check matrix of the complete code corresponding to the truncated code.
  • the K' column, and the last P column of the original check matrix, as the P*N' target check matrix, where N' K'+P.
  • the decoding object is decoded.
  • C includes a portion filled due to truncation, the length is N; the matrix H is the original check matrix, and the dimension is P*N.
  • the decoding object C' reduces the portion filled in C compared to the prior art, and the new matrix H' reduces the padding corresponding matrix block in H. Therefore, since the truncated code is decoded by the target check matrix smaller than the original check matrix, the complete code is not required to be decoded, the decoding throughput is improved, and the decoding efficiency is improved.
  • the target check matrix intercepted in the embodiment of the present invention may correspond to the truncated code, that is, the codeword of the truncated code is equal to the number of columns of the target check matrix; the number of columns of the target check matrix may also be more than
  • the codeword of the truncated code is smaller than the number of columns of the complete check matrix.
  • the number of columns of the matrix is equal. In this case, although the bits are required to be padded, only a small number of bits need to be filled, and the decoding efficiency can be improved as compared with the prior art.
  • the decoding method shown in FIG. 5 includes:
  • the check matrix H is intercepted to obtain a new matrix H'.
  • the step 505 is similar to the step 205, and the specific method in the 505 is similar to the 205, except that the LDPC code and the check matrix are different, but the specific processing process is the same. To avoid repetition, details are not described herein. Specifically, the difference is only the truncation code in 505, the complete code in 205, the corresponding check matrix in 505 is P*N' target check matrix, and 205 is P*N original check matrix.
  • step 506 is similar to step 206.
  • the specific method in 506 is similar to 206. The only difference is that the LDPC code and the check matrix are different, but the specific processing process is the same. To avoid repetition, details are not described herein.
  • step 507 is similar to step 207.
  • the specific method in 507 is similar to that of 207. The only difference is that the LDPC code and the check matrix are different, but the specific processing procedure is the same. To avoid repetition, details are not described herein.
  • step 508 is similar to step 208.
  • the specific method in 508 is similar to 208 except that the LDPC code and the check matrix are different, but the specific processing procedure is the same. To avoid repetition, details are not described herein.
  • the result of the hard decision is checked to determine whether the product of the matrix H' and the matrix C1' is equal to zero. If not equal to zero, the next iteration is performed, and step 506 is performed; otherwise, 512 is performed;
  • Step 511 is similar to step 211.
  • the specific method in 511 is similar to 211.
  • the difference is that the LDPC code and the check matrix are different, but the specific processing is the same. To avoid repetition, details are not described herein.
  • the pre-K' bit is output as the final output.
  • the target check matrix corresponding to the truncated code is intercepted from the original check matrix of the complete code corresponding to the truncated code, and the truncated code is decoded by using the target check matrix. Feasible and effective.
  • the LDPC truncation code is a Quasi-Cyclic Low Density Parity Check Code (QC-LDPC) truncation code, and the QC-LDPC truncation code is complete.
  • the original base matrix of the P*N original check matrix of the code has a dimension of P/L*N/L, and L is an expansion factor.
  • the decoding method further includes:
  • the target truncation code is decoded according to the target check matrix using a minimum and Min-sum decoding algorithm to obtain K' decoding bits.
  • Z preset log likelihood ratio LLR values are filled before and/or after K' bits in the LDPC truncation code according to a specific case, and a target truncation code is obtained, so that the target is obtained.
  • the padded bits may be located before K' bits or after K' bits.
  • the QC-LDPC check matrix is determined by two parameters, the base matrix H1 and the expansion factor L.
  • Each element in the base matrix represents a square matrix of L*L, and the square matrix value is determined by the value of that element.
  • the values of the elements in the base matrix can be divided into two types, -1 and non-1.
  • -1 represents a zero matrix of L*L
  • a value other than -1, such as k represents a matrix obtained by dividing the unit matrix of L*L by a column vector by right shifting k times, then 0 represents an L*L
  • the unit matrix; 1 represents the matrix obtained by the unit matrix being rotated right by the column vector.
  • k ranges from -1, 0, 1, ..., L-1.
  • Fig. 7 depicts the case where k is equal to the matrix content represented by the values of 0, 1, and 2. The case where k takes other values can be obtained by analogy, and will not be described again here.
  • this type of check matrix H can be represented by the base matrix H1 and the expansion factor L.
  • H1 needs to be stored, compared to the manner in which the original check matrix H is generally stored. The amount of storage is greatly reduced. Therefore, in many scenarios, QC-LDPC is widely used.
  • the embodiment of the present invention does not need to perform padding, and the specific processing procedure is similar to that of FIG. 5, except that the original base matrix is intercepted.
  • the front ceil (K'/L) column and the last P/L column obtain the P*N' target check matrix.
  • Other subsequent processing procedures are similar to the method of FIG. 5 and will not be described in detail herein.
  • the decoding method of the embodiment of the present invention needs to fill Z preset log likelihood ratio LLR values after K' bits in the LDPC truncation code to obtain a target truncation code, so that the target truncation code is obtained.
  • the purpose of padding bits is to make the code length of the target truncation code correspond to the target check matrix, so as to decode the target truncation code according to the target check matrix using the minimum and Min-sum decoding algorithm to obtain the front K. 'Decoding bits.
  • the target check matrix intercepted in the embodiment of the present invention may correspond to the truncated code, that is, the position of the target check matrix including the information bit of the truncated code in the complete code is greater than or equal to K'/ The number of columns of the smallest integer of L, and the post-P/L column.
  • the number of columns in the target check matrix is also In this case, more than the number of columns, but less than the number of columns of the complete check matrix, in this case, it is necessary to fill a certain padding bit on the basis of the truncated code according to the existing method, so that the padded codeword and target are filled.
  • the number of columns of the check matrix is equal. In this case, although the padding bits are also required, only a small number of bits need to be filled, and the decoding efficiency can be improved as compared with the prior art.
  • the decoding method shown in FIG. 8 includes:
  • the check matrix H is intercepted to obtain a new matrix H1'.
  • the pre-ceil (K'/L) column and the post-P/L column of the original base matrix are truncated to obtain a P*N' target check matrix, where ceil(K'/L) represents greater than or equal to K'.
  • ceil(K'/L) represents greater than or equal to K'.
  • N' (ceil (K' / L) + P / L) * L.
  • step 806 is similar to step 205, and the specific method in 806 is similar to 205, except that the LDPC code and the check matrix are different, but the specific processing process is the same. To avoid repetition, it will not be described in detail herein. Specifically, the difference is only the truncation code in 806, the complete code in 205, the corresponding check matrix in 806 is the P*N' target check matrix, and 205 is the P*N original check matrix.
  • step 807 is similar to step 206.
  • the specific method in 807 is similar to 206. The only difference is that the LDPC code and the check matrix are different, but the specific processing process is the same. To avoid repetition, details are not described herein.
  • variable node is updated according to the new check matrix H1'.
  • step 808 is similar to step 207.
  • the specific implementation in 808 is similar to that of 207.
  • the only difference is that the LDPC code and the check matrix are different, but the specific processing process is the same. To avoid repetition, details are not described herein.
  • step 809 is similar to step 208.
  • the specific method in 809 is similar to 208. The only difference is that the LDPC code and the check matrix are different, but the specific processing process is the same. To avoid repetition, details are not described herein.
  • H1'*C1" is equal to 0
  • the hard decision result is checked to determine whether the product of the matrix H1' and the matrix C" is equal to zero. If not equal to zero, the next iteration is performed, and step 807 is performed; otherwise, 813 is performed.
  • Step 812 is similar to step 211.
  • the specific method in 812 is similar to 211.
  • the difference is that the LDPC code and the check matrix are different, but the specific processing is the same. To avoid repetition, details are not described herein.
  • the pre-K' bit is output as the final output.
  • the target check matrix corresponding to the truncated code is intercepted from the original check matrix of the complete code corresponding to the truncated code, and the truncated code is decoded according to the target check matrix. Because the embodiment of the present invention uses the target check matrix smaller than the original check matrix to decode the truncated code, the complete code does not need to be decoded, and the decoding throughput and decoding efficiency are improved.
  • FIG. 1 to FIG. 8 are merely for facilitating the understanding of the embodiments of the present invention, and the embodiments of the present invention are not limited to the specific numerical values or specific examples illustrated. A person skilled in the art will be able to make various modifications and changes in accordance with the examples of FIG. 1 to FIG. 8 which are within the scope of the embodiments of the present invention.
  • the decoding method of the embodiment of the present invention is described in detail above with reference to FIG. 1 to FIG. 8.
  • the decoding apparatus of the embodiment of the present invention will be described below with reference to FIG. 9 and FIG.
  • FIG. 9 is a schematic block diagram of a decoding apparatus of an LDPC truncation code according to an embodiment of the present invention.
  • the decoding device 900 shown in FIG. 9 corresponds to the decoding method shown in FIG. 4, and the decoding device 900 can implement various processes in the decoding method embodiment of FIG. 4.
  • the specific functions of the decoding device 900 can be seen in FIG. Corresponding descriptions in the description, in order to avoid repetition, the detailed description is omitted as appropriate herein.
  • the decoding device 900 is configured for low density parity check code LDPC truncation code decoding, and may include: a truncation unit 910 and a decoding unit 920.
  • the intercepting unit 910 is configured to intercept a P*N original check matrix of the complete code corresponding to the truncated code, to obtain a P*N′ target check matrix, where the target check matrix includes at least the original check matrix
  • the position of the short code information bits in the complete code corresponds to the K' column and the last P column
  • N is the length of the complete code length corresponding to the truncation code
  • N' is the length of the code length corresponding to the target truncation code, K' +P ⁇ N' ⁇ N
  • the decoding unit 920 decodes the truncation code according to the target check matrix to obtain K' decoding bits.
  • the embodiment of the present invention intercepts the target check matrix corresponding to the truncated code from the original check matrix of the complete code corresponding to the truncated code, and decodes the truncated code according to the target check matrix,
  • the truncated code is decoded by using a target check matrix smaller than the original check matrix, and the complete code is not required to be decoded, thereby improving the decoding throughput and the decoding efficiency.
  • the embodiment of the present invention since the embodiment of the present invention does not need to fill the truncated code into a complete code and then performs decoding, the truncation code is directly decoded after the original check matrix is intercepted, or only a small portion is filled. The bit is decoded again to improve the decoding efficiency.
  • the embodiment of the present invention reduces the update calculation of the filled LLR value, and improves the processing capability of the decoding module. At the same time, the embodiment of the invention reduces the storage of the filled LLR value and reduces the resources occupied by the logic implementation.
  • the decoding unit 920 decodes the truncation code by using a minimum and Min-sum decoding algorithm according to the target check matrix to obtain K' decoding bits.
  • the intercepting unit 910 intercepts the original check moment corresponding to the position of the K' information bits in the complete code from the P*N original check matrix of the complete code corresponding to the truncated code.
  • the LDPC truncation code is a quasi-cyclic low-density parity check code QC-LDPC truncation code, and the original of the P*N original check matrix of the complete code corresponding to the QC-LDPC truncation code
  • the dimension of the base matrix is P/L*N/L, and L is the expansion factor.
  • the decoding device when K' is not an integer multiple of L, the decoding device further includes: a padding unit.
  • the decoding unit 920 is specifically configured to decode the target truncation code according to the target check matrix by using a minimum and Min-sum decoding algorithm to obtain K' decoding bits corresponding to the target truncation code.
  • FIG. 10 is a schematic block diagram of a decoding apparatus of an LDPC truncation code according to another embodiment of the present invention.
  • the decoding device 1000 shown in FIG. 10 corresponds to the decoding method shown in FIG. 4, and the decoding device 1000 can implement various processes in the decoding method embodiment of FIG. 4.
  • the specific function of the decoding device 1000 can be seen in FIG. Corresponding descriptions in the description, in order to avoid repetition, the detailed description is omitted as appropriate herein.
  • the decoding device 1000 is used for low density parity check code LDPC truncation code decoding, and may include: a processor 1010, a memory 1020, and a bus system 1030.
  • the processor 1010 calls the code stored in the memory 1020 through the bus system 1030, and intercepts the P row N' column from the P*N original check matrix of the complete code corresponding to the truncated code as the P*N' target school.
  • the length of the code length, N' is the length of the code length corresponding to the target check matrix, K'+P ⁇ N' ⁇ N; according to the target check matrix, the truncation code is decoded to obtain K' decoding bits. .
  • the embodiment of the present invention intercepts the target check matrix corresponding to the truncated code from the original check matrix of the complete code corresponding to the truncated code, and decodes the truncated code according to the target check matrix. Since the embodiment of the present invention uses the target check matrix smaller than the original check matrix to decode the truncated code, the complete code does not need to be decoded, and the decoding throughput and decoding efficiency are improved.
  • the embodiment of the present invention since the embodiment of the present invention does not need to fill the truncated code into a complete code and then performs decoding, the truncation code is directly decoded after the original check matrix is intercepted, or only a small portion is filled. The bit is decoded again to improve the decoding efficiency.
  • the embodiment of the present invention reduces the update calculation of the filled LLR value, and improves the processing capability of the decoding module. At the same time, the embodiment of the invention reduces the storage of the filled LLR value and reduces the resources occupied by the logic implementation.
  • the method disclosed in the foregoing embodiments of the present invention may be applied to the processor 1010 or implemented by the processor 1010.
  • the processor 1010 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the foregoing method may be completed by an integrated logic circuit of hardware in the processor 1010 or an instruction in a form of software.
  • the processor 1010 may be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a Field Programmable Gate Array (FPGA), or the like. Programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA Field Programmable Gate Array
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the steps of the method disclosed in the embodiments of the present invention may be directly implemented by the hardware decoding processor, or may be performed by a combination of hardware and software modules in the decoding processor.
  • the software module can be located in a random access memory (RAM), a flash memory, a read-only memory (ROM), a programmable read only memory or an electrically erasable programmable memory, a register, etc. In the storage medium.
  • the storage medium is located in the memory 1020.
  • the processor 1010 reads the information in the memory 1020 and completes the steps of the foregoing method in combination with hardware.
  • the bus system 1030 may include a power bus, a control bus, and a status signal bus in addition to the data bus. Wait. However, for clarity of description, various buses are labeled as the bus system 1030 in the figure.
  • the processor 1010 decodes the truncation code by using a minimum and Min-sum decoding algorithm according to the target check matrix to obtain K' decoding bits.
  • the processor 1010 intercepts, from the P*N original check matrix of the complete code corresponding to the truncated code, an original check matrix corresponding to a position of the K′ information bits in the complete code.
  • the K' column, and the last P column of the original check matrix, as the P*N' target check matrix, where N' K' + P.
  • the LDPC truncation code is a quasi-cyclic low-density parity check code QC-LDPC truncation code, and the original of the P*N original check matrix of the complete code corresponding to the QC-LDPC truncation code
  • the dimension of the base matrix is P/L*N/L, and L is the expansion factor.
  • the processor 1010 is specifically configured to decode the target truncation code according to the target check matrix by using a minimum and Min-sum decoding algorithm, and obtain K' decoding corresponding to the target truncation code. Bit.
  • system and “network” are used interchangeably herein.
  • the term “and/or” in this context is merely an association describing the associated object, indicating that there may be three relationships, for example, A and / or B, which may indicate that A exists separately, and both A and B exist, respectively. B these three situations.
  • the character "/" in this article generally indicates that the contextual object is an "or" relationship.
  • B corresponding to A means that B is associated with A, and B can be determined according to A.
  • determining B from A does not mean that B is only determined based on A, and that B can also be determined based on A and/or other information.
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of cells is only a logical function division.
  • multiple units or components may be combined or integrated. Go to another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, or an electrical, mechanical or other form of connection.
  • the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiments of the present invention.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • Computer readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another.
  • a storage medium may be any available media that can be accessed by a computer.
  • computer readable media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage media or other magnetic storage device, or can be used for carrying or storing Any other medium having the desired program code in the form of an instruction or data structure and accessible by a computer. Also.
  • any connection may suitably be a computer readable medium.
  • the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave
  • the coaxial cable , fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, wireless, and microwave are included in the fixing of the associated media.
  • a disk and a disc include a compact disc (CD), a laser disc, a compact disc, a digital versatile disc (DVD), a floppy disk, and a Blu-ray disc, wherein the disc is usually magnetically copied, and the disc is The laser is used to optically replicate the data. Combinations of the above should also be included within the scope of the computer readable media.

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Abstract

本发明实施例提供了一种低密度奇偶校验码LDPC截短码的译码方法和译码设备，该译码方法包括从截短码对应的完整码的P*N原始校验矩阵中截取P行N'列，作为P*N'目标校验矩阵，其中，N'列至少包括K'个信息比特在完整码中的位置对应的原始校验矩阵的K'列，和原始校验矩阵的最后P列，N为截短码对应的完整码长的长度，N'为目标校验矩阵对应的码长的长度，K'+P≤N'<N；根据目标校验矩阵，对截短码进行译码，获得K'个译码比特。本发明实施例由于采用的比原始校验矩阵小的目标校验矩阵对截短码译码，无需对完整码进行译码，提高了译码的吞吐量和译码效率。

Description

LDPC截短码的译码方法和译码设备 技术领域
本发明实施例涉及通信技术领域，特别涉及一种低密度奇偶校验码LDPC截短码的译码方法和译码设备。
背景技术
通信的目的是保障传递消息的可靠性、安全性及有效性。但是，有效性和可靠性是相互矛盾的，一般可在信息发送时，通过增加一定的冗余信息来达到通信的可靠性，但对系统的带宽造成了浪费，即降低了有效性。为了实现可靠的信息传输，学者们提出了纠错的编码方案，用来抵抗传输过程中信道噪声对所传信息的干扰，进而保证接收可靠的传输信息。
根据香农(Shannon)理论，香农限是纠错编码能进行有效纠错的最小比特信噪比。纠错编码性能的好坏，由逼近香农限的程度来决定。。20世纪90年代，Turbo码被提出，其性能十分接近香农限。继Turbo码后，低密度奇偶校验码(Low Density Parity Check Code，LDPC)又受到学者的广泛关注，近年来已经成为通信领域的研究热点。
一般而言，LDPC码长越长，译码性能越好，但长的码长意味着逻辑实现需要占用更多的资源，同时因为LDPC译码需要多次的迭代过程，造成译码模块的吞吐量很低。实际应用中，需要尽可能减少参入译码的数据量，从而减小逻辑实现占用的资源，同时提高译码吞吐量。
由于应用方便，LDPC截短码被很多标准广泛采用。LDPC截短码编码时，参入编码的信息比特少于完整的信息码长，零值被填充到剩余数据后面，使得总数据长度等于完整的信息码长度。然后，对信息码进行编码，产生校验位。最后，删除填充的零值，将数据和校验部分发送到信道中去。LDPC截短码译码时，传统的译码方法先填充特定的值到截短的位置，然后对完整的码字进行译码，最后只输出译码后的信息部分(小于完整信息码长度)。
传统LDPC截短码译码与完整码译码过程相同，处理的数据量也相同，但是输出有效数据长度短了，极端情况下，输出的有效数据长度是1，会导致LDPC截短码译码的吞吐量非常低。
发明内容
本发明实施例提供了一种LDPC截短码的译码方法和译码设备，该译码方法能够提高译码的吞吐量。
第一方面，提供了一种低密度奇偶校验码LDPC截短码的译码方法，该截短码包括K’个信息比特和P个校验比特，该译码方法包括：
从该截短码对应的完整码的P*N原始校验矩阵中截取P行N’列，作为P*N’目标校验矩阵，其中，该N’列至少包括该K’个信息比特在完整码中的位置对应的该原始校验矩阵的K’列，和该原始校验矩阵的最后P列，N为该截短码对应的完整码长的长度，N’为该目标校验矩阵对应的码长的长度，K’+P≤N’<N；
根据该目标校验矩阵，对该截短码进行译码，获得K’个译码比特。
结合第一方面，在第一种可能的实现方式中，该根据该目标校验矩阵，对该截短码进行译码，获得K’个译码比特，包括：
根据该目标校验矩阵，采用最小和Min-sum译码算法对该截短码进行译码，获得K’个译码比特。
结合第一方面或第一种可能的实现方式，在第二种可能的实现方式中，
该从该截短码对应的完整码的P*N原始校验矩阵中截取P行N’列，作为P*N’目标校验矩阵，包括：
从该截短码对应的完整码的P*N原始校验矩阵中截取与该K’个信息比特在完整码中的位置对应的该原始校验矩阵的K’列，和该原始校验矩阵的最后P列，作为P*N’目标校验矩阵，其中N’＝K’+P。
结合第一种可能的实现方式，在第三种可能的实现方式中，该截短码为准循环低密度奇偶校验码QC-LDPC截短码，该QC-LDPC截短码对应的完整码的P*N原始校验矩阵的原始基矩阵的维度为P/L*N/L，L为膨胀因子，
该从该截短码对应的完整码的P*N原始校验矩阵中截取P行N’列，作为P*N’目标校验矩阵，包括：
从该原始基矩阵中截取与该K’个信息比特在完整码中的位置对应的该原始基矩阵ceil(K’/L)列，和该原始基矩阵的最后P/L列，作为P*N’目标校验矩阵，其中，ceil(K’/L)表示取大于或等于K’/L的最小整数，N’＝(ceil(K’/L)+P/L)*L。
结合第三种可能的实现方式，在第四种可能的实现方式中，当该K’不 是L的整数倍时，在该根据该目标校验矩阵，采用最小和Min-sum译码算法对该截短码进行译码之前，该译码方法还包括：
在该LDPC截短码中的K’个比特前和/或后填充Z个预设对数似然比LLR值，获得目标截短码，使得目标截短码的码长为N’，Z＝N’-(K’+P)，
其中，该根据该目标校验矩阵，采用最小和Min-sum译码算法对该截短码进行译码，获得K’个比特，包括：
根据该目标校验矩阵采用最小和Min-sum译码算法对该目标截短码进行译码，获得K’个译码比特。
第二方面，提供了一种低密度奇偶校验码LDPC截短码的译码设备，该截短码包括K’个信息比特和P个校验比特，该译码设备包括：
截取单元，用于从该截短码对应的完整码的P*N原始校验矩阵中截取P行N’列，作为P*N’目标校验矩阵，其中，该N’列至少包括该K’个信息比特在完整码中的位置对应的该原始校验矩阵的K’列，和该原始校验矩阵的最后P列，N为该截短码对应的完整码长的长度，N’为该目标截短码对应的码长的长度，K’+P≤N’<N；
译码单元，根据该目标校验矩阵，对该截短码进行译码，获得K’个译码比特。
结合第二方面，在第一种可能的实现方式中，该译码单元，根据该目标校验矩阵，采用最小和Min-sum译码算法对该截短码进行译码，获得K’个译码比特。
结合第二方面或第二方面的第一种可能的实现方式，在第二种可能的实现方式中，
该截取单元从该截短码对应的完整码的P*N原始校验矩阵中截取与该K’个信息比特在完整码中的位置对应的该原始校验矩阵的K’列，和该原始校验矩阵的最后P列，作为P*N’目标校验矩阵，其中N’＝K’+P。
结合第二方面的第一种可能的实现方式，在第三种可能的实现方式中，该截短码为准循环低密度奇偶校验码QC-LDPC截短码，该QC-LDPC截短码对应的完整码的P*N原始校验矩阵的原始基矩阵的维度为P/L*N/L，L为膨胀因子，
该截取单元从该原始基矩阵中截取与该K’个信息比特在完整码中的位置对应的该原始基矩阵ceil(K’/L)列，和该原始基矩阵的最后P/L列，作为 P*N’目标校验矩阵，其中，ceil(K’/L)表示取大于或等于K’/L的最小整数，N’＝(ceil(K’/L)+P/L)*L。
结合第二方面的第三种可能的实现方式，在第四种可能的实现方式中，当该K’不是L的整数倍时，该译码设备还包括：
填充单元，用于在该译码单元根据该目标校验矩阵，采用最小和Min-sum译码算法对该截短码进行译码之前，在该LDPC截短码中的K’个比特前和/或后填充Z个预设对数似然比LLR值，获得目标截短码，使得目标截短码的码长为N’，Z＝N’-(K’+P)，
其中，该译码单元具体用于根据该目标校验矩阵采用最小和Min-sum译码算法对该目标截短码进行译码，获得K’个译码比特。
基于上述技术方案，本发明实施例通过从截短码对应的完整码的原始校验矩阵中截取与该截短码对应的目标校验矩阵，并根据所述目标校验矩阵，对所述截短码进行译码，由于本发明实施例采用比原始校验矩阵小的目标校验矩阵对截短码译码，无需对完整码进行译码，提高了译码的吞吐量和译码效率。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对本发明实施例中所需要使用的附图作简单地介绍，显而易见地，下面所描述的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是一种LDPC截短码的译码方法中填充比特的示意框图。
图2是一种LDPC截短码的译码方法的示意性流程图。
图3是一种LDPC截短码的译码方法的示意框图。
图4是根据本发明一个实施例的LDPC截短码的译码方法的示意性流程图。
图5是根据本发明另一实施例的LDPC截短码的译码方法的示意性流程图。
图6是根据本发明一个实施例的QC-LDPC码基矩阵的结构示意框图。
图7是根据本发明一个实施例的QC-LDPC码基矩阵的元素矩阵的结构示意框图。
图8是根据本发明另一实施例的LDPC截短码的译码方法的示意性流程图。
图9是根据本发明一个实施例的LDPC截短码的译码设备的示意框图。
图10是根据本发明另一实施例的LDPC截短码的译码设备的示意框图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明的一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都应属于本发明保护的范围。
应理解，本发明实施例的技术方案可以应用于各种通信系统，例如，可以应用于数字通信系统和光通信系统，或者说本发明实施例的技术方案可以应用于有线通信系统或无线通信系统，本发明实施例并不对此做限定。
还应理解，在本发明实施例中，译码设备可以作为一个模块集成在任意一个接收器中以用于译码，也可以直接是以下设备，包括但不限于无线或有线信号接收器、具有信号接收器功能的计算机或其他设备等。
需要说明的是，如图1所示，一种LDPC截短码译码方法如下，在译码前，需要将截短码填充成填充比特，形成完整码，然后才进行译码。
具体而言，设LDPC参数为(N,K,P)，其中N表示码字码长，K表示信息码长，P表示编码后产生的校验码长，有如下关系P＝N-K。特定LDPC的校验矩阵H是唯一的，其维度为P*N；并且H是稀疏矩阵，其中大部分元素的值等于0，只有极少数值等于1。
设截短码的信息码长为K’，满足K’<K；发送端在做LDPC编码的时候，先在K’个信息比特后面填充K-K’个零比特，组成K个信息比特，然后利用检验矩阵H对K个信息比特进行编码，得到P个检验比特；在发送到信道之前，需要将填充的K-K’个零比特删除掉，只发送K’+P个比特。
LDPC译码可以分为两大类：硬判决译码和软判决译码。硬判决译码的处理对象是二进制数据，计算数据量少，但译码性能很有限；软判决译码的处理对象是对数似然比(Log Likelihood Ratio，LLR)值，计算数据量相比较大很多，但具有很好的译码性能，在实际应用中，主要使用软判决译码的方式。因此，本发明实施例主要讨论采用软判决译码的方法。
接收端收到K’+P个LLR值后，需要先填充K-K’个特定的LLR值到发送端编码填充零比特的位置，形成总长度为N的码字；然后根据校验矩阵H及填充后的码字进行译码；其中，译码算法很多，这里以最小和(Min-sum)译码算法为例，描述译码流程。
设码长N＝7，信息码长K＝3，截短后的信息码长K’＝2，则校验码长P＝N-K＝4，校验矩阵H维度为4*7。下面结合图2和图3详细描述基于Min-sum译码算法流程。
201，开始。
202，设置最大迭代次数Iter，初始化I＝0。
具体地，该最大迭代次数例如可以为3、5、10等，初始化迭代次数I＝0。
203，接收包括(K'+P)个LLR值的截短码C'
204，填充(K-K')个LLR值，使得码长等于N，生成新的码字C。
例如，如图3(a)所示经过填充特定值后的软信息(即码字C)APP＝[c1c2c3c4c5c6c7]，如图3(a)所示，码字C包括7个LLR值，其中第3个值c3表示填充的LLR值，其中，
Figure PCTCN2015089687-appb-000001
LLR值定义为当前比特ri等于0的概率除以等于1的概率，然后对结果取对数。
205，利用C值初始化变量节点值。
校验矩阵H中1的分布如图3(b)所示，深色背景的方格代表1，没有背景的方格代表0；根据H矩阵1分布位置，用APP值初始化变量节点值Lqji，如公式(1)所示，其中，i是列索引，j是行索引，Lqji表示校验矩阵中第j行第i列的取值，Lci＝ci,i∈[1,7]。
Lqji＝Lci                                    (1)
例如，初始化后，第i列是1的位置的值均为ci。例如，第1列第1行的值为c1，第5列第三行的值为c5。
206，根据校验矩阵H，行更新校验节点。
逐行更新校验节点Lrji，如图3(c)所示；除去当前待更新的点，将本行其它校验节点的符号位相乘作为当前点的输出符号位；除出当前点，取其它校验节点绝对值的最小值作为当前点的输出绝对值；逐行更新，直到4行都 更新完毕。更新过程如公式(2)所示，其中，Rj/i表示第j行中，列索引不等于i的集合，Lrji表示校验矩阵行更新后第j行第i列的取值，
Figure PCTCN2015089687-appb-000002
表示除去当前待更新的第j行第i列的点，将j行其它校验节点的符号位相乘得到的第j行第i列的点的符号位，
Figure PCTCN2015089687-appb-000003
表示除出当前j行第i列的点，取其它校验节点绝对值的最小值得到的当前点的绝对值。应理解，在图3(c)中用Sign*Min(*,*)表示上述行更新的结果。
Figure PCTCN2015089687-appb-000004
βjl＝||Lqjl||           (3)
例如，行更新后，第1行第1列的值为Sign*Min(c3,c5)；第2行第2列的值为Sign*Min(c4,c6)。
207，根据校验矩阵H，列更新变量节点。
逐列更新变量节点Lqji，如图3(d)所示；除去当前待更新的点，将本列其它变量节点的值相加得到当前点的更新值；更新过程如公式(4)所示，其中Cj/i表示第i列中，行索引不等于j的集合，Lqji表示校验矩阵列更新后第j行第i列的取值。
Figure PCTCN2015089687-appb-000005
表示除去当前第j行第i列的的点，将i列其它变量节点的值相加得到第j行第i列的点的更新值。应理解，在图3(d)中，第1至第4行分别用A、B、C、D表示，列标用数字表示，例如，A1表示列更新后第1行第1列的点的取值，C5表示第3行第5列的点的取值。
Figure PCTCN2015089687-appb-000006
例如，列更新后，第1行第1列的值A1＝Sign*Min(c5,c7)。
208，计算总的变量节点值，对其做硬判，得到C1
硬判决，过程如图3(e)所示；将每列所有变量节点值相加，再加上对应位置输入的LLR原始值，得到总的变量节点值LQi，根据其符号位判决成1或0；具体地，根据以下公式确定其判决值：
Figure PCTCN2015089687-appb-000007
LLR(ri)<0    ri＝1
LLR(ri)>0    ri＝0
其中，ri表示当前比特，这里，ri＝LQi。
LQi的计算过程如公式(5)所示，其中Ci表示第i列的索引集合，
Figure PCTCN2015089687-appb-000008
表示i列所有变量节点值之和。
Figure PCTCN2015089687-appb-000009
例如，第1列对应的总的变量节点值为A1+C1+c1。
209，I是否等于Iter。
具体地，判断I是否等于最大迭代次数Iter。如果是(Y)即I＝Iter，则执行步骤212，如果否(N)即I<Iter,则执行步骤210,。
210，I＝I+1。
具体地，当I小于Iter时，使I的值增加1。
211，H*C1是否等于0。
根据硬判以后的码字C1与H矩阵进行校验，如果校验成功，即H*C1＝0，则迭代完成，执行步骤212，否则，H*C1不等于0，则如图3(f)所示，在每列已经列更新的变量节点基础上，加上当前列对应的原始输入LLR值Lcji，作为更新后的变量节点值Lqji，如公式(6)所示。
Figure PCTCN2015089687-appb-000010
之后，返回迭代执行步骤206。
例如，下一次迭代之前第1行第1列的值更新为A1+c1。
212，取C1中前K'个比特作为输出。
具体地，在达到最大迭代次数，或在校验成功以后，输出前K’(两个)比特作为最后的输出结果。
213，结束。
由此可见，上述的译码算法中，例如，设LDPC码长N＝16200，K＝14400，P＝1800，截短后的信息码长K’＝1，则按照上述的截短码译码方法，接收端需要先填充14399个LLR值，然后进行译码，译码完成后，只输出第一个比特作为最后的输出。根据图2和图3的描述，虽然只输出一个比特，但是参与迭代的数据长度还是16200。因此，现有技术下的LDPC截短码译码方法存在如下缺陷：每次迭代的行列更新都需要对填充的LLR值进行处理，增加了译码处理时间，降低了系统吞吐量。以上的操作需要额外的逻辑资源储存填充的数据，导致译码资源增加。
本发明实施例提供了一种LDPC截短码译码的简化方法，解决了上述技术下的LDPC截短码译码吞吐量低、占用资源多的问题。下面结合具体例子进行详细描述。
图4是根据本发明一个实施例的LDPC截短码的译码方法的示意性流程图。其中，该截短码包括K’个信息比特和P个校验比特，如图4所示的译码方法，可以由译码设备执行，具体地，该译码方法包括：
410，从截短码对应的完整码的P*N原始校验矩阵中截取P行N’列，作为P*N’目标校验矩阵，其中，N’列至少包括K’个信息比特在完整码中的位置对应的原始校验矩阵的K’列，和原始校验矩阵的最后P列，N为截短码对应的完整码长的长度，N’为目标校验矩阵对应的码长的长度，K’+P≤N’<N；
420，根据目标校验矩阵，对截短码进行译码，获得K’个译码比特。
因此，本发明实施例通过从截短码对应的完整码的原始校验矩阵中截取与该截短码对应的目标校验矩阵，并根据目标校验矩阵，对截短码进行译码，由于本发明实施例采用比原始校验矩阵小的目标校验矩阵对截短码译码，无需对完整码进行译码，提高了译码的吞吐量，提高了译码效率。
换句话说，由于本发明实施例无需将截短码填充成完整码后再进行译码，而是，截取原始校验矩阵后，直接对截短码进行译码，或者是仅填充一小部分比特再进行译码，提高了译码效率。
并且，本发明实施例减少了对填充LLR值的更新计算，提高了译码模块的处理能力；同时本发明实施例减少了对填充LLR值的存储，减少了逻辑实现时占用的资源。
应理解，在410中，本发明实施例中可以根据截短码截短的位置截取完整校验矩阵，具体而言，完整码的每个比特对应P*N原始校验矩阵的一列，本发明实施例，可以根据截短码中信息比特对应在完整码中的位置对应截取原始校验矩阵获得目标校验矩阵，其中，目标校验矩阵至少包括所有的信息比特对应的列和校验比特对应的列，且目标校验矩阵的列数小于原始校验矩阵的列数。
例如，当截短码的K’个信息比特位于完整码的前K’个比特时，目标校验矩阵至少包括原始校验矩阵的前K’列(原始校验矩阵的最前面K’列)和后P列(原始校验矩阵的最后P列)，再例如，当K’个信息比特位于完整码的中间K’个比特时，目标校验矩阵至少包括原始校验矩阵的对应的中间K’列和后P列，再例如，当K’个信息比特位于完整码的两段比特时，例如第一段包括a个比特，第二段包括b个比特，且a+b＝K’，则目标校验矩阵至少包括原始校验矩阵的对应的中间a列、b列和后P列。
应注意，下文中，仅以K’个信息比特位于完整码的前K’个比特时，目标校验矩阵至少包括原始校验矩阵的前K’列和后P列，为例进行详细说明，但本发明实施例并不限于此。
换句话说，以K’个信息比特位于完整码的前K’个比特时例子进行说明，仅仅是为了帮助本领域技术人员理解本发明实施例，而非要将本发明实施例限于所例示的具体数值或具体场景。本领域技术人员根据该列子，显然可以进行各种等价的修改或变化，例如，当K’个信息比特位于完整码的中间K’个比特时的情形，或者，当K’个信息比特位于完整码的中的几段时的情形，这样的修改或变化也落入本发明实施例的范围内。
应理解，本发明实施例中，获得的K’个译码比特为截短码的K’个信息比特所对应的译码比特。也就是说，即使有填充比特，最终的输出仅是截短码的K’个信息比特所对应的K’个译码比特，换句话说，最后只输出译码后的信息部分。
还应理解，本发明实施例中可以采用多种现有的方法，根据目标校验矩阵，对截短码进行译码，获得K’个译码比特。例如，可以根据目标校验矩阵，采用最小和Min-sum译码算法对截短码进行译码，获得K’个译码比特。本发明实施例并不限于此。
下面，采用最小和Min-sum译码算法对截短码进行译码为例，进行详细 说明。
需要说明的是，本发明实施例的可行性分析如下：
根据LLR的定义，如果当前比特对应的LLR值小于零，则说明当前比特为1的概率大，适合被判决为1；相反，如果LLR值大于零，则适合被判为0；并且LLR值的绝对值越大，被判为1或0的概率越大；如果LLR值正好等于零，说明当前比特等于0或1的概率相等，则被判为1或0都可以(说明发生错误，导致出现误码)。发送端对截短码编码的时候，先在截短的信息码后面填充K-K’个零值，然后编码。对应在接收端，预先知道填充的真实比特为0，所以需要填充一个正的较大LLR值，填充LLR值越大，该位置比特被反转的可能性越小，译码性能就越好。
根据上面的描述，图3(a)中填充的值c3是一个正的极大值，这意味着，与其它值相比，c3值大很多，则有如下分析：
参考图3(c)第一次行更新过程的描述，由于c3是一个正的极大值，c3没有对当前行其它校验节点的更新做出任何贡献；(首先，c3是正值，不会改变符号属性；其次，取最小值过程中，因为c3是极大值，它都不会被选为最小值；)
参考图3(d)列更新过程，同样，第三列c3值也没有对其它列变量节点更新做出任何贡献；
参考图3(e)硬判过程，7列数据中，只有第3列数据与c3相关；但由于A3和D3的值分别是其它行的最小值，它们与c3相加后，结果还是一个正的极大值，对应比特被硬判为0，与发送端填充的真实值相符；
参考图3(f)准备下一次行更新的数据，7列数据中，只有第3列有两个数据与c3相关，分别是c3+A3和c3+D3；由于A3和D3分别是第1行和第5行的最小值，则c3+A3和c3+D3还是两个正的极大值，可以近似认为c3+A3等于c3，c3+D3也等于c3；
一次迭代完成，进入下一次迭代进行行更新，(参考图3(c)，图3(f)替换图(b))进行行更新的过程；同样，由于第3列值比较大，可以认为是最大值，它们对行更新过程没有做出任何贡献；再进行列更新(参考图3(d))过程，同理，只有第3列包括有c3的值；之后经过硬判后，第3列的比特会被硬判为0；准备下一次行更新的数据，同理，只有第3列两个数据与c3相关，且c3的值是极大值。
从以上描述过程可以得出如下结论，采用Min-Sum算法对截短码译码时，现有算法填充的LLR值对算法更新的影响有限；只有当填充的c3较小，经过迭代后，c3所在位置的值更新为最小值时，才能影响到其它节点的更新，但这种情况下，c3所在位置的值已经很小，其符号甚至可能反转，导致误判，从而降低译码性能。因此可以看出，即使填充LLR值对迭代过程有影响，也只是负面的影响。所以在迭代过程中，填充的LLR可以不必参入更新过程。
因此，本发明实施例中将通过截取截短码对应的完整码的原始校验矩阵，获得与该截短码对应的目标校验矩阵，采用目标校验矩阵对截短码译码的方案是可行和有效的。
可选地，作为另一实施例，在410中，从截短码对应的完整码的P*N原始校验矩阵中截取与K’个信息比特在完整码中的位置对应的原始校验矩阵的K’列，和原始校验矩阵的最后P列，作为P*N’目标校验矩阵，其中N’＝K’+P。
例如，根据截短码信息码长K’和校验位P，截取原始校验矩阵H的前K’列和后P列，得到新的校验矩阵H’，现有方案中，译码对象C包括由于截短而填充的部分，长度为N；矩阵H是原始校验矩阵，维度为P*N。本发明方案中，相比较于现有方案，译码对象C’减少了C中填充的部分，新矩阵H’减少了H中填充对应的矩阵块。因此，由于采用的比原始校验矩阵小的目标校验矩阵对截短码译码，无需对完整码进行译码，提高了译码的吞吐量，提高了译码效率。
应理解，本发明实施例中截取的目标校验矩阵可以恰好与截短码对应，即截短码的码字与目标校验矩阵的列数相等；目标校验矩阵的列数也可以多于截短码的码字，但小于完整校验矩阵的列数，这种情况下，需要按照现有的方法在截短码的基础上填充一定的填充比特，使得填充后的码字与目标校验矩阵的列数相等，这种情况下虽然也需要填充比特，但只需填充少量的比特即可，相比于现有技术同样能够提高译码效率。
下面结合图5的具体例子进行详细描述。如图5所示的译码方法包括：
501，开始。
502，设置最大迭代次数Iter，初始化I＝0。
具体地，该最大迭代次数例如可以为3、5、10等，初始化迭代次数I＝0。
503，根据K'值，截取校验矩阵H，得到新的矩阵H'。
具体地，根据截短码信息码长K’，截取P*N原始校验矩阵H，得到新的P*N’校验矩阵H’，其中N’＝K’+P。
504，接收包括(K'+P)个LLR值的截短码C'
505，利用C'值初始化变量节点值。
具体地，步骤505与步骤205类似，505中的具体做法与205类似，区别仅仅在于LDPC码和校验矩阵不同，但具体处理的过程是相同的，为避免重复，此处不再详述，具体地，区别仅在于505中为截短码，205中为完整码，505中对应的校验矩阵为P*N’目标校验矩阵，205中为P*N原始校验矩阵。
506，根据新的校验矩阵H’，行更新校验节点。
具体地，步骤506与步骤206类似，506中的具体做法与206类似，区别仅仅在于LDPC码和校验矩阵不同，但具体处理的过程是相同的，为避免重复，此处不再详述。
507，根据新的校验矩阵H’，列更新变量节点。
具体地，步骤507与步骤207类似，507中的具体做法与207类似，区别仅仅在于LDPC码和校验矩阵不同，但具体处理的过程是相同的，为避免重复，此处不再详述。
508，计算总的变量节点值，对其做硬判，得到比特序列C1’。
具体地，步骤508与步骤208类似，508中的具体做法与208类似，区别仅仅在于LDPC码和校验矩阵不同，但具体处理的过程是相同的，为避免重复，此处不再详述。
509，I是否等于Iter
具体地，判断I是否等于最大迭代次数Iter。如果I＝Iter，则执行步骤512，如果I<Iter,则执行步骤510,。
510，I＝I+1
具体地，当I小于Iter时，使I的值增加1。
511，H’*C1’是否等于0
具体地，对硬判结果做校验，判断矩阵H’与矩阵C1’的乘积是否等于零，如果不等于零，则进入下一次迭代，执行步骤506，否则，执行512；
其中，步骤511与步骤211类似，511中的具体做法与211类似，区别仅仅在于LDPC码和校验矩阵不同，但具体处理的过程是相同的，为避免重复，此处不再详述。
512，取C1’中前K'个比特作为输出。
具体地，在达到最大迭代次数，或在校验成功以后，输出前K’比特作为最后的输出结果。
513，结束。
因此，本发明实施例中将通过从截短码对应的完整码的原始校验矩阵中截取与该截短码对应的目标校验矩阵，采用目标校验矩阵对截短码译码的方案是可行和有效的。
可选地，作为另一实施例，LDPC截短码为准循环低密度奇偶校验码(Quasi-Cyclic Low Density Parity Check Code，QC-LDPC)截短码，QC-LDPC截短码对应的完整码的P*N原始校验矩阵的原始基矩阵的维度为P/L*N/L，L为膨胀因子，
在410中，从原始基矩阵中截取与K’个信息比特在完整码中的位置对应的原始基矩阵ceil(K’/L)列，和原始基矩阵的最后P/L列，作为P*N’目标校验矩阵，其中，ceil(K’/L)表示取大于或等于K’/L的最小整数，N’＝(ceil(K’/L)+P/L)*L。
进一步地，作为另一实施例，当K’不是L的整数倍时，该译码方法还包括：
在LDPC截短码中的K’个比特前和/或后填充Z个预设对数似然比LLR值，获得目标截短码，使得目标截短码的码长为N’，Z＝N’-(K’+P)，
其中，在420中，根据目标校验矩阵采用最小和Min-sum译码算法对目标截短码进行译码，获得K’个译码比特。
应理解，本发明实施例中根据具体情况，在LDPC截短码中的K’个比特前和/或后填充Z个预设对数似然比LLR值，获得目标截短码，使得目标 截短码的码长为N’，Z＝N’-(K’+P)。例如，当截短码的K’个信息比特位于完整码中的位置时，填充的比特可以位于K’个比特前，也可以位于K’个比特后。
具体而言，在LDPC应用中，QC-LDPC由于具有更小的存储需求而成为主要的类型。QC-LDPC的校验矩阵由两个参数决定，基矩阵H1和膨胀因子L。图6描述了基矩阵H1的结构，其中膨胀因子L＝8。基矩阵中的每个元素代表着一个L*L的方阵，方阵值由该元素的值决定。根据示例中基矩阵的维度参数4*10(m＝4,n＝10)，及膨胀因子L＝8，可以得到原始校验矩阵H的维度为32*80(mL*nL)，进而得到LDPC的基本参数：N＝80，P＝32，K＝48。基矩阵中元素的值可以分为两种类型，-1和非-1。-1代表一个L*L的零矩阵；非-1的值，如k，它代表L*L的单位矩阵以列向量为单元循环右移k次后得到的矩阵，则0代表一个L*L的单位阵；1代表单位矩阵以列向量为单元循环右移一次得到的矩阵。k取值范围为-1、0、1、…、L-1。图7描述了k等于0、1和2值代表的矩阵内容的情形，k取其他值的情形以此类推能够得到，此处不再赘述。
根据QC-LDPC的描述可知，这种类型的校验矩阵H可以由基矩阵H1和膨胀因子L表示，在逻辑实现时，只需要存储H1，相比较于一般存储原始校验矩阵H的方式，存储量极大减小。因此，现在很多场景中，QC-LDPC被广泛应用。
应理解，当QC-LDPC码的信息比特个数K’是膨胀因子L的整数倍时，本发明实施例无需进行填充，具体的处理过程与图5类似，区别仅仅在于，截取原始基矩阵的前ceil(K’/L)列和后P/L列，获得P*N’目标校验矩阵。其他后续处理过程与图5的方法类似，此处不再详述。
当K’不是L的整数倍时，本发明实施例译码方法需要在LDPC截短码中的K’个比特后填充Z个预设对数似然比LLR值，获得目标截短码，使得目标截短码的码长为N’，Z＝N’-(K’+P)。填充比特的目的就是为了使得目标截短码的码长与目标校验矩阵相对应，以便于根据目标校验矩阵采用最小和Min-sum译码算法对目标截短码进行译码，获得前K’个译码比特。
应理解，本发明实施例中截取的目标校验矩阵可以恰好与截短码对应，即目标校验矩阵的包括与截短码的信息比特在完整码中的位置对应的大于或等于K’/L的最小整数的列数，和后后P/L列。目标校验矩阵的列数也可 以多于该列数，但小于完整校验矩阵的列数，这种情况下，需要按照现有的方法在截短码的基础上多填充一定的填充比特，使得填充后的码字与目标校验矩阵的列数相等，这种情况下虽然也需要填充比特，但只需填充少量的比特即可，相比于现有技术同样能够提高译码效率。
下面结合图8，详细说明K’不是L的整数倍时，本发明实施例具体的译码方法。
具体地，如图8所示的译码方法包括：
801，开始。
802，设置最大迭代次数Iter，初始化I＝0。
具体地，该最大迭代次数例如可以为3、5、10等，初始化迭代次数I＝0。
803，根据K'值，截取校验矩阵H，得到新的矩阵H1'。
具体地，截取原始基矩阵的前ceil(K’/L)列和后P/L列，获得P*N’目标校验矩阵，其中，ceil(K’/L)表示取大于或等于K’/L的最小整数，
N’＝(ceil(K’/L)+P/L)*L。
804，接收包括(K'+P)个LLR值的截短码C'
805，填充N'-(K'+P)个LLR值，使得码长等于N'，生成新的码字C”
在LDPC截短码中的K’个比特后填充Z个预设对数似然比LLR值，获得目标截短码，使得目标截短码的码长为N’，Z＝N’-(K’+P)。
806，利用C”值初始化变量节点值。
具体地，步骤806与步骤205类似，806中的具体做法与205类似，区别仅仅在于LDPC码和校验矩阵不同，但具体处理的过程是相同的，为避免重复，此处不再详述，具体地，区别仅在于806中为截短码，205中为完整码，806中对应的校验矩阵为P*N’目标校验矩阵，205中为P*N原始校验矩阵。
807，根据新的校验矩阵H1'，行更新校验节点。
具体地，步骤807与步骤206类似，807中的具体做法与206类似，区别仅仅在于LDPC码和校验矩阵不同，但具体处理的过程是相同的，为避免重复，此处不再详述。
808，根据新的校验矩阵H1'，列更新变量节点。
具体地，步骤808与步骤207类似，808中的具体做法与207类似，区别仅仅在于LDPC码和校验矩阵不同，但具体处理的过程是相同的，为避免重复，此处不再详述。
809，计算总的变量节点值，对其做硬判，得到比特序列C1”。
具体地，步骤809与步骤208类似，809中的具体做法与208类似，区别仅仅在于LDPC码和校验矩阵不同，但具体处理的过程是相同的，为避免重复，此处不再详述。
810，I是否等于Iter
具体地，判断I是否等于最大迭代次数Iter。如果I＝Iter，则执行步骤813，如果I<Iter,则执行步骤811。
811，I＝I+1
具体地，当I小于Iter时，使I的值增加1。
812，H1’*C1”是否等于0
具体地，对硬判结果做校验，判断矩阵H1’与矩阵C”的乘积是否等于零，如果不等于零，则进入下一次迭代，执行步骤807，否则，执行813。
其中，步骤812与步骤211类似，812中的具体做法与211类似，区别仅仅在于LDPC码和校验矩阵不同，但具体处理的过程是相同的，为避免重复，此处不再详述。
813，取C1”中前K'个比特作为输出。
具体地，在达到最大迭代次数，或在校验成功以后，输出前K’比特作为最后的输出结果。
814，结束。
因此，本发明实施例中将通过从截短码对应的完整码的原始校验矩阵中截取与该截短码对应的目标校验矩阵，并根据目标校验矩阵，对截短码进行译码，由于本发明实施例采用比原始校验矩阵小的目标校验矩阵对截短码译码，无需对完整码进行译码，提高了译码的吞吐量和译码效率。
应注意，图1至图8的例子仅仅是为了帮助本领域技术人员理解本发明实施例，而非要将本发明实施例限于所例示的具体数值或具体场景。本领域技术人员根据所给出的图1至图8的例子，显然可以进行各种等价的修改或变化，这样的修改或变化也落入本发明实施例的范围内。
上文中结合图1至图8详细描述了本发明实施例的译码方法，下面将结合图9和图10描述本发明实施例的译码设备。
图9是根据本发明一个实施例的LDPC截短码的译码设备的示意框图。图9所示的译码设备900与图4所示的译码方法相对应，译码设备900能够实现图4译码方法实施例中的各个过程，译码设备900的具体功能可参见图4中的相应描述，为避免重复，此处适当省略详细描述。译码设备900用于低密度奇偶校验码LDPC截短码译码，可以包括：截取单元910和译码单元920。
具体地，截取单元910用于截取截短码对应的完整码的P*N原始校验矩阵，获得P*N’目标校验矩阵，其中，目标校验矩阵至少包括原始校验矩阵中与截短码的信息比特在完整码中的位置对应的K’列和后P列，N为截短码对应的完整码长的长度，N’为目标截短码对应的码长的长度，K’+P≤N’<N；译码单元920根据目标校验矩阵，对截短码进行译码，获得K’个译码比特。
因此，本发明实施例通过从截短码对应的完整码的原始校验矩阵中截取与该截短码对应的目标校验矩阵，并根据目标校验矩阵，对截短码进行译码，由于本发明实施例采用比原始校验矩阵小的目标校验矩阵对截短码译码，无需对完整码进行译码，提高了译码的吞吐量和译码效率。
换句话说，由于本发明实施例无需将截短码填充成完整码后再进行译码，而是，截取原始校验矩阵后，直接对截短码进行译码，或者是仅填充一小部分比特再进行译码，提高了译码效率。
并且，本发明实施例减少了对填充LLR值的更新计算，提高了译码模块的处理能力；同时本发明实施例减少了对填充LLR值的存储，减少了逻辑实现时占用的资源。
可选地，作为另一实施例，译码单元920根据目标校验矩阵，采用最小和Min-sum译码算法对截短码进行译码，获得K’个译码比特。
可选地，作为另一实施例，截取单元910从截短码对应的完整码的P*N原始校验矩阵中截取与K’个信息比特在完整码中的位置对应的原始校验矩 阵的K’列，和原始校验矩阵的最后P列，作为P*N’目标校验矩阵，其中N’＝K’+P。
可替代地，作为另一实施例，LDPC截短码为准循环低密度奇偶校验码QC-LDPC截短码，QC-LDPC截短码对应的完整码的P*N原始校验矩阵的原始基矩阵的维度为P/L*N/L，L为膨胀因子，
截取单元910从原始基矩阵中截取与K’个信息比特在完整码中的位置对应的原始基矩阵ceil(K’/L)列，和原始基矩阵的最后P/L列，作为P*N’目标校验矩阵，其中，ceil(K’/L)表示取大于或等于K’/L的最小整数，N’＝(ceil(K’/L)+P/L)*L。
进一步地，作为另一实施例，当K’不是L的整数倍时，译码设备还包括：填充单元。
具体地，填充单元用于在译码单元根据目标校验矩阵，采用最小和Min-sum译码算法对截短码进行译码之前，在LDPC截短码中的K’个比特前和/或填充Z个预设对数似然比LLR值，获得目标截短码，使得目标截短码的码长为N’，Z＝N’-(K’+P)，
其中，译码单元920具体用于根据目标校验矩阵采用最小和Min-sum译码算法对目标截短码进行译码，获得目标截短码对应的K’个译码比特。
图10是根据本发明另一实施例的LDPC截短码的译码设备的示意框图。。图10所示的译码设备1000与图4所示的译码方法相对应，译码设备1000能够实现图4译码方法实施例中的各个过程，译码设备1000的具体功能可参见图4中的相应描述，为避免重复，此处适当省略详细描述。译码设备1000用于低密度奇偶校验码LDPC截短码译码，可以包括：包括处理器1010、存储器1020和总线系统1030。
具体地，处理器1010通过总线系统1030调用存储在存储器1020中的代码，从截短码对应的完整码的P*N原始校验矩阵中截取P行N’列，作为P*N’目标校验矩阵，其中，N’列至少包括K’个信息比特在完整码中的位置对应的原始校验矩阵的K’列，和原始校验矩阵的最后P列，N为截短码对应的完整码长的长度，N’为目标校验矩阵对应的码长的长度，K’+P≤N’<N；根据目标校验矩阵，对截短码进行译码，获得K’个译码比特。
因此，本发明实施例通过从截短码对应的完整码的原始校验矩阵中截取与该截短码对应的目标校验矩阵，并根据目标校验矩阵，对截短码进行译码， 由于本发明实施例采用比原始校验矩阵小的目标校验矩阵对截短码译码，无需对完整码进行译码，提高了译码的吞吐量和译码效率。
换句话说，由于本发明实施例无需将截短码填充成完整码后再进行译码，而是，截取原始校验矩阵后，直接对截短码进行译码，或者是仅填充一小部分比特再进行译码，提高了译码效率。
并且，本发明实施例减少了对填充LLR值的更新计算，提高了译码模块的处理能力；同时本发明实施例减少了对填充LLR值的存储，减少了逻辑实现时占用的资源。
上述本发明实施例揭示的方法可以应用于处理器1010中，或者由处理器1010实现。处理器1010可能是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法的各步骤可以通过处理器1010中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器1010可以是通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现成可编程门阵列(Field Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本发明实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本发明实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存取存储器(Random Access Memory，RAM)、闪存、只读存储器(Read-Only Memory，ROM)、可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器1020，处理器1010读取存储器1020中的信息，结合其硬件完成上述方法的步骤，该总线系统1030除包括数据总线之外，还可以包括电源总线、控制总线和状态信号总线等。但是为了清楚说明起见，在图中将各种总线都标为总线系统1030。
可选地，作为另一实施例，处理器1010根据目标校验矩阵，采用最小和Min-sum译码算法对截短码进行译码，获得K’个译码比特。
可选地，作为另一实施例，处理器1010从截短码对应的完整码的P*N原始校验矩阵中截取与K’个信息比特在完整码中的位置对应的原始校验矩阵的K’列，和原始校验矩阵的最后P列，作为P*N’目标校验矩阵，其中 N’＝K’+P。
可替代地，作为另一实施例，LDPC截短码为准循环低密度奇偶校验码QC-LDPC截短码，QC-LDPC截短码对应的完整码的P*N原始校验矩阵的原始基矩阵的维度为P/L*N/L，L为膨胀因子，
处理器1010从原始基矩阵中截取与K’个信息比特在完整码中的位置对应的原始基矩阵ceil(K’/L)列，和原始基矩阵的最后P/L列，作为P*N’目标校验矩阵，其中，ceil(K’/L)表示取大于或等于K’/L的最小整数，N’＝(ceil(K’/L)+P/L)*L。
进一步地，作为另一实施例，当K’不是L的整数倍时，处理器1010在译码单元根据目标校验矩阵，采用最小和Min-sum译码算法对截短码进行译码之前，在LDPC截短码中的K’个比特前和/或后填充Z个预设对数似然比LLR值，获得目标截短码，使得目标截短码的码长为N’，Z＝N’-(K’+P)；处理器1010具体用于根据目标校验矩阵采用最小和Min-sum译码算法对目标截短码进行译码，获得目标截短码对应的K’个译码比特。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本发明的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本发明的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本发明实施例的实施过程构成任何限定。
另外，本文中术语“系统”和“网络”在本文中常被可互换使用。本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
应理解，在本发明实施例中，“与A相应的B”表示B与A相关联，根据A可以确定B。但还应理解，根据A确定B并不意味着仅仅根据A确定B，还可以根据A和/或其它信息确定B。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实 现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、装置或单元的间接耦合或通信连接，也可以是电的，机械的或其它的形式连接。
作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本发明实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以是两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到本发明可以用硬件实现，或固件实现，或它们的组合方式来实现。当使用软件实现时，可以将上述功能存储在计算机可读介质中或作为计算机可读介质上的一个或多个指令或代码进行传输。计算机可读介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是计算机能够存取的任何可用介质。以此为例但不限于：计算机可读介质可以包括RAM、ROM、EEPROM、CD-ROM或其他光盘存储、磁盘存储介质或者其他磁存储设备、或者能够用于携带或存储 具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质。此外。任何连接可以适当的成为计算机可读介质。例如，如果软件是使用同轴电缆、光纤光缆、双绞线、数字用户线(DSL)或者诸如红外线、无线电和微波之类的无线技术从网站、服务器或者其他远程源传输的，那么同轴电缆、光纤光缆、双绞线、DSL或者诸如红外线、无线和微波之类的无线技术包括在所属介质的定影中。如本发明所使用的，盘(Disk)和碟(disc)包括压缩光碟(CD)、激光碟、光碟、数字通用光碟(DVD)、软盘和蓝光光碟，其中盘通常磁性的复制数据，而碟则用激光来光学的复制数据。上面的组合也应当包括在计算机可读介质的保护范围之内。
总之，以上所述仅为本发明技术方案的较佳实施例而已，并非用于限定本发明的保护范围。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种低密度奇偶校验码LDPC截短码的译码方法，其特征在于，所述截短码包括K’个信息比特和P个校验比特，所述译码方法包括：
    从所述截短码对应的完整码的P*N原始校验矩阵中截取P行N’列，作为P*N’目标校验矩阵，其中，所述N’列至少包括所述K’个信息比特在完整码中的位置对应的所述原始校验矩阵的K’列，和所述原始校验矩阵的最后P列，N为所述截短码对应的完整码长的长度，N’为所述目标校验矩阵对应的码长的长度，K’+P≤N’<N；
    根据所述目标校验矩阵，对所述截短码进行译码，获得K’个译码比特。
  2. 根据权利要求1所述的译码方法，其特征在于，
    所述根据所述目标校验矩阵，对所述截短码进行译码，获得K’个译码比特，包括：
    根据所述目标校验矩阵，采用最小和Min-sum译码算法对所述截短码进行译码，获得K’个译码比特。
  3. 根据权利要求1或2所述的译码方法，其特征在于，
    所述从所述截短码对应的完整码的P*N原始校验矩阵中截取P行N’列，作为P*N’目标校验矩阵，包括：
    从所述截短码对应的完整码的P*N原始校验矩阵中截取与所述K’个信息比特在完整码中的位置对应的所述原始校验矩阵的K’列，和所述原始校验矩阵的最后P列，作为P*N’目标校验矩阵，其中N’＝K’+P。
  4. 根据权利要求2所述的译码方法，其特征在于，
    所述截短码为准循环低密度奇偶校验码QC-LDPC截短码，所述QC-LDPC截短码对应的完整码的P*N原始校验矩阵的原始基矩阵的维度为P/L*N/L，L为膨胀因子，
    所述从所述截短码对应的完整码的P*N原始校验矩阵中截取P行N’列，作为P*N’目标校验矩阵，包括：
    从所述原始基矩阵中截取与所述K’个信息比特在完整码中的位置对应的所述原始基矩阵ceil(K’/L)列，和所述原始基矩阵的最后P/L列，作为P*N’目标校验矩阵，其中，ceil(K’/L)表示取大于或等于K’/L的最小整数，N’＝(ceil(K’/L)+P/L)*L。
  5. 根据权利要求4所述的译码方法，其特征在于，
    当所述K’不是L的整数倍时，在所述根据所述目标校验矩阵，采用最小和Min-sum译码算法对所述截短码进行译码之前，所述译码方法还包括：
    在所述截短码中的K’个比特前和/或后填充Z个预设对数似然比LLR值，获得目标截短码，使得目标截短码的码长为N’，Z＝N’-(K’+P)，
    其中，所述根据所述目标校验矩阵，采用最小和Min-sum译码算法对所述截短码进行译码，获得K’个比特，包括：
    根据所述目标校验矩阵采用最小和Min-sum译码算法对所述目标截短码进行译码，获得K’个译码比特。
  6. 一种低密度奇偶校验码LDPC截短码的译码设备，其特征在于，所述截短码包括K’个信息比特和P个校验比特，所述译码设备包括：
    截取单元，用于从所述截短码对应的完整码的P*N原始校验矩阵中截取P行N’列，作为P*N’目标校验矩阵，其中，所述N’列至少包括所述K’个信息比特在完整码中的位置对应的所述原始校验矩阵的K’列，和所述原始校验矩阵的最后P列，N为所述截短码对应的完整码长的长度，N’为所述目标截短码对应的码长的长度，K’+P≤N’<N；
    译码单元，根据所述目标校验矩阵，对所述截短码进行译码，获得K’个译码比特。
  7. 根据权利要求6所述的译码设备，其特征在于，
    所述译码单元，根据所述目标校验矩阵，采用最小和Min-sum译码算法对所述截短码进行译码，获得K’个译码比特。
  8. 根据权利要求6或7所述的译码设备，其特征在于，
    所述截取单元从所述截短码对应的完整码的P*N原始校验矩阵中截取与所述K’个信息比特在完整码中的位置对应的所述原始校验矩阵的K’列，和所述原始校验矩阵的最后P列，作为P*N’目标校验矩阵，其中N’＝K’+P。
  9. 根据权利要求7所述的译码设备，其特征在于，
    所述截短码为准循环低密度奇偶校验码QC-LDPC截短码，所述QC-LDPC截短码对应的完整码的P*N原始校验矩阵的原始基矩阵的维度为P/L*N/L，L为膨胀因子，
    所述截取单元从所述原始基矩阵中截取与所述K’个信息比特在完整码中的位置对应的所述原始基矩阵ceil(K’/L)列，和所述原始基矩阵的最后P/L列，作为P*N’目标校验矩阵，其中，ceil(K’/L)表示取大于或等于K’/L的最 小整数，N’＝(ceil(K’/L)+P/L)*L。
  10. 根据权利要求9所述的译码设备，其特征在于，
    当所述K’不是L的整数倍时，所述译码设备还包括：
    填充单元，用于在所述译码单元根据所述目标校验矩阵，采用最小和Min-sum译码算法对所述截短码进行译码之前，在所述LDPC截短码中的K’个比特前和/或后填充Z个预设对数似然比LLR值，获得目标截短码，使得目标截短码的码长为N’，Z＝N’-(K’+P)，
    其中，所述译码单元具体用于根据所述目标校验矩阵采用最小和Min-sum译码算法对所述目标截短码进行译码，获得K’个译码比特。
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