WO2019096184A1 - 阶梯码的解码方法、装置及存储介质 - Google Patents
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- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/251—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with block coding
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- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
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- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
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- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
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- H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
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Definitions
- the present application relates to the field of communications, for example, to a method, an apparatus, and a storage medium for decoding a ladder code.
- FEC Forward Error Correction
- NCG Net Coding Gain
- the Staircase code is an FEC code with correlation of a codeword proposed based on the structure of the product code.
- the basic principle is shown in FIG. 2 and FIG. 3.
- the information matrix block of B i, L is formed, and the immediately adjacent mr symbols are the parity code check bits, which constitute the check of B i, R Matrix block.
- the generation method of the check matrix block B i, R is as shown in FIG. 2 , which is obtained by [B i-1 T B i,L ] by (2m, 2m-r) block code encoding, where B i-1 T Transposed for the block matrix B i-1 .
- B 1, R is obtained by encoding [B 0 T B 1,L ] by m (2m, 2m-r) block codes, where B 0 T is the initial block of the staircase code, which is known. Symbol (for example, all zero symbols). Subsequent B i,R are successively obtained by [B i-1 T B i,L ] by (2m, 2m-r) block code encoding, as shown in FIG. 3, forming an infinite "staircase" form code structure.
- the block code used in the staircase code utilizes the correlation between the code words, so the error correction capability of the block code used in the staircase code is relative to the block code used in the TPC code.
- the minimum distance characteristic should be weakened, so the reduction of the minimum distance may lead to the occurrence of bit error leveling. Therefore, in the soft decoding method of the staircase code, how to use the correlation between codewords reasonably and efficiently is particularly important. There is no coding method capable of simultaneously applying hard coding and soft coding in the related art.
- the embodiment of the present application provides a method, an apparatus, and a storage medium for decoding a staircase staircase code, so as to avoid the case where there is no coding method capable of simultaneously applying hard coding and soft coding in the related art.
- a method for decoding a staircase staircase code includes: updating soft information of an initial S code block in a staircase code to obtain a first information block, and using the first information Updating the last ST coding blocks of the block and the T newly added coding blocks to obtain a second information block, where S and T are integers greater than 0; and the first T coding blocks and locations of the first information block Decoding the first ST coding blocks of the second information block to obtain a third information block, and outputting the pre-T block information as a decoder output; repeatedly performing the following operations: from the second information block or the third information block Selecting ST pieces of information, and updating the selected ST pieces of information together with the T newly added code blocks to obtain S updated pieces of information, and updating the S pieces of information
- the information block is used as a new second information block; the T1 to 2T block information in the third information block and the previous ST block information in the new second information block are decoded together to obtain a new first Three information blocks, outputting the first T block information
- a decoding apparatus for a staircase staircase code comprising: an updating module, configured to perform soft information update on an initial S coding block in a staircase code to obtain a first information block, and Updating the last ST coding blocks of the first information block and the T newly added coding blocks to obtain a second information block, where S and T are integers greater than 0; and decoding module is set to The first T coding blocks of an information block and the first ST coding blocks of the second information block are decoded to obtain a third information block, and the first T block information is output as a decoder output; and the processing module is set to repeatedly execute the following: Operation: selecting ST information blocks from the second information block or the third information block, and updating the selected ST information blocks together with the T newly added coding blocks to obtain soft information, S updated information blocks, and the information block after the S block update is used as a new second information block; the T+1 to 2T block information and the new number in the third information block
- a storage medium comprising a stored program, wherein the program is executed to perform the method of any of the above.
- processor configured to execute a program, wherein the program is executed to perform the method of any of the above.
- FIG. 1 is a block diagram of a typical transmission system in the related art
- FIG. 2 is a schematic diagram of a single block structure of a staircase code in the related art
- FIG. 3 is a schematic diagram of a code structure of a staircase code in the related art
- FIG. 4 is a flowchart of a method for decoding a staircase code according to an embodiment of the present application
- FIG. 5 is a flowchart of soft decoding of a staircase code according to an embodiment of the present application.
- FIG. 6 is a structural block diagram of a decoding apparatus for a staircase code according to an embodiment of the present application.
- the present application is directed to the case of the error leveling phenomenon caused by the error correction capability and the minimum distance characteristic in the related art, and proposes a decoding method of the staircase staircase code, which fully utilizes the soft decoding idea and the staircase of the packet TPC code.
- the characteristics of the correlation between the code words of the code achieve a good control of the phenomenon of error leveling.
- the method of the present application is not limited to the method of calculating the block code type and the external information used, and is applicable to various methods.
- FIG. 4 is a flowchart of a decoding method of a staircase code according to an embodiment of the present application. As shown in FIG. 4, the method includes step S402, step S404, and step S406.
- the first S information block is obtained by updating the initial S coding blocks in the staircase code to obtain the first information block, and the last ST coding blocks and the T newly added coding blocks of the first information block are updated.
- a second information block wherein S and T are integers greater than zero.
- step S404 the first T coding blocks of the first information block and the first S-T coding blocks of the second information block are decoded to obtain a third information block, and the pre-T block information is output as a decoder output.
- step S406 the following operations are repeatedly performed: selecting ST information blocks from the second information block or the third information block, and updating the selected ST information blocks together with the T newly added coding blocks. Obtaining S updated information blocks, and using the S block updated information block as a new second information block; for the T+1th to 2T block information in the third information block and the new second information block The pre-ST block information is decoded together to obtain a new third information block, and the pre-T block information is output as the output of the decoder.
- the last ST code blocks of the first information block and the T newly added code blocks are performed. Updating to obtain the second information block, decoding the first T coding blocks of the first information block and the first ST coding blocks of the second information block to obtain a third information block; making full use of the packet (Turbo Product Code, TPC) code.
- TPC Transmissionbo Product Code
- updating the soft information to the initial S coding blocks in the staircase code to obtain the first information block includes: performing soft information by performing N 1 _itr iterations on the initial S coding blocks B i The update obtains the first information block, where 1 ⁇ i ⁇ S, and N 1 _itr is an integer greater than zero.
- updating the soft information by performing N 1 _itr iterations on the initial S coding blocks B i includes a first update process and a second update process.
- the registers are configurable.
- updating the last ST coding blocks of the first information block and the T newly added coding blocks to obtain the second information block includes a third update process, a fourth update process, and a fifth update process.
- decoding the first T coding blocks of the first information block and the first ST coding blocks of the second information block to obtain the third information block includes one of: first T coding of the first information block Performing hard decoding on the first ST coding blocks of the block and the second information block to obtain a third information block; and performing soft decoding on the first T coding blocks of the first information block and the first ST coding blocks of the second information block to obtain a third information block Information block.
- hard decoding the first T coding blocks of the first information block and the first ST coding blocks of the second information block to obtain the third information block includes: obtaining the first information block and the second information by using the following formula:
- the obtained soft information is hard-cased by determining the sign bit as 0 bit or 1 bit by matching the sign bit of the element in the obtained soft information with the encoding rule.
- N 2 _itr decoding process when the N 2 _itr decoding process is repeatedly performed, when the block code has an extended parity bit, the previous N 3 _itr iterations will not satisfy the (2m, 2m-r) packet of the parity bit.
- the code decoding result is iterated, the recovery group code is used to decode the current input data, the subsequent iteration does not perform the check bit detection, and the decoding result is XORed to obtain the check digit, wherein the range of N 3 _itr is [1, N 2 _itr], N 2 _itr is an integer greater than 0.
- the current code word sequence is restored to the original input data.
- the pre-T block data obtained after the hard-segment processing is determined as the third
- the information block is output as a decoder.
- selecting ST information blocks from the second information block or the third information block comprises: hard decoding the first T coding blocks of the first information block and the first ST coding blocks of the second information block
- the ST information blocks are selected by: deleting the first T block data in the second information block to obtain ST information blocks; or selecting the 2T+1 block in the third information block and After the N_bh block, the original input data corresponding to the soft information of the T+N_bh+2 to the Sth block in the second information block is spliced as ST information blocks, wherein the value range of N_bh is [0, ST- 1].
- the ST information blocks are selected by: selecting the third information block from the third information block.
- FIG. 5 is a flowchart of soft decoding of a staircase code according to an embodiment of the present application. As shown in FIG. 5, the method includes steps S502 to S512.
- step S502 soft information is updated for the initial S B i blocks, B 0 , B 1 , ... B T-1 , B T , ... B S-1 . , B 0 1 , B 1 1 , ... B T-1 1 , B T 1 , ... B S-1 1 are obtained .
- the parameters S and T respectively represent the number of data blocks per soft decoding and the number of new data blocks added in the next decoding, and the support registers can be matched.
- step S504 the soft information B T 1 , ... B S-1 1 obtained by S502 and the newly added data blocks B S , B S+1 , ... B S+T- 1 Update the soft information to obtain B T 2 , ... B S-1 2 , B S 1 , B S+1 1 , ... B S+T-1 1 .
- step S506 the soft information B T 2 , ... B S-1 obtained by the soft information B 0 1 , B 1 1 , ... B T-1 1 and S104 obtained in S502.
- 2 Perform hard decoding or soft decoding to obtain B 0 2 , B 1 2 , ... B T-1 2 , B T 3 , ... B S-1 3 ; B 0 2 , B 1 2 , ... B T-1 2 data output, the decoder output is obtained.
- step S508 the post-S-T block soft information is selected according to the different decoding methods of S506, and the soft information is updated together with the newly added T-block data to obtain the S-block updated soft information data.
- step S510 the first T+1 to 2T block data obtained in S506 and the previous S-T block data obtained in S508 are hard-decoded or soft-decoded together, and the previous T-block data is output as the output of the decoder.
- step S512 S508 and S510 are repeatedly executed, and the source decoder continuously outputs T block stream data.
- the soft information is updated in S502 to the initial block of the S B i, the process comprising the working steps 1 to three.
- R i 0 is the original input data of the decoder corresponding to B i
- R i n is n times of iterative soft information corresponding to B i
- W i n is obtained by the code block [B i-1 T B i ]
- a i n is the reliability factor of the external information, and the value ranges from (0, 1), A 0 0 takes the value 1, and A 1 0 takes the smaller value.
- a i n is greater than or equal to A i n-1
- N 1 _itr supports register configurable.
- the step S504, the S blocks B i is updated soft information, to a working process comprising the step of step IV.
- R i 0 is the original input data of the decoder corresponding to B i
- a i-1 0 is greater than or equal to A i 0 .
- a i n is greater than or equal to A i n-1 .
- step S506 the S a hardware decoding blocks B i, the output Staircase overlapping code hardware decoding scheme to a process comprising the step of step five.
- R i n is the n iteration output corresponding to B i
- R i n-1 is the n-1 iteration output corresponding to B i , that is, n iteration inputs.
- W i n is the outer information obtained by the [B i-1 T B i ] code block.
- the soft information obtained in step S502 is hard-sent.
- the hard-segment method is to take the sign bit of the corresponding symbol, corresponding to the coding rule, and determine the sign bit as 0/1 bit.
- step four step three is repeated N 2 _itr times, and the final pre-T block data is output as a decoder.
- the N 2 _itr support register is configurable. When the block code has an extended check bit, the previous N 3 _itr iterations will not satisfy the (2m, 2m-r) block code decoding result iteration of the check bit, and the recovered block code decodes the current input data. Subsequent iterations do not perform check bit detection, but the decoded result is XORed to obtain a check bit.
- the N 3 _itr support register is configurable and has a value range of [1, N 2 _itr].
- step 5 in order to correct the decoder deadlock phenomenon, during the intermediate iteration of the decoder operation, when the packet decoder feeds back the error, the codeword sequence at this time is restored to the original input data. .
- the S blocks B i th normalized, soft decoding, soft decoding output Staircase program code overlapping process comprises a step to step five.
- R i 0 is the original input data of the decoder corresponding to B i
- R i n is the n iteration soft information corresponding to B i .
- W i n is the external information obtained by the [B i-1 T B i ] code block, and A i 0 is the reliability factor of the external information, and the value range is (0, 1), and A i-1 0 is greater than or equal to A i 0 .
- step 2 soft information is updated for the S B i block data obtained in step 1.
- step 4 the soft information obtained in step 3 is hard-sent.
- the hard-sent method is to take the sign bit of the corresponding symbol (or the corresponding element), corresponding to the coding rule, and determine the sign bit as 0/1 bit. .
- step 5 the pre-T block data obtained in step four is output as a decoder.
- the ST block soft information is selected in the step S508, and the selection process includes: if the step S506 adopts hard decoding, the soft information obtained in step S504 is discarded as the first block data, as the ST block soft information;
- the data block obtained by hard decoding in step S506 selects the second T+1 block and the subsequent N_bh block, and then splices the original input data corresponding to the soft information of the T+N_bh+2 to the S block obtained in step S504.
- N_bh has a value range of [0, S-T-1], and supports register configurable.
- step S506 employs soft decoding
- R i n is the n-th iteration soft information output corresponding to B i
- W i n is the outer information obtained by the [B i-1 T B i ] code block.
- the working process is the same as the processing in the first step to the fourth step included in the step S504.
- the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, by hardware, but in many cases, the former is A better implementation.
- the technical solution of the present application which is essential or contributes to the related art, may be embodied in the form of a software product stored in a storage medium such as a read only memory/random access memory. (Read Only Memory/Random access Memory, ROM/RAM), a disk, and an optical disk, including a plurality of instructions for causing a terminal device, which may be a mobile phone, a computer, a server, or a network device, to perform each embodiment of the present application. Said method.
- a decoding device for a staircase code is also provided.
- the device is configured to implement the foregoing embodiments and example embodiments, and details are not described herein.
- the term "module" may implement a combination of at least one of software and hardware for a predetermined function.
- the apparatus described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware, is also possible and contemplated.
- FIG. 6 is a structural block diagram of a decoding apparatus for a staircase code according to an embodiment of the present application. As shown in FIG. 6, the apparatus includes an update module 602, a decoding module 604, and a processing module 606.
- the updating module 602 is configured to perform soft information update on the initial S coding blocks in the staircase code to obtain a first information block, and update the last ST coding blocks and the T newly added coding blocks of the first information block. A second block of information is obtained, wherein S and T are both integers greater than zero.
- the decoding module 604 is connected to the update module 602, and is configured to decode the first T coding blocks of the first information block and the first ST coding blocks of the second information block to obtain a third information block, and output the first T block information as Decoder output.
- the processing module 606 is coupled to the decoding module 604, and is configured to repeatedly perform the following operations: selecting ST information blocks from the second information block or the third information block, and selecting the ST information blocks and the T newly added codes.
- the block performs soft information update together, and obtains S updated information blocks, and uses the S block updated information block as a new second information block; and the T+1 to 2T block information in the third information block.
- decoding the previous ST block information in the new second information block to obtain a new third information block, and outputting the previous T block information as the output of the decoder.
- the update module 602 when the first information block is updated by the initial S code blocks in the address code to obtain the first information block, the update module 602 includes: an update unit, configured to perform the initial S code blocks Bi.
- the first information block is obtained by updating the soft information in a manner of N 1 _itr iterations, where 1 ⁇ i ⁇ S, and N 1 _itr is an integer greater than 0.
- the original input data of the decoder, R i n is n times of iterative soft information corresponding to B i , W i n is the outer information obtained by the code block [B i-1 T B i ], and A i n is reliable for external information
- the degree factor is in the range of (0,1), A i-1 n takes a value of 1, and A i n takes the value n/N 1 _itr.
- N 1 _itr supports register configurable.
- the decoding module 604 includes one of the following: a hard decoding unit configured to hard decode the first T coding blocks of the first information block and the first ST coding blocks of the second information block to obtain the third information. And a soft decoding unit configured to soft decode the first T coding blocks of the first information block and the first ST coding blocks of the second information block to obtain a third information block.
- the obtained soft information is hard-cased by determining the sign bit as 0 bit or 1 bit by matching the sign bit of the element in the obtained soft information with the encoding rule.
- N 2 _itr decoding process when the N 2 _itr decoding process is repeatedly performed, when the block code has an extended parity bit, the previous N 3 _itr iterations will not satisfy the (2m, 2m-r) packet of the parity bit.
- the code decoding result is iterated, the recovery group code is used to decode the current input data, the subsequent iteration does not perform the check bit detection, and the decoding result is XORed to obtain the check digit, wherein the range of N 3 _itr is [1, N 2 _itr], N 2 _itr is an integer greater than 0.
- the current code word sequence is restored to the original input data.
- N 2 _itr , N 2 _itr an integer greater than 0; by The following method hardly judges the soft information obtained by the output processing: the symbol bit is determined to be 0 bit or 1 bit by matching the sign bit of the element in the obtained soft information with the encoding rule.
- the obtained previous T block data is determined as a third information block and is output as a decoder.
- the processing module 606 when ST information blocks are selected from the second information block or the third information block, the processing module 606 is configured to perform the following operations: when the first T coding blocks and the second information for the first information block When the first ST coding blocks of the block are hard-decoded to obtain the third information block, the ST information blocks are selected by: deleting the first T-block data in the second information block to obtain ST information blocks; or, selecting the second information block; The 2T+1 block and the following N_bh block in the information block are spliced together with the original input data corresponding to the T+N_bh+2 to the S-th block soft information in the second information block, as ST information blocks, where The value of N_bh is [0, ST-1].
- the ST information blocks are selected by: selecting the third information block from the third information block.
- R i n is the n-th iterative soft information output corresponding to B i
- W i n is obtained by [B i-1 T B i ] code block External information.
- the following describes the application in combination with a specific application scenario, and respectively describes a high-performance staircase soft decoding method and decoder device applied to a long haul scenario, and is applied to a metro/data center interconnection (metro/DCI).
- the low-power staircase soft decoding method and decoder device of the scene, and the hard decoding method and decoder device for short-distance transmission scene interconnection are described.
- a high performance staircase soft decoding process applied to a long haul scenario is provided in the first exemplary embodiment of the present application.
- the net coding gain requirement for FEC is very high.
- the number of iterations N 1 _itr and N 2 _itr can be configured to a larger value according to system requirements. Includes steps 1 through 6.
- step 1 the soft information is updated for the initial S B i blocks, B 0 , B 1 , ... B T-1 , B T , ... B S-1 . , B 0 1 , B 1 1 , ... B T-1 1 , B T 1 , . . . B S-1 1 are obtained .
- the parameters S and T respectively represent the number of data blocks per soft decoding and the number of new data blocks added in the next decoding, and the support registers can be matched.
- the steps of soft information update include steps 1 to 3.
- a i n is the reliability factor of the external information, and the value ranges from (0, 1), A 0 0 takes the value 1, and A 1 0 takes the smaller value.
- a i n is greater than or equal to A i n-1
- N 1 _itr supports register configurable.
- step two the soft information B T 1 , ... B S-1 1 obtained in step one and the newly added data blocks B S , B S+1 , ... B S+ T-1 updates the soft information to obtain B T 2 , ... B S-1 2 , B S 1 , B S+1 1 , ... B S+T-1 1 .
- the soft information update includes steps 1 to 4.
- a i n is greater than or equal to A i n-1 .
- ....B S-1 2 performs soft decoding and normalizes to obtain B 0 2 , B 1 2 , ... B T-1 2 , B T 2 , ... B S-1 2 .
- the data of B 0 2 , B 1 2 , ... B T-1 2 is output to obtain a decoder output result. Divided into steps 1 to 5.
- W i n is the external information obtained by the [B i-1 T B i ] code block, and A i 0 is the reliability factor of the external information, and the value range is (0, 1), and A i-1 0 is greater than or equal to A i 0 .
- step 2 the soft information is updated for the S B i block data obtained in step 1.
- step 4 the soft information obtained in step 3 is hard-sent.
- the hard-scoring method is to take the sign bit of the corresponding symbol, corresponding to the coding rule, and determine the sign bit as 0/1 bit.
- step 5 the pre-T block data obtained in step 4 is output as a decoder.
- step 4 the S-T block soft information is selected, and the new T block data is updated together with the soft information, and the soft information data after the S block update is obtained, and is divided into steps 1 and 2.
- step 2 the soft information is updated on the processing of steps 1 to 4 included in step 2.
- step 5 the T+1 to 2T block data obtained in the third step and the pre-S-T block data obtained in the fourth step are hard-decoded or soft-decoded together, and the pre-T block data is output as the output of the decoder.
- step 6 the steps 4 and 5 are repeatedly performed to obtain the T-stream data output by the decoder.
- a low power staircase soft decoding process applied to a metro/data center (metro/DCI) scenario is provided in the second embodiment of the present application.
- the power consumption and delay requirements of the FEC are very high under the premise of satisfying the net coding gain of the system.
- the number of iterations N 1 _itr and N 2 _itr can be based on System requirements are configured to smaller values, and the hard-rule staircase scheme with lower power consumption and latency can be used at the overlap. Specifically, it includes steps 1 to 6.
- step 1 the soft information is updated for the initial S B i blocks, B 0 , B 1 , ... B T-1 , B T , ... B S-1 . , B 0 1 , B 1 1 , ... B T-1 1 , B T 1 , ... B S-1 1 are obtained .
- the parameters S and T respectively represent the number of data blocks per soft decoding and the number of new data blocks added in the next decoding, and the support registers can be matched.
- the steps of soft information update are divided into steps 1 to 3.
- a i n is the reliability factor of the external information, and the value ranges from (0, 1), A 0 0 takes the value 1, and A 1 0 takes the smaller value.
- a i n is greater than or equal to A i n-1
- N 1 _itr supports register configurable.
- step two the soft information B T 1 , ... B S-1 1 obtained in step one and the newly added data blocks B S , B S+1 , ... B S+T -1 updates the soft information to obtain B T 2 , ... B S-1 2 , B S 1 , B S+1 1 , ... B S+T-1 1 .
- the soft information update is divided into steps 1 to 4.
- a i n is greater than or equal to A i n-1 .
- step three the soft information B 0 1 , B 1 1 , ... B T-1 1 obtained in step one and the soft information B T 2 , ... B S obtained in step two are obtained.
- -1 2 performs hard decoding to obtain B 0 2 , B 1 2 , ... B T-1 2 , B T 3 , ... B S-1 3 .
- the data of B 0 2 , B 1 2 , ... B T-1 2 are output to obtain a decoder output result, which is divided into steps 1 to 5.
- R i n is the n iteration output corresponding to B i
- R i n-1 is the n-1 iteration output corresponding to B i , that is, n iteration inputs.
- W i n is the outer information obtained by the [B i-1 T B i ] code block.
- step 2 the soft information obtained in step one is hard-sent, and the hard-sent method is to take the sign bit of the corresponding symbol, corresponding to the coding rule, and determine the sign bit as 0/1 bit.
- step 4 is repeated N 2 _itr times, and the final pre-T block data is output as a decoder.
- the N 2 _itr support register is configurable. When the block code has an extended check bit, the previous N 3 _itr iterations will not satisfy the (2m, 2m-r) block code decoding result iteration of the check bit, and the recovered block code decodes the current input data. Subsequent iterations do not perform check bit detection, but the decoded result is XORed to obtain a check bit.
- the N 3 _itr support register is configurable and has a value range of [1, N 2 _itr].
- step 5 in order to correct the decoder deadlock phenomenon, during the intermediate iteration of the decoder operation, when the packet decoder feeds back the error, the codeword sequence at this time is restored to the original input data. .
- step 4 the S-T block soft information is selected, and the new T block data is updated together with the soft information, and the soft information data after the S block update is obtained, and is divided into steps 1 and 2.
- step 1 the soft information obtained in step 2 is discarded as the pre-T block data as the ST block soft information; the data block obtained by hard decoding in step 3 may be selected, and the 2T+1 block and the subsequent N_bh block are selected. Then, the original input data corresponding to the soft information of the T+N_bh+2 to the Sth block obtained in the second step is spliced as the ST block soft information.
- N_bh has a value range of [0, S-T-1], and supports register configurable.
- step 2 the processing of steps 1 to 4 included in step 2 performs update of the soft information.
- step 5 the T+1 to 2T block data obtained in the third step and the pre-S-T block data obtained in S1008 are hard-decoded or soft-decoded together, and the pre-T block data is output as the output of the decoder.
- step 6 the steps 4 and 5 are repeatedly performed to obtain the T-stream data output by the decoder.
- a staircase hard decoding process for short-distance transmission scenario interconnection is provided.
- the FEC hard decision net coding gain requirement is very high, and the control of the error leveling phenomenon is more important.
- steps 1 through 6 can be performed.
- step 1 the initial S B i blocks, B 0 , B 1 , ... B T-1 , B T , ... B S-1 , are hard decoded to obtain B 0 1 , B 1 1 , ... B T-1 1 , B T 1 , ... B S-1 1 .
- the parameters S and T respectively represent the number of data blocks decoded each time and the number of new data blocks added in the next decoding, and the support registers can be matched.
- Step one includes steps 1 to 5.
- step 1 the S block data is hard-judged to obtain S hard-thought data blocks.
- steps 3 and 4 are repeated a total of N 1 _itr times to obtain final hard decision data.
- the N 1 _itr support register is configurable.
- step two the hard decision information B T 1 , ... B S-1 1 obtained in step one and the newly added data blocks B S , B S+1 , ... B S+ T-1 performs hard decoding to obtain B T 2 , ... B S-1 2 , B S 1 , B S+1 1 , ... B S+T-1 1 .
- the method is as in step one.
- B S-1 2 performs hard decoding to obtain B 0 2 , B 1 2 , ... B T-1 2 , B T 3 , ... B S-1 3 .
- the data of B 0 2 , B 1 2 , ... B T-1 2 is output to obtain a decoder decoding result.
- Step 3 includes steps 1 to 4.
- steps 1 and 2 are repeated a total of N 2 _itr times to obtain final decoded output data.
- the N 2 _itr support register is configurable.
- the previous iterations will iterate over the (2m, 2m-r) block code decoding result of the check bit, and restore the block code to decode the current input data.
- no check bit detection is performed, and the decoded result is XORed to obtain a check bit.
- step 4 in order to correct the decoder deadlock phenomenon, during the intermediate iteration of the decoder operation, when the packet decoder feeds back the error, the codeword sequence at this time is restored to the original input data. .
- step 4 the 2T+1 to 3T data block obtained in the third step is hard-coded together with the newly added T-block data.
- step 5 the T+1 to 2T block data after the soft decoding in step 3 and the S-T block data in the fourth step are hard decoded together, and the previous T block data is output as the output of the decoder.
- step 6 the steps 4 and 5 are repeatedly performed to obtain the T-stream data output by the decoder.
- the embodiment of the present application further provides a storage medium including a stored program, wherein the program runs to perform the method described in any of the above.
- the foregoing storage medium may include, but is not limited to, a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.
- ROM read-only memory
- RAM random access memory
- mobile hard disk a magnetic disk
- optical disk a variety of media that can store program code.
- Embodiments of the present application also provide a processor configured to execute a program, wherein the program executes the steps of any of the above methods when executed.
- the example examples in this embodiment may refer to the examples described in the foregoing embodiments and the optional embodiments, and details are not described herein again.
- the same code length and redundancy existing in the related art can be avoided, and the block code used in the staircase code is weaker than the block code used in the TPC code, and the error correction capability and the minimum distance characteristic are weakened.
- a reduction in the minimum distance may result in the occurrence of a bit error leveling phenomenon.
- the embodiments in the present application can reasonably and efficiently utilize the correlation between codewords to avoid the situation in the related art that there is no coding method capable of simultaneously applying hard coding and soft coding, thereby achieving better than the TPC code.
- the performance of the waterfall area, and the error leveling phenomenon is well controlled.
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Abstract
Description
Claims (14)
- 一种阶梯staircase码的解码方法,包括:对staircase码中的初始的S个编码块进行软信息的更新得到第一信息块,并将所述第一信息块的后S-T个编码块和T个新增加的编码块进行更新得到第二信息块,其中,S和T均为大于0的整数;对所述第一信息块的前T个编码块和所述第二信息块的前S-T个编码块进行解码得到第三信息块,输出前T块信息作为译码器输出;重复执行以下操作:从所述第二信息块或所述第三信息块中选取S-T个信息块,并对选取的所述S-T个信息块与T个新增加的编码块一并进行软信息的更新,得到S个更新后的信息块,并将所述S个更新后的信息块作为新的第二信息块;对所述第三信息块中的第T+1到2T块信息和所述新的第二信息块中的前S-T块信息一并进行解码得到新的第三信息块,输出前T块信息作为译码器的输出。
- 根据权利要求1所述的方法,其中,对staircase码中的初始的S个编码块进行软信息的更新得到第一信息块包括:通过对所述初始的S个编码块B i进行N 1_itr次迭代的方式进行软信息的更新得到所述第一信息块,其中,1≤i≤S,N 1_itr为大于0的整数。
- 根据权利要求2所述的方法,其中,通过对所述初始的S个编码块B i进行N 1_itr次迭代的方式进行软信息的更新包括:第一更新处理,所述第一更新处理为通过如下公式对码块[B i-1 T B i],i=1,进行软信息的更新:[R i-1 n,R i n]=[R i-1 0,R i 0]+[A i-1 n,A i n]×W i n,n=1,其中,R i 0为B i对应的译码器原始输入数据,R i n为B i对应的n次迭代软信息,W i n为码块[B i-1 T B i]求得的外信息,A i n为外信息的可靠度因子且取值范围为(0,1],A i-1 n取值为1,A i n取值为n/N 1_itr;第二更新处理,所述第二更新处理为通过如下公式对码块[R i-1 T B i],i=2,...S-1,进行软信息更新:[R i-1 n,R i n]=[R i-1 0,R i 0]+[A i-1 n,A i n]×W i n,n=1,其中,A i-1 n大于或等于A i n;对码块[R i-1 T R i],i=1,...S-1,重复进行所述第一更新处理和所述第二更新处理,其中,在重复执行的过程中n=2,...N 1_itr,A i n大于或等于A i n-1,N 1_itr支持寄存器可配置。
- 根据权利要求1所述的方法,其中,将所述第一信息块的后S-T个编码块和T个新增加的编码块进行更新得到第二信息块包括:第三更新处理,所述第三更新处理为通过如下公式对码块[R i-1 T R i],i=1,...S-T-1,进行软信息更新:[R i-1 n,R i n]=[R i-1 0,R i 0]+[A i-1 n,A i n]×W i n,n=1,其中,R i 0为编码块B i对应的译码器原始输入数据,R i n为B i对应的n次迭代软信息,W i n为码块[B i-1 T B i]求得的外信息,A i n为外信息的可靠度因子且取值范围为(0,1],A i-1 n取值为1,A i n取值为n/N 1_itr;第四更新处理,所述第四更新处理为通过如下公式对码块[R i-1 T B i],i=S-T,进行软信息更新:[R S-T-1 n,R S-T n]=[R S-T-1 0,R s-T 0]+[A S-T-1 n,A S-T n]×W i n-1,n=1;第五更新处理,所述第五更新处理为通过如下公式对码块[B i-1 T B i],i=S-T+1,...S-T-1,进行软信息更新:[R i-1 n,R i n]=[R i-1 0,R i 0]+[A i-1 n,A i n]×W i n,n=1;重复执行所述第三更新处理,所述第四更新处理以及所述第五更新处理得到所述第二信息块,其中A i n大于或等于A i n-1,在重复执行的过程中n=2,...N 1_itr。
- 根据权利要求1所述的方法,其中,对所述第一信息块的前T个编码块和所述第二信息块的前S-T个编码块进行解码得到第三信息块包括以下之一:对所述第一信息块的前T个编码块和所述第二信息块的前S-T个编码块进行硬解码得到所述第三信息块;以及对所述第一信息块的前T个编码块和所述第二信息块的前S-T个编码块进行软解码得到所述第三信息块。
- 根据权利要求5所述的方法,其中,对所述第一信息块的前T个编码块和所述第二信息块的前S-T个编码块进行硬解码得到所述第三信息块包括:通过如下公式得到所述第一信息块和所述第二信息块的软信息:[R i-1 n,R i n]=[R i-1 n-1,R i n-1]+W i n,n=N 1_itr,其中,R i n为编码块B i对应的n次迭代软信息,W i n为码块[B i-1 T B i]求得的外信息;通过如下方式对得到的软信息进行硬判:通过将得到的所述软信息中的元素的符号位与编码规则相对应的方式,将符号位判决为0比特或1比特;通过如下方式进行译码处理:逐次对S-1个[B i-1 T B i],对应的硬判结果,进行(2m,2m-r)分组码译码,其中,i=2,...S;重复执行N 2_itr次所述译码处理,并将译码后的S块数据确定为所述第三信息块,并将前T块数据作为译码器的输出。
- 根据权利要求6所述的方法,其中,在重复执行N 2_itr次所述译码处理时,当分组码带有扩展校验位时,前面N 3_itr次迭代将不满足校验位的(2m,2m-r)分组码译码结果迭代,恢复成分组码译码当前输入数据,后面的迭代不进行校验位检测,并将译码结果异或模2,得到校验位,其中,N 3_itr取值范围为[1,N 2_itr],N 2_itr为大于0的整数。
- 根据权利要求6所述的方法,其中,在重复执行N 2_itr次所述译码处理的过程中,当处理所述译码处理的分组译码器反馈纠正错误时,将当前的码字序列恢复成最原始的输入数据。
- 根据权利要求5所述的方法其中,对所述第一信息块的前T个编码块和所述第二信息块的前S-T个编码块进行软解码得到所述第三信息块包括:在对所述第一信息块和所述第二信息块进行归一化处理后,通过如下公式得到所述第一信息块和所述第二信息块的软信息:[R i-1 n,R i n]=[R i-1 0,R i 0]+[A i-1 n,A i n]×W i n,n=N 1_itr,其中,R i 0为编码块B i对应的译码器原始输入数据,R i n为B i对应的n次迭代软信息,W i n为码块[B i-1 T B i]求得的外信息,A i n为外信息的可靠度因子且取值范围为(0,1],A i-1 n取值为1,A i n取值为(n-1)/N 1_itr;重复执行输出处理,其中,在重复执行的过程中n=2,...N 2_itr,其中,N 2_itr为大于0的整数;在进行最后一次迭代时,执行如下输出处理:按照如下公式得到译码器的软信息输出:[R i-1 n,R i n]=[R i-1 n-1,R i n-1]+W i n,n=N 2_itr;通过如下方式对通过输出处理得到的软信息进行硬判:通过将得到的软信息中的元素的符号位与编码规则相对应的方式,将符号位判决为0比特或1比特;将经过硬判处理后得到的前T块数据确定为所述第三信息块,并作为译码器输出。
- 根据权利要求1所述的方法,其中,从所述第二信息块或所述第三信息块中选取S-T个信息块包括:当对所述第一信息块的前T个编码块和所述第二信息块的前S-T个编码块 进行硬解码得到所述第三信息块时,通过如下方式选取S-T个信息块:将所述第二信息块中的前T块数据丢掉,得到所述S-T个信息块;或者,选取所述第三信息块中第2T+1块及其后的N_bh块,再拼接所述第二信息块中的第T+N_bh+2到第S块软信息所对应的原始输入数据,作为所述S-T个信息块,其中,N_bh取值范围为[0,S-T-1];当对所述第一信息块的前T个编码块和所述第二信息块的前S-T个编码块进行软解码得到所述第三信息块时,通过如下方式选取S-T个信息块:从所述第三信息块中选取第2T+1到第S+T块数据作为所述S-T个信息块,生成方法为:[R i-1 n,Ri n]=[R i-1 0,R i 0]+[A i-1 n,A i n]×W i n,n=N 2_itr,其中,R i n为B i对应的n次迭代软信息输出,W i n为[B i-1 T B i]码块所求得的外信息。
- 一种阶梯staircase码的解码装置,包括:更新模块,设置为对staircase码中的初始的S个编码块进行软信息的更新得到第一信息块,并将所述第一信息块的后S-T个编码块和T个新增加的编码块进行更新得到第二信息块,其中,S和T均为大于0的整数;解码模块,设置为对所述第一信息块的前T个编码块和所述第二信息块的前S-T个编码块进行解码得到第三信息块,输出前T块信息作为译码器输出;处理模块,设置为重复执行以下操作:从所述第二信息块或所述第三信息块中选取S-T个信息块,并对选取的所述S-T个信息块与T个新增加的编码块一并进行软信息的更新,得到S个更新后的信息块,并将所述S个更新后的信息块作为新的第二信息块;对所述第三信息块中的第T+1到2T个块信息和所述新的第二信息块中的前S-T块信息一并进行解码得到新的第三信息块,输出前T块信息作为译码器的输出。
- 根据权利要求11所述的装置,其中,在对staircase码中的初始的S个编码块进行软信息的更新得到第一信息块时,所述更新模块包括:更新单元,设置为通过对所述初始的S个编码块B i进行N 1_itr次迭代的方式进行软信息的更新得到所述第一信息块,其中,1≤i≤S,N 1_itr为大于0的整数。
- 一种存储介质,所述存储介质包括存储的程序,其中,所述程序运行时执行权利要求1至10中任一项所述的方法。
- 一种处理器,所述处理器设置为运行程序,所述程序运行时执行权利要求1至10中任一项所述的方法。
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CN201711133350.5A CN109787641B (zh) | 2017-11-15 | 2017-11-15 | staircase码的解码方法、装置及存储介质 |
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CN114079539B (zh) * | 2021-07-28 | 2023-11-28 | 珠海市杰理科技股份有限公司 | 一种无线信息交流方法及无线通信设备 |
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US20210175908A1 (en) | 2021-06-10 |
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