JP6446730B2 - データをデコードするための方法およびデコーダ - Google Patents
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- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0047—Decoding adapted to other signal detection operation
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- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
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- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
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- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1108—Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
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- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
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- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
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- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
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- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
- H03M13/4138—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors soft-output Viterbi algorithm based decoding, i.e. Viterbi decoding with weighted decisions
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- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0052—Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
Description
本開示は、米国特許法第119条(e)による、2013年3月7日に出願された、米国仮出願第61/774、167による利益を主張し、参照により本明細書にその全体が組み込まれる。
Claims (18)
- データをデコードするための方法であって、
第1の時点において、可変ノードのための可変ノード値を受信する段階と、
第2の時点において、前記可変ノードのための信頼性データを受信する段階と、
更新された可変ノード値を生成すべく、前記第1の時点の後および前記第2の時点の前に、第1のデコードスキームを使用して、前記可変ノードをデコードする段階と、
前記第2の時点の後、前記第1のデコードスキームとは異なる第2のデコードスキームを使用して、前記更新された可変ノード値に基づいて前記可変ノードをデコードする段階と、を備え、
前記第1のデコードスキームは、前記可変ノード値に基づく硬デコードスキームであり、前記第2のデコードスキームは、前記更新された可変ノード値および前記信頼性データに基づく軟デコードスキームである、方法。 - 前記第2の時点より後、第3の時点において、前記可変ノードのための追加の信頼性データを受信する段階と、
前記第3の時点の後、第3のデコードスキームを使用して前記可変ノードをデコードする段階と、をさらに備える、請求項1に記載の方法。 - 前記可変ノードのための前記可変ノード値を受信する段階は、メモリに対し、読み取り動作を実行する命令を送信することを含む、請求項1または2に記載の方法。
- 前記可変ノードのための前記信頼性データを受信する段階は、前記メモリに対し、1または複数の追加の読み取り動作を実行する命令を送信することを含む、請求項3に記載の方法。
- 前記メモリは、NANDフラッシュメモリである請求項3に記載の方法。
- 前記第1のデコードスキームの結果をバッファに格納する段階をさらに備え、
前記第2のデコードスキームを使用して、前記可変ノードをデコードする段階は、前記バッファからの前記第1のデコードスキームの前記結果を取得する段階を含み、前記結果は前記更新された可能ノード値を含む、請求項1から5のいずれか一項に記載の方法。 - 前記第1のデコードスキームが成功したことを判断する段階と、
前記第2の時点の前に、前記デコードする段階を終了する段階と、をさらに備える、請求項1から6のいずれか一項に記載の方法。 - 前記第2の時点において、前記信頼性データを受信する段階および前記第2のデコードスキームを使用して、前記可変ノードをデコードする段階は、前記第1のデコードスキームが成功しないことの判断に応答して実行される、請求項1から7のいずれか一項に記載の方法。
- 1または複数の可変ノード値は、更新された複数の可変ノード値のどの組み合わせが最も満足されないチェックノード数を減少するかに基づいて選択的に更新される、請求項1から8のいずれか一項に記載の方法。
- 第1の時点において、可変ノードのための可変ノード値を受信し、
第2の時点において、前記可変ノードのための信頼性データを受信し、
更新された可変ノード値を生成すべく、前記第1の時点の後および前記第2の時点の前に、第1のデコードスキームを使用して、前記可変ノードをデコードし、
前記第2の時点の後、前記第1のデコードスキームとは異なる第2のデコードスキームを使用して、前記更新された可変ノード値に基づいて前記可変ノードをデコードする、デコード回路を備え、
前記第1のデコードスキームは、前記可変ノード値に基づく硬デコードスキームであり、前記第2のデコードスキームは、前記更新された可変ノード値および前記信頼性データに基づく軟デコードスキームである、デコーダ。 - 前記デコード回路はさらに、
前記第2の時点より後、第3の時点において、前記可変ノードのための追加の信頼性データを受信し、
前記第3の時点の後、第3のデコードスキームを使用して前記可変ノードをデコードする、請求項10に記載のデコーダ。 - 前記デコード回路は、メモリに対し、読み取り動作を実行する命令を送信することによって、前記可変ノードのための前記可変ノード値を受信する、請求項10または11に記載のデコーダ。
- 前記デコード回路は、前記メモリに対し、1または複数の追加の読み取り動作を実行する命令を送信することによって、前記可変ノードのための前記信頼性データを受信する、請求項12に記載のデコーダ。
- 前記メモリは、NANDフラッシュメモリである、請求項12に記載のデコーダ。
- 前記デコード回路はさらに、前記第1のデコードスキームの結果をバッファに格納し、
前記デコード回路は、前記バッファからの前記第1のデコードスキームの前記結果を取得することによって、前記第2のデコードスキームを使用して、前記可変ノードをデコードし、前記結果は前記更新された可能ノード値を含む、請求項10から14のいずれか一項に記載のデコーダ。 - 前記デコード回路はさらに、
前記第1のデコードスキームが成功したことを判断し、
前記第2の時点の前に、前記デコードすることを終了する、請求項10から15のいずれか一項に記載のデコーダ。 - 前記デコード回路は、前記第1のデコードスキームが成功しないことの判断に応答して、前記第2の時点において、前記信頼性データを受信し、前記第2のデコードスキームを使用して、前記可変ノードをデコードする、請求項10から16のいずれか一項に記載のデコーダ。
- 1または複数の可変ノード値は、更新された複数の可変ノード値のどの組み合わせが最も満足されないチェックノード数を減少するかに基づいて選択的に更新される、請求項10から17のいずれか一項に記載のデコーダ。
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US14/197,408 | 2014-03-05 | ||
US14/197,408 US9369152B2 (en) | 2013-03-07 | 2014-03-05 | Systems and methods for decoding with late reliability information |
PCT/US2014/020775 WO2014138246A1 (en) | 2013-03-07 | 2014-03-05 | Systems and methods for decoding with late reliability information |
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US9369152B2 (en) | 2016-06-14 |
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