CN105247808B - 使用后期可靠性信息进行解码的系统和方法 - Google Patents
使用后期可靠性信息进行解码的系统和方法 Download PDFInfo
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- CN105247808B CN105247808B CN201480011709.XA CN201480011709A CN105247808B CN 105247808 B CN105247808 B CN 105247808B CN 201480011709 A CN201480011709 A CN 201480011709A CN 105247808 B CN105247808 B CN 105247808B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1108—Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/3707—Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
- H03M13/4138—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors soft-output Viterbi algorithm based decoding, i.e. Viterbi decoding with weighted decisions
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0047—Decoding adapted to other signal detection operation
- H04L1/005—Iterative decoding, including iteration between signal detection and decoding operation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0052—Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Probability & Statistics with Applications (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Mathematical Physics (AREA)
- Quality & Reliability (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Error Detection And Correction (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
Description
Claims (20)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US201361774167P | 2013-03-07 | 2013-03-07 | |
US61/774,167 | 2013-03-07 | ||
PCT/US2014/020775 WO2014138246A1 (en) | 2013-03-07 | 2014-03-05 | Systems and methods for decoding with late reliability information |
Publications (2)
Publication Number | Publication Date |
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CN105247808A CN105247808A (zh) | 2016-01-13 |
CN105247808B true CN105247808B (zh) | 2019-03-22 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201480011709.XA Active CN105247808B (zh) | 2013-03-07 | 2014-03-05 | 使用后期可靠性信息进行解码的系统和方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US9369152B2 (zh) |
JP (1) | JP6446730B2 (zh) |
KR (1) | KR20150128750A (zh) |
CN (1) | CN105247808B (zh) |
WO (1) | WO2014138246A1 (zh) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9467170B2 (en) * | 2013-05-17 | 2016-10-11 | Marvell World Trade Ltd. | NAND flash memory systems with efficient soft information interface |
KR102110767B1 (ko) * | 2013-12-24 | 2020-06-09 | 삼성전자 주식회사 | 메모리 컨트롤러 구동방법 및 메모리 컨트롤러 |
US10084481B2 (en) | 2014-12-18 | 2018-09-25 | Apple Inc. | GLDPC soft decoding with hard decision inputs |
US10484129B2 (en) * | 2016-01-21 | 2019-11-19 | Qualcomm Incorporated | Protocol layer packet coding for transmitter/receiver buffer optimization |
CN105897277B (zh) * | 2016-03-28 | 2019-06-14 | 北京交大思诺科技股份有限公司 | 解码器解码性能分析方法及装置 |
TWI594255B (zh) * | 2016-07-01 | 2017-08-01 | 群聯電子股份有限公司 | 解碼方法、記憶體控制電路單元及記憶體儲存裝置 |
CN107590018B (zh) * | 2016-07-07 | 2020-12-01 | 群联电子股份有限公司 | 译码方法、存储器控制电路单元及存储器存储装置 |
TWI670715B (zh) * | 2017-04-06 | 2019-09-01 | 群聯電子股份有限公司 | 解碼方法、記憶體儲存裝置及記憶體控制電路單元 |
US10707899B2 (en) | 2017-08-31 | 2020-07-07 | SK Hynix Inc. | Bit-flipping decoder for G-LDPC codes with syndrome-decoding for component codes |
US10511326B2 (en) * | 2017-11-14 | 2019-12-17 | Nyquist Semiconductor Limited | Systems and methods for decoding error correcting codes |
US10491244B2 (en) * | 2017-11-14 | 2019-11-26 | Nyquist Semiconductor Limited | Systems and methods for decoding error correcting codes |
KR20200020535A (ko) * | 2018-08-17 | 2020-02-26 | 에스케이하이닉스 주식회사 | 에러 정정 장치, 그것의 동작 방법 및 그것을 포함하는 전자 장치 |
KR20200022136A (ko) * | 2018-08-22 | 2020-03-03 | 에스케이하이닉스 주식회사 | 에러 정정 장치 및 그것을 포함하는 전자 장치 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1713531A (zh) * | 2004-06-23 | 2005-12-28 | 株式会社东芝 | 解码用ldpc码编码的数据的解码装置和方法 |
Family Cites Families (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1605624B1 (en) | 2003-03-20 | 2012-07-25 | Fujitsu Limited | Error controller |
US7441178B2 (en) * | 2005-02-24 | 2008-10-21 | Keyeye Communications | Low complexity decoding of low density parity check codes |
US7587657B2 (en) | 2005-04-29 | 2009-09-08 | Agere Systems Inc. | Method and apparatus for iterative error-erasure decoding |
WO2009072103A2 (en) * | 2007-12-05 | 2009-06-11 | Densbits Technologies Ltd. | Flash memory apparatus and methods using a plurality of decoding stages including optional use of concatenated bch codes and/or designation of 'first below' cells |
US8312354B1 (en) * | 2007-12-27 | 2012-11-13 | Marvell International Ltd. | Method and apparatus for improved performance of iterative decoders on channels with memory |
KR101436505B1 (ko) * | 2008-01-03 | 2014-09-02 | 삼성전자주식회사 | 메모리 장치 |
US8230312B1 (en) * | 2008-01-09 | 2012-07-24 | Marvell International Ltd. | Iterative decoder memory arrangement |
KR101425020B1 (ko) * | 2008-03-17 | 2014-08-04 | 삼성전자주식회사 | 메모리 장치 및 데이터 판정 방법 |
US20100037121A1 (en) | 2008-08-05 | 2010-02-11 | The Hong Kong University Of Science And Technology | Low power layered decoding for low density parity check decoders |
US8291285B1 (en) * | 2008-09-18 | 2012-10-16 | Marvell International Ltd. | Circulant processing scheduler for layered LDPC decoder |
KR101466270B1 (ko) | 2008-09-19 | 2014-11-28 | 삼성전자주식회사 | 비휘발성 메모리 시스템 및 그것의 데이터 처리 방법 |
KR101535225B1 (ko) * | 2009-01-06 | 2015-07-09 | 삼성전자주식회사 | 디코딩 방법 및 그 방법을 이용하는 메모리 시스템 장치 |
US8560917B2 (en) | 2009-01-27 | 2013-10-15 | International Business Machines Corporation | Systems and methods for efficient low density parity check (LDPC) decoding |
US8443267B2 (en) | 2009-04-28 | 2013-05-14 | Lsi Corporation | Systems and methods for hard decision assisted decoding |
US8438461B2 (en) * | 2009-10-12 | 2013-05-07 | Marvell World Trade Ltd. | Power consumption in LDPC decoder for low-power applications |
US8504887B1 (en) * | 2009-12-24 | 2013-08-06 | Marvell International Ltd. | Low power LDPC decoding under defects/erasures/puncturing |
US8572463B2 (en) * | 2010-02-01 | 2013-10-29 | Sk Hynix Memory Solutions Inc. | Quasi-cyclic LDPC encoding and decoding for non-integer multiples of circulant size |
EP2545554A4 (en) | 2010-03-12 | 2015-03-11 | Lsi Corp | LDPC CLEARANCE DECODING FOR FLASH MEMORY |
US8341486B2 (en) | 2010-03-31 | 2012-12-25 | Silicon Laboratories Inc. | Reducing power consumption in an iterative decoder |
US8627175B2 (en) * | 2010-09-27 | 2014-01-07 | Seagate Technology Llc | Opportunistic decoding in memory systems |
US20120240007A1 (en) * | 2010-10-20 | 2012-09-20 | Stec, Inc. | Ldpc decoding for solid state storage devices |
US8694868B1 (en) * | 2010-10-21 | 2014-04-08 | Marvell International Ltd. | Systems and methods for performing multi-state bit flipping in an LDPC decoder |
KR101792868B1 (ko) * | 2010-11-25 | 2017-11-02 | 삼성전자주식회사 | 플래시 메모리 장치 및 그것의 읽기 방법 |
JP2012181761A (ja) | 2011-03-02 | 2012-09-20 | Toshiba Corp | 半導体メモリ装置および復号方法 |
US8806309B2 (en) | 2011-06-13 | 2014-08-12 | Silicon Motion Inc. | Method for controlling message-passing algorithm based decoding operation by referring to statistics data of syndromes of executed iterations and related control apparatus thereof |
US8938660B1 (en) * | 2011-10-10 | 2015-01-20 | Marvell International Ltd. | Systems and methods for detection and correction of error floor events in iterative systems |
US8910028B1 (en) * | 2011-10-27 | 2014-12-09 | Marvell International Ltd. | Implementation of LLR biasing method in non-binary iterative decoding |
US9009578B1 (en) * | 2011-11-11 | 2015-04-14 | Marvell International Ltd. | Methodology for improved bit-flipping decoder in 1-read and 2-read scenarios |
US8819515B2 (en) | 2011-12-30 | 2014-08-26 | Lsi Corporation | Mixed domain FFT-based non-binary LDPC decoder |
KR101968746B1 (ko) * | 2011-12-30 | 2019-04-15 | 삼성전자주식회사 | 저장 장치로부터 데이터를 읽는 읽기 방법, 에러 정정 장치, 그리고 에러 정정 코드 디코더를 포함하는 저장 시스템 |
US8739004B2 (en) | 2012-05-10 | 2014-05-27 | Lsi Corporation | Symbol flipping LDPC decoding system |
US9612903B2 (en) | 2012-10-11 | 2017-04-04 | Micron Technology, Inc. | Updating reliability data with a variable node and check nodes |
US8996969B2 (en) * | 2012-12-08 | 2015-03-31 | Lsi Corporation | Low density parity check decoder with miscorrection handling |
US9083383B1 (en) | 2013-01-29 | 2015-07-14 | Xilinx, Inc. | Parity check matrix |
US9124300B2 (en) * | 2013-02-28 | 2015-09-01 | Sandisk Technologies Inc. | Error correction coding in non-volatile memory |
KR102349209B1 (ko) * | 2013-03-21 | 2022-01-10 | 마벨 월드 트레이드 리미티드 | 멀티-스테이지 소프트 입력 디코딩을 위한 방법 및 시스템 |
US20150169406A1 (en) * | 2013-12-16 | 2015-06-18 | Sandisk Technologies Inc. | Decoding techniques for a data storage device |
KR20150091693A (ko) * | 2014-02-03 | 2015-08-12 | 삼성전자주식회사 | 플래쉬 메모리 읽기 방법 |
-
2014
- 2014-03-05 US US14/197,408 patent/US9369152B2/en active Active
- 2014-03-05 CN CN201480011709.XA patent/CN105247808B/zh active Active
- 2014-03-05 WO PCT/US2014/020775 patent/WO2014138246A1/en active Application Filing
- 2014-03-05 KR KR1020157026504A patent/KR20150128750A/ko not_active IP Right Cessation
- 2014-03-05 JP JP2015561611A patent/JP6446730B2/ja active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1713531A (zh) * | 2004-06-23 | 2005-12-28 | 株式会社东芝 | 解码用ldpc码编码的数据的解码装置和方法 |
Also Published As
Publication number | Publication date |
---|---|
CN105247808A (zh) | 2016-01-13 |
US20140258809A1 (en) | 2014-09-11 |
JP6446730B2 (ja) | 2019-01-09 |
US9369152B2 (en) | 2016-06-14 |
JP2016514428A (ja) | 2016-05-19 |
WO2014138246A1 (en) | 2014-09-12 |
KR20150128750A (ko) | 2015-11-18 |
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Effective date of registration: 20200426 Address after: Singapore City Patentee after: Marvell Asia Pte. Ltd. Address before: Ford street, Grand Cayman, Cayman Islands Patentee before: Kaiwei international Co. Effective date of registration: 20200426 Address after: Ford street, Grand Cayman, Cayman Islands Patentee after: Kaiwei international Co. Address before: Hamilton, Bermuda Patentee before: Marvell International Ltd. Effective date of registration: 20200426 Address after: Hamilton, Bermuda Patentee after: Marvell International Ltd. Address before: Babado J San Mega Le Patentee before: MARVELL WORLD TRADE Ltd. |