WO2017067203A1 - 共用协议层的多通道显示接口信号生成系统及方法 - Google Patents

共用协议层的多通道显示接口信号生成系统及方法 Download PDF

Info

Publication number
WO2017067203A1
WO2017067203A1 PCT/CN2016/087209 CN2016087209W WO2017067203A1 WO 2017067203 A1 WO2017067203 A1 WO 2017067203A1 CN 2016087209 W CN2016087209 W CN 2016087209W WO 2017067203 A1 WO2017067203 A1 WO 2017067203A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
channel
interface
test sequence
data packet
Prior art date
Application number
PCT/CN2016/087209
Other languages
English (en)
French (fr)
Chinese (zh)
Inventor
郑增强
许恩
欧昌东
许笛
帅敏
邓标华
Original Assignee
武汉精测电子技术股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉精测电子技术股份有限公司 filed Critical 武汉精测电子技术股份有限公司
Priority to JP2018520165A priority Critical patent/JP6592596B2/ja
Priority to KR1020187014464A priority patent/KR102070533B1/ko
Publication of WO2017067203A1 publication Critical patent/WO2017067203A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/10—Use of a protocol of communication by packets in interfaces along the display data pipeline

Definitions

  • the present invention relates to the field of display and test of a liquid crystal module of a DP (DisplayPort display interface) interface, and in particular, to a multi-channel display interface signal generation system and method sharing a protocol layer.
  • DP DisplayPort display interface
  • the traditional LVDS (Low-Voltage Differential Signaling) interface cannot meet the size of small-sized LCD modules. Requirements for EMI (Electromagnetic Interference) and power consumption.
  • EMI Electromagnetic Interference
  • the reason why the traditional LVDS interface can not meet the above requirements is as follows: as the resolution increases, the bandwidth required for the signal increases accordingly, and the rate of each group of wires of the LVDS interface is low.
  • the ASIC proprietary chip can only support the output of the signal of the separate display interface. When generating the multi-channel display interface signal, multiple chips are needed, and multiple controllers are needed at the same time, which is large in size and high in power consumption.
  • the multi-channel display interface is implemented in the field programmable gate array, and the display interface encoder resource is occupied more, occupying the field programmable gate array FPGA resource area.
  • An object of the present invention is to provide a multi-channel display interface signal generating system and method sharing a protocol layer,
  • the system and method can reduce the occupation of the field programmable gate array logic resources, reduce the occupied area of the field programmable gate array resources, reduce the power consumption of the field programmable gate array, and improve the integration degree of the field programmable gate array.
  • a multi-channel display interface signal generating system of a shared protocol layer designed by the present invention includes a data group packet and control symbol generating unit, a data multiplexing unit, and a state monitoring and assembling unit, wherein the data group The signal output end of the packet and control symbol generating unit is connected to the signal input end of the state monitoring and assembling unit through the data multiplexing unit, the state monitoring and assembling unit includes a plurality of signal assembly channels, and the control signal communication end of the data multiplexing unit is used.
  • the data packet and control symbol generating unit is configured to generate data stream structure attribute information, a test sequence, and a frame control symbol required by the display interface protocol according to the received external image signal, And grouping the pixel data of the received external image signal according to the display interface protocol; the data multiplexing unit assembling the channel test state according to the signal acquired from the test state monitoring end of the corresponding signal assembly channel, and corresponding data stream structure attribute Information, test sequences, frame control symbols, and pixel data Assigning to a corresponding signal assembly channel in the state monitoring and assembly unit; the state monitoring and assembling unit is configured to receive the received data stream structure attribute information, the test sequence, the frame control symbol, and the pixel data packet according to the test state of each assembly channel Generate corresponding multi-channel display interface signals.
  • a multi-channel display interface signal generating method sharing a protocol layer includes the following steps:
  • Step 1 The data group packet and the control symbol generating unit receive external image information, and the data stream packet and the main data stream attribute generator of the control symbol generating unit generate data stream structure attribute information of the display interface protocol according to the external image information;
  • test sequence generation module generates various types of test sequences required for displaying the interface protocol according to the external image information
  • the frame control symbol generating module generates a frame control character of the display interface protocol according to the external image information
  • the pixel data packet module forms a corresponding data packet for the pixel data in the external image information according to the display interface protocol
  • Step 2 The data multiplexing unit assembles the channel test state information from the corresponding signal acquired by the test state monitoring end of each signal assembly channel, and according to the test state information, the corresponding data stream structure attribute information, the test sequence, the frame control character, and Pixel data packets are allocated to corresponding signal assembly channels in the state monitoring and assembly unit;
  • Step 3 Each auxiliary channel signal control and status monitoring module monitors an auxiliary channel of the corresponding liquid crystal display module a communication link test state of the signal communication end, the corresponding control unit assembles the data stream structure attribute information, the test sequence, the frame control character, and the pixel data packet under the rule of the display interface protocol according to the communication link state control signal assembly module, Finally, each signal assembly module generates a corresponding display interface signal, that is, the generation of the multi-channel display interface signal is completed.
  • the present invention Compared with the traditional multi-ASIC display chip to generate multi-channel display interface signals, the present invention only needs three data modules: a data packet and a control symbol generating unit, a data multiplexing unit, and a state monitoring and assembling unit. Small, low energy consumption, more suitable for testing small and medium size LCD modules.
  • the present invention adopts the data multiplexing unit for data distribution, so that the front end only needs to set one data group packet and the control symbol generating unit.
  • the logic resource occupation of the field programmable gate array is reduced, the integration degree of the display interface signal generation system is improved, and the liquid crystal module of more and more miniaturization can be better adapted.
  • Figure 1 is a block diagram showing the structure of the present invention.
  • 1 - data packet and control symbol generation unit 1.1 - main stream attribute generator, 1.2 - test sequence generation module, 1.3 - frame control symbol generation module, 1.4 - pixel data packet module, 2 - data multiplexing Unit, 3-state monitoring and assembly unit, 3.1-signal assembly module, 3.2-control unit, 3.3-auxiliary channel signal control and status monitoring module, 4-serial deserializer.
  • the multi-channel display interface signal generating system of the shared protocol layer as shown in FIG. 1 includes a data packet and control symbol generating unit 1, a data multiplexing unit 2, and a state monitoring and assembling unit 3, as described in FIG.
  • the signal output end of the data packet and control symbol generating unit 1 is connected to the signal input end of the state monitoring and assembling unit 3 through the data multiplexing unit 2.
  • the state monitoring and assembling unit 3 includes a plurality of signal assembly channels, and data multiplexing
  • the control signal communication end of unit 2 is used to connect the test state monitoring end of each signal assembly channel; the data group package and the control symbol are generated.
  • the unit 1 is configured to generate data stream structure attribute information, a test sequence, and a frame control symbol required by the display interface protocol according to the received external image signal, and group the pixel data of the received external image signal according to the display interface protocol;
  • the multiplexing unit 2 assembles the channel test state according to the signal acquired from the test state monitoring end of the corresponding signal assembly channel, and assigns the corresponding data stream structure attribute information, the test sequence, the frame control symbol, and the pixel data packet to the state monitoring and assembling unit 3 a corresponding signal assembly channel;
  • the state monitoring and assembling unit 3 is configured to generate the corresponding multi-channel display interface signal according to the test state of each assembly channel by the received data stream structure attribute information, the test sequence, the frame control character and the pixel data packet. .
  • each of the signal assembly channels in the state monitoring and assembling unit 3 includes a signal assembly module 3.1, a control unit 3.2, and an auxiliary channel signal control and status monitoring module 3.3, wherein the signal assembly module 3.1
  • the signal input end is connected to the signal output end corresponding to the data multiplexing unit 2, and the signal output end of the signal assembly module 3.1 is an output channel of the signal assembly channel, and the output channel of the signal assembly channel is used for connecting the high-speed data signal corresponding to the liquid crystal display module.
  • a hot plug detection (HPD, Hot Plug Detection) communication terminal, the auxiliary channel signal (AUX, Auxiliary) control and the first communication end of the state monitoring module 3.3 are connected to the auxiliary of the liquid crystal display module
  • the channel signal communication end (ie, the input end), the auxiliary channel signal control and the signal output end of the state monitoring module 3.3 are connected to the signal input end of the corresponding control unit 3.2, and the control signal output end of the control unit 3.2 is connected to the control end of the corresponding signal assembly module 3.1.
  • the auxiliary channel signal control and the test status monitoring terminal of the status monitoring module 3.3 are connected to the data.
  • the auxiliary channel signal control and status monitoring module 3.3 is responsible for communicating with the auxiliary channel signal communication terminal of the liquid crystal module and monitoring the state of the link.
  • the signal assembly module 3.1 is responsible for assembling the data from the data multiplexing unit 2 into display interface signals according to the state of the link.
  • the control unit 3.2 detects the state of the current link through the auxiliary channel signal control and status monitoring module 3.3, and the control signal assembly module 3.1 operates.
  • the data packet and control symbol generating unit 1 includes a main stream attribute generator 1.1 (MSA Gen, Main Stream Attribute Generator), a test sequence generating module 1.2 (TP Gen), and a frame control symbol generating module 1.3. (Frame Control Symbol Generator) and Pixel Packetizer, wherein the main stream attribute generator 1.1, the test sequence generation module 1.2, the frame control symbol generation module 1.3, and the pixel data packet module 1.4
  • the signal input terminal can receive external image signals, the main data stream attribute generator 1.1, the test sequence generation module 1.2, the frame control symbol generation module 1.3, and the pixel data group package module 1.4.
  • the signal output terminal is connected to the signal input terminal of the data multiplexing unit 2.
  • the output channels of each of the signal assembly channels are connected with corresponding serial deserializers 4 (SERDES), and the output channels of each signal assembly channel are connected by corresponding serial deserializers 4 High-speed data signal and hot-swap detection signal communication terminal of the liquid crystal display module.
  • the serial deserializer 4 is used to convert the encoded parallel data into serial data output.
  • a multi-channel display interface signal generating method sharing a protocol layer includes the following steps:
  • Step 1 The data packet and control symbol generating unit 1 receives external image information, which may be generated by a video signal generator, or may be through a TTL signal (transistor transistor logic) or an LVDS signal or MIPI signal (Mobile Industry Processor Interface) or VX1 signal (V-By-One, digital interface standard dedicated to image transmission) demodulated, the data packet and control symbol generating unit 1 main
  • the data stream attribute generator 1.1 generates data stream structure attribute information of the display interface protocol according to the external image information;
  • test sequence generation module 1.2 generates various types of test sequences required for displaying the interface protocol according to the external image information
  • the frame control symbol generating module 1.3 generates a frame control character of the display interface protocol according to the external image information
  • the pixel data group packet module 1.4 forms a corresponding data packet for the pixel data in the external image information according to the display interface protocol;
  • Step 2 The data multiplexing unit 2 assembles the channel test state information from the corresponding signal obtained by the test state monitoring end of each signal assembly channel, and according to the test state information, the corresponding data stream structure attribute information, the test sequence, and the frame control character. And the pixel data packet is allocated to the corresponding signal assembly channel in the state monitoring and assembling unit 3;
  • Step 3 Each auxiliary channel signal control and status monitoring module 3.3 monitors the communication link test status of the auxiliary channel signal communication end of the corresponding liquid crystal display module, and the corresponding control unit 3.2 assembles the module 3.1 pair data according to the communication link state control signal.
  • the stream structure attribute information, the test sequence, the frame control character and the pixel data packet are assembled under the rules of the display interface protocol, and finally each signal assembly module 3.1 generates a corresponding display interface signal, that is, the generation of the multi-channel display interface signal is completed.
  • the data stream structure attribute information includes a position parameter between the field synchronization signal, the line synchronization signal, and the data valid signal.
  • the position parameters between the field sync signal, the line sync signal and the data valid signal include a front shoulder, a back shoulder, a pulse width, and a field blanking and line blanking parameter.
  • the frame control character includes a blank start control (BS, Blank Start), a blank end control (BE, Blank End), and a video frame start control (FS, Frame Start). And the video frame end control character (FE, Frame End).
  • BS blank start control
  • BE blank End
  • FS video frame start control
  • FE Frame End
  • the communication link test state of the auxiliary channel signal communication end of the liquid crystal display module includes a recovery clock training state, a symbol alignment training state, and a video mode state.
  • the test sequence in step 1 of the above technical solution includes a recovery clock training test sequence and a symbol alignment training test sequence.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Controls And Circuits For Display Device (AREA)
PCT/CN2016/087209 2015-10-23 2016-06-27 共用协议层的多通道显示接口信号生成系统及方法 WO2017067203A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2018520165A JP6592596B2 (ja) 2015-10-23 2016-06-27 共有プロトコル層マルチチャンネル表示インタフェース信号生成システム及び方法
KR1020187014464A KR102070533B1 (ko) 2015-10-23 2016-06-27 공유 프로토콜 계층의 멀티 채널 디스플레이 인터페이스 신호의 생성 시스템

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510700176.2 2015-10-23
CN201510700176.2A CN105427772B (zh) 2015-10-23 2015-10-23 共用协议层的多通道显示接口信号生成系统及方法

Publications (1)

Publication Number Publication Date
WO2017067203A1 true WO2017067203A1 (zh) 2017-04-27

Family

ID=55505943

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/087209 WO2017067203A1 (zh) 2015-10-23 2016-06-27 共用协议层的多通道显示接口信号生成系统及方法

Country Status (4)

Country Link
JP (1) JP6592596B2 (ja)
KR (1) KR102070533B1 (ja)
CN (1) CN105427772B (ja)
WO (1) WO2017067203A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113573000A (zh) * 2021-07-27 2021-10-29 武汉帆茂电子科技有限公司 一种基于FPGA的Displayport HBR3信号转换装置
CN113872699A (zh) * 2021-11-08 2021-12-31 中国电信股份有限公司 光发射装置、方法及光模块
CN114446210A (zh) * 2022-01-28 2022-05-06 冠捷显示科技（厦门）有限公司 一种适配液晶面板的Scaler主板检测方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105427772B (zh) * 2015-10-23 2017-12-05 武汉精测电子技术股份有限公司 共用协议层的多通道显示接口信号生成系统及方法
CN107071520B (zh) * 2017-04-11 2020-03-20 西安航天华迅科技有限公司 一种CoaXPress高速图像接口协议IP的实现方法
CN109194889B (zh) * 2018-08-16 2020-11-20 长芯盛（武汉）科技有限公司 用于dp接口的低速信号转换模块

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070247395A1 (en) * 2006-04-20 2007-10-25 Keith Barraclough Communications multiplexing with packet-communication networks
CN101162575A (zh) * 2006-10-12 2008-04-16 佳能株式会社 显示控制设备和方法、显示设备和处理方法、多显示系统
US20120183073A1 (en) * 2011-01-17 2012-07-19 Jaime Milstein Systems and methods for wavelet and channel-based high definition video encoding
CN104867470A (zh) * 2015-06-12 2015-08-26 武汉精测电子技术股份有限公司 基于fpga的逻辑画面中嵌入图文信息的装置及方法
CN104900204A (zh) * 2015-06-12 2015-09-09 武汉精测电子技术股份有限公司 基于fpga的逻辑画面叠加装置及方法
CN105427772A (zh) * 2015-10-23 2016-03-23 武汉精测电子技术股份有限公司 共用协议层的多通道显示接口信号生成系统及方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101472843B1 (ko) * 2008-07-11 2014-12-15 삼성디스플레이 주식회사 디스플레이 포트 기능 테스트 장치, 이를 이용하는디스플레이 포트 기능 테스트 시스템 및 방법
US20100177016A1 (en) * 2009-01-13 2010-07-15 Henry Zeng Multi-monitor display
CN102446477B (zh) * 2011-12-30 2013-11-20 武汉精测电子技术股份有限公司 一种带有dp接口的液晶模组测试装置及测试方法
CN103105684B (zh) * 2013-01-22 2015-09-16 北京京东方光电科技有限公司 液晶显示模块测试方法、装置、系统及测试设备

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070247395A1 (en) * 2006-04-20 2007-10-25 Keith Barraclough Communications multiplexing with packet-communication networks
CN101162575A (zh) * 2006-10-12 2008-04-16 佳能株式会社 显示控制设备和方法、显示设备和处理方法、多显示系统
US20120183073A1 (en) * 2011-01-17 2012-07-19 Jaime Milstein Systems and methods for wavelet and channel-based high definition video encoding
CN104867470A (zh) * 2015-06-12 2015-08-26 武汉精测电子技术股份有限公司 基于fpga的逻辑画面中嵌入图文信息的装置及方法
CN104900204A (zh) * 2015-06-12 2015-09-09 武汉精测电子技术股份有限公司 基于fpga的逻辑画面叠加装置及方法
CN105427772A (zh) * 2015-10-23 2016-03-23 武汉精测电子技术股份有限公司 共用协议层的多通道显示接口信号生成系统及方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113573000A (zh) * 2021-07-27 2021-10-29 武汉帆茂电子科技有限公司 一种基于FPGA的Displayport HBR3信号转换装置
CN113872699A (zh) * 2021-11-08 2021-12-31 中国电信股份有限公司 光发射装置、方法及光模块
CN114446210A (zh) * 2022-01-28 2022-05-06 冠捷显示科技（厦门）有限公司 一种适配液晶面板的Scaler主板检测方法
CN114446210B (zh) * 2022-01-28 2023-12-29 冠捷显示科技（厦门）有限公司 一种适配液晶面板的Scaler主板检测方法

Also Published As

Publication number Publication date
JP6592596B2 (ja) 2019-10-16
CN105427772B (zh) 2017-12-05
CN105427772A (zh) 2016-03-23
JP2019504521A (ja) 2019-02-14
KR20180072790A (ko) 2018-06-29
KR102070533B1 (ko) 2020-01-28

Similar Documents

Publication Publication Date Title
WO2017067203A1 (zh) 共用协议层的多通道显示接口信号生成系统及方法
EP3142360B1 (en) Multimedia signal transmission device and transmission method thereof
CN105023549A (zh) 分辨率自适应的mipi图形信号产生装置及方法
CN110581963B (zh) 一种v-by-one信号转换方法、装置及电子设备
CN104795039A (zh) 基于fpga实现mipi信号传输调整的方法和装置
CN103428532A (zh) 多媒体信号传输系统、多媒体信号切换装置及多媒体信号传输方法
CN105472288A (zh) 一种v-by-one视频信号单路转多路的装置及方法
CN103700319A (zh) 一种拼接式显示装置
CN105491318A (zh) 一种dp视频信号单路转多路的装置及方法
CN104537999B (zh) 一种可依据系统复杂程度灵活配置的面板内部接口及其协议
US20240029619A1 (en) Display device driving control circuit assembly and display device
CN105118409B (zh) 基于fpga的v‑by‑one编解码系统及方法
CN207458549U (zh) Led系统
CN111063285A (zh) 显示控制系统和显示单元板
CN106652892B (zh) Led灯板模组
CN206274660U (zh) 一种视频处理系统
CN213960238U (zh) 一种显示装置及系统
CN105516632B (zh) Lvds视频信号转换为dp1.2视频信号的方法及系统
CN101729845A (zh) Camera-Link数字视频信息叠加方法
KR101013890B1 (ko) 무선통신모듈이 적용된 화상검사장치
CN113470587A (zh) 显示设备控制电路、显示主机设备及显示系统
CN104717440A (zh) Led发送卡级联接口
KR101550810B1 (ko) 엠에이치엘/에이치디엠아이 연결 장치 및 이를 이용한 신호 변환 방법
CN212909517U (zh) 一种适合mipi d-phy信号的传输电路及其应用
TWI651002B (zh) 訊號傳輸裝置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16856643

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2018520165

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20187014464

Country of ref document: KR

Kind code of ref document: A

122 Ep: pct application non-entry in european phase

Ref document number: 16856643

Country of ref document: EP

Kind code of ref document: A1