WO2017054301A1 - 薄膜晶体管阵列基板及液晶显示面板 - Google Patents

薄膜晶体管阵列基板及液晶显示面板 Download PDF

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Publication number
WO2017054301A1
WO2017054301A1 PCT/CN2015/095287 CN2015095287W WO2017054301A1 WO 2017054301 A1 WO2017054301 A1 WO 2017054301A1 CN 2015095287 W CN2015095287 W CN 2015095287W WO 2017054301 A1 WO2017054301 A1 WO 2017054301A1
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Prior art keywords
strip
thin film
film transistor
holes
transistor array
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PCT/CN2015/095287
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English (en)
French (fr)
Inventor
陈归
陈彩琴
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Wuhan China Star Optoelectronics Technology Co Ltd
TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US14/908,101 priority Critical patent/US9857653B2/en
Publication of WO2017054301A1 publication Critical patent/WO2017054301A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0445—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0446—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/273—Interconnections for measuring or testing, e.g. probe pads
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention claims the priority of the prior application entitled “Thin-film Transistor Array Substrate and Liquid Crystal Display Panel”, filed on September 28, 2015, the disclosure of which is incorporated herein by reference. .
  • the present invention relates to the field of liquid crystal display, and in particular to a thin film transistor array substrate and a liquid crystal display panel.
  • Liquid Crystal Display is a common electronic device that is favored by users because of its low power consumption, small size, and light weight.
  • Touch display integration is also known as a hot spot along the display panel, and low temperature poly-silicon (LTPS) in cell technology is regarded as a high-end technology in this field.
  • LTPS low temperature poly-silicon
  • the so-called in cell technology refers to embedding the touch panel function into a liquid crystal pixel (Pixel).
  • the sensing trace, the gate line and the data line of the sensing electrode have a large overlapping area with the common electrode layer, and therefore, the sensing electrode A large capacitance is formed between the sensing trace and the common electrode layer, between the gate line and the common electrode layer, and between the data line and the common electrode layer.
  • the sensing trace, the gate line, the data line and the common electrode layer of the sensing electrode have resistance, the resistance capacitance (RC) of the pixel is relatively large, thereby affecting the display of the entire liquid crystal display panel. effect.
  • the RC load of the pixel is large, and the display effect of the entire liquid crystal display panel is not good.
  • the present invention provides a thin film transistor array substrate, the thin film transistor array substrate comprising:
  • the substrate including opposite first and second surfaces;
  • a thin film transistor array disposed on the first surface
  • the common electrode layer is insulated from the thin film transistor array, and the public
  • the common electrode includes a plurality of first strip holes
  • the sensing electrode layer is insulated from the common electrode layer, and the sensing electrode layer includes a plurality of sensing units and a plurality of sensing traces, and the sensing unit is arranged in a row and a column.
  • the sensing traces are electrically connected to each row or column of sensing units, respectively, and the sensing traces are disposed corresponding to the first strip holes.
  • the thin film transistor array substrate further includes:
  • gate lines disposed on the thin film crystal array, the gate lines being arranged in a first direction and extending in a second direction;
  • a plurality of data lines disposed on the gate line, the data lines being arranged along the second direction and extending along the first direction;
  • the common electrode layer is disposed on the data line and insulated from the data line and the gate line, the first strip hole is disposed corresponding to the gate line, or the first strip hole corresponds to The data line is set.
  • a dimension of the first stripe hole corresponding to the width of the gate line is less than or equal to a width of the gate line;
  • the size of the first strip hole corresponding to the width of the data line is less than or equal to the width of the data line.
  • each of the first strip-shaped holes comprises a plurality of first sub-strip holes, and the first sub-strip holes are spaced apart.
  • the first sub strip holes are arranged along the first direction and extend along the second direction; when the first strip shape When the holes are disposed corresponding to the data lines, the first sub-strip holes are arranged along the second direction and extend along the first direction.
  • the thin film transistor array substrate includes a second strip-shaped hole, and when the first strip-shaped hole is disposed corresponding to the gate line, the second strip-shaped hole is disposed corresponding to the data line; When the one-shaped hole is disposed corresponding to the data line, the second strip-shaped hole is disposed corresponding to the gate line.
  • the size of the second stripe hole corresponding to the width of the data line is less than or equal to the width of the data line; when the second strip When the shape hole is disposed corresponding to the gate line, the size of the second strip hole corresponding to the width of the gate line is less than or equal to the width of the gate line.
  • each of the second strip-shaped holes comprises a plurality of second sub-bar-shaped holes, and the second sub-bar-shaped holes are spaced apart Set.
  • the second sub-bar-shaped hole when the second strip-shaped hole is disposed corresponding to the data line, the second sub-bar-shaped hole is arranged along the second direction and extends along the first direction; when the second strip When the shaped holes are disposed corresponding to the gate lines, the second sub-bar shaped holes are arranged along the first direction and extend in the second direction.
  • the present invention also provides a liquid crystal display panel comprising the thin film transistor array substrate according to any of the above embodiments.
  • the thin film transistor array substrate and the liquid crystal display panel of the present invention have a first strip hole disposed on the common electrode layer, and the first strip hole is disposed corresponding to the sensing trace.
  • FIG. 1 is a schematic structural view of a thin film transistor array substrate according to a preferred embodiment of the present invention.
  • FIG. 2 is a schematic enlarged view of a portion II of FIG. 1 of the present invention.
  • Figure 3 is a schematic cross-sectional view of the III-III of Figure 2 of the present invention.
  • Figure 4 is a schematic view showing the distribution of the first sub-strip holes in the first strip-shaped hole of the present invention.
  • Figure 5 is a schematic view showing the distribution of the second sub-bar-shaped holes in the second strip-shaped hole of the present invention
  • FIG. 6 is a schematic structural view of a liquid crystal display panel according to a preferred embodiment of the present invention.
  • FIG. 1 is a schematic structural view of a thin film transistor array substrate according to a preferred embodiment of the present invention
  • FIG. 2 is a schematic enlarged view of a portion II of FIG. 1 according to the present invention
  • the thin film transistor array substrate 100 includes a substrate 110, a thin film transistor array 120, a sensing electrode layer 160, a plurality of gate lines 130, a plurality of data lines 140, and a common electrode layer 150.
  • the substrate 110 includes a first surface 111 and a second surface 112 disposed opposite to each other, and the thin film transistor array 120 is disposed on the first surface 111.
  • the common electrode layer 150 is insulated from the thin film transistor array 120, and the common electrode layer 150 includes a plurality of first strip holes 151.
  • the sensing electrode layer 160 is insulated from the common electrode layer 150, and the sensing electrode layer 160 includes a plurality of sensing units 161 and a plurality of sensing traces 162, and the sensing unit 160 is arranged in a row and a row.
  • the sensing traces 162 are electrically connected to each row or column of sensing units, respectively, and the sensing traces 162 are disposed corresponding to the first strip holes 151.
  • the gate lines 130 are disposed on the thin film transistor array 120, and the gate lines 130 are arranged along the first direction D1 and extend along the second direction D2.
  • the data lines 140 are disposed on the gate lines 130, and the data lines 140 are arranged along the second direction D2 and extend along the first direction D1.
  • the common electrode layer 150 is disposed on the data line 140 and insulated from the data line 140 and the gate line 130.
  • the first strip hole 151, the first strip hole 151 corresponds to the The gate line 130 is disposed, or the first strip hole 151 is disposed corresponding to the data line 140.
  • the substrate 110 may be a transparent substrate such as a glass substrate or a plastic substrate.
  • the material of the substrate 110 is not limited.
  • the thin film transistor array 120 is disposed on the first surface 111 of the substrate 110.
  • the The two surfaces 112 are surfaces disposed adjacent to the backlight module.
  • the thin film transistor array 120 may also be disposed on the second surface 112.
  • the first surface 111 of the substrate 110 is adjacent to the backlight module. Set the surface.
  • the thin film transistor array 120 includes a plurality of thin film transistors distributed in a matrix for controlling pixels in a liquid crystal display panel.
  • the thin film transistor includes a gate, a source, and a drain, the gate is configured to receive a gate voltage, and control the source under the control of the gate voltage And turning on or off the drain. When the source and the drain are turned on under the control of the gate voltage, the thin film transistor is turned on; when the source and the source When the drain is turned off under the control of the gate voltage, the thin film transistor is turned off.
  • the gate line 130 is disposed on the thin film transistor array 120, and an insulating layer a is disposed between the gate line 130 and the thin film transistor 120, and the gate line 130 and the gate of the thin film transistor are electrically connected. Connection for outputting the gate voltage.
  • the gate lines 130 are arranged along the first direction D1 and extend along the second direction D2.
  • the first direction D1 is the Y-axis direction
  • the second direction D2 is the X-axis direction.
  • the first direction D1 and the second direction D2 may not be the Y-axis direction and the X-axis direction, and the first direction D1 and the second direction D2 are also Can not be perpendicular to each other.
  • the data line 140 is disposed on the gate line 130, and the data line 140 and the gate line 130 are insulated from each other, and the data line 140 is disposed to cross the gate line 130.
  • the data lines 140 are arranged along the second direction D2 and extend along the first direction D1.
  • an insulating layer b is disposed between the data line 140 and the gate line 130 to insulate the data line 140 from the gate line 130 from each other.
  • the common electrode layer 150 is disposed on the data line 140 and insulated from the data line 140 and the gate line 130. Specifically, an insulating layer c may be disposed on the data line 140, and the common electrode layer 150 is disposed on the insulating layer c.
  • the material of the insulating layer c may be, but not limited to, one of silicon nitride (SiNx), silicon dioxide (SiO 2 ), silicon oxynitride, and combinations thereof.
  • the first strip hole 151 is described as an example corresponding to the gate line 130.
  • the size of the first strip hole 151 corresponding to the width of the gate line 130 is less than or equal to the width of the gate line 130.
  • the gates The dimension on the width of the line 130 is a dimension along the first direction D1
  • the dimension of the first strip-shaped aperture 151 corresponding to the width of the gate line 130 is the first strip-shaped aperture 151 at the The size of one direction D1.
  • the size of the first strip hole 151 corresponding to the width of the gate line 130 is less than or equal to the width of the gate line 130, that is, the size of the first strip hole 151 in the first direction D1 is smaller than Or equal to the width of the gate line 130.
  • the size of the first strip hole 151 corresponding to the width of the data line 140 is less than or equal to The width of the data line 140.
  • the width of the data lines 140 since the data lines 140 are arranged along the second direction D2 and extend along the first direction D1, the width of the data lines 140 The upper dimension is a dimension along the second direction D2, and the size of the first strip hole 151 corresponding to the data line 140 is the first strip hole 151 in the second direction D2. size.
  • the size of the first strip hole 151 corresponding to the width of the data line 140 is less than or equal to the width of the data line 140, that is, the size of the first strip hole 151 in the second direction D2 is less than or equal to The width of the data line 140.
  • each of the first strip-shaped holes 151 includes a plurality of first sub-strip holes 1511, and the first sub-strip holes 1511 are spaced apart.
  • the first strip holes 151 are disposed corresponding to the gate lines 130, the first sub strip holes 1511 are arranged along the first direction D1 and extend along the second direction D2, please refer to FIG. .
  • the first sub strip holes 1511 are arranged along the second direction D2 and extend along the first direction D1. It can be understood that the shape of each of the first sub-strip holes 1511 may be the same or different, and the first sub-strip hole 1511 is not limited in this embodiment.
  • the thin film transistor array substrate 100 further includes a second strip hole 152.
  • the second strip hole 152 is disposed corresponding to the data line 140.
  • the first strip hole 151 is disposed corresponding to the data line 140
  • the second strip hole 152 is disposed corresponding to the gate line 130.
  • the size of the second strip hole 152 corresponding to the width of the data line 140 is less than or equal to the width of the data line 140.
  • the size of the second strip hole 152 corresponding to the width of the gate line 130 is less than or equal to the width of the gate line 130.
  • each of the second strip-shaped apertures 152 includes a plurality of second sub-striped apertures 1521, the second sub-striped apertures 1521 being spaced apart.
  • the second strip holes 152 are disposed corresponding to the data lines 140, the second sub strip holes 1521 are arranged along the second direction D2 and extend along the first direction D1.
  • the second sub strip holes 1521 are arranged along the first direction D1 and extend along the second direction D2, as shown in FIG. Show.
  • the thin film transistor array substrate 100 may include only the first strip hole 151, and the first strip hole 151 includes a plurality of first sub strip holes 1511 as described above. Or the thin The film transistor array substrate 100 may also include only the second strip hole 152, and the second strip hole 152 includes a plurality of second sub strip holes 1511 as described above. Alternatively, the thin film transistor array substrate 100 may include the first strip hole 151 and the second strip hole 152 at the same time, and the first strip hole 151 includes a plurality of first sub strip holes as described above. 1511. Alternatively, the thin film transistor array substrate 100 may include the first strip hole 151 and the second strip hole 152 at the same time, and the second strip hole 152 includes a plurality of second sub strip holes as described above.
  • the thin film transistor array substrate 100 includes the first strip hole 151 and the second strip hole 152 at the same time, and the first sub strip hole 151 includes a plurality of first sub strips as described above.
  • the aperture 1511 and the second sub-bar aperture 152 include a plurality of second sub-bar apertures 1521 as previously described.
  • the sensing electrode layer 160 is transparent, and the material of the sensing electrode layer 160 may be, but not limited to, a material such as indium oxide.
  • Each row or each column of the sensing electrode layer 160 is electrically connected to a driving chip through a touch panel trace 162, and the sensing unit 160 is configured to receive the driving chip. The electrical signal is output and the change in the sensed signal is transmitted to the driver chip for processing.
  • the sensing electrode layer 160 is disposed on the common electrode layer 150 through the insulating layer d.
  • the sensing electrode layer 160 has a touch sensing function, that is, in the present embodiment, the touch panel function is embedded in the liquid crystal pixel, that is, the so-called in cell technology.
  • the thin film transistor array substrate 100 of the present invention has a first strip hole 151 disposed on the common electrode layer 150, and the first strip hole 151 is disposed corresponding to the sensing trace 162, thereby The area of overlap between the common electrode layer 150 and the sensing trace 162 is reduced, thereby reducing the capacitance between the common electrode layer 150 and the sensing trace 162, thereby reducing The RC load of the pixel improves the quality of the liquid crystal display panel using the thin film transistor array substrate 100.
  • the thin film transistor array substrate 100 of the present invention has a first strip hole 151 disposed on the common electrode layer 150, and the first strip hole 151 corresponds to the gate line 130 or the data line 140.
  • the capacitance either reduces the capacitance between the common electrode layer 150 and the data line 140, thereby reducing the RC load of the pixel, and improving the use of the thin film transistor array substrate 100. The display quality of the LCD panel.
  • FIG. 6 is a schematic structural diagram of a liquid crystal display panel according to a preferred embodiment of the present invention.
  • the liquid crystal display panel 10 includes the thin film transistor array substrate 100.
  • the thin film transistor array substrate 100 refer to the foregoing description, and details are not described herein again.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
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Abstract

一种薄膜晶体管阵列基板（100）及液晶显示面板。该薄膜晶体管阵列基板（100）包括：基板（110），该基板（110）包括相对设置的第一表面（111）及第二表面（112）；薄膜晶体管阵列（120），设置在第一表面（111）上；公共电极层（150），该公共电极层（150）与薄膜晶体管阵列（120）绝缘设置，且公共电极层（150）包括多个第一条形孔（151）；感测电极层（160），该感测电极层（160）与公共电极层（150）绝缘设置，且感测电极层（160）包括多个感测单元（161）及多个感测走线（162），感测单元（161）呈行列分布，感测走线（162）分别电连接每行或者每列感测单元（161），感测走线（162）对应第一条形孔（151）设置。

Description

薄膜晶体管阵列基板及液晶显示面板
本发明要求2015年9月28日递交的发明名称为“薄膜晶体管阵列基板及液晶显示面板”的申请号201510626558.5的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及液晶显示领域，尤其涉及一种薄膜晶体管阵列基板及液晶显示面板。
背景技术
液晶显示面板(Liquid Crystal Display,LCD)是一种常见的电子设备，由于其具有功耗低、体积小、质量轻等特点而受到用户的青睐。触控显示一体化也称为沿显示面板研究的热点，而低温多晶硅(Low Temperature Poly-silicon，LTPS)in cell技术被视为该领域的高端技术。所谓in cell技术，是指将触控面板功能嵌入到液晶像素(Pixel)中。在传统的像素的设计过程中，感测电极的感测走线、栅极线(gate line)和数据线(data line)与公共电极层之间有较大的重叠面积，因此，感测电极的感测走线与公共电极层之间，所述栅极线与所述公共电极层之间，以及数据线与公共电极层之间形成了较大的电容。同时，由于感测电极的感测走线、栅极线、数据线及公共电极层之间均具有电阻，因此，像素的电阻电容(RC)负载较大，从而影响了整个液晶显示面板的显示效果。综上所述，现有技术中像素的RC负载较大，整个液晶显示面板的显示效果不佳。
发明内容
本发明提供了一种薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：
基板，所述基板包括相对设置的第一表面及第二表面；
薄膜晶体管阵列，设置在所述第一表面上；
公共电极层，所述公共电极层与所述薄膜晶体管阵列绝缘设置，且所述公 共电极包括多个第一条形孔；
感测电极层，所述感测电极层与所述公共电极层绝缘设置，且所述感测电极层包括多个感测单元及多个感测走线，感测单元呈行列分布，所述感测走线分别电连接每行或者每列感测单元，所述感测走线对应所述第一条形孔设置。
其中，所述薄膜晶体管阵列基板还包括：
多个栅极线，设置在所述薄膜晶体阵列上，所述栅极线沿第一方向排列且沿第二方向延伸；
多个数据线，设置在所述栅极线上，所述数据线沿所述第二方向排列且沿所述第一方向延伸；
所述公共电极层设置在所述数据线上且与所述数据线及所述栅极线绝缘，所述第一条形孔对应所述栅极线设置，或者所述第一条形孔对应所述数据线设置。
其中，当所述第一条形孔对应所述栅极线设置时，所述第一条形孔对应所述栅极线宽度上的尺寸小于或等于所述栅极线的宽度；当所述第一条形孔对应所述数据线设置时，所述第一条形孔对应所述数据线宽度上的尺寸小于或等于所述数据线的宽度。
其中，每条第一条形孔包括多个第一子条形孔，所述第一子条形孔间隔设置。
其中，当所述第一条形孔对应所述栅极线设置时，所述第一子条形孔沿所述第一方向排列且沿所述第二方向延伸；当所述第一条形孔对应所述数据线设置时，所述第一子条形孔沿所述第二方向排列且沿所述第一方向延伸。
其中，所述薄膜晶体管阵列基板包括第二条形孔，当所述第一条形孔对应所述栅极线设置时，所述第二条形孔对应所述数据线设置；当所述第一条形孔对应所述数据线设置时，所述第二条形孔对应所述栅极线设置。
其中，当所述第二条形孔对应所述数据线设置时，所述第二条形孔对应所述数据线宽度上的尺寸小于或等于所述数据线的宽度；当所述第二条形孔对应所述栅极线设置时，所述第二条形孔对应所述栅极线宽度上的尺寸小于或等于所述栅极线的宽度。
其中，每条第二条形孔包括多个第二子条形孔，所述第二子条形孔间隔设 置。
其中，所述当所述第二条形孔对应所述数据线设置时，所述第二子条形孔沿所述第二方向排列且沿所述第一方向延伸；当所述第二条形孔对应所述栅极线设置时，所述第二子条形孔沿所述第一方向排列且沿所述第二方向延伸。
本发明还提供了一种液晶显示面板，所述液晶显示面板包括前述任一实施方式所述的薄膜晶体管阵列基板。
相较于现有技术，本发明的薄膜晶体管阵列基板及液晶显示面板将所述公共电极层上设置第一条形孔，且使得所述第一条形孔对应所述感测走线设置，从而使得所述公共电极层与所述感测走线之间的重叠面积减小，从而减小了所述公共电极层与所述感测走线之间的电容，从而减小了像素的RC负载，提高了使用所述薄膜晶体管阵列基板的液晶显示面板的显示品质。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的薄膜晶体管阵列基板的结构示意图。
图2为本发明图1中II处的放大结构示意图。
图3为本发明图2中III-III的剖面结构示意图。
图4为本发明的第一条形孔中的第一子条形孔的分布示意图。
图5为本发明的第二条形孔中的第二子条形孔的分布示意图
图6为本发明一较佳实施方式的液晶显示面板的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请一并参阅图1、图2及图3，图1为本发明一较佳实施方式的薄膜晶体管阵列基板的结构示意图；图2为本发明图1中II处的放大结构示意图；图3为本发明图2中III-III的剖面结构示意图。所述薄膜晶体管阵列基板100包括基板110、薄膜晶体管阵列120、感测电极层160、多个栅极线130、多个数据线140及公共电极层150。所述基板110包括相对设置的第一表面111和第二表面112，所述薄膜晶体管阵列120设置在所述第一表面111上。所述公共电极层150与所述薄膜晶体管阵列120绝缘设置，且所述公共电极层150包括多个第一条形孔151。所述感测电极层160与所述公共电极层150绝缘设置，且所述感测电极层160包括多个感测单元161及多个感测走线162，所述感测单元160呈行列分布，所述感测走线162分别电连接每行或者每列感测单元，所述感测走线162对应所述第一条形孔151设置。
所述栅极线130设置在所述薄膜晶体管阵列120上，且所述栅极线130沿第一方向D1排列且沿第二方向D2延伸。所述数据线140设置在所述栅极线130上，所述数据线140沿所述第二方向D2排列且沿所述第一方向D1延伸。所述公共电极层150设置在所述数据线140上且与所述数据线140及所述栅极线130绝缘，所述第一条形孔151，所述第一条形孔151对应所述栅极线130设置，或者所述第一条形孔151对应所述数据线140设置。
所述基板110可以为玻璃基板、塑料基板等透明的基板，在本实施中，不对所述基板110的材料做限定。可以理解地，在本实施方式中，以所述薄膜晶体管阵列120设置在所述基板110的所述第一表面111上为例进行说明，在本实施方式中，所述基板110的所述第二表面112为邻近背光模组设置的表面。可以理解地，在其他实施方式中，所述薄膜晶体管阵列120也可以设置在所述第二表面112上，在本实施方式中，所述基板110的所述第一表面111为邻近背光模组设置的表面。
所述薄膜晶体管阵列120包括呈矩阵状分布的多个薄膜晶体管，所述薄膜晶体管用于控制液晶显示面板中像素点。所述薄膜晶体管包括栅极(gate)、源极(source)及漏极(drain)，所述栅极用于接收一栅极电压，并在所述栅极电压的控制下控制所述源极及所述漏极的导通或者截止。当所述源极及所述漏极在所述栅极电压的控制下导通时，所述薄膜晶体管导通；当所述源极及所 述漏极在所述栅极电压的控制下截止时，所述薄膜晶体管断开。
所述栅极线130设置在所述薄膜晶体管阵列120上，所述栅极线130与所述薄膜晶体管120之间设置绝缘层a，所述栅极线130与所述薄膜晶体管的栅极电连接，用于输出栅极电压。所述栅极线130沿第一方向D1排列且沿第二方向D2延伸。在本实施方式中，所述第一方向D1为Y轴方向，所述第二方向D2为X轴方向。可以理解地，在其他实施方式中，所述第一方向D1与所述第二方向D2也可以不为Y轴方向与X轴方向，且所述第一方向D1与所述第二方向D2也可以不相互垂直。
所述数据线140设置在所述栅极线130上，且所述数据线140与所述栅极线130彼此绝缘，且所述数据线140与所述栅极线130交叉设置。所述数据线140沿第二方向D2排列且沿所述第一方向D1延伸。在本实施方式中，所述数据线140与所述栅极线130之间设置一绝缘层b，以实现所述数据线140与所述栅极线130彼此绝缘。
所述公共电极层150设置在所述数据线140上且与所述数据线140以及所述栅极线130绝缘。具体地，所述数据线140上可以设置一绝缘层c，所述公共电极层150设置在所述绝缘层c上。所述绝缘层c的材料可以为但不仅限于为氮化硅(SiNx)、二氧化硅(SiO2)、氮氧化硅及其组合的其中之一。
在本实施方式中，以所述第一条形孔151对应所述栅极线130设置为例进行描述，此时，所述第一条形孔151对应所述栅极线130设置时，所述第一条形孔151对应所述栅极线130宽度上的尺寸小于或等于所述栅极线130的宽度。当所述第一条形孔151对应所述栅极线130设置时，由于所述栅极线130沿所述第一方向D1排列且沿所述第二方向D2延伸，因此，所述栅极线130宽度上的尺寸为沿所述第一方向D1的尺寸，所述第一条形孔151对应所述栅极线130宽度上的尺寸即为所述第一条形孔151在所述第一方向D1的尺寸。所述第一条形孔151对应所述栅极线130宽度上的尺寸小于或等于所述栅极线130的宽度，即所述第一条形孔151在所述第一方向D1的尺寸小于或等于所述栅极线130的宽度。
可以理解地，在其他实施方式中，当所述第一条形孔150对应所述数据线140设置时，所述第一条形孔151对应所述数据线140宽度上的尺寸小于或等 于所述数据线140的宽度。当所述第一条形孔151对应所述数据线140设置时，由于所述数据线140沿所述第二方向D2排列且沿所述第一方向D1延伸，因此，所述数据线140宽度上的尺寸为沿所述第二方向D2方向的尺寸，所述第一条形孔151对应所述数据线140上的尺寸即为所述第一条形孔151在所述第二方向D2的尺寸。所述第一条形孔151对应所述数据线140宽度上的尺寸小于或等于所述数据线140的宽度，即所述第一条形孔151在所述第二方向D2的尺寸小于或等于所述数据线140的宽度。
在一实施方式中，每条第一条形孔151包括多个第一子条形孔1511，所述第一子条形孔1511间隔设置。当所述第一条形孔151对应所述栅极线130设置时，所述第一子条形孔1511沿所述第一方向D1排列且沿所述第二方向D2延伸，请参阅图4。当所述第一条形孔151对应所述数据线140设置时，所述第一子条形孔1511沿所述第二方向D2排列且沿所述第一方向D1延伸。可以理解地，各个第一子条形孔1511的形状可以相同，也可以不同，在本实施方式中不对所述第一子条形孔1511进行限定。
所述薄膜晶体管阵列基板100还包括第二条形孔152，当所述第一条形孔151对应所述栅极线130设置时，所述第二条形孔152对应所述数据线140设置。当所述第一条形孔151对应所述数据线140设置时，所述第二条形孔152对应所述栅极线130设置。
当所述第二条形孔152对应所述数据线140设置时，所述第二条形孔152对应所述数据线140宽度上的尺寸小于或等于所述数据线140的宽度。当所述第二条形孔152对应所述栅极线130设置时，所述第二条形孔152对应所述栅极线130宽度上的尺寸小于或等于所述栅极线130的宽度。
在一实施方式中，每条第二条形孔152包括多个第二子条形孔1521，所述第二子条形孔1521间隔设置。当所述第二条形孔152对应所述数据线140设置时，所述第二子条形孔1521沿所述第二方向D2排列且沿所述第一方向D1延伸。当所述第二条形孔152对应所述栅极线130设置时，所述第二子条形孔1521沿所述第一方向D1排列且沿所述第二方向D2延伸，如图5所示。
可以理解地，所述薄膜晶体管阵列基板100可以仅包括第一条形孔151，所述第一条形孔151中包括如前述的多个第一子条形孔1511。或者，所述薄 膜晶体管阵列基板100也可仅仅包括第二条形孔152，所述第二条形孔152中包括如前述的多个第二子条形孔1511。或者，所述薄膜晶体管阵列基板100可同时包括所述第一条形孔151及所述第二条形孔152，所述第一条形孔151包括如前述的多个第一子条形孔1511。或者，所述薄膜晶体管阵列基板100可同时包括所述第一条形孔151及所述第二条形孔152，所述第二条形孔152包括如前述的多个第二子条形孔1512。或者，所述薄膜晶体管阵列基板100同时包括所述第一条形孔151及所述第二条形孔152，且所述第一子条形孔151包括如前述的多个第一子条形孔1511且所述第二子条形孔152包括如前述的多个第二子条形孔1521。
所述感测电极层160为透明的，所述感测电极层160的材料可以为但不仅限于为氧化铟等材料。所述感测电极层160中的每行或者每列感测单元160通过一个感测走线162(touch panel trace)与一驱动芯片电连接，所述感测单元160用于接收所述驱动芯片输出的电信号，并将感测到的信号的变化传输至所述驱动芯片处理。在本实施方式中，所述感测电极层160通过绝缘层d设置在所述公共电极层150上。在本实施方式中，将所述感测电极层160具有触摸感测功能，即本实施方式中，将触摸面板功能嵌入到了液晶像素中，即本所谓的in cell技术。
相较于现有技术，本发明的薄膜晶体管阵列基板100将公共电极层150上设置第一条形孔151，且使得所述第一条形孔151对应所述感测走线162设置，从而使得所述公共电极层150与所述感测走线162之间的重叠面积减小，从而减小了所述公共电极层150与所述感测走线162之间的电容，从而减小了像素的RC负载，提高了使用所述薄膜晶体管阵列基板100的液晶显示面板的品质。
进一步地，本发明的薄膜晶体管阵列基板100将所述公共电极层150上设置第一条形孔151，且使得所述第一条形孔151对应所述栅极线130或者所述数据线140设置，从而使得所述公共电极层150与所述栅极线130或者所述数据线140之间的重叠面积减小，从而减小了所述公共电极层150与所述栅极线130之间的电容或者减小了所述公共电极层150与所述数据线140之间的电容，从而减小了像素的RC负载，提高了使用所述薄膜晶体管阵列基板100的 液晶显示面板的显示品质。
下面结合图1至图5对本发明的液晶显示面板进行介绍。请参阅图6，图6为本发明一较佳实施方式的液晶显示面板的结构示意图。所述液晶显示面板10包括所述薄膜晶体管阵列基板100。所述薄膜晶体管阵列基板100请参阅前述描述，在此不再赘述。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (18)

  1. 一种薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板包括：
    基板，所述基板包括相对设置的第一表面及第二表面；
    薄膜晶体管阵列，设置在所述第一表面上；
    公共电极层，所述公共电极层与所述薄膜晶体管阵列绝缘设置，且所述公共电极包括多个第一条形孔；
    感测电极层，所述感测电极层与所述公共电极层绝缘设置，且所述感测电极层包括多个感测单元及多个感测走线，感测单元呈行列分布，所述感测走线分别电连接每行或者每列感测单元，所述感测走线对应所述第一条形孔设置。
  2. 如权利要求1所述的薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板还包括：
    多个栅极线，设置在所述薄膜晶体阵列上，所述栅极线沿第一方向排列且沿第二方向延伸；
    多个数据线，设置在所述栅极线上，所述数据线沿所述第二方向排列且沿所述第一方向延伸；
    所述公共电极层设置在所述数据线上且与所述数据线及所述栅极线绝缘，所述第一条形孔对应所述栅极线设置，或者所述第一条形孔对应所述数据线设置。
  3. 如权利要求2所述的薄膜晶体管阵列基板，其中，当所述第一条形孔对应所述栅极线设置时，所述第一条形孔对应所述栅极线宽度上的尺寸小于或等于所述栅极线的宽度；当所述第一条形孔对应所述数据线设置时，所述第一条形孔对应所述数据线宽度上的尺寸小于或等于所述数据线的宽度。
  4. 如权利要求1所述的薄膜晶体管阵列基板，其中，每条第一条形孔包括多个第一子条形孔，所述第一子条形孔间隔设置。
  5. 如权利要求4所述的薄膜晶体管阵列基板，其中，当所述第一条形孔对应所述栅极线设置时，所述第一子条形孔沿所述第一方向排列且沿所述第二方向延伸；当所述第一条形孔对应所述数据线设置时，所述第一子条形孔沿所述第二方向排列且沿所述第一方向延伸。
  6. 如权利要求2所述的薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板包括第二条形孔，当所述第一条形孔对应所述栅极线设置时，所述第二条形孔对应所述数据线设置；当所述第一条形孔对应所述数据线设置时，所述第二条形孔对应所述栅极线设置。
  7. 如权利要求6所述的薄膜晶体管阵列基板，其中，当所述第二条形孔对应所述数据线设置时，所述第二条形孔对应所述数据线宽度上的尺寸小于或等于所述数据线的宽度；当所述第二条形孔对应所述栅极线设置时，所述第二条形孔对应所述栅极线宽度上的尺寸小于或等于所述栅极线的宽度。
  8. 如权利要求7所述的薄膜晶体管阵列基板，其中，每条第二条形孔包括多个第二子条形孔，所述第二子条形孔间隔设置。
  9. 如权利要求8所述的薄膜晶体管阵列基板，其中，所述当所述第二条形孔对应所述数据线设置时，所述第二子条形孔沿所述第二方向排列且沿所述第一方向延伸；当所述第二条形孔对应所述栅极线设置时，所述第二子条形孔沿所述第一方向排列且沿所述第二方向延伸。
  10. 一种液晶显示面板，其中，所述液晶显示面板包括薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：
    基板，所述基板包括相对设置的第一表面及第二表面；
    薄膜晶体管阵列，设置在所述第一表面上；
    公共电极层，所述公共电极层与所述薄膜晶体管阵列绝缘设置，且所述公共电极包括多个第一条形孔；
    感测电极层，所述感测电极层与所述公共电极层绝缘设置，且所述感测电极层包括多个感测单元及多个感测走线，感测单元呈行列分布，所述感测走线分别电连接每行或者每列感测单元，所述感测走线对应所述第一条形孔设置。
  11. 如权利要求10所述的液晶显示面板，其中，所述薄膜晶体管阵列基板还包括：
    多个栅极线，设置在所述薄膜晶体阵列上，所述栅极线沿第一方向排列且沿第二方向延伸；
    多个数据线，设置在所述栅极线上，所述数据线沿所述第二方向排列且沿所述第一方向延伸；
    所述公共电极层设置在所述数据线上且与所述数据线及所述栅极线绝缘，所述第一条形孔对应所述栅极线设置，或者所述第一条形孔对应所述数据线设置。
  12. 如权利要求11所述的液晶显示面板，其中，当所述第一条形孔对应所述栅极线设置时，所述第一条形孔对应所述栅极线宽度上的尺寸小于或等于所述栅极线的宽度；当所述第一条形孔对应所述数据线设置时，所述第一条形孔对应所述数据线宽度上的尺寸小于或等于所述数据线的宽度。
  13. 如权利要求10所述的液晶显示面板，其中，每条第一条形孔包括多个第一子条形孔，所述第一子条形孔间隔设置。
  14. 如权利要求13所述的液晶显示面板，其中，当所述第一条形孔对应所述栅极线设置时，所述第一子条形孔沿所述第一方向排列且沿所述第二方向延伸；当所述第一条形孔对应所述数据线设置时，所述第一子条形孔沿所述第二方向排列且沿所述第一方向延伸。
  15. 如权利要求11所述的液晶显示面板，其中，所述薄膜晶体管阵列基板包括第二条形孔，当所述第一条形孔对应所述栅极线设置时，所述第二条形孔 对应所述数据线设置；当所述第一条形孔对应所述数据线设置时，所述第二条形孔对应所述栅极线设置。
  16. 如权利要求15所述的液晶显示面板，其中，当所述第二条形孔对应所述数据线设置时，所述第二条形孔对应所述数据线宽度上的尺寸小于或等于所述数据线的宽度；当所述第二条形孔对应所述栅极线设置时，所述第二条形孔对应所述栅极线宽度上的尺寸小于或等于所述栅极线的宽度。
  17. 如权利要求16所述的液晶显示面板，其中，每条第二条形孔包括多个第二子条形孔，所述第二子条形孔间隔设置。
  18. 如权利要求17所述的液晶显示面板，其中，所述当所述第二条形孔对应所述数据线设置时，所述第二子条形孔沿所述第二方向排列且沿所述第一方向延伸；当所述第二条形孔对应所述栅极线设置时，所述第二子条形孔沿所述第一方向排列且沿所述第二方向延伸。
PCT/CN2015/095287 2015-09-28 2015-11-23 薄膜晶体管阵列基板及液晶显示面板 Ceased WO2017054301A1 (zh)

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