WO2017049020A1 - Appareil et procédés pour piloter des dispositifs d'affichage - Google Patents

Appareil et procédés pour piloter des dispositifs d'affichage Download PDF

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Publication number
WO2017049020A1
WO2017049020A1 PCT/US2016/052032 US2016052032W WO2017049020A1 WO 2017049020 A1 WO2017049020 A1 WO 2017049020A1 US 2016052032 W US2016052032 W US 2016052032W WO 2017049020 A1 WO2017049020 A1 WO 2017049020A1
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WIPO (PCT)
Prior art keywords
voltage
gate
display
decay
electro
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PCT/US2016/052032
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English (en)
Inventor
Kenneth R. Crounse
Teck Ping SIM
Karl Raymond Amundson
Zdzislaw Jan Szymborski
Original Assignee
E Ink Corporation
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Priority claimed from US15/014,236 external-priority patent/US10475396B2/en
Application filed by E Ink Corporation filed Critical E Ink Corporation
Priority to CN202110538254.9A priority Critical patent/CN113241041B/zh
Priority to JP2018513624A priority patent/JP6871241B2/ja
Priority to CN201680053155.9A priority patent/CN108028034B/zh
Priority to EP16847345.2A priority patent/EP3350798B1/fr
Priority to KR1020187007515A priority patent/KR102158965B1/ko
Priority to KR1020207026733A priority patent/KR102308589B1/ko
Publication of WO2017049020A1 publication Critical patent/WO2017049020A1/fr
Priority to HK18107010.1A priority patent/HK1247729A1/zh

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Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3433Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
    • G09G3/344Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices based on particles moving in a fluid or in a gas, e.g. electrophoretic devices
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00Details of flat display driving waveforms
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/04Structural and physical details of display devices
    • G09G2300/0469Details of the physics of pixel operation
    • G09G2300/0473Use of light emitting or modulating elements having two or more stable states when no power is applied
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243Details of the generation of driving signals
    • G09G2310/0251Precharge or discharge of pixel before applying new pixel voltage
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/0267Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00Control of display operating conditions
    • G09G2320/02Improving the quality of display appearance
    • G09G2320/0204Compensation of DC component across the pixels in flat panels
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00Control of display operating conditions
    • G09G2320/04Maintaining the quality of display appearance
    • G09G2320/043Preventing or counteracting the effects of ageing
    • G09G2320/048Preventing or counteracting the effects of ageing using evaluation of the usage time
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02Details of power systems and of start or stop of display operation
    • G09G2330/021Power management, e.g. power saving
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02Details of power systems and of start or stop of display operation
    • G09G2330/028Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • This invention relates to methods for driving bistable electro-optic displays, and to apparatus for use in such methods. More specifically, this invention relates to driving methods and apparatus for adjusting the gate on voltage value after an active update to reduce transistor degradation associated with voltage stress that may be caused by remnant voltage discharging.
  • an apparatus for driving an electro-optic display may comprise a first switch designed to supply a voltage to the electro-optic display during a first driving phase, a second switch designed to control the voltage during a second driving phase, and a resistor coupled to the first and second switches for controlling the rate of decay of the voltage during the second driving phase.
  • a first switch designed to supply a voltage to the electro-optic display during a first driving phase
  • a second switch designed to control the voltage during a second driving phase
  • a resistor coupled to the first and second switches for controlling the rate of decay of the voltage during the second driving phase.
  • FIG. 1A is a schematic of a simple gate on voltage electrical circuit of an electro-optic display, according to some embodiments.
  • FIG. IB is a graph showing gate on voltage versus time during an active update and a voltage decay phase, which includes a post-drive discharge phase, where the gate on voltage decays exponential to ground, according to some embodiments.
  • FIG. 1C is a graph showing gate on voltage versus time during an active update and a voltage decay phase having a preferred voltage profile, according to some embodiments.
  • FIG. 2A is a schematic of a gate on voltage electrical circuit, including a resistor, of an electro-optic display, according to some embodiments.
  • FIG. 2B is a graphical schematic depicting the gate on voltage over time for the circuit of FIG. 2 A, according to some embodiments.
  • FIG. 3A is a schematic of a gate on voltage electrical circuit, including a resistor and a capacitor, of an electro-optic display, according to some embodiments.
  • FIG. 3B is a graphical schematic depicting the gate on voltage over time for the circuit of FIG. 3A, according to some embodiments.
  • FIG. 4A is a schematic of a gate on voltage electrical circuit, including resistors and capacitors, of an electro-optic display, according to some embodiments.
  • FIG. 4B is a graphical schematic depicting the gate on voltage over time for the circuit of FIG. 4 A, according to some embodiments.
  • FIG. 5A is a schematic of a gate on voltage electrical circuit, including a resistor and a capacitor, of an electro-optic display, according to some embodiments.
  • FIG. 5B is a schematic of a gate on voltage electrical circuit, including resistors and capacitors, of an electro-optic display, according to some embodiments.
  • FIG. 6A is a schematic of a gate on voltage electrical circuit, including multiple capacitors and resistors, of an electro-optic display, according to some embodiments.
  • FIG. 6B is a graphical schematic depicting the gate on voltage over time for the circuit of FIG. 6 A, according to some embodiments.
  • FIG. 7 is a schematic of a gate on voltage electrical circuit, including a Zener diode, of an electro-optic display, according to some embodiments.
  • FIG. 8A is a schematic of a gate on voltage electrical circuit, including a resistor and a capacitor, of an electro-optic display, according to some embodiments.
  • FIG. 8B is a graphical schematic depicting the gate on voltage over time for the circuit of FIG. 8 A, according to some embodiments.
  • FIG. 9 is a graphical illustration of a comparison on the performances of the device illustrated in FIG. 8A to a conventional device.
  • FIG. 1 OA is a graph showing the maximum graytone shift against a number of updates with and without remnant voltage discharging, according to some embodiments.
  • FIG. 10B is a graph showing the maximum ghost shift against a number of updates with and without remnant discharging, according to some embodiments.
  • FIG. 11 A is a graph showing the maximum graytone shift against a number of updates with remnant discharging, without remnant discharging, and with remnant discharging and negative biasing, according to some embodiments.
  • FIG. 1 IB is a graph showing the maximum ghost shift against a number of updates with remnant discharging, without remnant discharging, and with remnant voltage discharging and reduced charge biasing, according to some embodiments.
  • FIG. 12A is a schematic of a signal-timing diagram showing the gate voltage against time, according to some embodiments.
  • FIG. 12B is a schematic of a signal-timing diagram showing voltages against time, according to some embodiments.
  • Electro-optic displays comprise a layer of electro-optic material, a term which is used herein in its conventional meaning in the imaging art to refer to a material having first and second display states differing in at least one optical property, the material being changed from its first to its second display state by application of an electric field to the material.
  • the electro-optic medium may be a solid (such displays may hereinafter for convenience be referred to as "solid electro-optic displays"), in the sense that the electro-optic medium has solid external surfaces, although the medium may, and often does, have internal liquid- or gas-filled spaces.
  • solid electro-optic displays includes encapsulated electrophoretic displays, encapsulated liquid crystal displays, and other types of displays discussed below.
  • the optical property may be color perceptible to the human eye, it may be another optical property, such as optical transmission, reflectance, luminescence or, in the case of displays intended for machine reading, pseudo-color in the sense of a change in reflectance of electromagnetic wavelengths outside the visible range.
  • gray state is used herein in its conventional meaning in the imaging art to refer to a state intermediate two extreme optical states of a pixel, and does not necessarily imply a black-white transition between these two extreme states.
  • extreme states are white and deep blue, so that an intermediate "gray state” would actually be pale blue. Indeed, as already mentioned the transition between the two extreme states may not be a color change at all.
  • bistable and “bistability” are used herein in their conventional meaning in the art to refer to displays comprising display elements having first and second display states differing in at least one optical property, and such that after any given element has been driven, by means of an addressing pulse of finite duration, to assume either its first or second display state, after the addressing pulse has terminated, that state will persist for at least several times, for example at least four times, the minimum duration of the addressing pulse used to change the state of the display element. It is shown in published U.S. Patent Application No.
  • the term "remnant voltage” is used herein to refer to a persistent or decaying electric field that may remain in an electro-optic display after an addressing pulse (a voltage pulse used to change the optical state of the electro-optic medium) is terminated.
  • the rate of decay of a remnant voltage of an electro-optic display may become low as the remnant voltage approaches a threshold value.
  • Even low remnant voltages e.g., remnant voltages of approximately 200 mV or less
  • remnant impulse to the electro-optic medium, and strictly speaking this remnant impulse, rather than the remnant voltage, may be responsible for the effects on the optical states of electro-optic displays normally considered as caused by remnant voltage.
  • remnant voltages can lead to undesirable effects on the images displayed on electro-optic displays, including, without limitation, so-called “ghosting” phenomena, in which, after the display has been rewritten, traces of the previous image are still visible.
  • a "shift" in the optical state associated with an addressing pulse refers to a situation in which a first application of a particular addressing pulse to an electro-optic display results in a first optical state (e.g., a first gray tone), and a subsequent application of the same addressing pulse to the electro-optic display results in a second optical state (e.g., a second gray tone).
  • Remnant voltages may give rise to shifts in optical state because the voltage applied to a pixel of the electro-optic display during application of an addressing pulse includes the sum of the remnant voltage and the voltage of the addressing pulse.
  • a “drift" in the optical state of a display over time refers to a situation in which the optical state of an electro-optic display changes while the display is at rest (e.g., during a period in which an addressing pulse is not applied to the display). Remnant voltages may give rise to drifts in optical state because the optical state of a pixel may depend on the pixel's remnant voltage, and a pixel's remnant voltage may decay over time.
  • edge ghosting refers to a situation in which, after the electro- optic display has been rewritten, traces of the previous image(s) are still visible. Remnant voltages may give rise to "edge ghosting," a type of ghosting in which an outline (edge) of a portion of a previous image remains visible.
  • impulse is used herein in its conventional meaning in the imaging art of the integral of voltage with respect to time.
  • bistable electro-optic media act as charge transducers, and with such media an alternative definition of impulse, namely the integral of current over time (which is equal to the total charge applied) may be used.
  • the appropriate definition of impulse should be used, depending on whether the medium acts as a voltage-time impulse transducer or a charge impulse transducer.
  • electro-optic displays are known.
  • One type of electro-optic display is a rotating bichromal member type as described, for example, in U.S. Pat. Nos. 5,808,783; 5,777,782; 5,760,761 ; 6,054,071 6,055,091 ; 6,097,531; 6,128,124; 6,137,467; and 6,147,791 (although this type of display is often referred to as a "rotating bichromal ball" display, the term "rotating bichromal member" is preferred as more accurate since in some of the patents mentioned above the rotating members are not spherical).
  • Such a display uses a large number of small bodies (which may be, without limitation, spherical or cylindrical) which have two or more sections with differing optical characteristics, and an internal dipole. These bodies are suspended within liquid-filled vacuoles within a matrix, the vacuoles being filled with liquid so that the bodies are free to rotate. The appearance of the display is changed by applying an electric field thereto, thus rotating the bodies to various positions and varying which of the sections of the bodies is seen through a viewing surface.
  • This type of electro-optic medium may be bistable.
  • electro-optic display uses an electrochromic medium, for example an electrochromic medium in the form of a nanochromic film comprising an electrode formed at least in part from a semi-conducting metal oxide and a plurality of dye molecules capable of reversible color change attached to the electrode; see, for example O'Regan, B., et al., Nature 1991, 353, 737; and Wood, D., Information Display, 18(3), 24 (March 2002). See also Bach, U., et al., Adv. Mater., 2002, 14(11), 845. Nanochromic films of this type are also described, for example, in U.S. Pat. No. 6,301,038, International Application Publication No. WO 01/27690, and in U.S. Patent Application 2003/0214695. This type of medium may be bistable.
  • electro-optic display is the particle-based electrophoretic display, in which a plurality of charged particles move through a suspending fluid under the influence of an electric field.
  • Electrophoretic displays can have attributes of good brightness and contrast, wide viewing angles, state bistability, and low power consumption when compared with liquid crystal displays. Nevertheless, there may be problems with the long-term image quality of some particle-based electrophoretic displays. For example, particles that make up some electrophoretic displays may settle, resulting in inadequate service-life for such displays.
  • electrophoretic media may include a suspending fluid.
  • This suspending fluid may be a liquid, but electrophoretic media can be produced using gaseous suspending fluids; see, for example, Kitamura, T., et al., "Electrical toner movement for electronic paper-like display", IDW Japan, 2001, Paper HCSl-1, and Yamaguchi, Y., et al., "Toner display using insulative particles charged triboelectrically", IDW Japan, 2001, Paper AMD4-4).
  • Some gas-based electrophoretic media may be susceptible to the same types of problems as some liquid-based electrophoretic media due to particle settling, when the media are used in an orientation which permits such settling, for example in a sign where the medium is disposed in a vertical plane. Indeed, particle settling appears to be a more serious problem in some gas-based electrophoretic media than in some liquid-based ones, since the lower viscosity of gaseous suspending fluids as compared with liquid ones allows more rapid settling of the electrophoretic particles.
  • Encapsulated electrophoretic media comprise numerous small capsules, each of which itself comprises an internal phase containing electrophoretically-mobile particles in a fluid medium, and a capsule wall surrounding the internal phase. Typically, the capsules are themselves held within a polymeric binder to form a coherent layer positioned between two electrodes.
  • the charged particles and the fluid are not encapsulated within microcapsules but instead are retained within a plurality of cavities formed within a carrier medium, typically a polymeric film.
  • a carrier medium typically a polymeric film.
  • Electrophoretic particles, fluids and fluid additives see for example
  • a related type of electrophoretic display is a so-called "microcell
  • electrophoretic display In a microcell electrophoretic display, the charged particles and the suspending fluid are not encapsulated within microcapsules but instead are retained within a plurality of cavities formed within a carrier medium, e.g., a polymeric film. See, for example, International Application Publication No. WO 02/01281, and published U.S.
  • microcell electrophoretic displays can refer to all such display types, which may also be described collectively as “microcavity electrophoretic displays” to generalize across the morphology of the walls.
  • electro-optic display is an electro-wetting display developed by Philips and described in Hayes, R. A., et al., "Video-Speed Electronic Paper Based on Electrowetting," Nature, 425, 383-385 (2003). It is shown in copending application Ser. No. 10/711,802, filed Oct. 6, 2004, that such electro-wetting displays can be made bistable.
  • bistable ferroelectric liquid crystal displays are known in the art and have exhibited remnant voltage behavior.
  • electrophoretic media may be opaque (since, for example, in many electrophoretic media, the particles substantially block transmission of visible light through the display) and operate in a reflective mode
  • some electrophoretic displays can be made to operate in a so-called "shutter mode" in which one display state is substantially opaque and one is light-transmissive. See, for example, the patents U.S. Pat. Nos. 6,130,774 and
  • An encapsulated or microcell electrophoretic display may not suffer from the clustering and settling failure mode of traditional electrophoretic devices and may provide further advantages, such as the ability to print or coat the display on a wide variety of flexible and rigid substrates.
  • the word “printing” is intended to include all forms of printing and coating, including, but without limitation: pre-metered coatings such as patch die coating, slot or extrusion coating, slide or cascade coating, curtain coating; roll coating such as knife over roll coating, forward and reverse roll coating; gravure coating; dip coating; spray coating; meniscus coating; spin coating; brush coating; air knife coating; silk screen printing processes; electrostatic printing processes; thermal printing processes; inkjet printing processes; electrophoretic deposition; and other similar techniques.
  • pre-metered coatings such as patch die coating, slot or extrusion coating, slide or cascade coating, curtain coating
  • roll coating such as knife over roll coating, forward and reverse roll coating
  • gravure coating dip coating
  • spray coating meniscus coating
  • spin coating spin coating
  • brush coating air knife coating
  • silk screen printing processes electrostatic printing processes
  • thermal printing processes inkjet printing processes
  • electrophoretic deposition electrophoretic deposition
  • the bistable or multi-stable behavior of particle-based electrophoretic displays, and other electro-optic displays displaying similar behavior is in marked contrast to that of liquid crystal displays ("LCDs"). Twisted nematic liquid crystals are not bi- or multi-stable but act as voltage transducers, so that applying a given electric field to a pixel of such a display produces a specific gray level at the pixel, regardless of the gray level previously present at the pixel.
  • LC displays are only driven in one direction (from non-transmissive or “dark” to transmissive or “light”), the reverse transition from a lighter state to a darker one being effected by reducing or eliminating the electric field.
  • the gray level of a pixel of an LC display is not sensitive to the polarity of the electric field, only to its magnitude, and indeed for technical reasons commercial LC displays usually reverse the polarity of the driving field at frequent intervals.
  • bistable electro- optic displays act, to a first approximation, as impulse transducers, so that the final state of a pixel depends not only upon the electric field applied and the time for which this field is applied, but also upon the state of the pixel prior to the application of the electric field.
  • a high-resolution display may include individual pixels which are addressable without interference from adjacent pixels.
  • One way to obtain such pixels is to provide an array of non-linear elements, such as transistors or diodes, with at least one non-linear element associated with each pixel, to produce an "active matrix" display.
  • An addressing or pixel electrode, which addresses one pixel, is connected to an appropriate voltage source through the associated non-linear element.
  • the non-linear element is a transistor
  • the pixel electrode may be connected to the drain of the transistor, and this arrangement will be assumed in the following description, although it is essentially arbitrary and the pixel electrode could be connected to the source of the transistor.
  • the pixels may be arranged in a two-dimensional array of rows and columns, such that any specific pixel is uniquely defined by the intersection of one specified row and one specified column.
  • the sources of all the transistors in each column may be connected to a single column electrode, while the gates of all the transistors in each row may be connected to a single row electrode; again the assignment of sources to rows and gates to columns may be reversed if desired.
  • the display may be written in a row-by-row manner.
  • the row electrodes are connected to a row driver, which may apply to a selected row electrode a voltage such as to ensure that all the transistors in the selected row are conductive, while applying to all other rows a voltage such as to ensure that all the transistors in these non-selected rows remain non-conductive.
  • the column electrodes are connected to column drivers, which place upon the various column electrodes voltages selected to drive the pixels in a selected row to their desired optical states.
  • the aforementioned voltages are relative to a common front electrode which may be provided on the opposed side of the electro-optic medium from the non-linear array and extends across the whole display.) After a pre-selected interval known as the "line address time,” a selected row is deselected, another row is selected, and the voltages on the column drivers are changed so that the next line of the display is written.
  • a preferred embodiment for dissipating remnant voltage brings all pixel transistors into conduction for an extended time.
  • all pixel transistors may be brought into conduction by bringing gate line (as referred to herein as "select line”) voltage relative to the source line voltages to values that bring pixel transistors to a state where they are relatively conductive compared to the non- conductive state used to isolate pixels from source lines as part of normal active-matrix drive.
  • a specially designed circuitry may provide for addressing all pixels at the same time.
  • select line control circuitry typically does not bring all gate lines to values that achieve the above- mentioned conduction state for all pixel transistors.
  • a convenient way to achieve this condition is afforded by select line driver chips that have an input control line that allows an external signal to impose a condition where all select line outputs receive a voltage supplied to the select driver chosen to bring pixel transistors into conduction. By applying the appropriate voltage value to this special input control line, all transistors may be brought into conduction.
  • some select drivers have a "Xon" control line input.
  • the gate on voltage is routed to all the select lines.
  • the description of this invention is written for backplane that employs n-type pixel transistors. In this case the gate on voltage is positive.
  • backplane made with p-type pixel transistors all the methods described here can be employed by inverting all the voltages described and shown in this invention. In this case the gate on voltage would be negative.
  • the gate on voltage is an important voltage for the purpose of dissipating remnant voltage of an electro-optic active matrix display.
  • Application of the gate on voltage across the entire display is integral to the "post-drive discharge” which is typically applied at the end of the "active drive phase” (also referred to herein as “image update” or “active update period”).
  • the "post-drive discharge phase” (also referred to herein as “remnant voltage discharge phase” or “remnant voltage discharging”) is part of the "voltage decay phase” and, if the post-drive discharge phase is equal to the voltage decay phase, these terms may be used interchangeably (and herein are used interchangeably).
  • Post-drive discharging may be performed after every active update, after a specified number of active updates, after a specified period of time or when requested by a user. Further, post-drive discharging may be interrupted by an active update such that the gate on voltage value may not reach a zero value.
  • the present invention describes apparatuses and methods for adjusting the gate on voltage value after the active update phase.
  • Electro-optic displays may receive power from external electronics, such as a display controller and supply voltages from "power management” circuitry.
  • the power management circuitry may supply multiple voltages, including “gate on voltage” supplied to gate lines (also referred to herein as “select lines") to bring transistors on selected lines into conduction.
  • the power management circuitry may be discrete components or an integrated circuit (e.g., Power Management Integrated Circuit (“PMIC”)). Additional circuitry may include pulldown resistor(s) and/or pulldown capacitor(s).
  • FIG. 1A is a schematic of a simple gate on voltage electrical circuit of an electro-optic display using a PMIC 102 that shows the gate on voltage line 104 from the PMIC 102 to the gate driver 106 of the active matrix display.
  • the circuitry of FIG. 1 allows for controlling the gate on voltage 104 at the end of an active drive by changing the value of the pull down resistor R 108.
  • a high value for R 108 would slow the gate on voltage decay rate while a low value of R 108 would speed up the gate on voltage decay rate.
  • the pulldown resistor (“R") 108 will cause the gate on line 104 to decay exponentially to zero volts with a time constant given by the resistor value ("R") times the line capacitance (“C”).
  • the voltage decay through the R resistor 108 may be calculated as follows:
  • V 0 is the initial voltage and where the line capacitance C includes the parasitic capacitance of the voltage line and any capacitance that designed as part of the PMIC to stabilize the voltage.
  • 62/111,927 takes advantage of the slow decay in the gate on voltage.
  • the gate on voltage is allowed to decay typically through resistors connected to ground.
  • all active-matrix select lines are brought to the gate on voltage, which decay to ground from its value during active display driving.
  • FIG. IB is a graph showing gate on voltage versus time during an active update and a voltage decay phase, which includes a post-drive discharge phase, where the gate on voltage decays exponentially to ground.
  • a "post-drive discharge" period is defined as starting at a time ti and ending at a time t 2 .
  • the time ti may be as small as zero, in which case the post-drive discharge begins immediately after the update, or may be delayed until the gate on voltage value decays or decreases to a preferred value.
  • the time t 2 is chosen to be large enough that the post-drive discharge is effective in sufficiently reducing charge polarization in the display or, if time allows, until the gate on voltage decays to zero volts.
  • This invention controls the "gate on” voltage to achieve these advantages by shaping the time profile of the "gate on” voltage during the post-drive discharge phase.
  • the invention makes use of a metric, K, which is useful for assessing the advantageous nature of the "gate on” voltage profile during the post-drive discharge phase:
  • T m is the total time that the "gate on” voltage lies between a low voltage magnitude (V L ) and a high voltage magnitude (V H ) within a time domain starting at the end of a display update and up to a time t 2 after the end of the update
  • Th is the total time that the "gate on” voltage is greater than VH
  • t 2 is the time of the end of post-drive discharge when it is not interrupted by other display processes such as a next image update.
  • the values VL and VH may be later defined or bounded based upon display performance and usage. Assigning values for VL and VH is described in more detail below.
  • the voltages are defined relative to another voltage and are all relative to the "zero voltage” or “ground” for the driving electronics (source and/or select drivers and display controller).
  • Natural K (Knatura ) may be define as:
  • Vo is the "gate on” voltage applied during an image update or active update (as described above, all voltages are defined relative to the "gate off voltage for the display under consideration).
  • a normalized K referred to here as a:
  • K, K na turai and alpha are all functions of the time ti and voltage parameters VL and VH.
  • a preferred voltage profile has alpha greater than 2, alpha greater than 5 or, preferably, alpha greater than 20, and where the values of VL and VH meet at least 2 of the following constraints: 1) VL is at least 5% of Vo; 2) VH is at less than 80% of Vo; 3) VH is greater than VL; and 4) (VH - VL)/[( VH + VL)/2] > 0.1.
  • the fourth constraint may be met to assure that the separation between VH and VL is significant compared to the average of VH and VL.
  • FIG. 1C is a graph showing gate on voltage versus time during an active update and a voltage decay phase having a preferred voltage profile.
  • the dashed line previously depicted and described in FIG. IB, shows a typical exponential decay after an active update.
  • the solid line shows an example of a more advantageous voltage profile of a post-drive discharge phase where the gate on voltage value rapidly decays or is reduced to a lower value, then decays from this reduced value over time of post-drive discharge.
  • the initial rapid reduction of the gate on value after the active update is completed prior to "turning on" all the select lines.
  • all select lines may be turned on after the gate on voltage value is initially reduced and has decayed to a desired value or after a predetermined time. All select lines may be turned off (t 2 ) after post-drive discharge is effective in sufficiently reducing charge polarization in the display or, alternatively, after the gate on voltage decays to zero volts.
  • FIG. 2 A is a schematic of the simple electrical circuit layout of FIG. 1 A further comprising a "single pole, single throw” switch (“SWl") 210 (which, as shown, is “open”) between the PMIC 202 and the gate driver 206.
  • SWl single pole, single throw switch
  • the circuit actively drives the gate driver 206.
  • the SWl switch 210 is opened (at the end of the active drive), the PMIC 202 will cease to drive the gate high voltage 206 and the gate on voltage decay rate will be determined by the pulldown resistor R 208 and the various capacitances experienced by the gate on line 204.
  • FIG. 2B is a graphical schematic depicting the gate on voltage over time of the circuit of FIG. 2A during the active drive phase 220 when the SWl switch is closed and the voltage decay phase 222 when the SWl switch is open.
  • FIG. 3A is a schematic of a gate on voltage electrical circuit according to an embodiment of the present invention.
  • FIG. 3A shows the gate on voltage line 304 with a first "single pole, single throw” switch (“SWl”) 310 from the PMIC 302 to the gate driver 306 of the active matrix display.
  • the circuitry further comprises a resistor R 308, a second "single pole, double throw” switch (“SW2") 312 (which, as shown, is at position "a”) and a pulldown capacitor (“Ci”) 314.
  • SWl and SW2 are programmed to open and close approximately simultaneously, such that only one switch will be engaged at a time.
  • SWl closes and SW2 opens during active display driving while SWl opens and SW2 closes during voltage decay phase and post-drive discharging.
  • SWl is an example of a single pole, single throw switch where it is only connected when the closed position.
  • SW2 is an example of a single pole, double throw switch where it switches between two points such that it is always connected to either position "a" or position "b".
  • the gate on voltage value may be reduced to a lower value and, then, may decay from this reduced voltage value.
  • the drive voltage (“V") decay may be calculated according to the following equation: [0094] where C is the line capacitance of the gate on line 304 and Vo is the initial voltage.
  • FIG. 3B is a graphical schematic depicting the gate on voltage over time for the circuit of FIG. 3A during the active drive phase 320, when the SWl switch is closed and the SW2 switch is in position "a", and the voltage decay phase 322, when the SWl switch is open and the SW2 switch is connected to position "b".
  • the PMIC drives the gate driver 306.
  • the voltage value is pulled quickly to a smaller voltage value (i.e., V 0 C/(C+Ci)) and decays from this smaller value 322 at a rate determined by pulldown resistor R 308 and capacitance of C and Ci.
  • FIG. 4A is a schematic of a gate on voltage electrical circuit according to another embodiment of the present invention.
  • FIG. 4A shows the gate on voltage line 404 with a first switch (“SWl") 410 from the PMIC 402 to the gate driver 406 of the active matrix display.
  • the circuitry further comprises a resistor R 408, a second switch (“SW2") 412 (which, as shown, is in position "a"), a pulldown capacitor (“Ci”) 414 and a second pulldown resistor (“Ri”) 416.
  • the pulldown capacitor Ci 414 and pulldown resistor Ri 416 are in series with SW2 412; however, their positions in relation to SW2 may be swapped.
  • the PMIC drives the gate driver 406 at the active drive gate on voltage value and charges capacitor Ci 414.
  • the gate on voltage value is reduced to the value of capacitor Ci 414 and decays at rate determined by resistors R 408 and Ri 416.
  • the addition of the capacitor Ci and resistors R and Ri allows for a greater degree of control over the initial reduction and the decay rate of the gate on voltage value.
  • FIG. 5A is a schematic of a gate on voltage electrical circuit according to another embodiment of the present invention that is equivalent to FIG. 3A.
  • FIG. 5A shows the gate on voltage line 504 with a first switch (“SWl") 510 from the PMIC 502 to the gate driver 506 of the active matrix display.
  • the circuitry further comprises a second single pole, double throw switch (“SW2") 512 (which, as shown, is in position "a") positioned on the gate on voltage line 504.
  • SW2 512 engages a pulldown resistor R 508 and a pulldown capacitor Ci 514.
  • the active drive phase as depicted in FIG. 3B 320
  • capacitor Ci 514 will be charged.
  • the voltage decay phase as depicted in FIG. 3B 322
  • the voltage value will initially drop to the value of capacitor Ci 514, then decay at a rate determined by resistor R 508.
  • the PMIC may drive the gate on voltage at +22 volts.
  • a gate on voltage value of +22 volts is excessive and a reduced gate high voltage value is preferred.
  • remnant voltage discharge may be achieved by using a voltage value of about +8 volts.
  • a preferred circuit of FIG. 5 A includes a capacitor Ci sufficient to bring the gate on voltage down quickly to about 10 to 12 volts after the active drive phase.
  • the preferred capacitor Ci value is about equal to the capacitance of the gate on line when it is attached to the display (SW2 is in position "b") but the PMIC is disconnected (SW1 is in position "b").
  • a single capacitance value Ci will not apply to all displays, but may be selected based on the desired initial voltage drop.
  • resistor R 508 a single resistor value will not apply to all displays, but may be selected based on the desired voltage decay rate.
  • FIG. 5B is a schematic of a gate on voltage electrical circuit according to another embodiment of the present invention that is equivalent to FIG. 4A.
  • FIG. 5B is a schematic of the electrical circuitry of FIG. 5A further comprising a pulldown resistor Ri 516.
  • SW2 512 engages a pulldown resistor R 508, pulldown capacitor Ci 514 and pulldown resistor Ri 516.
  • FIG. 6A is a schematic of a gate on voltage electrical circuit according to another embodiment of the present invention.
  • FIG. 6A shows the gate on voltage line 604 with a first switch (“SW1") 610 from the PMIC 602 to the gate driver 606 of the active matrix display.
  • the circuitry further comprises a pulldown resistor R 608, a pulldown capacitor (“Ci”) 614, a second pulldown resistor (“Ri”) 618, a second pulldown capacitor (“C 2 ”) 616, and a second switch (“SW2”) 612 (which, as shown, is “open”) positioned between the resistor Ri 618 and the pulldown capacitor C2 616.
  • the pulldown capacitor Ci 614, the pulldown resistor Ri 618 and the pulldown capacitor C2 616 are in series. [00102] When the PMIC brings the gate on line to V 0 volts by closing SW1 and opening SW2, the voltage across Ci rises to V 0 *C2/(Ci+C2).
  • the capacitors Ci and C2 are chosen to set this voltage to the low level desired during the post-drive discharge period.
  • the resistor Ri 618 is chosen to avoid current spikes that cannot be supported by the PMIC and the value of Ri could be 0 ohms, in which case Ri is not essential. It is also noted here that the position of Ri 618 and Ci 614 could be swapped.
  • the PMIC drives the gate driver 606 at the gate on voltage value for the active driving and charges capacitors Ci and C 2 , to voltage values that sum up to the "gate on" voltage value.
  • the gate on voltage value drops to the level of the voltage that was across Ci during the active drive and then decays from this lower value.
  • capacitors Ci and C2 and resistors R and Ri allow for a greater degree of control over the initial reduction in the gate on voltage value, both in time and amount of reduction, and the rate of decay after the initial drop in value. These values may be set to optimize the reduction in voltage value during the voltage decay phase, or one or both of these resistors could be removed from the electrical circuit.
  • FIG. 7 is a schematic of a gate on voltage electrical circuit according to another embodiment of the present invention.
  • FIG. 7 shows the gate on voltage line 704 with a first switch (“SW1") 710 from the PMIC 702 to the gate driver 706 of the active matrix display.
  • the circuitry further comprises a second switch (“SW2") 712 (which, as shown, is “open") positioned on the gate on voltage line 704.
  • SW2 712 engages a pulldown resistor R 708 and a Zener diode 714.
  • a Zener diode is a commercially available diode which allows current to flow in the forward direction in the same manner as an ideal diode, but also, allows it to flow in the reverse direction when the voltage is above a certain value (" breakdown voltage"). Zener diodes are available with different breakdown voltages and may be selected based on the desired breakdown voltage value for a particular display. A Zener diode is non-linear between voltage and current, but is predictable in how it reacts to voltage and current.
  • a Zener diode will quickly drop voltage when current is high but, once when the breakdown voltage is reached, the current shuts off. This is another way to quickly drop the gate on voltage value during the voltage decay phase. It may be desirable to use more than one Zener diode in place of the one shown in FIG 7. It is common practice to use a series of two or more Zener diodes in order to achieve a desired voltage above which the series of Zener diodes will conduct current. A series of Zener diodes may be employed to gain flexibility in choosing the voltage above which the voltage is dropped through conduction through the Zener diodes. In this case, the effective "breakdown voltage" of such a series of Zener diodes is the sum of the "breakdown voltage" of each of the constituent Zener diodes.
  • SW2 is "single pole, double throw” switch and relies upon capacitor value to achieve a desired voltage at the start of the post-drive discharge session.
  • SW2 is a "single pole, single throw” switch, which is much simpler. It uses a Zener diode to control the desired voltage, which gives more certain control of the voltage during the discharge phase than the circuits that employ capacitors to control the voltage during the discharge phase.
  • the resistor in the diagram is optional. We perhaps should show this example but also show one without the resistor or explain that the resistor value could be zero.
  • the power management circuitry (such as a power management integrated circuit, PMIC) may be configured to actively control the gate on voltage.
  • the gate on value may be set to allow pixels to be sufficiently charged to desired voltages for successful display operation.
  • the gate on voltage may be set to a reduced value where the lower magnitude is sufficient to achieve post-drive discharging.
  • the PMIC manages the gate on voltage control using a switch that switches the gate on voltage output to the display between a voltage value for actively driving the display and a different voltage value for post- drive discharging.
  • the switch is internal to the PMIC. In other embodiments, the switch and electrical circuitry is external to the PMIC.
  • FIG.8A illustrates yet another embodiment in accordance with the present subject matter presented herein.
  • FIG.8A illustrates a gate on voltage line 804 coupled to a first switch (“SWl") 810 from a PMIC to the gate driver 806 of an active matrix display, the SWl coupled to a first voltage source 812 configured to provide a first voltage to the display.
  • a second voltage source 816 usually a low voltage source, may also be coupled to the gate on voltage line 804 through a second switch (“SW2") 814 and configured to provide a second voltage to the active matrix display.
  • a capacitor C 818 and a resistor R 820 maybe connected in parallel in reference to the voltage line 804 and the gate driver 806 to provide greater control over the decay of the gate on voltage.
  • FIG. 8B illustrates the decay of the gate on voltage as configured by the circuit illustrated in FIG. 8A.
  • an active phase 840 When SWl is closed and SW2 is in a position "a"
  • the PMIC drives the display at the active drive gate on voltage value and charges capacitor C 818.
  • a second active phase 842 When SWl is in a position "b" and SW2 is closed, the PMIC drives the display at a voltage that dictated by the second voltage source 816.
  • the display is driven at a voltage level approximate to the voltage value supplied by the second voltage source 816, and the capacitor C 818 is charged or discharged accordingly in reference to the second voltage source 816's voltage value.
  • the gate on voltage is designed to decay at a rate determined by a combination of capacitor C 818 and Resistor R 820. This configuration allows for a faster initial reduction in the gate on voltage and thus expedites the overall decay process and improves the device reliability.
  • the subject matter described herein also provides methods of driving a bistable electro-optic display having a plurality of pixels in an active matrix array.
  • active matrix transistors are available commercially, including amorphous silicon, microcrystalline, polysilicon, and organic among others.
  • Transistors in an active matrix display are typically designed to support an ON:OFF ratio of 1: 1000 as most active matrix displays have about 1000 rows.
  • n-channel n-type
  • a-Si TFT amorphous silicon thin film transistor
  • the transistor is in its ON state (row is selected) when there is a positive voltage on the gate-to-source and is in its OFF state when there is a negative voltage on the gate-to- source.
  • n-type thin film pixel transistors typically experience a positive to negative charge ratio of 1 : 1000.
  • p-channel a-Si TFT in an active matrix display, the voltage polarity is reversed.
  • the p-type transistor is in its ON state when there is a negative voltage on the gate-to-source and is in its OFF state when there is a positive voltage on the gate-to-source.
  • p-type thin film pixel transistors typically experience a negative to positive charge ratio of 1 : 1000.
  • the ON:OFF ratio is altered so that the transistor is ON more often than the normal ratio, the transistor may degrade and adversely affect the optical performance of the display.
  • Amorphous silicon transistors are highly susceptible to degradation due to atypical charge biasing.
  • One method for reducing this type of transistor degradation is to standardize the ON: OFF ratio by turning the transistor to its OFF position so that the ON: OFF ratio will be closer to its typical value of 1: 1000, as described more fully herein.
  • a remnant voltage of a pixel of an electro-optic display may be discharged by activating the pixel's transistor (i.e., turning all transistors ON) and setting the voltages of the front and rear electrodes of the pixel to approximately a same value for a period of time.
  • the amount of remnant voltage discharged by a pixel during a remnant voltage discharge pulse may depend, at least in part, on the rate at which the pixel discharges the remnant voltage, and on the duration of the remnant voltage discharge pulse.
  • the duration of the period during which a remnant voltage discharge pulse is applied may be at least 50 ms, at least 100 ms, at least 300 ms, at least 500 ms, at least 1 sec or any other suitable duration.
  • all pixel transistors may be brought into conduction by bringing gate line voltage relative to the source line voltages to values that bring pixel transistors to a state where they are relatively conductive compared to the non-conductive state used to isolate pixels from source lines as part of normal active-matrix drive.
  • this may be achieved by bringing gate lines to values substantially higher than source line voltage values.
  • p-type thin film pixel transistors this may be achieved by bringing gate lines to values substantially lower than source line voltage values.
  • all pixel transistors may be brought into conduction by bringing gate line voltages to zero and source line voltages to a negative (or, for p-type transistors, a positive) voltage.
  • select line control circuitry typically does not bring all gate lines to values that achieve the above-mentioned conduction state for all pixel transistors.
  • select line driver chips that have an input control line that allows an external signal to impose a condition where all select line outputs receive a voltage supplied to the select driver chosen to bring pixel transistors into conduction.
  • select driver chips By applying the appropriate voltage value to this special input control line, all transistors may be brought into conduction.
  • some select drivers have a "Xon" control line input. By choosing a voltage value to input to the Xon pin input to the select drivers, the "gate high" voltage is routed to all the select lines and turns all transistors to the ON state.
  • the positive to negative charge ratio experienced by, for example, the n-type transistors may change from approximately 1: 1000 to approximately 1 : 10 or even 1 :1.
  • This atypical charge bias may cause transistor degradation and reduced display performance.
  • the current and voltage ("IV") curve of a display shifts in value. If the IV curve shifts to a higher value, more voltage is needed to activate the transistor switch. The effect of the shift in the IV curve may be shown by optically measuring resultant graytone shift and ghosting shift in display reflectance
  • Graytone Placement measures the optical state resulting from applying the 16 transitions to all possible graytones (including black and white) when starting from a white image
  • graytone placement shift is the absolute value of the maximum L* shift over the 16 graytones at time k, which may be defined by the number of sequences, minus the graytone shift at time zero.
  • GTP shift is an absolute measurement of the 16 transitions.
  • Ghosting measures the remaining 240 transitions from all possible 16 graytones except white to all possible 16 graytones, and subtracts the GTP value for the final displayed graytone. That is, the ghost measurement compares the optical state of a graytone when it transitions from a non-white graytone to the optical state of that same graytone when it transitions from white.
  • ghost shift is the absolute value of the maximum ghosting at time k, which may be defined by the number of sequences, minus the ghosting at time zero.
  • ghost shift is a relative measurement based on GTP values.
  • FIG. 1 OA is a graph showing the results of an accelerated reliability test at 45 degrees Celsius measuring the optical response shift by maximum absolute graytone shift against the number of updates with remnant voltage discharging 1002 and without remnant voltage discharging 1004, according to some embodiments.
  • Each usage year is assumed to have 50,000 updates.
  • the additional ON time the transistor experiences as a result of the remnant voltage discharging results in a significant graytone shift of approximately 2 L* after approximately 100,000 updates (or over approximately two years).
  • FIG. 10B is a graph showing the results of an accelerated reliability test at 45 degrees Celsius measuring the optical response shift by maximum absolute ghost shift against the number of updates with remnant voltage discharging 1006 and without remnant voltage discharging 1008, according to some embodiments.
  • Each usage year is assumed to have 50,000 updates.
  • the additional ON time the transistor experiences as a result of the remnant voltage discharging results in a significant ghost shift of approximately 3 L* after approximately 100,000 updates (or over
  • FIG. 11 A is a graph showing the results of an accelerated reliability test at 45 degrees Celsius measuring the optical response shift by maximum absolute graytone shift against the number of updates with remnant voltage discharging 1102, without remnant voltage discharging 1104, and with remnant voltage discharging and standardization of the ON:OFF ratio 1110, according to some embodiments.
  • Each usage year is assumed to have 50,000 updates.
  • the additional ON time the transistor experiences as a result of the remnant voltage discharging 1102 results in a significant graytone shift of approximately 2 L* after approximately 100,000 updates (or over approximately two years) as compared to updates without the discharging 1104.
  • updates with remnant voltage discharging are standardized or offset by turning the transistors to the OFF position for an additional period of time 1110, the resulting of graytone shift after approximately 100,000 updates is only about 0.25 L* as compared to updates without the discharging 1104.
  • FIG. 1 IB is a graph showing the results of an accelerated reliability test at 45 degrees Celsius measuring the optical response shift by maximum absolute ghost shift against the number of updates with remnant voltage discharging 1106, without remnant voltage discharging 1108, and with remnant voltage discharging and standardization of the ON:OFF ratio 1112, according to some embodiments.
  • Each usage year is assumed to have 50,000 updates.
  • the additional ON time the transistor experiences as a result of the remnant voltage discharging 1106 results in a significant ghost shift of approximately 3 L* after approximately 100,000 updates (or over
  • FIG. 12A is a schematic signal-timing diagram showing the gate voltage against time, according to some embodiments.
  • FIG. 12A depicts applied gate voltage over time diagram for one optical update, which includes an active update period 1202 - each positive and negative transition reflects a single frame in a series of multiple frames during the active update period, an remnant voltage discharge (ON state) period 1204, and an OFF state period, in an active matrix display having n-type transistors.
  • an n-type transistor a positive gate voltage is applied to achieve an ON state 1204 while a negative voltage is applied to achieve an OFF state 1206.
  • the active update period may be 500 ms
  • the ON period may be lsec
  • the OFF period may be 2 sees.
  • the remnant voltage discharge pulse (ON state) 1204 is run after the active update (i.e., optical update) 302 to drain residual charge.
  • the OFF state is run after the ON state to achieve an ON: OFF ratio closer to the typical 1 : 1000 ratio. While the 1: 1000 ratio may not be achieved, an ON:OFF ratio that approximates the 1 : 1000 ratio, even if it is only 1 : 10, will reduce transistor degradation.
  • FIG. 12B is a schematic signal-timing diagram showing multiple voltages against time with a display utilizing an Xon connection to turn ON all transistors
  • FIG. 12B depicts applied voltages over time diagram for one optical update, which includes an active update period 1202, an remnant voltage discharge (ON state) period 1204, and an OFF state period, in an active matrix display having n-type transistors.
  • the four voltages shown are high level gate line voltage (“VDDH”) 1212, low level gate line voltage (“VEE”) 1218, front electrode voltage
  • VCOM voltage 1216 and Xon voltage 1214.
  • Each voltage has a separate zero voltage axis which is depicted as a solid gray line. Voltages above the solid gray line indicate positive voltages while voltages below the solid gray line indicate negative voltages.
  • FIG. 12B the overall gate voltage depicted in FIG. 12A is a combination of VDDH and VEE voltages.
  • the gate driver output enabled voltage (VGDOE) (not shown), which controls which gate voltage (i.e., VEE or VDDH) is applied.
  • the Xon voltage activates all transistors simultaneously when brought to ground, which turns all transistors ON during the discharge period 1204.
  • VDDH is brought to ground and the transistors experience the applied VEE (negative voltage), which is controlled to approach zero towards the end of the period.
  • VEE negative voltage
  • the ON:OFF ratio more closely reflects its typical value of 1: 1000. While maintaining the ON:OFF ratio at 1 : 1000 is preferred, any ON:OFF period that moves the ratio towards its typical value, even if it is only 1: 10, 1 :50 or 1 : 100, may prevent transistor degradation.
  • the OFF period adds time to each update.
  • the OFF period may be preassigned a definite amount of time, may be determined by a controller based on the frequency of updates and/or may be interrupted.
  • the OFF period preferably occurs after the ON period, but may occur at other times, including before an active update period.
  • the OFF period may range from 500 ms to 4 sec, preferably from 1 sec to 2 sees.
  • the OFF period may be extended to up to 10 sees.

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Abstract

L'invention concerne un appareil pour piloter un dispositif d'affichage électro-optique, lequel appareil peut comprendre un premier commutateur conçu pour fournir une tension au dispositif d'affichage électro-optique durant une première phase de pilotage, un second commutateur conçu pour commander la tension durant une seconde phase de pilotage et une résistance couplée aux premier et second commutateurs pour commander la vitesse de chute de la tension durant la seconde phase de pilotage.
PCT/US2016/052032 2015-09-16 2016-09-16 Appareil et procédés pour piloter des dispositifs d'affichage WO2017049020A1 (fr)

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CN202110538254.9A CN113241041B (zh) 2015-09-16 2016-09-16 用于驱动显示器的装置和方法
JP2018513624A JP6871241B2 (ja) 2015-09-16 2016-09-16 ディスプレイを駆動するための装置および方法
CN201680053155.9A CN108028034B (zh) 2015-09-16 2016-09-16 用于驱动显示器的装置和方法
EP16847345.2A EP3350798B1 (fr) 2015-09-16 2016-09-16 Appareil et procédés pour piloter des dispositifs d'affichage
KR1020187007515A KR102158965B1 (ko) 2015-09-16 2016-09-16 디스플레이들을 구동하기 위한 장치 및 방법들
KR1020207026733A KR102308589B1 (ko) 2015-09-16 2016-09-16 디스플레이들을 구동하기 위한 장치 및 방법들
HK18107010.1A HK1247729A1 (zh) 2015-09-16 2018-05-29 用於驅動顯示器的裝置和方法

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US15/014,236 2016-02-03
US15/014,236 US10475396B2 (en) 2015-02-04 2016-02-03 Electro-optic displays with reduced remnant voltage, and related apparatus and methods
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US11257445B2 (en) * 2019-11-18 2022-02-22 E Ink Corporation Methods for driving electro-optic displays
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EP3350798B1 (fr) 2023-07-26
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CN108028034B (zh) 2021-06-04
CN113241041A (zh) 2021-08-10
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EP3350798C0 (fr) 2023-07-26
KR102158965B1 (ko) 2020-09-23
KR102308589B1 (ko) 2021-10-01
KR20200110475A (ko) 2020-09-23
KR20180030949A (ko) 2018-03-26
EP3350798A4 (fr) 2019-06-05
TW201719616A (zh) 2017-06-01
JP6871241B2 (ja) 2021-05-12
CN108028034A (zh) 2018-05-11
CN113241041B (zh) 2024-01-05
EP3350798A1 (fr) 2018-07-25

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