WO2017045352A1 - 显示基板及其驱动方法、显示装置 - Google Patents

显示基板及其驱动方法、显示装置 Download PDF

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Publication number
WO2017045352A1
WO2017045352A1 PCT/CN2016/073873 CN2016073873W WO2017045352A1 WO 2017045352 A1 WO2017045352 A1 WO 2017045352A1 CN 2016073873 W CN2016073873 W CN 2016073873W WO 2017045352 A1 WO2017045352 A1 WO 2017045352A1
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Prior art keywords
gate
data
control
pixel
strobe
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PCT/CN2016/073873
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English (en)
French (fr)
Inventor
孙拓
马占洁
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京东方科技集团股份有限公司
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Priority to US15/325,053 priority Critical patent/US10373547B2/en
Publication of WO2017045352A1 publication Critical patent/WO2017045352A1/zh

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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a display substrate, a driving method thereof, and a display device.
  • each data line is connected to a column of pixels (the pixel here refers to the smallest unit for performing illumination control, which corresponds to a minimum defined by two adjacent data lines and two adjacent gate lines). Area), each data line is connected to the data voltage input in the fan-out area.
  • the display device In a relatively large display device such as a display, a mobile phone, or a PAD, the display device has a large head space, and can provide a fan-out area with a large area, thereby accommodating a sufficient number of data lines at the position.
  • some small-shaped display devices such as smart watches
  • it is required to greatly compress the head space, and in order to accommodate each data line, the fan-out area cannot be designed too small, which increases the design of the display device. Difficulty.
  • the present invention provides a display substrate including a substrate and a plurality of data lines, a plurality of gate lines and a plurality of pixels formed on the substrate, and having a plurality of data voltage input terminals; the display substrate The method further includes a plurality of gate switch arrays and a plurality of gate control circuits formed on the substrate, and having a plurality of gate control signal inputs; wherein
  • Each strobe switch array includes a plurality of strobe switches, a first end of each strobe switch is connected to a corresponding one of the data lines, and a second end of each strobe switch is connected to the same data voltage input end, each The control terminals of the strobe switch are connected to the same strobe control circuit; each data line connected to the strobe switch array is connected to two columns of pixels, and the gate lines connected to one column of the two columns of pixels are connected to the other column of pixels Different grid lines;
  • Each of the gate control circuits is connected to the plurality of gate control signal inputs and the corresponding one of the gate switch arrays, and is adapted to connect the connected gate switches under the control of the gate control signals input by the gate control signal input terminals
  • Each of the strobe switches in the array is timed on.
  • the gate control signal input end includes a strobe signal input end and a control Signal input terminal;
  • Each of the gate control circuits includes a plurality of gate control switch groups, each of the gate control switch groups includes two gate control switches, and the first ends of the two gate control switches are connected to the control terminals of the same gate switch.
  • the second ends of the two gate control switches are respectively connected to the corresponding gate signal input terminals, and the control terminals of the two gate control switches are respectively connected to the corresponding control signal input terminals; and each of the gate control circuits
  • the strobe signal input terminals connected to the strobe control switch are different from each other, and the strobe switches connected to the respective strobe control switch groups are different from each other.
  • each of the gate control circuits corresponds to two control signal inputs, and a control terminal of one of the gate control switches is connected to one of the two control signal inputs.
  • the control terminal of the other gate control switch is connected to the other of the two control signal inputs.
  • the display substrate further includes a pixel driving circuit and a data voltage writing control line formed on the substrate;
  • Each pixel includes a pixel driving circuit, the pixel driving circuit is connected to the data line and the gate line corresponding to the pixel, and is connected to the data voltage writing control line, and the pixel driving circuit is adapted to be under the control of the data voltage writing control line Writing a data voltage applied to the data line connected to the pixel driving circuit to the first node, writing the data voltage to the second node under the control of the gate line, and generating the voltage according to the voltage of the second node The current that drives the pixel.
  • one column of the two columns of pixels connected to the same data line is misaligned with the other column of pixels.
  • the present invention also provides a method for driving the above display substrate, comprising:
  • Gating control connected to the gate control circuit connected to the gate switch array for the gate switch array to which the plurality of pixels are connected when refreshing a plurality of pixels connected to each gate line
  • a strobe control signal is applied to the signal input terminal to make each strobe switch in the strobe switch array turn on and off, and when each strobe switch is turned on, the data voltage input connected to the strobe switch array is input. Applying a data voltage corresponding to a pixel connected to the data line to which the gate switch is connected; and applying a gate scan signal on the gate line to write a data voltage applied to the data voltage input terminal Corresponding pixels.
  • the method further includes: after receiving the pixel data sent by the host, The order in which each pixel is connected to the data voltage input terminal is determined according to a preset gate line turn-on sequence and a gate switch turn-on sequence, and the received pixel data is rearranged according to the determined order.
  • the method further includes: when a data voltage corresponding to a pixel connected to the data line connected to the strobe switch is applied to the data voltage input terminal connected to the strobe switch array, where the pixel is connected Applying a control signal to the data voltage write control line, causing the data voltage applied to the data voltage input terminal to be written to the first node;
  • applying a gate scan signal on the gate line and writing a data voltage applied to the data voltage input terminal to the corresponding pixel comprises:
  • a gate scan signal is applied to the gate lines such that a data voltage written to a first node of each pixel is written to a second node of the pixel.
  • the present invention further provides a display driving system comprising: a gate driving circuit, a gate driving circuit and a data driving circuit; wherein, when refreshing a plurality of pixels connected to each gate line:
  • the gate driving circuit is configured to apply a gate on a gate control signal input terminal connected to the gate control circuit connected to the gate switch array for the gate switch array to which the plurality of pixels are connected Controlling a signal such that each of the strobe switches in the strobe switch array is timed on;
  • the data driving circuit is configured to apply, when each of the strobe switches is turned on, a data corresponding to a pixel connected to the data line connected to the strobe switch on the data voltage input end connected to the strobe switch array Voltage;
  • the gate driving circuit is configured to apply a gate scan signal on the gate line to write a data voltage applied to the data voltage input terminal into a corresponding pixel.
  • the data driving circuit includes a rearrangement module, configured to determine, according to a preset gate line conduction sequence and a gate switch conduction sequence, each pixel is connected to the data voltage input after receiving the pixel data sent by the host. The order of the ends, and the received pixel data is rearranged according to the determined order.
  • the system further includes a logic control circuit, and the logic control circuit includes a rearrangement module, configured to follow a preset gate line conduction sequence and a gate switch conduction sequence after receiving the pixel data sent by the host. Determining the order in which each pixel is connected to the data voltage input, rearranging the received pixel data according to the determined order, and rearranging The latter data is input to the data drive circuit.
  • the logic control circuit includes a rearrangement module, configured to follow a preset gate line conduction sequence and a gate switch conduction sequence after receiving the pixel data sent by the host. Determining the order in which each pixel is connected to the data voltage input, rearranging the received pixel data according to the determined order, and rearranging The latter data is input to the data drive circuit.
  • the present invention also provides a display device comprising the above display substrate.
  • each data line is connected to two columns of pixels, and two columns of pixels connected to the same data line are connected to different gate lines, so that the corresponding drive display can be greatly compressed.
  • the number of data lines used makes it possible to reduce the area of the fan-out area required to accommodate the data lines, so that the corresponding display device can have a small head space, thereby making it possible to reduce the design difficulty of the corresponding display device.
  • a plurality of data lines are connected to the same input terminal, which is equivalent to driving the plurality of columns of pixels by using the same input terminal, thereby reducing the number of data driving circuits to be used and reducing the manufacturing cost of the display device. .
  • FIG. 1 is a schematic structural diagram of a display substrate according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic structural view of a pixel driving circuit
  • FIG. 3 is a timing diagram of key signals when the pixel circuit of FIG. 1 is driven
  • FIG. 5 is a flow chart showing a display driving method when the data driving circuit includes a rearrangement module
  • FIG. 6 is a flow chart of a display driving method when the logic control circuit includes a rearrangement module
  • FIG. 7 is a schematic structural diagram of a display substrate according to Embodiment 2 of the present invention.
  • the present invention provides a display substrate including a substrate and a plurality of data lines, a plurality of gate lines and a plurality of pixels formed on the substrate, and having a plurality of data voltage input terminals; the display substrate The method further includes a plurality of gate switch arrays and a plurality of gate control circuits formed on the substrate, and having a plurality of gate control signal inputs; wherein
  • Each strobe switch array includes a plurality of strobe switches, a first end of each strobe switch is connected to a corresponding one of the data lines, and a second end of each strobe switch is connected to the same data voltage input end, each The control terminals of the strobe switch are connected to the same strobe control circuit; each data line connected to the strobe switch array is connected to two columns of pixels, and one of the two columns of pixels The gate lines connected to the column pixels are different from the gate lines connected to the other column of pixels;
  • Each of the gate control circuits is connected to the plurality of gate control signal inputs and the corresponding one of the gate switch arrays, and is adapted to connect the connected gate switches under the control of the gate control signals input by the gate control signal input terminals
  • Each of the strobe switches in the array is timed on.
  • each data line is connected to two columns of pixels, and two columns of pixels connected to the same data line are connected to different gate lines, so that the corresponding drive display can be greatly compressed.
  • the number of data lines used makes it possible to reduce the area of the fan-out area required to accommodate the data lines, so that the corresponding display device can have a small head space, thereby making it possible to reduce the design difficulty of the corresponding display device.
  • a plurality of data lines are connected to the same data voltage input terminal, which is equivalent to driving the plurality of columns of pixels by using the same input terminal, thereby reducing the number of data driving circuits to be used and reducing the display device. production cost.
  • the present invention also provides a driving method of a display substrate, which can be used to drive the display substrate according to the first aspect, the method comprising:
  • Gating control connected to the gate control circuit connected to the gate switch array for the gate switch array to which the plurality of pixels are connected when refreshing a plurality of pixels connected to each gate line
  • a strobe control signal is applied to the signal input terminal to make each strobe switch in the strobe switch array turn on and off, and when each strobe switch is turned on, the data voltage input connected to the strobe switch array is input. Applying a data voltage corresponding to a pixel connected to the data line to which the gate switch is connected; and applying a gate scan signal on the gate line to write a data voltage applied to the data voltage input terminal Corresponding pixels.
  • the present invention further provides a display driving system comprising: a gate driving circuit, a gate driving circuit and a data driving circuit; when refreshing a plurality of pixels connected to each gate line:
  • the gate driving circuit is configured to apply a gate on a gate control signal input terminal connected to the gate control circuit connected to the gate switch array for the gate switch array to which the plurality of pixels are connected Controlling a signal such that each of the strobe switches in the strobe switch array is timed on;
  • the data driving circuit is configured to apply, when each of the strobe switches is turned on, a data corresponding to a pixel connected to the data line connected to the strobe switch on the data voltage input end connected to the strobe switch array Voltage;
  • the gate driving circuit is configured to apply a gate scan signal on the gate line to write a data voltage applied to the data voltage input terminal into a corresponding pixel.
  • the specific structure of the above display substrate may be various, and the corresponding driving method and manufacturing method may also be different, which will be described in detail below with reference to the accompanying drawings.
  • the display substrate provided by the present invention may include a plurality of gate switch arrays and a plurality of gate control circuits, each of which is connected to a data voltage input terminal and a gate control circuit.
  • the following description will be made in connection with the case where one of the gate switch arrays is connected to its corresponding data voltage input terminal and gate control circuit.
  • FIG. 1 is a schematic structural diagram of a partial area of a display substrate according to an embodiment of the present invention.
  • the display substrate includes: a substrate (not shown) and a plurality of data lines D1-D3 and two gate lines Gn_O and Gn_E formed on the substrate (n is any positive integer smaller than M, and M is the number of rows of the display substrate ), and a plurality of pixels P1-P6 located in the nth row.
  • the display substrate further has a data voltage input terminal Data in; wherein each data line is connected to two columns of pixels, and in each row, two pixels connected to the same data line are connected with different gate lines.
  • the data line D1 connects the two columns of pixels P1 and P2, and the pixel P1 is connected to the gate line Gn_O, and the pixel P2 is connected to the gate line Gn_E.
  • the display substrate further includes a gate switch array and a gate control circuit formed on the substrate.
  • the gate switch array includes three gate switches 101-103, and the gate control circuit includes six gate control switches 201-206.
  • the display substrate further has a plurality of gate control signal input terminals, and the gate control signal input terminals may include strobe signal input terminals MUX1, MUX2 Vietnamese MUX6, and control signal input terminals SW_E and SW_O.
  • Each of the three strobe switches corresponds to one data line, and the first end of each strobe switch is connected to a corresponding data line, and the second end of each strobe switch is connected to the data voltage input Data in.
  • the first end of the gate switch 101 is connected to the corresponding data line D1, and the second end thereof is connected to the data voltage input terminal Data in.
  • the six strobe control switches are divided into three strobe control switch groups, each strobe control switch group corresponding to one strobe switch; each strobe control switch group includes two strobe control switches, belonging to the same strobe control
  • the first ends of the two gate control switches of the switch group are connected to the control terminals of the corresponding gate switches, and the second ends of the two gate control switches belonging to the same gate control switch group are respectively connected to the corresponding ones.
  • the control terminals of the two gate control switches belonging to the same gate control switch group are respectively connected to the corresponding control signal input terminals.
  • the first ends of the two gate control switches 201 and 202 are both connected to the control terminal of the corresponding gate switch 101, the second end of the gate control switch 201 is connected to the gate signal input terminal MUX1, and the control terminal is connected with the control signal.
  • the input terminal SW_O; and the second end of the gate control switch 202 is connected to the strobe signal input terminal MUX4, and the control terminal thereof is connected to the control signal input terminal SW_E.
  • the display substrate in FIG. 1 may be, for example, an AMOLED display substrate or a liquid crystal display substrate.
  • the pixel driving circuit and the data voltage writing control line formed on the substrate may be further included.
  • Each pixel driving circuit is connected to a pixel and a data line and a gate line connected to the pixel, and is connected to the data voltage writing control line, and is adapted to be applied to the pixel driving circuit under the control of the data voltage writing control line.
  • the data voltage on the data line is written to the first node, the data voltage is written to the second node under the control of the gate line, and the current for driving the pixel is generated according to the voltage of the second node.
  • the specific structure of such a pixel driving circuit can be various, such as shown in FIG. 2 is a common pixel driving circuit.
  • the pixel driving circuit has a first node N1 and a second node N2.
  • the first node N1 and the second node N2 are both connected to the capacitor C and connected to different plates of the capacitor C.
  • the second node N2 is also connected to the driving transistor.
  • the gate of the DT In the pixel driving circuit, the gate of the first switching transistor T1 is connected to the data voltage write control line En, the source is connected to the data line Dm, and the drain is connected to the first node N1.
  • the first transistor T1 can be turned on by applying a corresponding control signal on the data voltage write control line En, thereby writing the data voltage applied to the data line Dm to the first node N1. Then, by floating the second node N2, a gate scan driving signal is applied on the gate line Gn connected to the gate of the switching transistor T2 to which the first node N1 is connected to turn on the switching transistor T2, and the switch is turned on.
  • the source Ref of the transistor T2 applies another voltage, and the voltage of the second node N2 can be jumped, so that the data voltage written to the first node N1 is written into the second node N2.
  • the detailed process of operation of the pixel driving circuit shown in FIG. 2 will not be described in detail herein.
  • the data connected to each pixel connected to the gate line Gn_O may be first refreshed in the manner shown in FIG. 3, and then connected to the gate line Gn_E.
  • Each pixel performs data refresh.
  • a strobe signal may be sequentially applied to each strobe signal input terminal to which the gate control switches 201, 203, and 205 are connected (hypothetical selection in FIG.
  • the pass signal is low level, so that the strobe switches 101, 102, and 103 are sequentially turned on, and are strobed
  • the switch 101 is turned on, a data voltage corresponding to the pixel P1 is applied to the data line D1.
  • the gate switch 102 is turned on, a data voltage corresponding to the pixel P3 is applied to the data line D2, and the gate switch 103 is turned on.
  • a data voltage corresponding to the pixel P5 is applied to the data line D3, and a control signal is applied to the data voltage write control line to which each pixel is connected, thereby writing the data voltage applied to the data voltage input terminal to a first node in the pixel; thereafter, a gate scan signal is applied on the gate line Gn_O, so that the data voltage of the first node written to each of the pixels P1, P3, and P5 is correspondingly written to the second node of each pixel on.
  • the second node here connects the gate of the drive transistor in the data drive circuit.
  • the order in which the data voltage of each pixel is written to each pixel is P1-P3-P5-P2-P4-P6.
  • the order of the pixel data sent by the general host to the data driving circuit is P1-P2-P3-P4-P5-P6. Therefore, in order to write the correct data voltage to each pixel, the above-described pixel data can be rearranged. Specifically, the rearrangement process herein can be performed by a data driving circuit.
  • the data driving circuit may include a rearrangement module for rearranging pixel data, and the rearrangement module is configured to follow a preset gate line conduction sequence and strobe after receiving the pixel data sent by the host.
  • the switch conduction sequence determines the order in which the respective pixels are connected to the data voltage input terminal, and rearranges the received pixel data according to the determined order.
  • FIG. 4 it is a schematic diagram showing the arrangement order of pixel data corresponding to each pixel before and after rearrangement. Before rearrangement, the order of pixel data corresponding to each pixel is P1-P2-P3-P4-P5-P6. After rearrangement, the order of pixel data corresponding to each pixel is P1-P3-P5-P2-P4- P6.
  • FIG. 5 including:
  • Step 501 the pixel data is written into the data driving circuit
  • Step 502 The data driving circuit rearranges the written pixel data.
  • Step 503 the data driving circuit writes a data voltage to the odd column pixels
  • Step 504 the data driving circuit writes a data voltage to the even column of pixels
  • Step 505 displaying a light.
  • step 503 and step 504 may be consistent with the driving method illustrated in FIG. 3 described above, and will not be described in detail herein.
  • the above rearrangement module may also be disposed in other circuits.
  • the logic control circuit can be, for example, an FPGA.
  • the rearrangement module is configured to follow the preset gate line conduction sequence and select after receiving the pixel data sent by the host.
  • the pass switch conduction sequence determines the order in which the respective pixels are connected to the data voltage input terminal, rearranges the received pixel data according to the determined order, and inputs the rearranged data to the data drive circuit.
  • the rearrangement result can be referred to FIG. 4, and will not be described in detail herein.
  • the flow of the foregoing driving method may refer to FIG. 6, and may include:
  • Step 601 the pixel data is written into the logic control circuit
  • Step 602 The logic control circuit rearranges the written pixel data.
  • Step 603 the logic control circuit writes the rearranged pixel data into the data driving circuit
  • Step 604 the data driving circuit writes a data voltage to the odd column pixels
  • Step 605 the data driving circuit writes a data voltage to the even column of pixels
  • Step 606 displaying the light.
  • the display substrate is an AMOLED display substrate.
  • the display substrate may be a liquid crystal display substrate.
  • the data driving circuit is in an odd column. While the pixel writes the data voltage, the gate scan signal may be applied on the gate line to which the odd-numbered column pixel is connected; and when the data drive circuit writes the data voltage to the even-numbered column pixel, the gate connected to the even-numbered column pixel may be connected. A gate scan signal is applied on the line.
  • FIG. 1 Another embodiment of the present invention provides a display substrate.
  • the structure of the display substrate can be referred to FIG. Different from FIG. 1 , the first column of pixels and the pixels of the second column of the two columns of pixels connected to each data line are misaligned in the row direction.
  • the two pixels P1 and P2 connected to the same data line D1 are not aligned in the row direction, but are misaligned.
  • Other structures and driving methods of the display substrate provided in the second embodiment can be similar to those in the first embodiment, and will not be described in detail herein.
  • the pixel driving circuits provided in the respective pixels can be arranged in two rows, and the gate lines can also be arranged in two rows. This is okay Avoid mutual interference between the grid lines.
  • the present invention provides a display device comprising the above display substrate.

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Abstract

一种显示基板及其驱动方法、显示装置，该显示基板包括形成在基底上的多个选通开关阵列和多个选通控制电路；其中，每一个选通开关阵列包括多个选通开关（101-103），每个选通开关（101-103）的第一端连接到相应的一条数据线（D1-D3），第二端均连接到同一数据电压输入端（Data in），控制端均连接到同一选通控制电路；每一条数据线（D1-D3）连接两列像素（P1,P2)，且两列像素（P1，P2)所连接的栅线(Gn_O，Gn_E)不同；每一个选通控制电路连接到多个选通控制信号输入端和相应的一个选通开关阵列，适于在选通控制信号输入端输入的选通控制信号的控制下将所连接的选通开关阵列中的各个选通开关（101-103）分时导通。显示基板可以大幅压缩所使用的数据线（D1-D3）的数量，从而能够降低容纳数据线（D1-D3）所需的扇出区域的面积。

Description

显示基板及其驱动方法、显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种显示基板及其驱动方法、显示装置。
背景技术
一般的显示装置中，每一条数据线连接一列像素(这里的像素指的是进行发光控制的最小单元，其对应于两条相邻的数据线和两条相邻的栅线所限定的一个最小区域)，各条数据线在扇出区域连接到数据电压输入端。在显示器、手机、PAD等较为大型的显示装置中，显示装置的顶端空间较大，可以提供面积较大的扇出区域，从而在该位置容纳足够多的数据线。但是在一些较小的异形显示装置(比如智能手表)的设计中，要求将顶端空间大幅压缩，而为了容纳各条数据线，扇出区域又无法设计的过小，这增加了显示装置的设计难度。
发明内容
本发明的一个目的是提供一种可以具有较小的顶端空间的显示装置。
第一方面，本发明提供了一种显示基板，包括基底以及形成在所述基底上的多条数据线、多条栅线和多个像素，并具有多个数据电压输入端；所述显示基板还包括形成在所述基底上的多个选通开关阵列和多个选通控制电路，并具有多个选通控制信号输入端；其中，
每一个选通开关阵列包括多个选通开关，每个选通开关的第一端连接到相应的一条数据线，每个选通开关的第二端均连接到同一数据电压输入端，每个选通开关的控制端均连接到同一选通控制电路；与选通开关阵列相连的每一条数据线连接两列像素，且两列像素中的一列像素所连接的栅线与另一列像素所连接的栅线不同；
每一个选通控制电路连接到多个选通控制信号输入端和相应的一个选通开关阵列，适于在选通控制信号输入端输入的选通控制信号的控制下将所连接的选通开关阵列中的各个选通开关分时导通。
进一步的，所述选通控制信号输入端包括选通信号输入端和控制 信号输入端；
每一个选通控制电路包括多个选通控制开关组，每一个选通控制开关组包括两个选通控制开关，两个选通控制开关的第一端连接到同一选通开关的控制端，两个选通控制开关的第二端分别连接到相应的选通信号输入端，两个选通控制开关的控制端分别连接到相应的控制信号输入端；且每一个选通控制电路中的各个选通控制开关所连接的选通信号输入端彼此不同，各个选通控制开关组所连接的选通开关彼此不同。
进一步的，每个选通控制电路对应于两个控制信号输入端，每一个选通控制开关组中的一个选通控制开关的控制端连接所述两个控制信号输入端中的一个控制信号输入端，另一个选通控制开关的控制端连接所述两个控制信号输入端中的另一个控制信号输入端。
进一步的，显示基板还包括形成在基底上的像素驱动电路和数据电压写入控制线；
每一个像素包括一个像素驱动电路，该像素驱动电路连接该像素对应的数据线和栅线，并连接数据电压写入控制线，该像素驱动电路适于在数据电压写入控制线的控制下将施加到该像素驱动电路所连接的数据线上的数据电压写入到第一节点，在栅线的控制下将所述数据电压写入到第二节点，并根据第二节点的电压产生用于驱动该像素的电流。
进一步的，连接到同一数据线的两列像素中的一列像素与另一列像素错位排列。
第二方面，本发明还提供了一种驱动上述显示基板的方法，包括：
在对每条栅线所连接的多个像素进行刷新时，对于所述多个像素所连接的选通开关阵列，在与该选通开关阵列所连接的选通控制电路相连接的选通控制信号输入端上施加选通控制信号，使该选通开关阵列中的各个选通开关分时导通，并在每一个选通开关导通时，在该选通开关阵列所连接的数据电压输入端上施加与该选通开关所连接的数据线连接的像素相对应的数据电压；以及，在所述栅线上施加栅极扫描信号，使施加到所述数据电压输入端的数据电压写入到对应的像素中。
进一步的，所述方法还包括：在接收到主机发送的像素数据之后， 按照预设的栅线导通顺序和选通开关导通顺序确定各个像素接入到数据电压输入端的顺序，并根据所确定的顺序对接收到的像素数据进行重排。
进一步的，所述方法还包括：在该选通开关阵列所连接的数据电压输入端上施加与该选通开关所连接的数据线连接的像素相对应的数据电压时，在该像素所连接的数据电压写入控制线上施加控制信号，使施加到该数据电压输入端上的数据电压写入到第一节点；
其中，在所述在该栅线上施加栅极扫描信号、使施加到所述数据电压输入端上的数据电压写入到对应的像素中包括：
在各个选通开关分时导通之后，在所述栅线上施加栅极扫描信号，使写入到每一个像素的第一节点的数据电压写入到该像素的第二节点。
第三方面，本发明还提供了一种显示驱动系统，包括：选通驱动电路，栅极驱动电路和数据驱动电路；其中，在对每条栅线所连接的多个像素进行刷新时：
所述选通驱动电路，用于对于所述多个像素所连接的选通开关阵列，在与该选通开关阵列所连接的选通控制电路相连接的选通控制信号输入端上施加选通控制信号，使该选通开关阵列中的各个选通开关分时导通；
所述数据驱动电路，用于在每一个选通开关导通时，在该选通开关阵列所连接的数据电压输入端上施加与该选通开关所连接的数据线连接的像素相对应的数据电压；
所述栅极驱动电路，用于在所述栅线上施加栅极扫描信号，使施加到所述数据电压输入端的数据电压写入到对应的像素中。
进一步的，所述数据驱动电路包括重排模块，用于在接收到主机发送的像素数据之后，按照预设的栅线导通顺序和选通开关导通顺序确定各个像素接入到数据电压输入端的顺序，并根据所确定的顺序对接收到的像素数据进行重排。
进一步的，所述系统还包括逻辑控制电路，所述逻辑控制电路包括重排模块，用于在接收到主机发送的像素数据之后，按照预设的栅线导通顺序和选通开关导通顺序确定各个像素接入到数据电压输入端的顺序，根据所确定的顺序对接收到的像素数据进行重排，并将重排 后的数据输入到数据驱动电路。
第四方面，本发明还提供了一种显示装置，包括上述显示基板。
在本发明提供的显示基板中，每一条数据线连接两列像素，且连接到同一数据线的两列像素连接不同的栅线，这样就可以在完成相应的驱动显示的情况下，大幅压缩所使用的数据线的数量，从而能够降低容纳数据线所需的扇出区域的面积，使得相应的显示装置可以具有较小的顶端空间，由此能够降低相应的显示装置的设计难度。同时，在本发明中，多条数据线连接到同一输入端，这样相当于采用同一输入端对多列像素进行驱动，从而可以减小所要使用的数据驱动电路的数量，降低显示装置的制作成本。
附图说明
图1为本发明实施例一提供的一种显示基板的结构示意图；
图2为一种像素驱动电路的结构示意图；
图3为对图1中的像素电路进行驱动时关键信号的时序图；
图4为进行重排前后各个像素数据的顺序关系图；
图5为数据驱动电路包含重排模块时的显示驱动方法的流程图；
图6为逻辑控制电路包含重排模块时的显示驱动方法的流程图；
图7为本发明实施例二提供的一种显示基板的结构示意图。
具体实施方式
下面结合附图和实施例，对本发明的具体实施方式作进一步描述。以下实施例仅用于更加清楚地说明本发明的技术方案，而不能以此来限制本发明的保护范围。
第一方面，本发明提供了一种显示基板，包括基底以及形成在所述基底上的多条数据线、多条栅线和多个像素，并具有多个数据电压输入端；所述显示基板还包括形成在所述基底上的多个选通开关阵列和多个选通控制电路，并具有多个选通控制信号输入端；其中，
每一个选通开关阵列包括多个选通开关，每个选通开关的第一端连接到相应的一条数据线，每个选通开关的第二端均连接到同一数据电压输入端，每个选通开关的控制端均连接到同一选通控制电路；与选通开关阵列相连的每一条数据线连接两列像素，且两列像素中的一 列像素所连接的栅线与另一列像素所连接的栅线不同；
每一个选通控制电路连接到多个选通控制信号输入端和相应的一个选通开关阵列，适于在选通控制信号输入端输入的选通控制信号的控制下将所连接的选通开关阵列中的各个选通开关分时导通。
在本发明提供的显示基板中，每一条数据线连接两列像素，且连接到同一数据线的两列像素连接不同的栅线，这样就可以在完成相应的驱动显示的情况下，大幅压缩所使用的数据线的数量，从而能够降低容纳数据线所需的扇出区域的面积，使得相应的显示装置可以具有较小的顶端空间，由此能够降低相应的显示装置的设计难度。同时，在本发明中，多条数据线连接到同一数据电压输入端，这样相当于采用同一输入端对多列像素进行驱动，从而可以减小所要使用的数据驱动电路的数量，降低显示装置的制作成本。
第二方面，本发明还提供了一种显示基板的驱动方法，可以用于驱动根据第一方面的显示基板，该方法包括：
在对每条栅线所连接的多个像素进行刷新时，对于所述多个像素所连接的选通开关阵列，在与该选通开关阵列所连接的选通控制电路相连接的选通控制信号输入端上施加选通控制信号，使该选通开关阵列中的各个选通开关分时导通，并在每一个选通开关导通时，在该选通开关阵列所连接的数据电压输入端上施加与该选通开关所连接的数据线连接的像素相对应的数据电压；以及，在所述栅线上施加栅极扫描信号，使施加到所述数据电压输入端的数据电压写入到对应的像素中。
第三方面，本发明还提供了一种显示驱动系统，包括：选通驱动电路，栅极驱动电路和数据驱动电路；在对每条栅线所连接的多个像素进行刷新时：
所述选通驱动电路，用于对于所述多个像素所连接的选通开关阵列，在与该选通开关阵列所连接的选通控制电路相连接的选通控制信号输入端上施加选通控制信号，使该选通开关阵列中的各个选通开关分时导通；
所述数据驱动电路，用于在每一个选通开关导通时，在该选通开关阵列所连接的数据电压输入端上施加与该选通开关所连接的数据线连接的像素相对应的数据电压；
所述栅极驱动电路，用于在所述栅线上施加栅极扫描信号，使施加到所述数据电压输入端的数据电压写入到对应的像素中。
在具体实施时，上述的显示基板的具体结构可能有多种，相应的驱动方法和制作方法也可能各不相同，下面将结合附图进行详细说明。
此外，在具体实施时，本发明提供的显示基板可以包括多个选通开关阵列和多个选通控制电路，每一个选通开关阵列连接一个数据电压输入端和一个选通控制电路。以下结合其中一个选通开关阵列连接到与其对应的数据电压输入端和选通控制电路的情况进行说明。
实施例一
参见图1，图1为本发明实施例提供的一种显示基板的部分区域的结构示意图。显示基板包括：基底(图中未示出)以及形成在基底上的多条数据线D1-D3和两条栅线Gn_O和Gn_E(n为小于M的任意正整数，M为显示基板的行数)，以及位于第n行的多个像素P1-P6。显示基板还具有数据电压输入端Data in；其中每一条数据线对应连接两列像素，而每一行中，连接到同一数据线的两个像素所连接的栅线不同。比如，数据线D1连接两列像素P1和P2，且像素P1连接到栅线Gn_O，而像素P2连接到栅线Gn_E。
另外该显示基板还包括形成在基底上的选通开关阵列和选通控制电路。选通开关阵列包括三个选通开关101-103，选通控制电路包括6个选通控制开关201-206。该显示基板还具有多个选通控制信号输入端，所述选通控制信号输入端可以包括选通信号输入端MUX1、MUX2.....MUX6，以及控制信号输入端SW_E和SW_O。3个选通开关中的每一个选通开关对应于一条数据线，且每个选通开关的第一端连接到对应的数据线，每个选通开关的第二端均连接到数据电压输入端Data in。比如，选通开关101的第一端连接到对应的数据线D1，其第二端连接到数据电压输入端Data in。6个选通控制开关分为三个选通控制开关组，每一个选通控制开关组对应于一个选通开关；每一个选通控制开关组包括两个选通控制开关，属于同一选通控制开关组的两个选通控制开关的第一端均连接到与其对应的选通开关的控制端，属于同一选通控制开关组的两个选通控制开关的第二端分别连接到相应的选通信号输入端，属于同一选通控制开关组的两个选通控制开关的控制端分别连接到相应的控制信号输入端。比如，属于同一选通控制开关组的 两个选通控制开关201和202的第一端均连接到与其对应的选通开关101的控制端，选通控制开关201的第二端连接选通信号输入端MUX1，其控制端连接控制信号输入端SW_O；而选通控制开关202的第二端连接选通信号输入端MUX4，其控制端连接控制信号输入端SW_E。
在具体实施时，图1中的显示基板例如可以为AMOLED显示基板，也可以为液晶显示基板。当上述的显示基板为AMOLED显示基板时，还可以包括：形成在基底上的像素驱动电路和数据电压写入控制线。每一个像素驱动电路连接一个像素以及该像素所连接的数据线和栅线，并连接数据电压写入控制线，适于在数据电压写入控制线的控制下将施加到像素驱动电路所连接的数据线上的数据电压写入到第一节点，在栅线的控制下将数据电压写入到第二节点，并根据第二节点的电压产生用于驱动该像素的电流。在具体实施时，这样的像素驱动电路的具体结构可以有多种，比如图2中所示出的就是一种常见的像素驱动电路。该像素驱动电路具有第一节点N1和第二节点N2，第一节点N1和第二节点N2均连接到电容C上，且连接到电容C的不同极板，第二节点N2还连接到驱动晶体管DT的栅极。在该像素驱动电路中，第一开关晶体管T1的栅极连接数据电压写入控制线En，源极连接数据线Dm，漏极连接第一节点N1。通过在数据电压写入控制线En上施加对应的控制信号，可以将第一晶体管T1开启，从而将施加到数据线Dm上的数据电压写入到第一节点N1。之后，再通过使第二节点N2浮接，在第一节点N1所连接的开关晶体管T2的栅极所连接的栅线Gn上施加栅极扫描驱动信号以使开关晶体管T2导通，并在开关晶体管T2的源极Ref施加另一电压，能够使第二节点N2的电压发生跳变，这样，就将写入到第一节点N1的数据电压写入到了第二节点N2中。对图2中所示的像素驱动电路工作的详细过程，在此不再详细说明。
对于这样的显示基板，可以采用如下方式进行驱动。
在需要对图1中的第n行像素P1-P6进行数据刷新时，可以按照图3所示的方式，首先对栅线Gn_O所连接的各个像素进行数据刷新，之后对栅线Gn_E所连接的各个像素进行数据刷新。具体来说，在对栅线Gn_O所连接的各个像素进行数据刷新时，可以在选通控制开关201、203、205所连接的各个选通信号输入端依次施加选通信号(图3中假设选通信号为低电平)，使选通开关101、102和103依次导通，并在选通 开关101导通时，在数据线D1上施加与像素P1对应的数据电压，在选通开关102导通时，在数据线D2上施加与像素P3对应的数据电压，在选通开关103导通时，在数据线D3上施加与像素P5对应的数据电压，且在每一个像素所连接的数据电压写入控制线上施加控制信号，从而使施加到数据电压输入端上的数据电压写入到该像素内的第一节点；之后，在栅线Gn_O上施加栅极扫描信号，使写入到各个像素P1、P3和P5的第一节点的数据电压相应地写入到各个像素的第二节点上。这里的第二节点连接数据驱动电路中的驱动晶体管的栅极。对于栅线Gn_E所连接的各个像素进行数据刷新的过程也可以参考图3，该过程与对栅线Gn_O所连接的各个像素进行数据刷新的过程一致，在此不再详细说明。
从上述的驱动过程中可以看出，在具体实施时，各个像素的数据电压写入到各个像素的顺序是P1-P3-P5-P2-P4-P6。而一般的主机发送到数据驱动电路的像素数据的排列顺序为P1-P2-P3-P4-P5-P6。因此，为了将正确的数据电压写入到各个像素，可以对上述的像素数据进行重排。具体来说，这里的重排过程可以由数据驱动电路执行。此时，上述数据驱动电路可以包括用于对像素数据进行重排的重排模块，该重排模块用于在接收到主机发送的像素数据之后，按照预设的栅线导通顺序和选通开关导通顺序确定各个像素接入到数据电压输入端的顺序，并根据所确定的顺序对接收到的像素数据进行重排。参见图4，其为重排前和重排后各个像素对应的像素数据的排列顺序示意图。重排前，各个像素对应的像素数据的排列顺序为P1-P2-P3-P4-P5-P6，重排后，各个像素对应的像素数据的排列顺序为P1-P3-P5-P2-P4-P6。
此时，上述驱动方法的流程可以参考图5，包括：
步骤501，像素数据写入数据驱动电路；
步骤502，数据驱动电路对写入的像素数据进行重排；
步骤503，数据驱动电路向奇数列像素写入数据电压；
步骤504，数据驱动电路向偶数列像素写入数据电压；
步骤505，发光显示。
步骤503和步骤504的过程可以与上述的图3中示出的驱动方法一致，在此不再详细说明。
或者，在具体实施时，上述的重排模块也可以设置在其他电路中， 比如可以设置在逻辑控制电路(这里的逻辑控制电路例如可以为FPGA)中，此时，该重排模块用于在接收到主机发送的像素数据之后，按照预设的栅线导通顺序和选通开关导通顺序确定各个像素接入到数据电压输入端的顺序，根据所确定的顺序对接收到的像素数据进行重排，并将重排后的数据输入到数据驱动电路。当利用重排模块对上述的各个像素数据进行重排时，重排结果可以参考图4，在此不再详细说明。
此时，上述驱动方法的流程可以参考图6，可以包括：
步骤601，像素数据写入逻辑控制电路；
步骤602，逻辑控制电路对写入的像素数据进行重排；
步骤603，逻辑控制电路将重排后的像素数据写入数据驱动电路；
步骤604，数据驱动电路向奇数列像素写入数据电压；
步骤605，数据驱动电路向偶数列像素写入数据电压；
步骤606，发光显示。
当然，在实际应用中，上述的重排过程也可以由主机或者其他功能模块执行，相应的技术方案同样能够完成对数据电压的正确写入。因此，相应的技术方案也应该落入本发明的保护范围内。
不难理解的是，虽然本发明实施例中是以显示基板为AMOLED显示基板进行的说明，但是在具体实施时，上述的显示基板也可以为液晶显示基板，此时，数据驱动电路向奇数列像素写入数据电压的同时，可以在奇数列像素所连接的栅线上施加栅极扫描信号；而在数据驱动电路向偶数列像素写入数据电压的同时，可以在偶数列像素所连接的栅线上施加栅极扫描信号。
实施例二
本发明实施例二还提供了另外一种显示基板，该显示基板的结构可以参考图7。与图1不同的是，每一条数据线所连接的两列像素中的第一列像素与第二列像素在行方向上错位排列。比如，连接到同一数据线D1上的两个像素P1和P2在行方向不对齐，而是错位排列。实施例二提供的显示基板的其他结构以及驱动方法可以与实施例一类似，在此不再详细说明。
在实施例二中，由于像素交错布置，因此设置在各个像素中的像素驱动电路可以分两行布置，而栅线也可以分两行布置。这样，可以 避免栅线之间的相互干扰。
第四方面，本发明提供了一种显示装置，包括上述的显示基板。
以上所述仅是本发明的具体实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明技术原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为涵盖在本发明的保护范围内。

Claims (12)

  1. 一种显示基板，包括基底以及形成在所述基底上的多条数据线、多条栅线和多个像素，并具有多个数据电压输入端；其中，所述显示基板还包括形成在所述基底上的多个选通开关阵列和多个选通控制电路，并具有多个选通控制信号输入端；其中，
    每一个选通开关阵列包括多个选通开关，每个选通开关的第一端连接到相应的一条数据线，每个选通开关的第二端均连接到同一数据电压输入端，每个选通开关的控制端均连接到同一选通控制电路；与选通开关阵列相连的每一条数据线连接两列像素，且两列像素中的一列像素所连接的栅线与另一列像素所连接的栅线不同；
    每一个选通控制电路连接到多个选通控制信号输入端和相应的一个选通开关阵列，适于在选通控制信号输入端输入的选通控制信号的控制下将所连接的选通开关阵列中的各个选通开关分时导通。
  2. 如权利要求1所述的显示基板，其中，所述选通控制信号输入端包括选通信号输入端和控制信号输入端；
    每一个选通控制电路包括多个选通控制开关组，每一个选通控制开关组包括两个选通控制开关，两个选通控制开关的第一端连接到同一选通开关的控制端，两个选通控制开关的第二端分别连接到相应的选通信号输入端，两个选通控制开关的控制端分别连接到相应的控制信号输入端；且每一个选通控制电路中的各个选通控制开关所连接的选通信号输入端彼此不同，各个选通控制开关组所连接的选通开关彼此不同。
  3. 如权利要求2所述的显示基板，其中，每个选通控制电路对应于两个控制信号输入端，每一个选通控制开关组中的一个选通控制开关的控制端连接所述两个控制信号输入端中的一个控制信号输入端，另一个选通控制开关的控制端连接所述两个控制信号输入端中的另一个控制信号输入端。
  4. 如权利要求2或3所述的显示基板，还包括形成在基底上的像素驱动电路和数据电压写入控制线；
    每一个像素包括一个像素驱动电路，该像素驱动电路连接该像素对应的数据线和栅线，并连接数据电压写入控制线，该像素驱动电路 适于在数据电压写入控制线的控制下将施加到该像素驱动电路所连接的数据线上的数据电压写入到第一节点，在栅线的控制下将所述数据电压写入到第二节点，并根据第二节点的电压产生用于驱动该像素的电流。
  5. 如权利要求1所述的显示基板，其中，连接到同一条数据线的两列像素中的一列像素与另一列像素错位排列。
  6. 一种驱动如权利要求1-5中任一项所述的显示基板的方法，包括：
    在对每条栅线所连接的多个像素进行刷新时，对于所述多个像素所连接的选通开关阵列，在与该选通开关阵列所连接的选通控制电路相连接的选通控制信号输入端上施加选通控制信号，使该选通开关阵列中的各个选通开关分时导通，并在每一个选通开关导通时，在该选通开关阵列所连接的数据电压输入端上施加与该选通开关所连接的数据线连接的像素相对应的数据电压；以及
    在所述栅线上施加栅极扫描信号，使施加到所述数据电压输入端的数据电压写入到对应的像素中。
  7. 如权利要求6所述的方法，还包括：在接收到主机发送的像素数据之后，按照预设的栅线导通顺序和选通开关导通顺序确定各个像素接入到数据电压输入端的顺序，并根据所确定的顺序对接收到的像素数据进行重排。
  8. 如权利要求6所述的方法，还包括：在该选通开关阵列所连接的数据电压输入端上施加与该选通开关所连接的数据线连接的像素相对应的数据电压时，在该像素所连接的数据电压写入控制线上施加控制信号，使施加到该数据电压输入端上的数据电压写入到第一节点；
    其中，在所述栅线上施加栅极扫描信号、使施加到所述数据电压输入端的数据电压写入到对应的像素中包括：
    在各个选通开关分时导通之后，在所述栅线上施加栅极扫描信号，使写入到每一个像素的第一节点的数据电压写入到该像素的第二节点。
  9. 一种显示驱动系统，包括：选通驱动电路，栅极驱动电路和数据驱动电路；其中，在对每条栅线所连接的多个像素进行刷新时：
    所述选通驱动电路，用于对于所述多个像素所连接的选通开关阵 列，在与该选通开关阵列所连接的选通控制电路相连接的选通控制信号输入端上施加选通控制信号，使该选通开关阵列中的各个选通开关分时导通；
    所述数据驱动电路，用于在每一个选通开关导通时，在该选通开关阵列所连接的数据电压输入端上施加与该选通开关所连接的数据线连接的像素相对应的数据电压；
    所述栅极驱动电路，用于在所述栅线上施加栅极扫描信号，使施加到所述数据电压输入端的数据电压写入到对应的像素中。
  10. 如权利要求9所述的系统，其中，
    所述数据驱动电路包括重排模块，用于在接收到主机发送的像素数据之后，按照预设的栅线导通顺序和选通开关导通顺序确定各个像素接入到数据电压输入端的顺序，并根据所确定的顺序对接收到的像素数据进行重排。
  11. 如权利要求9所述的系统，还包括逻辑控制电路，所述逻辑控制电路包括重排模块，用于在接收到主机发送的像素数据之后，按照预设的栅线导通顺序和选通开关导通顺序确定各个像素接入到数据电压输入端的顺序，根据所确定的顺序对接收到的像素数据进行重排，并将重排后的数据输入到数据驱动电路。
  12. 一种显示装置，包括如权利要求1-5中任一项所述的显示基板。
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