CN105096809A - 显示基板及其驱动方法、显示装置 - Google Patents

显示基板及其驱动方法、显示装置 Download PDF

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Publication number
CN105096809A
CN105096809A CN201510599760.3A CN201510599760A CN105096809A CN 105096809 A CN105096809 A CN 105096809A CN 201510599760 A CN201510599760 A CN 201510599760A CN 105096809 A CN105096809 A CN 105096809A
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pixel
gating
data
input end
gating switch
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CN105096809B (zh
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孙拓
马占洁
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to CN201510599760.3A priority Critical patent/CN105096809B/zh
Publication of CN105096809A publication Critical patent/CN105096809A/zh
Priority to PCT/CN2016/073873 priority patent/WO2017045352A1/zh
Priority to US15/325,053 priority patent/US10373547B2/en
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  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

本发明提供了一种显示基板及其驱动方法、显示装置，该显示基板包括形成在基底上的选通开关阵列和选通控制电路；其中，每一个选通开关阵列包括多个选通开关，各个选通开关的第一端一对一连接一条数据线，第二端均连接到同一数据电压输入端，控制端均连接到同一选通控制电路；每一条数据线连接两列像素，且两列像素所连接的栅线不同；每一个选通控制电路连接多个选通控制信号输入端和一个选通开关阵列，适于在选通控制信号输入端输入的选通控制信号的控制下将所连接的选通开关阵列中的各个选通开关分时导通。本发明提供的显示基板可以大幅压缩所使用的数据线的数量，从而能够降低容纳数据线所需的扇出区域的面积。

Description

显示基板及其驱动方法、显示装置
技术领域
本发明涉及显示技术领域，尤其涉及一种显示基板及其驱动方法、显示装置。
背景技术
一般的显示装置中，每一条数据线连接一列像素(这里的像素指进行发光控制的最小单元，对应于两条相邻的数据线和两条相邻的实现所限定的一个最小区域)，各条数据线在扇出区域连接到数据电压输入端。在显示器、手机、PAD等较为大型的显示装置中，显示装置的顶端空间较大，可以提供面积较大的扇出区域，从而在该处位置处容纳足够多的数据线。但是在一些较小的异形显示装置(比如智能手表)的设计时，要求将顶端空间大幅压缩，而为了容纳各条数据线，扇出区域又无法设计的过小，增加了显示装置的设计难度。
发明内容
本发明的一个目的是提供一种可以具有较小的顶端空间的显示装置。
第一方面，本发明提供了一种显示基板，包括基底以及形成在所述基底上的多条数据线、多条栅线和多个像素，并具有多个数据电压输入端；所述显示基板还包括形成在所述基底上的选通开关阵列和选通控制电路，并具有多个选通控制信号输入端；其中，
每一个选通开关阵列包括多个选通开关，各个选通开关的第一端一对一连接一条数据线，第二端均连接到同一数据电压输入端，控制端均连接到同一选通控制电路；与选通开关阵列相连的每一条数据线连接两列像素，且两列像素中的第一列像素所连接的栅线与另一列像素所连接的栅线不同；
每一个选通控制电路连接多个选通控制信号输入端和一个选通开关阵列，适于在选通控制信号输入端输入的选通控制信号的控制下将所连接的选通开关阵列中的各个选通开关分时导通。
进一步的，所述选通控制信号输入端包括选通信号输入端和控制信号输入端；
每一个选通控制电路包括多个选通控制开关组，每一个选通控制开关组包括两个选通控制开关，两个选通控制开关的第一端连接同一选通开关的控制端，第二端各自连接一个选通信号输入端，控制端各自连接到一个控制信号输入端；且每一个选通控制电路中的各个选通控制开关所连接的选通信号输入端各不相同，每一个选通控制开关组所连接选通开关与另一个选通控制开关组所连接选通开关不同。
进一步的，同一选通控制电路对应于两个控制信号输入端，每一个选通控制开关组中的一个选通控制开关的控制端连接其中一个控制信号输入端，另一个选通控制开关的控制端连接另一个控制信号输入端。
进一步的，还包括形成在基底上的像素驱动电路和数据电压写入控制线；
每一个像素包括一个像素驱动电路，该像素驱动电路连接该像素对应的数据线和栅线，并连接数据电压写入控制线，适于在数据电压写入控制线的控制下将施加到所连接的数据线上的数据电压写入到第一节点，并在栅线的控制下将数据电压写入到第二节点，并根据第二节点的电压产生用于驱动该像素的电流。
进一步的，连接到同一列数据线的两列子像素中一列子像素与另一列子像素错位排列。
第二方面，本发明还提供了一种驱动上述任一项所述的显示基板的方法，包括：
在需要对一条栅线所连接的各个像素进行刷新时，对于所连接的数据线连接所述各个像素的每一个选通开关阵列，在该选通开关阵列所连接的选通控制电路所连接的选通控制信号输入端上施加选通控制信号，使该选通开关阵列中的各个选通开关分时导通，并在每一个选通开关导通时，在该选通开关阵列所连接的数据电压输入端上施加该选通开关所连接的数据线所连接的像素对应的数据电压；在该栅线上施加栅极扫描信号，使施加到数据电压输入端的数据电压写入到对应的像素中。
进一步的，所述方法还包括：在接收到主机发送的像素数据之后，按照预设的栅线导通顺序和选通开关导通顺序确定各个像素接入到数据电压输入端的顺序，并根据所确定的顺序对接收到的像素数据进行重排。
进一步的，所述显示基板为包括像素驱动电路和数据电压写入控制线时，所述方法还包括：在该选通开关阵列所连接的数据电压输入端上施加该选通开关所连接的数据线所连接的像素对应的数据电压时，在该像素所连接的数据电压写入控制线上施加控制信号使施加到该数据电压输入端上的数据电压写入到第一节点；
所述在该栅线上施加栅极扫描信号，使施加到数据线上的数据电压写入到对应的像素中，包括：
在各个选通开关分时导通之后，在该栅线上施加栅极扫描信号使写入到每一个像素的第一节点的数据电压写入到该像素的第二节点。
第三方面，本发明还提供了一种显示驱动系统，包括：选通驱动电路，栅极驱动电路和数据驱动电路；在需要对一条栅线所连接的各个像素进行刷新时，
所述选通驱动电路，用于对于所连接的数据线连接所述各个像素的每一个选通开关阵列，在该选通开关阵列所连接的选通控制电路所连接的选通信号输入端上施加选通控制信号，使该选通开关阵列中的各个选通开关分时导通；
所述数据驱动电路，用于在每一个选通开关导通时，在该选通开关阵列所连接的数据电压输入端上施加该选通开关所连接的数据线所连接的像素对应的数据电压；
所述栅极驱动电路，用于在该栅线上施加栅极扫描信号，使施加到数据电压输入端的数据电压写入到对应的像素中。
进一步的，所述数据驱动电路包括重排模块，用于在接收到主机发送的像素数据之后，按照预设的栅线导通顺序和选通开关导通顺序确定各个像素接入到数据电压输入端的顺序，并根据所确定的顺序对接收到的像素数据进行重排。
进一步的，包括逻辑控制电路，所述逻辑控制电路包括重排模块，用于在接收到主机发送的像素数据之后，按照预设的栅线导通顺序和选通开关导通顺序确定各个像素接入到数据电压输入端的顺序，并根据所确定的顺序对接收到的像素数据进行重排，并将重排后的数据输入到数据驱动电路。
第四方面，本发明还提供了一种显示装置，包括上述任一项所述的显示基板。
本发明提供的显示基板中，每一条数据线连接两列像素，且连接到同一数据线中的两个像素连接不同的栅线，这样就可以在完成相应的驱动显示的情况下，大幅压缩所使用的数据线的数量，从而能够降低容纳数据线所需的扇出区域的面积，使得相应的显示装置可以具有较小的顶端空间，能够降低相应的显示装置的设计难度。同时本发明中，多条数据线连接到同一输入端，这样相当于将采用同一输入端对多列的像素进行驱动，可以减小所需要使用的数据驱动电路的数量，降低显示装置的制作成本。
附图说明
图1为本发明实施例一提供的一种显示基板的结构示意图；
图2为一种像素驱动电路的结构示意图；
图3为对图1中的像素电路进行驱动时关键信号的时序图；
图4为进行重排前后各个像素数据的顺序关系图；
图5为数据驱动电路包含重排模块时的显示驱动方法的流程图；
图6为逻辑控制电路包含重排模块时的显示驱动方法的流程图；
图7为实施例二提供的一种显示基板的结构示意图。
具体实施方式
下面结合附图和实施例，对本发明的具体实施方式作进一步描述。以下实施例仅用于更加清楚地说明本发明的技术方案，而不能以此来限制本发明的保护范围。
第一方面，本发明提供了一种显示基板，包括基底以及形成在所述基底上的多条数据线、多条栅线和多个像素，并具有多个数据电压输入端；还包括形成在所述基底上的选通开关阵列和选通控制电路，所述显示基板还具有多个选通控制信号输入端；其中，
每一个选通开关阵列包括多个选通开关，各个选通开关的第一端一对一连接一条数据线，第二端均连接到同一数据电压输入端，控制端均连接到同一选通控制电路；与选通开关阵列相连的每一条数据线连接两列像素，且两列像素中的第一列像素所连接的栅线与另一列像素所连接的栅线不同；
每一个选通控制电路连接多个选通控制信号输入端和一个选通开关阵列，适于在选通控制信号输入端输入的选通控制信号的控制下将所连接的选通开关阵列中的各个选通开关分时导通。
本发明提供的显示基板中，每一条数据线连接两列像素，且连接到同一数据线中的两个像素连接不同的栅线，这样就可以在完成相应的驱动显示的情况下，大幅压缩所使用的数据线的数量，从而能够降低容纳数据线所需的扇出区域的面积，使得相应的显示装置可以具有较小的顶端空间，能够降低相应的显示装置的设计难度。同时本发明中，多条数据线连接到同一数据电压输入端，这样相当于将采用同一输入端对多列的像素进行驱动，可以减小所需要使用的数据驱动电路的数量，降低显示装置的制作成本。
第二方面，本发明还提供了一种显示基板的驱动方法，可以用于驱动第一方面所述的显示基板，该方法包括：
在需要对一条栅线所连接的各个像素进行刷新时，对于所连接的数据线连接所述各个像素的每一个选通开关阵列，在该选通开关阵列所连接的选通控制电路所连接的选通控制信号输入端上施加选通控制信号，使该选通开关阵列中的各个选通开关分时导通，并在每一个选通开关导通时，在该选通开关阵列所连接的数据电压输入端上施加该选通开关所连接的数据线所连接的像素对应的数据电压；在该栅线上施加栅极扫描信号，使施加到数据电压输入端的数据电压写入到对应的像素中。
第三方面，本发明还提供了一种显示驱动系统，包括：选通驱动电路，栅极驱动电路和数据驱动电路；在需要对一条栅线所连接的各个像素进行刷新时，
所述选通驱动电路，用于对于所连接的数据线连接所述各个像素的每一个选通开关阵列，在该选通开关阵列所连接的选通控制电路所连接的选通信号输入端上施加选通控制信号，使该选通开关阵列中的各个选通开关分时导通；
所述数据驱动电路，用于在每一个选通开关导通时，在该选通开关阵列所连接的数据电压输入端上施加该选通开关所连接的数据线所连接的像素对应的数据电压；
所述栅极驱动电路，用于在该栅线上施加栅极扫描信号，使施加到数据电压输入端的数据电压写入到对应的像素中。
在具体实施时，上述的显示基板的具体结构可能有多种，相应的驱动方法和制作方法也可能各不相同，下面结合附图进行详细说明。在具体实施时，本发明提供的显示基板可以包括多个的选通开关阵列和选通控制电路，每一个选通开关阵列连接一个数据电压输入端和一个选通控制电路；以下结合其中一个选通开关阵列连接其对应的数据电压输入端和选通控制电路的情况进行说明。
实施例一
参见图1，为本发明提供的一种显示基板的在部分区域的结构示意图，包括：基底(图中未示出)以及形成在基底上的多条数据线D1-D3和两条栅线Gn_O和Gn_E(n为小于M的任意正整数，M为显示基板的行数)，以及位于第n行的多个像素P1-P6，并具有一个数据电压输入端Datain；其中每一条数据线对应连接两列像素，而每一行中，连接到同一数据线的两个像素所连接的栅线不同。比如数据线D1连接两列的像素P1和P2，且像素P1连接到栅线Gn_O，而像素P2连接到栅线Gn1_E；
另外该显示基板还包括形成在基底上的选通开关阵列和选通控制电路，选通开关阵列包括三个选通开关101-103，选通控制电路包括6个选通控制开关201-206，该显示基板还具有多个选通控制信号输入端，该选通控制信号输入端可以包括选通信号输入端MUX1、MUX2…..MUX6、控制信号输入端SW_E和SW_O；3个选通开关中的每一个选通开关对应于一条数据线，且第一端连接其对应的数据线，第二端均连接到数据电压输入端Datain，比如选通开关101的第一端连接对应的数据线D1，第二端连接到数据电压输入端Datain。6个选通控制开关分为三个选通控制开关组，每一个选通控制开关组对应于一个选通开关；每一个选通控制开关组包括两个选通控制开关，属于同一选通控制开关组的两个选通控制开关的第一端均连接其对应的选通开关的控制端，第二端各自连接一个选通信号输入端，控制端各自连接一个控制信号输入端：比如属于同一选通控制开关组的两个选通控制开关201和202的第一端均连接所对应的选通开关101，选通控制开关201的第二端连接一个选通信号输入端MUX1，控制端连接一个控制信号输入端SW_O；而选通控制开关202的第二端连接一个选通信号输入端MUX4，控制端连接一个控制信号输入端SW_E。
在具体实施时，图1中的显示基板可以为AMOLED显示基板，也可以为液晶显示基板。在当上述的显示基板为AMOLED显示基板时，还可以包括：形成在基底上的像素驱动电路和数据电压写入控制线，每一个像素驱动电路连接一个像素以及该像素所连接的数据线和栅线，并连接数据电压写入控制线，适于在数据电压写入控制线的控制下将施加到所连接的数据线上的数据电压写入到第一节点，并在栅线的控制下将数据电压写入到第二节点，并根据第二节点的电压产生用于驱动该像素的电流。在具体实施时，这样的像素驱动电路的具体结构可以有多种，比如图2中所示出的就是一种常见的像素驱动电路，该像素驱动电路具有第一节点N1和第二节点N2，第一节点N1和第二节点N2均连接到电容上，且连接电容C的不同极板，第二节点N2还连接驱动晶体管DT的栅极，该像素驱动电路中，第一开关晶体管T1的栅极连接数据电压写入控制线En，源极连接数据线Dm，漏极连接第一节点N1，通过在数据电压写入控制线EM施加对应的控制信号可以将第一晶体管T1开启，将施加到数据线Dm上的数据电压写入到第一节点N1，之后在通过使第二节点N2浮接，并在第一节点N2所连接的开关晶体管T2的栅极所连接的栅线Gn上施加栅极扫描驱动信号使开关晶体管T2导通，并在开关晶体管T2的源极Ref施加另一电压，能够使第二节点N2的电压发生跳变，这样就将写入到第一节点N1的数据电压写入到了第二节点N2中。对图2中所示的像素驱动电路的详细过程本发明不再详细说明。
在此不再详细说明。对于这样的显示基板，可以采用如下方式进行驱动：
在需要对图1中的第n行像素P1-P6进行数据刷新时，可以按照图3所示的方式，首先对栅线Gn_O所连接的各个像素进行数据刷新，之后对栅线Gn_E所连接的各个像素进行数据刷新；具体来说，在对栅线Gn_O所连接的各个像素进行数据刷新时，可以在选通控制开关201、202、203所连接的各个选通信号输入端依次施加选通信号(图3中假设选通信号为低电平)使选通开关101、102和103依次导通，并在选通开关导通101导通时，在数据线D1上施加像素P1对应的数据电压，在选通开关导通102导通时，在数据线D1上施加像素P3对应的数据电压，在选通开关导通103导通时，在数据线D1上施加像素P5对应的数据电压，且在每一个像素所连接的数据电压写入控制线上施加控制信号使施加到该数据电压输入端上的数据电压写入到该像素内的第一节点；之后在栅线Gn_O上施加栅极扫描信号使写入到各个像素P1、P3和P5的第一节点的电压对应写入到各个像素的第二节点上。这里的第二节点连接数据驱动电路中的驱动晶体管的栅极。对栅线Gn_E所连接的各个像素进行数据刷新的过程也可以参考图3，该过程与对栅线Gn_O所连接的各个像素进行数据刷新的过程一致，在此不再详细说明。
在具体实施时，从上述的驱动过程中可以看出，在具体实施时，各个像素的数据电压写入的到各个像素的顺序是P1-P3-P5-P2-P4-P6，而一般的主机发送到数据驱动电路的像素数据的排列顺序为P1-P2-P3-P4-P5-P6，这样为了将正确的数据电压写入到各个像素，可以对上述的像素数据进行重排，具体来说，这里的重排过程可以由数据驱动电路执行，此时上述数据驱动电路可以包括用于对像素数据进行重排的重排模块，该重排模块用于在接收到主机发送的像素数据之后，按照预设的栅线导通顺序和选通开关导通顺序确定各个像素接入到数据电压输入端的顺序，并根据所确定的顺序对接收到的像素数据进行重排。参见图4，为重排前和重排后各个像素对应的像素数据的排列顺序示意图。重排前，各个像素对应的像素数据的排列顺序为P1-P2-P3-P4-P5-P6，重排后，各个像素对应的像素数据的排列顺序为P1-P3-P5-P2-P4-P6。
此时上述驱动方法的流程可以参考图5，包括：
步骤501，像素数据写入数据驱动电路；
步骤502，数据驱动电路对写入的像素数据进行重排；
步骤503，数据驱动电路向奇数列像素写入数据电压；
步骤504，数据驱动电路向偶数列像素写入数据电压；
步骤505，发光显示。
步骤503和步骤504的过程可以与上述的图3中示出的驱动方法一致，在此不再详细说明。
或者，在具体实施时，上述的重排模块也可以设置在其他电路中，比如可以设置在逻辑控制电路(这里的逻辑控制电路可以具体为FPGA)中，此时该重排模块用于在接收到主机发送的像素数据之后，按照预设的栅线导通顺序和选通开关导通顺序确定各个像素接入到数据电压输入端的顺序，并根据所确定的顺序对接收到的像素数据进行重排，并将重排后的数据输入到数据驱动电路。当这里的重排模块用于对上述的各个像素数据进行重排时，重排结果可以参考图4，在此不再详细说明。
此时上述驱动方法的流程可以参考图6，可以包括：
步骤601，像素数据写入逻辑控制电路；
步骤602，逻辑控制电路对写入的像素数据进行重排；
步骤603，逻辑控制电路将重排后的像素数据写入数据驱动电路；
步骤604，数据驱动电路向奇数列像素写入数据电压；
步骤605，数据驱动电路向偶数列像素写入数据电压；
步骤606，发光显示。
当然在实际应用中，上述的重排过程也可以由主机或者其他功能模块执行，相应的技术方案同样能够完成对数据电压的正确写入，相应的技术方案也应该落入本发明的保护范围。
不难理解的是，虽然本发明实施例中是以显示基板为AMOLED显示基板进行的说明，但是在具体实施时，上述的显示基板也可以为液晶显示基板，此时，数据驱动电路向奇数列像素写入数据电压的同时，可以在奇数列像素所连接的栅线上施加栅极扫描信号；而在数据驱动电路向偶数列像素写入数据电压的同时，可以在偶数列像素所连接的栅线上施加栅极扫描信号。
实施例二
本发明实施例二还提供了另外一种显示基板，该显示基板的结构可以参考图7，与图1不同的是，每一条数据线所连接的两列像素中第一列像素与第二列像素在行方向上错位排列。比如连接到同一数据线D1上的两个像素P1和P2在行方向不对齐，而是错位排列。实施例二提供的显示基板的其他结构以及驱动方法可以实施例一，在此不再详细说明。
实施例二中，由于像素交错布置，设置在各个像素中的像素驱动电路可以分两行布置，而栅线也可以分两行布置，这样可以避免栅线之间的相互干扰。
第四方面，本发明提供了一种显示装置，包括上述的显示基板。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明技术原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (12)

1.一种显示基板，包括基底以及形成在所述基底上的多条数据线、多条栅线和多个像素，并具有多个数据电压输入端；其特征在于，所述显示基板还包括形成在所述基底上的选通开关阵列和选通控制电路，并具有多个选通控制信号输入端；其中，
每一个选通开关阵列包括多个选通开关，各个选通开关的第一端一对一连接一条数据线，第二端均连接到同一数据电压输入端，控制端均连接到同一选通控制电路；与选通开关阵列相连的每一条数据线连接两列像素，且两列像素中的第一列像素所连接的栅线与另一列像素所连接的栅线不同；
每一个选通控制电路连接多个选通控制信号输入端和一个选通开关阵列，适于在选通控制信号输入端输入的选通控制信号的控制下将所连接的选通开关阵列中的各个选通开关分时导通。
2.如权利要求1所述的显示基板，其特征在于，所述选通控制信号输入端包括选通信号输入端和控制信号输入端；
每一个选通控制电路包括多个选通控制开关组，每一个选通控制开关组包括两个选通控制开关，两个选通控制开关的第一端连接同一选通开关的控制端，第二端各自连接一个选通信号输入端，控制端各自连接到一个控制信号输入端；且每一个选通控制电路中的各个选通控制开关所连接的选通信号输入端各不相同，每一个选通控制开关组所连接选通开关与另一个选通控制开关组所连接选通开关不同。
3.如权利要求2的所述的显示基板，其特征在于，同一选通控制电路对应于两个控制信号输入端，每一个选通控制开关组中的一个选通控制开关的控制端连接其中一个控制信号输入端，另一个选通控制开关的控制端连接另一个控制信号输入端。
4.如权利要求2或3所述的显示基板，其特征在于，还包括形成在基底上的像素驱动电路和数据电压写入控制线；
每一个像素包括一个像素驱动电路，该像素驱动电路连接该像素对应的数据线和栅线，并连接数据电压写入控制线，适于在数据电压写入控制线的控制下将施加到所连接的数据线上的数据电压写入到第一节点，并在栅线的控制下将数据电压写入到第二节点，并根据第二节点的电压产生用于驱动该像素的电流。
5.如权利要求1所述的显示基板，其特征在于，连接到同一列数据线的两列子像素中一列子像素与另一列子像素错位排列。
6.一种驱动如权利要求1-5任一项所述的显示基板的方法，其特征在于，包括：
在需要对一条栅线所连接的各个像素进行刷新时，对于所连接的数据线连接所述各个像素的每一个选通开关阵列，在该选通开关阵列所连接的选通控制电路所连接的选通控制信号输入端上施加选通控制信号，使该选通开关阵列中的各个选通开关分时导通，并在每一个选通开关导通时，在该选通开关阵列所连接的数据电压输入端上施加该选通开关所连接的数据线所连接的像素对应的数据电压；在该栅线上施加栅极扫描信号，使施加到数据电压输入端的数据电压写入到对应的像素中。
7.如权利要求6所述的方法，其特征在于，所述方法还包括：在接收到主机发送的像素数据之后，按照预设的栅线导通顺序和选通开关导通顺序确定各个像素接入到数据电压输入端的顺序，并根据所确定的顺序对接收到的像素数据进行重排。
8.如权利要求6所述的方法，其特征在于，所述显示基板为如权利要求4所述的显示基板，所述方法还包括：在该选通开关阵列所连接的数据电压输入端上施加该选通开关所连接的数据线所连接的像素对应的数据电压时，在该像素所连接的数据电压写入控制线上施加控制信号使施加到该数据电压输入端上的数据电压写入到第一节点；
所述在该栅线上施加栅极扫描信号，使施加到数据线上的数据电压写入到对应的像素中，包括：
在各个选通开关分时导通之后，在该栅线上施加栅极扫描信号使写入到每一个像素的第一节点的数据电压写入到该像素的第二节点。
9.一种显示驱动系统，其特征在于，包括：选通驱动电路，栅极驱动电路和数据驱动电路；在需要对一条栅线所连接的各个像素进行刷新时，
所述选通驱动电路，用于对于所连接的数据线连接所述各个像素的每一个选通开关阵列，在该选通开关阵列所连接的选通控制电路所连接的选通信号输入端上施加选通控制信号，使该选通开关阵列中的各个选通开关分时导通；
所述数据驱动电路，用于在每一个选通开关导通时，在该选通开关阵列所连接的数据电压输入端上施加该选通开关所连接的数据线所连接的像素对应的数据电压；
所述栅极驱动电路，用于在该栅线上施加栅极扫描信号，使施加到数据电压输入端的数据电压写入到对应的像素中。
10.如权利要求9所述的系统，其特征在于，
所述数据驱动电路包括重排模块，用于在接收到主机发送的像素数据之后，按照预设的栅线导通顺序和选通开关导通顺序确定各个像素接入到数据电压输入端的顺序，并根据所确定的顺序对接收到的像素数据进行重排。
11.如权利要求9所述的系统，其特征在于，其特征在于，包括逻辑控制电路，所述逻辑控制电路包括重排模块，用于在接收到主机发送的像素数据之后，按照预设的栅线导通顺序和选通开关导通顺序确定各个像素接入到数据电压输入端的顺序，并根据所确定的顺序对接收到的像素数据进行重排，并将重排后的数据输入到数据驱动电路。
12.一种显示装置，其特征在于，包括如权利要求1-5任一项所述的显示基板。
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