WO2017035880A1 - 薄膜晶体管阵列基板及液晶显示面板 - Google Patents

薄膜晶体管阵列基板及液晶显示面板 Download PDF

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Publication number
WO2017035880A1
WO2017035880A1 PCT/CN2015/090330 CN2015090330W WO2017035880A1 WO 2017035880 A1 WO2017035880 A1 WO 2017035880A1 CN 2015090330 W CN2015090330 W CN 2015090330W WO 2017035880 A1 WO2017035880 A1 WO 2017035880A1
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Prior art keywords
layer
thin film
film transistor
light shielding
array substrate
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English (en)
French (fr)
Inventor
陈归
陈彩琴
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Wuhan China Star Optoelectronics Technology Co Ltd
TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US14/902,551 priority Critical patent/US9897881B2/en
Publication of WO2017035880A1 publication Critical patent/WO2017035880A1/zh
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si

Definitions

  • the present invention relates to the field of display, and in particular to a thin film transistor array substrate and a liquid crystal display panel.
  • the liquid crystal display panel is a commonly used electronic device, and has been favored by users because of its low power consumption, small size, and light weight.
  • Amorphous silicon has a low electron mobility
  • low temperature Ploy-silicon LTPS
  • the switching device made of low temperature polysilicon can be applied to make the liquid crystal display panel have higher resolution and low power consumption. Therefore, low temperature polysilicon has been widely used and studied.
  • LTPS-based high-pixel liquid crystal display panels require precise process and optimized pixel design.
  • the width of the data line in the pixel design is an important consideration.
  • the width of the data line with a smaller width will increase the aperture ratio, which also connects the through-hole of the low-temperature polysilicon layer on the data line.
  • the design has increased the requirements. It is necessary to design a data line of a smaller width.
  • the source connected to the data line needs to be connected to the low temperature polysilicon through the through hole. In the process, the through hole is limited by the limit of the photoresist exposure machine, and cannot be done. Smaller.
  • the widths of the data line, the source, and the low temperature polysilicon layer at the through hole connection are generally smaller than the above
  • the width of the data line, the source, and the low temperature polysilicon layer other than the hole connection is large, however, this affects the aperture ratio of the liquid crystal display panel.
  • the electric field effect of the data line, the source, and the low temperature polysilicon layer at the connection of the through holes affects the reverse direction of the liquid crystal, so that a wider black matrix layer needs to be disposed on the color filter substrate to block the One step affects the aperture ratio of the liquid crystal display panel.
  • the present invention provides a thin film transistor array substrate, the thin film transistor array substrate comprising:
  • a light shielding layer disposed at a middle portion of a surface of the substrate
  • a low temperature polysilicon layer disposed on the buffer layer and corresponding to the light shielding layer;
  • a metal layer is disposed on the insulating layer, and the metal layer is connected to the low temperature polysilicon layer through the through hole.
  • the insulating layer is a gate insulating layer.
  • the metal layer includes a data line and a source connected to the data line, the metal lines are equal in width, and a portion of the source adjacent to the data line is disposed corresponding to the through hole, and passes through The through hole is connected to the low temperature polysilicon layer.
  • the width of the light shielding layer is greater than the width of the metal layer, and the width of the light shielding layer is greater than or equal to the width of the through hole.
  • the material of the light shielding layer is metal
  • the material of the light shielding layer comprises Mo.
  • the thin film transistor array substrate includes a thin film transistor including the low temperature polysilicon layer, the insulating layer and the metal layer, and the thin film transistor is a top gate thin film transistor or a bottom gate thin film transistor .
  • the thin film transistor array substrate further includes:
  • a second transparent conductive layer overlying the passivation layer.
  • the first transparent conductive layer is a pixel electrode
  • the second transparent conductive layer is a common electrode Floor.
  • the present invention also provides a liquid crystal display panel comprising the thin film transistor array substrate according to any of the above embodiments.
  • the thin film transistor array substrate of the present invention and the liquid crystal display panel including the thin film transistor array substrate are provided with a light shielding layer in the middle of the surface of the substrate, and the low temperature polysilicon layer passes through a buffer layer and The light shielding layer is disposed correspondingly, the insulating layer covers the low temperature polysilicon layer, and a through hole is disposed on the insulating layer, and a width of the through hole is smaller than a width of the light shielding layer, and the metal layer is disposed on the And insulating the layer, and the metal layer is connected to the low temperature polysilicon layer through the through hole.
  • the thin film transistor array substrate of the present invention is provided with a light shielding layer on the surface of the substrate, and the light shielding layer is electrically insulated from the low temperature polysilicon layer and the metal layer through the buffer layer.
  • the arrangement of the light shielding layer does not introduce an electric field effect, and thus does not affect the guiding of the liquid crystal, thereby facilitating the improvement of the aperture ratio of the liquid crystal display panel to which the thin film transistor array substrate is applied.
  • the thin film transistor array substrate of the present invention does not affect the orientation of the liquid crystal, the thin film transistor array substrate in the present invention does not need to provide a wider black matrix layer on the color filter substrate to further block the film. The aperture ratio of the liquid crystal display panel to which the thin film transistor array substrate is applied.
  • FIG. 1 is a schematic plan view showing a planar structure of a thin film transistor array substrate according to a preferred embodiment of the present invention
  • Figure 2 is a schematic cross-sectional view along line I-I of Figure 1;
  • FIG. 3 is a schematic plan view showing a liquid crystal display panel according to a preferred embodiment of the present invention.
  • FIG. 1 is a schematic diagram showing the planar structure of a thin film transistor array substrate according to a preferred embodiment of the present invention.
  • 2 is a schematic cross-sectional view along line I-I of FIG. 1.
  • the thin film transistor array substrate 100 includes a substrate 110, a light shielding layer 120, a buffer layer 130, a low temperature polysilicon layer 140, an insulating layer 150, and a metal layer 160.
  • the light shielding layer 120 is disposed at a middle portion of a surface of the substrate 110, the buffer layer 130 covers the light shielding layer 120, and the low temperature polysilicon layer 140 is disposed on the buffer layer 130, and the light shielding layer 120 corresponds.
  • the insulating layer 150 covers the low temperature polysilicon layer 140, and the through hole 151 is disposed on the insulating layer 150.
  • the width of the through hole 151 is smaller than the width of the light shielding layer 120.
  • the metal layer 160 is disposed on the insulating layer 150, and the metal layer 160 is connected to the low temperature polysilicon layer 140 through the through hole 151.
  • the thin film transistor array substrate 100 includes a thin film transistor including a low temperature polysilicon layer 140, the insulating layer 150 and the metal layer 160, and the thin film transistor is a top gate thin film transistor or a bottom gate thin film. Transistor.
  • the thin film transistor includes a gate, a source, and a drain.
  • the gate is configured to receive a control signal and control conduction or deactivation of the source and drain under control of the control signal.
  • the gate controls the source and the drain to be turned on under the control of the control signal the source and the drain are electrically connected, and a path is formed between the source and the drain
  • the thin film transistor is turned on.
  • the gate controls the source and the drain to be turned off under the control of the control signal the source and the drain are insulated, and between the source and the drain The via is not formed and the thin film transistor is turned off (ie, not turned on).
  • the substrate 110 is transparent, and the substrate 110 can be, but not limited to, a plastic substrate or a glass substrate.
  • the substrate 110 includes a first surface 110a and a second surface 110b disposed opposite to each other, and the surface of the light shielding layer 120 disposed on the surface of the substrate 110 may be disposed on the first surface of the substrate 110
  • the light shielding layer 120 may also be disposed on the second surface 110b of the substrate 110 on the 110a.
  • the light shielding layer 120 is disposed on the first surface 110a of the substrate 110 as an example for description.
  • the light shielding layer 120 is disposed at a middle portion of a surface of the substrate 110, that is, the light shielding layer 120 is disposed at a middle portion of the first surface 110a of the substrate 110.
  • the light shielding layer 120 is configured to prevent the thin film transistor in the thin film transistor array substrate from facing the second surface of the substrate 110 The direction of 110b leaks light.
  • the material of the light shielding layer 120 is metal, and the material of the light shielding layer 120 may be, but not limited to, Mo.
  • the width of the light shielding layer 120 is greater than the width of the metal layer 160, and the width of the light shielding layer 120 is greater than or equal to the width of the through hole 151.
  • the width of the through hole 151 is a minimum width which can be prepared by being limited by the limit of the photoresist exposure machine.
  • the width of the light shielding layer 120 is greater than the width of the metal layer 160, and is smaller than the width of the data line and the source at the connection of the through holes in the background art of the present invention.
  • the width of the metal layer 160 is greater than or equal to the width of the through hole 151, and is smaller than the width of the data line and the source line at the through hole connection in the background art of the present invention.
  • the buffer layer 130 is disposed between the light shielding layer 120 and the low temperature polysilicon layer 140 for electrically insulating the light shielding layer 120 and the low temperature polysilicon layer 140.
  • the buffer layer 130 is also used to buffer damage to the substrate 110 during the preparation of the thin film transistor array substrate 100.
  • the low temperature polysilicon layer 140 is disposed on the buffer layer 130 and corresponds to the light shielding layer 120.
  • the low temperature polysilicon layer 140 corresponds to the light shielding layer 120
  • the projection of the low temperature polysilicon layer 140 on the first surface 110a of the substrate 110 falls on the light shielding layer 120 in the Within the projection on the first surface 110a of the substrate 110.
  • the projection of the low temperature polysilicon layer 140 on the first surface 110a of the substrate 110 is named as a first projection
  • the projection of the light shielding layer 120 on the first surface 110a of the substrate 110 Named second projection, in one embodiment, the first projection falls within the second projection, and the center of the first projection coincides with the center of the second projection.
  • the first projection falls within the second projection, and a center of the first projection does not coincide with a center of the second projection, an edge of the first projection and the The edges of the second projection do not coincide. In another embodiment, the first projection falls within the second projection, and an edge of the first projection coincides with an edge portion of the second projection.
  • the insulating layer 150 is a gate insulating layer, and the material of the insulating layer 150 may be, but not limited to, an oxide of silicon (such as SiO2) and a nitrogen-silicon compound (SiNx, where x is a natural number capable of forming a nitrogen-silicon compound. For example, x can be 4) and so on.
  • the metal layer 160 is disposed on the insulating layer 150, and the metal layer 160 is connected to the low temperature polysilicon layer 140 through the through hole 151.
  • the metal layer 160 includes a data line 161 and The source 162 is connected to the data line 161. The width of the metal line is equal. The portion of the source 162 adjacent to the data line 161 is disposed corresponding to the through hole 151, and the through hole 151 is The low temperature polysilicon layer 140 is connected.
  • the thin film transistor array substrate 100 further includes a planarization layer 170, a first transparent conductive layer 180a, a passivation layer 190, and a second transparent conductive layer 180b.
  • the flat layer 170 covers the metal layer 160
  • the first transparent conductive layer 180a covers the flat layer 170
  • the passivation layer 190 covers the first transparent conductive layer 180a.
  • the second transparent conductive layer 180b covers the passivation layer 190.
  • the planarization layer 170 is an organic planarization layer
  • the first transparent conductive layer 180a may be, but not limited to, indium tin oxide (ITO)
  • the second transparent conductive layer 180b may be, but is not limited to, As indium tin oxide
  • the material of the passivation layer 190 may be an oxide of silicon (such as SiO 2 ), a silicon nitride compound, or the like.
  • the first transparent conductive layer 180a is a pixel electrode
  • the second transparent conductive layer 180b is a common electrode layer.
  • the thin film transistor array substrate 100 of the present invention is provided with a light shielding layer 120 in the middle of the surface of the substrate 110, and the low temperature polysilicon layer 140 is disposed corresponding to the light shielding layer 130 through a buffer layer 130.
  • the insulating layer 150 covers the low temperature polysilicon layer 140 and the through hole 151 is disposed on the insulating layer 150, and the width of the through hole 151 is smaller than the width of the light shielding layer 120, and the metal layer 160 is disposed on the The insulating layer 150 is disposed on the insulating layer 150, and the metal layer 160 is connected to the low temperature polysilicon layer 140 through the through holes 151.
  • the thin film transistor array substrate 100 of the present invention is provided with a light shielding layer 120 on the surface of the substrate 110, and the light shielding layer 120 passes through the buffer layer 130 and the low temperature polysilicon layer 140 and the metal layer 160. Electrically, therefore, the arrangement of the light shielding layer 120 does not introduce an electric field effect, and thus does not affect the guiding of the liquid crystal, thereby facilitating the improvement of the aperture ratio of the liquid crystal display panel to which the thin film transistor array substrate 100 is applied. Further, since the thin film transistor array substrate 100 of the present invention does not affect the orientation of the liquid crystal, the thin film transistor array substrate 100 of the present invention does not need to provide a wider black matrix layer on the color filter substrate to block. The aperture ratio of the liquid crystal display panel to which the thin film transistor array substrate 100 is applied is further improved.
  • FIG. 3 is a schematic diagram showing the planar structure of a liquid crystal display panel according to a preferred embodiment of the present invention.
  • the liquid crystal display panel 10 includes the thin film transistor array substrate 100 and the liquid crystal display panel described in FIG. 1 and FIG.
  • the 10 further includes a color substrate 300 and a liquid crystal layer 500.
  • the thin film transistor array substrate 100 is disposed opposite to the color filter substrate 300, and the liquid crystal layer 500 is disposed between the thin film transistor array substrate 100 and the color filter substrate 300.
  • the thin film transistor array substrate 100 includes a substrate 110, a light shielding layer 120, a buffer layer 130, a low temperature polysilicon layer 140, an insulating layer 150, and a metal layer 160.
  • the light shielding layer 120 is disposed at a middle portion of a surface of the substrate 110, the buffer layer 130 covers the light shielding layer 120, and the low temperature polysilicon layer 140 is disposed on the buffer layer 130, and the light shielding layer 120 corresponds.
  • the insulating layer 150 covers the low temperature polysilicon layer 140, and the through hole 151 is disposed on the insulating layer 150. The width of the through hole 151 is smaller than the width of the light shielding layer 120.
  • the metal layer 160 is disposed on the insulating layer 150, and the metal layer 160 is connected to the low temperature polysilicon layer 140 through the through hole 151.
  • the thin film transistor array substrate 100 includes a thin film transistor including a low temperature polysilicon layer 140, the insulating layer 150 and the metal layer 160, and the thin film transistor is a top gate thin film transistor or a bottom gate thin film. Transistor.
  • the thin film transistor includes a gate, a source, and a drain.
  • the gate is configured to receive a control signal and control conduction or deactivation of the source and drain under control of the control signal.
  • the gate controls the source and the drain to be turned on under the control of the control signal the source and the drain are electrically connected, and a path is formed between the source and the drain
  • the thin film transistor is turned on.
  • the gate controls the source and the drain to be turned off under the control of the control signal the source and the drain are insulated, and between the source and the drain The via is not formed and the thin film transistor is turned off (ie, not turned on).
  • the substrate 110 is transparent, and the substrate 110 can be, but not limited to, a plastic substrate or a glass substrate.
  • the substrate 110 includes a first surface 110a and a second surface 110b disposed opposite to each other, and the surface of the light shielding layer 120 disposed on the surface of the substrate 110 may be disposed on the first surface of the substrate 110
  • the light shielding layer 120 may also be disposed on the second surface 110b of the substrate 110 on the 110a.
  • the light shielding layer 120 is disposed on the first surface 110a of the substrate 110 as an example for description.
  • the light shielding layer 120 is disposed at a middle portion of a surface of the substrate 110, that is, the light shielding layer 120 is disposed at a middle portion of the first surface 110a of the substrate 110.
  • the light shielding layer 120 is configured to prevent the thin film transistor in the thin film transistor array substrate from facing the second surface of the substrate 110 The direction of 110b leaks light.
  • the material of the light shielding layer 120 is metal, and the material of the light shielding layer 120 may be, but not limited to, Mo.
  • the width of the light shielding layer 120 is greater than the width of the metal layer 160, and the width of the light shielding layer 120 is greater than or equal to the width of the through hole 151.
  • the width of the through hole 151 is a minimum width which can be prepared by being limited by the limit of the photoresist exposure machine.
  • the width of the light shielding layer 120 is greater than the width of the metal layer 160, and is smaller than the width of the data line and the source at the connection of the through holes in the background art of the present invention.
  • the width of the metal layer 160 is greater than or equal to the width of the through hole 151, and is smaller than the width of the data line and the source line at the through hole connection in the background art of the present invention.
  • the buffer layer 130 is disposed between the light shielding layer 120 and the low temperature polysilicon layer 140 for electrically insulating the light shielding layer 120 and the low temperature polysilicon layer 140.
  • the buffer layer 130 is also used to buffer damage to the substrate 110 during the preparation of the thin film transistor array substrate 100.
  • the low temperature polysilicon layer 140 is disposed on the buffer layer 130 and corresponds to the light shielding layer 120.
  • the low temperature polysilicon layer 140 corresponds to the light shielding layer 120
  • the projection of the low temperature polysilicon layer 140 on the first surface 110a of the substrate 110 falls on the light shielding layer 120 in the Within the projection on the first surface 110a of the substrate 110.
  • the projection of the low temperature polysilicon layer 140 on the first surface 110a of the substrate 110 is named as a first projection
  • the projection of the light shielding layer 120 on the first surface 110a of the substrate 110 Named second projection, in one embodiment, the first projection falls within the second projection, and the center of the first projection coincides with the center of the second projection.
  • the first projection falls within the second projection, and a center of the first projection does not coincide with a center of the second projection, an edge of the first projection and the The edges of the second projection do not coincide. In another embodiment, the first projection falls within the second projection, and an edge of the first projection coincides with an edge portion of the second projection.
  • the insulating layer 150 is a gate insulating layer, and the material of the insulating layer 150 may be, but not limited to, an oxide of silicon (such as SiO2) and a nitrogen-silicon compound (SiNx, where x is a natural number capable of forming a nitrogen-silicon compound. For example, x can be 4) and so on.
  • the metal layer 160 is disposed on the insulating layer 150, and the metal layer 160 is connected to the low temperature polysilicon layer 140 through the through hole 151.
  • the metal layer 160 includes a data line 161 and The source 162 is connected to the data line 161. The width of the metal line is equal. The portion of the source 162 adjacent to the data line 161 is disposed corresponding to the through hole 151, and the through hole 151 is The low temperature polysilicon layer 140 is connected.
  • the thin film transistor array substrate 100 further includes a planarization layer 170, a first transparent conductive layer 180a, a passivation layer 190, and a second transparent conductive layer 180b.
  • the flat layer 170 covers the metal layer 160
  • the first transparent conductive layer 180a covers the flat layer 170
  • the passivation layer 190 covers the first transparent conductive layer 180a.
  • the second transparent conductive layer 180b covers the passivation layer 190.
  • the planarization layer 170 is an organic planarization layer
  • the first transparent conductive layer 180a may be, but not limited to, indium tin oxide (ITO)
  • the second transparent conductive layer 180b may be, but is not limited to, As indium tin oxide
  • the material of the passivation layer 190 may be an oxide of silicon (such as SiO 2 ), a silicon nitride compound, or the like.
  • the first transparent conductive layer 180a is a pixel electrode
  • the second transparent conductive layer 180b is a common electrode layer.
  • the thin film transistor array substrate 100 in the liquid crystal display panel 10 of the present invention is provided with a light shielding layer 120 in the middle of the surface of the substrate 110, and the low temperature polysilicon layer 140 passes through a buffer layer 130 and the
  • the light shielding layer 130 is disposed correspondingly, the insulating layer 150 covers the low temperature polysilicon layer 140, and the through hole 151 is disposed on the insulating layer 150, and the width of the through hole 151 is smaller than the width of the light shielding layer 120, the metal A layer 160 is disposed on the insulating layer 150, and the metal layer 160 is connected to the low temperature polysilicon layer 140 through the through holes 151.
  • the thin film transistor array substrate 100 of the present invention is provided with a light shielding layer 120 on the surface of the substrate 110, and the light shielding layer 120 passes through the buffer layer 130 and the low temperature polysilicon layer 140 and the metal layer 160. Electrically insulating, therefore, the arrangement of the light shielding layer 120 does not introduce an electric field effect, and thus does not affect the guiding of the liquid crystal, thereby facilitating the improvement of the aperture ratio of the liquid crystal display panel 10 to which the thin film transistor array substrate 100 is applied. . Further, since the thin film transistor array substrate 100 of the present invention does not affect the orientation of the liquid crystal, the thin film transistor array substrate 100 of the present invention does not need to provide a wider black matrix layer on the color filter substrate to block. The aperture ratio of the liquid crystal display panel 10 to which the thin film transistor array substrate 100 is applied is further improved.

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Abstract

一种薄膜晶体管阵列基板（100）以及液晶显示面板（10）。薄膜晶体管阵列基板（100）包括：基板（110）；遮光层（120），设置在基板（110）的表面的中部；缓冲层（130），覆盖遮光层（120）上；低温多晶硅层（140），设置在缓冲层（130）上，且与遮光层（120）相对应；绝缘层（150），覆盖低温多晶硅层（140），绝缘层（150）上设置贯孔（151），其中，贯孔（151）的宽度小于遮光层（120）的宽度；金属层（160），设置在绝缘层（150）上，且金属层（160）通过贯孔（151）与低温多晶硅层（140）相连。薄膜晶体管阵列基板（100）及液晶显示面板（10）具有较高的开口率。

Description

薄膜晶体管阵列基板及液晶显示面板
本发明要求2015年8月28日递交的发明名称为“薄膜晶体管阵列基板及液晶显示面板”的申请号201510540298.X的在先申请优先权，上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉及显示领域，尤其涉及一种薄膜晶体管阵列基板及液晶显示面板。
背景技术
液晶显示面板是一种常用的电子设备，由于其具有功耗低、体积小、重量轻等特点，因此备受用户的青睐。随着平面显示技术的发展，具有高像素、更低能耗的液晶显示面板的需求被提出。非晶硅的电子迁移率较低，而低温多晶硅(Low Temperature Ploy-silicon，LTPS)可以在低温下制作，且拥有比非晶硅更高的电子迁移率。其次，低温多晶硅制作的开关器件可应用于使液晶显示面板具有更高的分辨率和低能耗。因此，低温多晶硅得到了广泛地应用和研究。目前，基于LTPS的高像素的液晶显示面板要求精准的工艺制程以及优化的像素设计。其中，像素设计中的数据线(data line)的宽度是一个重要的考量指标，较小宽度的数据线的宽度将带来开口率的提高，这也对数据线上连接低温多晶硅层的贯孔的设计提高了要求。设计上需要设计较小宽度的数据线，然而，与数据线相连的源极需要通过所述贯孔与低温多晶硅相连，在工艺上，所述贯孔受到光阻曝光机极限的限制，无法做的更小。为了防止蚀刻所述贯孔时将所述贯孔蚀刻过大而引起的漏光问题，处于所述贯孔连接处的数据线、源极以及所述低温多晶硅层的宽度通常会分别比所述贯孔连接处以外的数据线、源极及低温多晶硅层的宽度较大，然而，这样一来，影响了液晶显示面板的开口率。进一步地，处于所述贯孔连接处的数据线、源极以及低温多晶硅层的电场效应会影响到液晶的倒向，从而需要在彩膜基板上设置更宽的黑矩阵层去遮挡，进 一步影响了液晶显示面板的开口率。
发明内容
本发明提供一种薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：
基板；
遮光层，设置在所述基板的表面的中部；
缓冲层，覆盖所述遮光层上；
低温多晶硅层，设置在所述缓冲层上，且与所述遮光层相对应；
绝缘层，覆盖所述低温多晶硅层，所述绝缘层上设置贯孔，其中，所述贯孔的宽度小于所述遮光层的宽度；
金属层，设置在所述绝缘层上，且所述金属层通过所述贯孔与所述低温多晶硅层相连。
其中，所述绝缘层为栅极绝缘层。
其中，所述金属层包括数据线及与所述数据线相连的源极，所述金属线各处的宽度相等，所述源极邻近所述数据线的部分对应所述贯孔设置，且通过所述贯孔与所述低温多晶硅层相连。
其中，所述遮光层的宽度大于所述金属层的宽度，且所述遮光层的宽度大于或等于所述贯孔的宽度。
其中，所述遮光层的材料为金属。
其中，所述遮光层的材料包括Mo。
其中，所述薄膜晶体管阵列基板包括薄膜晶体管，所述薄膜晶体管包括所述低温多晶硅层，所述绝缘层及所述金属层，所述薄膜晶体管为顶栅型薄膜晶体管或者为底栅型薄膜晶体管。
其中，所述薄膜晶体管阵列基板还包括：
平坦层，覆盖在所述金属层上；
第一透明导电层，覆盖在所述平坦层上；
钝化层，覆盖在所述第一透明导电层上；
第二透明导电层，覆盖在所述钝化层上。
其中，所述第一透明导电层为像素电极，所述第二透明导电层为公共电极 层。
本发明还提供一种液晶显示面板，所述液晶显示面板包括前述任意实施方式所述的薄膜晶体管阵列基板。
相较于现有技术，本发明的薄膜晶体管阵列基板以及包括所述薄膜晶体管阵列基板的液晶显示面板，在所述基板的表面的中部设置一层遮光层，且低温多晶硅层通过一缓冲层与所述遮光层对应设置，所述绝缘层覆盖所述低温多晶硅层且所述绝缘层上设置贯孔，且所述贯孔的宽度小于所述遮光层的宽度，所述金属层设置在所述绝缘层上，且所述金属层通过所述贯孔与所述低温多晶硅层相连。由此可见，本发明的薄膜晶体管阵列基板在所述基板的表面上设置遮光层，且所述遮光层通过所述缓冲层与所述低温多晶硅层以及所述金属层电性绝缘，因此，所述遮光层的设置不会引入电场效应，进而不会影响到液晶的导向，从而有利于提升所述薄膜晶体管阵列基板所应用到的液晶显示面板的开口率。进一步地，由于本发明的薄膜晶体管阵列基板不会影响到液晶的导向，因此，本发明中的薄膜晶体管阵列基板中也不需要在彩膜基板上设置更宽的黑矩阵层去遮挡，进一步提升了所述薄膜晶体管阵列基板所应用到的液晶显示面板的开口率。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图：
图1为本发明一较佳实施方式的薄膜晶体管阵列基板的平面结构示意图；
图2为图1中沿I-I沿线的剖面结构示意图；
图3为本发明一较佳实施方式的液晶显示面板的平面结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是 全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请一并参阅图1和图2，图1为本发明一较佳实施方式的薄膜晶体管阵列基板的平面结构示意图。图2为图1中沿I-I沿线的剖面结构示意图。所述薄膜晶体管阵列基板100包括基板110、遮光层120、缓冲层130、低温多晶硅层140、绝缘层150以及金属层160。所述遮光层120设置在所述基板110的表面的中部，所述缓冲层130覆盖所述遮光层120上，所述低温多晶硅层140设置在所述缓冲层130上，且与所述遮光层120相对应。所述绝缘层150覆盖所述低温多晶硅层140上，且所述绝缘层150上设置贯孔151，其中，所述贯孔151的宽度小于所述遮光层120的宽度。所述金属层160设置在所述绝缘层150上，且所述金属层160通过所述贯孔151与所述低温多晶硅层140相连。
所述薄膜晶体管阵列基板100中包括薄膜晶体管，所述薄膜晶体管包括低温多晶硅层140，所述绝缘层150及所述金属层160，所述薄膜晶体管为顶栅型薄膜晶体管或者为底栅型薄膜晶体管。所述薄膜晶体管包括栅极、源极及漏极。所述栅极用于接收控制信号，并在所述控制信号的控制下控制所述源极和漏极的导通或者截止。当所述栅极在所述控制信号的控制下控制所述源极和漏极导通时，所述源极和所述漏极电连接，所述源极及所述漏极之间形成通路，所述薄膜晶体管导通。当所述栅极在所述控制信号的控制下控制所述源极和所述漏极截止时，所述源极和所述漏极之间绝缘，所述源极及所述漏极之间不能形成通路，所述薄膜晶体管截止(即，不导通)。
所述基板110为透明的，所述基板110可以为但不限于为塑料基板或者为玻璃基板。所述基板110包括相对设置的第一表面110a以及第二表面110b，所述遮光层120设置在所述基板110的表面可以为所述遮光层120设置在所述基板110的所述第一表面110a上，也可以为所述遮光层120设置在所述基板110的所述第二表面110b上。接下来以所述遮光层120设置在所述基板110的第一表面110a上为例进行说明。
所述遮光层120设置在所述基板110的表面的中部，即，所述遮光层120设置在所述基板110的所述第一表面110a的中部。所述遮光层120用于防止所述薄膜晶体管阵列基板中的薄膜晶体管朝向所述基板110的所述第二表面 110b的方向漏光。在一实施方式中，所述遮光层120的材料为金属，所述遮光层120的材料可以为但不限于为Mo。所述遮光层120的宽度大于所述金属层160的宽度，且所述遮光层120的宽度大于或等于所述贯孔151的宽度。其中，所述贯孔151的宽度为受限于光阻曝光机的极限的限制而能够制备出来的最小的宽度。所述遮光层120的宽度大于所述金属层160的宽度，且小于本发明的背景技术中在处于所述贯孔连接处的数据线、源极的宽度。所述金属层160的宽度大于或等于所述贯孔151的宽度，且小于本发明的背景技术中处于所述贯孔连接处的数据线、源极线的宽度。
所述缓冲层130设置在所述遮光层120以及所述低温多晶硅层140之间，用于将所述遮光层120以及所述低温多晶硅层140电性绝缘。所述缓冲层130还用于缓冲所述薄膜晶体管阵列基板100的制备过程中对所述基板110的损伤。
所述低温多晶硅层140设置在所述缓冲层130上，且与所述遮光层120相对应。这里，所述低温多晶硅层140与所述遮光层120相对应是指，所述低温多晶硅层140在所述基板110的所述第一表面110a上的投影落在所述遮光层120在所述基板110的所述第一表面110a上的投影内。为了方便描述，所述低温多晶硅层140在所述基板110的所述第一表面110a的投影命名为第一投影，所述遮光层120在所述基板110的所述第一表面110a上的投影命名为第二投影，在一实施方式中，所述第一投影落在所述第二投影内，且所述第一投影的中心与所述第二投影的中心重合。在另一实施方式中，所述第一投影落在所述第二投影内，且所述第一投影的中心与所述第二投影的中心不重合，所述第一投影的边缘与所述第二投影的边缘不重合。在另一实施方式中，所述第一投影落在所述第二投影内，且所述第一投影的边缘与所述第二投影的边缘部分重合。
所述绝缘层150为栅极绝缘层，所述绝缘层150的材料可以为但不仅限于为硅的氧化物(比如SiO2)、氮硅化合物(SiNx，其中，x为能够形成氮硅化合物的自然数，比如，x可以为4)等。
所述金属层160设置在所述绝缘层150上，且所述金属层160通过所述贯孔151与所述低温多晶硅层140相连。所述金属层160包括数据线161及与所 述数据线161相连的源极162，所述金属线各处的宽度相等，所述源极162邻近所述数据线161的部分对应所述贯孔151设置，且通过所述贯孔151与所述低温多晶硅层140相连。
所述薄膜晶体管阵列基板100还包括平坦层170、第一透明导电层180a、钝化层190以及第二透明导电层180b。所述平坦层170覆盖在所述金属层160上，所述第一透明导电层180a覆盖在所述平坦层170上，所述钝化层190覆盖在所述第一透明导电层180a上，所述第二透明导电层180b覆盖在所述钝化层190上。在一实施方式中，所述平坦层170为有机平坦层，所述第一透明导电层180a可以为但不仅限于为氧化铟锡(ITO)，所述第二透明导电层180b可以为但不仅限于为氧化铟锡，所述钝化层190的材料可以为硅的氧化物(比如SiO2)、氮硅化合物等。在一实施方式中，所述第一透明导电层180a为像素电极，所述第二透明导电层180b为公共电极层。
相较于现有技术，本发明的薄膜晶体管阵列基板100在所述基板110的表面的中部设置一层遮光层120，且低温多晶硅层140通过一缓冲层130与所述遮光层130对应设置，所述绝缘层150覆盖所述低温多晶硅层140且所述绝缘层150上设置贯孔151，且所述贯孔151的宽度小于所述遮光层120的宽度，所述金属层160设置在所述绝缘层150上，且所述金属层160通过所述贯孔151与所述低温多晶硅层140相连。由此可见，本发明的薄膜晶体管阵列基板100在所述基板110的表面上设置遮光层120，且所述遮光层120通过所述缓冲层130与所述低温多晶硅层140以及所述金属层160电性绝缘，因此，所述遮光层120的设置不会引入电场效应，进而不会影响到液晶的导向，从而有利于提升所述薄膜晶体管阵列基板100所应用到的液晶显示面板的开口率。进一步地，由于本发明的薄膜晶体管阵列基板100不会影响到液晶的导向，因此，本发明中的薄膜晶体管阵列基板100中也不需要在彩膜基板上设置更宽的黑矩阵层去遮挡，进一步提升了所述薄膜晶体管阵列基板100所应用到的液晶显示面板的开口率。
下面结合图1和图2对本发明的液晶显示面板进行介绍。请参阅图3，图3为本发明一较佳实施方式的液晶显示面板的平面结构示意图。所述液晶显示面板10包括图1及图2所述的薄膜晶体管阵列基板100、所述液晶显示面板 10还包括彩基板300以及液晶层500。所述薄膜晶体管阵列基板100与所述彩膜基板300相对设置，所述液晶层500设置在所述薄膜晶体管阵列基板100与所述彩膜基板300之间。
所述薄膜晶体管阵列基板100包括基板110、遮光层120、缓冲层130、低温多晶硅层140、绝缘层150以及金属层160。所述遮光层120设置在所述基板110的表面的中部，所述缓冲层130覆盖所述遮光层120上，所述低温多晶硅层140设置在所述缓冲层130上，且与所述遮光层120相对应。所述绝缘层150覆盖所述低温多晶硅层140上，且所述绝缘层150上设置贯孔151，其中，所述贯孔151的宽度小于所述遮光层120的宽度。所述金属层160设置在所述绝缘层150上，且所述金属层160通过所述贯孔151与所述低温多晶硅层140相连。
所述薄膜晶体管阵列基板100中包括薄膜晶体管，所述薄膜晶体管包括低温多晶硅层140，所述绝缘层150及所述金属层160，所述薄膜晶体管为顶栅型薄膜晶体管或者为底栅型薄膜晶体管。所述薄膜晶体管包括栅极、源极及漏极。所述栅极用于接收控制信号，并在所述控制信号的控制下控制所述源极和漏极的导通或者截止。当所述栅极在所述控制信号的控制下控制所述源极和漏极导通时，所述源极和所述漏极电连接，所述源极及所述漏极之间形成通路，所述薄膜晶体管导通。当所述栅极在所述控制信号的控制下控制所述源极和所述漏极截止时，所述源极和所述漏极之间绝缘，所述源极及所述漏极之间不能形成通路，所述薄膜晶体管截止(即，不导通)。
所述基板110为透明的，所述基板110可以为但不限于为塑料基板或者为玻璃基板。所述基板110包括相对设置的第一表面110a以及第二表面110b，所述遮光层120设置在所述基板110的表面可以为所述遮光层120设置在所述基板110的所述第一表面110a上，也可以为所述遮光层120设置在所述基板110的所述第二表面110b上。接下来以所述遮光层120设置在所述基板110的第一表面110a上为例进行说明。
所述遮光层120设置在所述基板110的表面的中部，即，所述遮光层120设置在所述基板110的所述第一表面110a的中部。所述遮光层120用于防止所述薄膜晶体管阵列基板中的薄膜晶体管朝向所述基板110的所述第二表面 110b的方向漏光。在一实施方式中，所述遮光层120的材料为金属，所述遮光层120的材料可以为但不仅限于为Mo。所述遮光层120的宽度大于所述金属层160的宽度，且所述遮光层120的宽度大于或等于所述贯孔151的宽度。其中，所述贯孔151的宽度为受限于光阻曝光机的极限的限制而能够制备出来的最小的宽度。所述遮光层120的宽度大于所述金属层160的宽度，且小于本发明的背景技术中在处于所述贯孔连接处的数据线、源极的宽度。所述金属层160的宽度大于或等于所述贯孔151的宽度，且小于本发明的背景技术中处于所述贯孔连接处的数据线、源极线的宽度。
所述缓冲层130设置在所述遮光层120以及所述低温多晶硅层140之间，用于将所述遮光层120以及所述低温多晶硅层140电性绝缘。所述缓冲层130还用于缓冲所述薄膜晶体管阵列基板100的制备过程中对所述基板110的损伤。
所述低温多晶硅层140设置在所述缓冲层130上，且与所述遮光层120相对应。这里，所述低温多晶硅层140与所述遮光层120相对应是指，所述低温多晶硅层140在所述基板110的所述第一表面110a上的投影落在所述遮光层120在所述基板110的所述第一表面110a上的投影内。为了方便描述，所述低温多晶硅层140在所述基板110的所述第一表面110a的投影命名为第一投影，所述遮光层120在所述基板110的所述第一表面110a上的投影命名为第二投影，在一实施方式中，所述第一投影落在所述第二投影内，且所述第一投影的中心与所述第二投影的中心重合。在另一实施方式中，所述第一投影落在所述第二投影内，且所述第一投影的中心与所述第二投影的中心不重合，所述第一投影的边缘与所述第二投影的边缘不重合。在另一实施方式中，所述第一投影落在所述第二投影内，且所述第一投影的边缘与所述第二投影的边缘部分重合。
所述绝缘层150为栅极绝缘层，所述绝缘层150的材料可以为但不仅限于为硅的氧化物(比如SiO2)、氮硅化合物(SiNx，其中，x为能够形成氮硅化合物的自然数，比如，x可以为4)等。
所述金属层160设置在所述绝缘层150上，且所述金属层160通过所述贯孔151与所述低温多晶硅层140相连。所述金属层160包括数据线161及与所 述数据线161相连的源极162，所述金属线各处的宽度相等，所述源极162邻近所述数据线161的部分对应所述贯孔151设置，且通过所述贯孔151与所述低温多晶硅层140相连。
所述薄膜晶体管阵列基板100还包括平坦层170、第一透明导电层180a、钝化层190以及第二透明导电层180b。所述平坦层170覆盖在所述金属层160上，所述第一透明导电层180a覆盖在所述平坦层170上，所述钝化层190覆盖在所述第一透明导电层180a上，所述第二透明导电层180b覆盖在所述钝化层190上。在一实施方式中，所述平坦层170为有机平坦层，所述第一透明导电层180a可以为但不仅限于为氧化铟锡(ITO)，所述第二透明导电层180b可以为但不仅限于为氧化铟锡，所述钝化层190的材料可以为硅的氧化物(比如SiO2)、氮硅化合物等。在一实施方式中，所述第一透明导电层180a为像素电极，所述第二透明导电层180b为公共电极层。
相较于现有技术，本发明的液晶显示面板10中的薄膜晶体管阵列基板100在所述基板110的表面的中部设置一层遮光层120，且低温多晶硅层140通过一缓冲层130与所述遮光层130对应设置，所述绝缘层150覆盖所述低温多晶硅层140且所述绝缘层150上设置贯孔151，且所述贯孔151的宽度小于所述遮光层120的宽度，所述金属层160设置在所述绝缘层150上，且所述金属层160通过所述贯孔151与所述低温多晶硅层140相连。由此可见，本发明的薄膜晶体管阵列基板100在所述基板110的表面上设置遮光层120，且所述遮光层120通过所述缓冲层130与所述低温多晶硅层140以及所述金属层160电性绝缘，因此，所述遮光层120的设置不会引入电场效应，进而不会影响到液晶的导向，从而有利于提升所述薄膜晶体管阵列基板100所应用到的液晶显示面板10的开口率。进一步地，由于本发明的薄膜晶体管阵列基板100不会影响到液晶的导向，因此，本发明中的薄膜晶体管阵列基板100中也不需要在彩膜基板上设置更宽的黑矩阵层去遮挡，进一步提升了所述薄膜晶体管阵列基板100所应用到的液晶显示面板10的开口率。
以上所揭露的仅为本发明一种较佳实施例而已，当然不能以此来限定本发明之权利范围，本领域普通技术人员可以理解实现上述实施例的全部或部分流程，并依本发明权利要求所作的等同变化，仍属于发明所涵盖的范围。

Claims (18)

  1. 一种薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板包括：
    基板；
    遮光层，设置在所述基板的表面的中部；
    缓冲层，覆盖所述遮光层上；
    低温多晶硅层，设置在所述缓冲层上，且与所述遮光层相对应；
    绝缘层，覆盖所述低温多晶硅层，所述绝缘层上设置贯孔，其中，所述贯孔的宽度小于所述遮光层的宽度；
    金属层，设置在所述绝缘层上，且所述金属层通过所述贯孔与所述低温多晶硅层相连。
  2. 如权利要求1所述的薄膜晶体管阵列基板，其中，所述绝缘层为栅极绝缘层。
  3. 如权利要求1所述的薄膜晶体管阵列基板，其中，所述金属层包括数据线及与所述数据线相连的源极，所述金属线各处的宽度相等，所述源极邻近所述数据线的部分对应所述贯孔设置，且通过所述贯孔与所述低温多晶硅层相连。
  4. 如权利要求3所述的薄膜晶体管阵列基板，其中，所述遮光层的宽度大于所述金属层的宽度，且所述遮光层的宽度大于或等于所述贯孔的宽度。
  5. 如权利要求1所述的薄膜晶体管阵列基板，其中，所述遮光层的材料为金属。
  6. 如权利要求5所述的薄膜晶体管阵列基板，其中，所述遮光层的材料包括Mo。
  7. 如权利要求1所述的薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板包括薄膜晶体管，所述薄膜晶体管包括所述低温多晶硅层，所述绝缘层及所述金属层，所述薄膜晶体管为顶栅型薄膜晶体管或者为底栅型薄膜晶体管。
  8. 如权利要求1所述的薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板还包括：
    平坦层，覆盖在所述金属层上；
    第一透明导电层，覆盖在所述平坦层上；
    钝化层，覆盖在所述第一透明导电层上；
    第二透明导电层，覆盖在所述钝化层上。
  9. 如权利要求8所述的薄膜晶体管阵列基板，其中，所述第一透明导电层为像素电极，所述第二透明导电层为公共电极层。
  10. 一种液晶显示面板，其中，所述液晶显示面板包括薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板包括：
    基板；
    遮光层，设置在所述基板的表面的中部；
    缓冲层，覆盖所述遮光层上；
    低温多晶硅层，设置在所述缓冲层上，且与所述遮光层相对应；
    绝缘层，覆盖所述低温多晶硅层，所述绝缘层上设置贯孔，其中，所述贯孔的宽度小于所述遮光层的宽度；
    金属层，设置在所述绝缘层上，且所述金属层通过所述贯孔与所述低温多晶硅层相连。
  11. 如权利要求10所述的液晶显示面板，其中，所述绝缘层为栅极绝缘层。
  12. 如权利要求10所述的液晶显示面板，其中，所述金属层包括数据线及与所述数据线相连的源极，所述金属线各处的宽度相等，所述源极邻近所述 数据线的部分对应所述贯孔设置，且通过所述贯孔与所述低温多晶硅层相连。
  13. 如权利要求12所述的液晶显示面板，其中，所述遮光层的宽度大于所述金属层的宽度，且所述遮光层的宽度大于或等于所述贯孔的宽度。
  14. 如权利要求10所述的液晶显示面板，其中，所述遮光层的材料为金属。
  15. 如权利要求14所述的液晶显示面板，其中，所述遮光层的材料包括Mo。
  16. 如权利要求10所述的液晶显示面板，其中，所述薄膜晶体管阵列基板包括薄膜晶体管，所述薄膜晶体管包括所述低温多晶硅层，所述绝缘层及所述金属层，所述薄膜晶体管为顶栅型薄膜晶体管或者为底栅型薄膜晶体管。
  17. 如权利要求10所述的液晶显示面板，其中，所述薄膜晶体管阵列基板还包括：
    平坦层，覆盖在所述金属层上；
    第一透明导电层，覆盖在所述平坦层上；
    钝化层，覆盖在所述第一透明导电层上；
    第二透明导电层，覆盖在所述钝化层上。
  18. 如权利要求17所述的液晶显示面板，其中，所述第一透明导电层为像素电极，所述第二透明导电层为公共电极层。
PCT/CN2015/090330 2015-08-28 2015-09-23 薄膜晶体管阵列基板及液晶显示面板 Ceased WO2017035880A1 (zh)

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CN108447873A (zh) * 2018-03-19 2018-08-24 武汉华星光电技术有限公司 一种阵列基板及制备方法
KR102936407B1 (ko) * 2019-12-30 2026-03-06 엘지디스플레이 주식회사 박막 트랜지스터 및 이를 이용한 표시패널

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