WO2017034203A1 - Oxide transistor and manufacturing method therefor - Google Patents
Oxide transistor and manufacturing method therefor Download PDFInfo
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- WO2017034203A1 WO2017034203A1 PCT/KR2016/009000 KR2016009000W WO2017034203A1 WO 2017034203 A1 WO2017034203 A1 WO 2017034203A1 KR 2016009000 W KR2016009000 W KR 2016009000W WO 2017034203 A1 WO2017034203 A1 WO 2017034203A1
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- oxide
- thin film
- substrate
- active layer
- mixed solution
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000010409 thin film Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000004528 spin coating Methods 0.000 claims abstract description 20
- 238000000137 annealing Methods 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims abstract description 10
- 230000001678 irradiating effect Effects 0.000 claims abstract description 7
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 5
- 239000010703 silicon Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 35
- 239000000243 solution Substances 0.000 claims description 19
- 239000010408 film Substances 0.000 claims description 12
- 239000011259 mixed solution Substances 0.000 claims description 11
- 229910052738 indium Inorganic materials 0.000 claims description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 5
- NJWNEWQMQCGRDO-UHFFFAOYSA-N indium zinc Chemical compound [Zn].[In] NJWNEWQMQCGRDO-UHFFFAOYSA-N 0.000 claims description 5
- 239000011701 zinc Substances 0.000 claims description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 4
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910052725 zinc Inorganic materials 0.000 claims description 3
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 2
- ZMKRJDCTUNZSFT-UHFFFAOYSA-N [O--].[O--].[O--].[Y+3].[In+3] Chemical compound [O--].[O--].[O--].[Y+3].[In+3] ZMKRJDCTUNZSFT-UHFFFAOYSA-N 0.000 claims description 2
- 229910052733 gallium Inorganic materials 0.000 claims description 2
- KYKLWYKWCAYAJY-UHFFFAOYSA-N oxotin;zinc Chemical compound [Zn].[Sn]=O KYKLWYKWCAYAJY-UHFFFAOYSA-N 0.000 claims description 2
- 239000011787 zinc oxide Substances 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 2
- 238000000576 coating method Methods 0.000 claims 2
- 239000012212 insulator Substances 0.000 abstract 2
- 239000000203 mixture Substances 0.000 abstract 1
- YRKCREAYFQTBPV-UHFFFAOYSA-N acetylacetone Chemical compound CC(=O)CC(C)=O YRKCREAYFQTBPV-UHFFFAOYSA-N 0.000 description 4
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000003153 chemical reaction reagent Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- XNWFRZJHXBZDAG-UHFFFAOYSA-N 2-METHOXYETHANOL Chemical compound COCCO XNWFRZJHXBZDAG-UHFFFAOYSA-N 0.000 description 1
- 241000252506 Characiformes Species 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000002894 chemical waste Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- YZZFBYAKINKKFM-UHFFFAOYSA-N dinitrooxyindiganyl nitrate;hydrate Chemical compound O.[In+3].[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O YZZFBYAKINKKFM-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000307 polymer substrate Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000003381 stabilizer Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- YZYKBQUWMPUVEN-UHFFFAOYSA-N zafuleptine Chemical compound OC(=O)CCCCCC(C(C)C)NCC1=CC=C(F)C=C1 YZYKBQUWMPUVEN-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Definitions
- the present invention relates to an oxide transistor manufacturing technology, and more particularly to an oxide transistor having a bottom gate structure and a method of manufacturing the same.
- TFTs thin film transistors
- the TFT thus manufactured may be applied to various flexible electronic devices implemented on a polymer substrate.
- Photolithography is mainly used as a TFT process for forming electrodes or wirings according to the prior art.
- the photolithography method after forming a conductive film by an existing film forming method, such as sputtering, plating, or CDD, by applying a photosensitive material on a substrate, and developing by irradiating with light, the conductive film is etched according to a resist pattern. The electrode or wiring pattern of the functional thin film is formed.
- This photolithography method requires extensive equipment and complicated processes such as a vacuum device in forming, patterning, film forming, and etching the thin film.
- a vacuum device in forming, patterning, film forming, and etching the thin film.
- the material use efficiency is only a few percent, when the process is terminated, it cannot be reused and must be disposed of, resulting in high manufacturing costs and a large amount of unnecessary chemical waste.
- the present invention has been made in the technical background as described above, and an object thereof is to provide an oxide transistor capable of lowering the process temperature and a method of manufacturing the same.
- An oxide transistor includes a substrate used as a gate electrode; A gate insulating film formed on the substrate; In the process of spin coating a mixed solution of a semiconductor material having a band gap greater than or equal to a predetermined reference value on the silicon insulating film for a predetermined time to form an oxide active layer and then annealing Oxide thin film formed according to; And source and drain electrodes formed by depositing aluminum on the oxide thin film.
- an oxide transistor wherein the oxide is irradiated with ultraviolet rays during a spin coating process of a mixed solution of a semiconductor material having a band gap (gap) on the substrate on which the silicon gate insulating film is formed.
- Forming an active layer Forming an oxide thin film by annealing the substrate on which the oxide active layer is formed; And depositing aluminum on the oxide thin film to form source and drain electrodes.
- the process temperature can be lowered and the transistor performance can be improved.
- FIG 1 illustrates an oxide transistor according to an embodiment of the present invention.
- FIG 2 illustrates an oxide transistor manufacturing process according to an embodiment of the present invention.
- 3A and 3B are graphs showing an output curve (drain current) and a transfer curve of an oxide transistor manufactured by varying ultraviolet irradiation time during spin coating, respectively, according to an embodiment of the present invention.
- FIG. 1 is a diagram illustrating an oxide transistor according to an embodiment of the present invention
- FIG. 2 is a diagram illustrating an oxide transistor manufacturing process according to an embodiment of the present invention.
- an oxide transistor having a top-contact bottom-gate structure has been described as an example.
- an oxide transistor 10 includes a substrate 110, a gate insulating layer 120, an IZO thin film 130, and source and drain electrodes 141 and 142. .
- the substrate 110 is manufactured using a 600um heavy doped n-type Si wafer, and is used as a gate electrode.
- the gate insulating layer 120 is formed on the substrate 110 and is formed by growing silicon dioxide (SiO 2 ) to a thickness of 100 nm through a thermal oxidation process in a furnace.
- the substrate 110 on which the gate insulating film 120 is formed may be used to form the IZO thin film 130 after standard cleaning by, for example, piranha cleaning.
- the IZO thin film 130 is formed by annealing the oxide active layer formed by irradiating ultraviolet rays while spin-processing an indium-zinc solution onto the substrate 110 to evaporate the remaining solvent.
- the indium zinc solution may be prepared through the following process. Specifically, 2-methoxyethanol is used as a solvent for preparing a 0.1 M indium and zinc solution. To the indium solution, acetylacetone is added as a stabilizer for dissolving reagents, NH 3 is added as a catalyst for rapid reaction, and zinc solution is added with only acetylacetone, which is stabilized at 60 ° C. for 1 hour. ). In this case, indium nitrate hydrate [In (NO 3 ) 32 O], zinc acetate dihydrate [Zn (CH 3 COO) 22 O] is used as the reagent. Thereafter, the In solution and the Zn solution were mixed at a ratio of 7: 3, and steering was performed at room temperature for 2 hours.
- 2-methoxyethanol is used as a solvent for preparing a 0.1 M indium and zinc solution.
- acetylacetone is added as a stabilizer for dissolving reagents
- NH 3 is added as a catalyst for
- the indium-zinc solution described above may be replaced with a mixed solution of other semiconductor materials having a band gap of more than a predetermined reference value.
- the predetermined reference value may be 3.5, which is a band gap of the IZO semiconductor thin film.
- the mixed solution of another semiconductor material may be an oxide-based semiconductor indium gallium zinc oxide (IYO), zinc tin oxide (IGZO), indium yttrium oxide (ZTO), or the like.
- the oxide active layer rotates the substrate 110 at a predetermined speed, and coats an indium-zinc solution with a thickness of 20 to 30 nm, while applying predetermined ultraviolet rays to the upper portion of the gate insulating film 120. It may be formed by irradiation for a predetermined time.
- the spin speed of the substrate 110 during the spin coating is 1500rpm
- the predetermined ultraviolet light may have a wavelength of 300nm ⁇ 450nm.
- the intensity of the ultraviolet ray is 1200mW / cm 2 It may be a time of 60 seconds or more while the irradiation time of the ultraviolet ray is 90 seconds or less.
- the predetermined intensity and irradiation time of ultraviolet rays may be determined in consideration of the on / off ratio and mobility characteristics. For example, UV irradiation time during spin coating becomes shorter as the intensity of ultraviolet light increases, but as a result of the test, the on / off ratio and mobility of the oxide transistor 10 according to the embodiment of the present invention can be maintained above a predetermined value. It can be set to.
- the constant values of the on / off ratio and mobility may be 10 4 and 3 cm 2 / Vs, respectively.
- the overall process time can be shortened, and the temperature of the solution process can be lowered to fabricate a flexible device.
- the IZO thin film 130 may be formed by annealing the substrate 110 coated with the oxide active layer at a temperature of 350 ° C. in a furnace for 4 hours.
- annealing using the furnace may prevent performance unevenness for each device, and an annealing using the furnace after UV irradiation and spin may prevent the device from deteriorating characteristics due to the annealing. Can be.
- the source and drain electrodes 141 and 142 may deposit an aluminum source having a thickness of 100 nm by using a metal evaporator at positions where the source and drain electrodes of the IZO thin film 130 will be formed. It is formed as.
- the embodiment of the present invention can shorten the process step by using the solution process, and can shorten the process time by simultaneously proceeding the UV irradiation and the solution process, and lower the temperature of the solution process to provide a flexible device. I can make it.
- the embodiment of the present invention can maintain the device-specific performance to some extent, and can prevent the deterioration of the characteristics of the device due to the annealing.
- the embodiment of the present invention can be applied to a transparent electronic device by fabricating an indium-zinc oxide semiconductor transistor having a large band gap.
- embodiments of the present invention may improve characteristics of various fields such as oxide transistors, display backplane devices, flexible electronic devices, and transparent electronic devices.
- FIGS. 3A and 3B are graphs illustrating output curves (drain currents) and transfer curves of oxide transistors manufactured by varying ultraviolet irradiation time during spin coating, respectively, according to an embodiment of the present invention.
- the source electrode of the oxide transistor was grounded, and a voltage was applied to the drain electrode and the gate electrode.
- 3a and 3b (a) is not irradiated with ultraviolet light during spin coating, (b) is irradiated with ultraviolet light for 30 seconds during spin coating, (c) is 60 seconds irradiated with ultraviolet light during spin coating and (d) are graphs when 90 seconds of ultraviolet radiation was applied during spin coating.
- the on / off ratio is 10 7
- the mobility is 3 cm 2 / Vs or more.
- the mobility is excellent in more than 5cm 2 / Vs, it can be seen that the on / off ratio is low as 10 4 .
- the present invention it is possible to assist in manufacturing an oxide transistor capable of guaranteeing an on / off ratio and mobility to some extent as the UV irradiation time is adjusted during the spin coating process.
Abstract
An oxide transistor and a manufacturing method therefor are disclosed. According to one aspect of the present invention, the oxide transistor comprises: a substrate to be used as a gate electrode; a gate insulator formed on the substrate; an oxide thin film formed by forming an oxide active layer by irradiating predetermined ultraviolet rays for a predetermined time during a step of spin coating, on the upper part of the silicon insulator, a mixture solution of a semiconductor material having a band gap of a predetermined reference value or more, and then annealing the same; and source and drain electrodes formed by depositing aluminum on the upper part of the oxide thin film.
Description
본 발명은 산화물 트랜지스터 제조 기술에 관한 것으로서, 더 구체적으로는 하부 게이트 구조의 산화물 트랜지스터 및 그 제조 방법에 관한 것이다.The present invention relates to an oxide transistor manufacturing technology, and more particularly to an oxide transistor having a bottom gate structure and a method of manufacturing the same.
최근, 박막트랜지스터(이하 TFT)를 용액상태의 저온공정으로 제조하고자 하는 연구가 활발히 진행되고 있다. 이러한 제조방법의 가장 큰 장점은 기존의 진공장치를 기반으로 전자기능성 박막을 형성했던 공정에 비해 상대적으로 저렴한 제조비용으로 박막을 제조할 수 있다는 점이다. In recent years, research has been actively conducted to manufacture thin film transistors (hereinafter referred to as TFTs) by a low temperature process in a solution state. The biggest advantage of this manufacturing method is that the thin film can be manufactured at a relatively low manufacturing cost compared to the process of forming the electronic functional thin film based on the conventional vacuum apparatus.
또한, 상기 용액공정으로 제조된 TFT를 차세대 플렉서블 디스플레이의 구동소자나 바코드를 대체하는 개별물품단위 인식용 초저가 RFID 태그의 로직회로 등으로 활용하기 위해 많은 연구가 진행되고 있다. In addition, a lot of research is being conducted to utilize the TFT manufactured by the solution process as a logic circuit of a low-cost RFID tag for recognizing an individual article unit that replaces a driving element or a barcode of a next-generation flexible display.
더 나아가, 이렇게 제조된 TFT는 고분자 기판위에 구현되는 다양한 플렉서블 전자소자에 적용될 수 있다.Furthermore, the TFT thus manufactured may be applied to various flexible electronic devices implemented on a polymer substrate.
종래 기술에 따른 전극 또는 배선 등을 형성하는 TFT 공정으로는 포토리소그래피법이 주로 사용된다. 포토리소그래피법은 스퍼터법, 도금, 또는 ＣＶＤ법과 같이 기존 성막법에 의해 도전막을 형성한 후, 기판상에 감광재를 도포하고, 광을 조사하여 현상한 후, 레지스트 패턴에 따라 도전막을 에칭함으로써, 기능 박막의 전극 또는 배선패턴을 형성하는 단계를 거친다. Photolithography is mainly used as a TFT process for forming electrodes or wirings according to the prior art. In the photolithography method, after forming a conductive film by an existing film forming method, such as sputtering, plating, or CDD, by applying a photosensitive material on a substrate, and developing by irradiating with light, the conductive film is etched according to a resist pattern. The electrode or wiring pattern of the functional thin film is formed.
이러한 포토리소그래피법은 박막의 형성, 패터닝, 성막처리 및 에칭 처리시에 진공장치 등의 대대적인 설비와 복잡한 공정을 필요로 한다. 또한, 재료 사용 효율이 수 % 정도에 지나지 않아 공정이 종료되면 재사용이 불가하고 폐기할 수 밖에 없으므로 제조 비용이 높고 불필요한 화학폐기물을 다량 발생시킬 수 있다.This photolithography method requires extensive equipment and complicated processes such as a vacuum device in forming, patterning, film forming, and etching the thin film. In addition, since the material use efficiency is only a few percent, when the process is terminated, it cannot be reused and must be disposed of, resulting in high manufacturing costs and a large amount of unnecessary chemical waste.
본 발명은 전술한 바와 같은 기술적 배경에서 안출된 것으로서, 공정 온도를 낮출 수 있는 산화물 트랜지스터 및 그 제조 방법을 제공하는 것을 그 목적으로 한다.The present invention has been made in the technical background as described above, and an object thereof is to provide an oxide transistor capable of lowering the process temperature and a method of manufacturing the same.
본 발명의 목적은 이상에서 언급한 목적으로 제한되지 않으며, 언급되지 않은 또 다른 목적들은 아래의 기재로부터 당업자에게 명확하게 이해될 수 있을 것이다.The object of the present invention is not limited to the above-mentioned object, and other objects that are not mentioned will be clearly understood by those skilled in the art from the following description.
본 발명의 일면에 따른 산화물 트랜지스터는, 게이트 전극으로 사용되는 기판; 상기 기판 상에 형성된 게이트절연막; 상기 실리콘 절연막의 상부에 밴드갭(Gap)이 기설정된 기준치 이상인 반도체 물질의 혼합 용액을 스핀코팅(Spin Coating)하는 공정중에 기설정된 자외선을 기설정된 시간동안 조사하여 산화물 활성층을 형성한 후 어닐링(annealing)함에 따라 형성된 산화물 박막; 및 상기 산화물 박막의 상부에 알루미늄을 증착하여 형성된 소스 및 드레인 전극을 포함하는 것을 특징으로 한다.An oxide transistor according to one aspect of the present invention includes a substrate used as a gate electrode; A gate insulating film formed on the substrate; In the process of spin coating a mixed solution of a semiconductor material having a band gap greater than or equal to a predetermined reference value on the silicon insulating film for a predetermined time to form an oxide active layer and then annealing Oxide thin film formed according to; And source and drain electrodes formed by depositing aluminum on the oxide thin film.
본 발명의 다른 면에 따른 산화물 트랜지스터 제조 방법은, 실리콘 게이트절연막이 형성된 기판에 밴드갭(Gap)이 기설정된 기준치 이상인 반도체 물질의 혼합 용액을 회전코팅(Spin Coating)하는 공정 중에 자외선을 조사하여 산화물 활성층을 형성하는 단계; 상기 산화물 활성층이 형성된 상기 기판을 어닐링(annealing)함에 따라 산화물 박막을 형성하는 단계; 및 상기 산화물 박막의 상부에 알루미늄을 증착하여 소스 및 드레인 전극을 형성하는 단계를 포함하는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of manufacturing an oxide transistor, wherein the oxide is irradiated with ultraviolet rays during a spin coating process of a mixed solution of a semiconductor material having a band gap (gap) on the substrate on which the silicon gate insulating film is formed. Forming an active layer; Forming an oxide thin film by annealing the substrate on which the oxide active layer is formed; And depositing aluminum on the oxide thin film to form source and drain electrodes.
본 발명에 따르면, 공정 온도를 낮출 수 있고 트랜지스터 성능을 개선할 수 있다.According to the present invention, the process temperature can be lowered and the transistor performance can be improved.
도 1은 본 발명의 실시예에 따른 산화물 트랜지스터를 도시한 도면.1 illustrates an oxide transistor according to an embodiment of the present invention.
도 2는 본 발명의 실시예에 따른 산화물 트랜지스터 제조 공정을 도시한 도면.2 illustrates an oxide transistor manufacturing process according to an embodiment of the present invention.
도 3a 및 도 3b는 각기 본 발명의 실시예에 따른 스핀코팅시에 자외선 조사시간을 달리하여 제조된 산화물 트랜지스터의 출력 커브(드레인 전류)와 전달 커브를 도시한 그래프.3A and 3B are graphs showing an output curve (drain current) and a transfer curve of an oxide transistor manufactured by varying ultraviolet irradiation time during spin coating, respectively, according to an embodiment of the present invention.
본 발명의 전술한 목적 및 그 이외의 목적과 이점 및 특징, 그리고 그것들을 달성하는 방법은 첨부되는 도면과 함께 상세하게 후술되어 있는 실시예들을 참조하면 명확해질 것이다. 그러나 본 발명은 이하에서 개시되는 실시예들에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예들은 본 발명의 개시가 완전하도록 하며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이며, 본 발명은 청구항의 범주에 의해 정의될 뿐이다. 한편, 본 명세서에서 사용된 용어는 실시예들을 설명하기 위한 것이며 본 발명을 제한하고자 하는 것은 아니다. 본 명세서에서, 단수형은 문구에서 특별히 언급하지 않는 한 복수형도 포함한다. 명세서에서 사용되는 "포함한다(comprises)" 및/또는 "포함하는(comprising)"은 언급된 구성소자, 단계, 동작 및/또는 소자는 하나 이상의 다른 구성소자, 단계, 동작 및/또는 소자의 존재 또는 추가를 배제하지 않는다.BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, advantages and features of the present invention, and methods of achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Meanwhile, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, “comprises” and / or “comprising” refers to a component, step, operation and / or device that is present in one or more other components, steps, operations and / or elements. Or does not exclude additions.
이제 본 발명의 실시예에 대하여 첨부한 도면을 참조하여 상세히 설명하기로 한다. 도 1은 본 발명의 실시예에 따른 산화물 트랜지스터를 도시한 도면이고, 도 2는 본 발명의 실시예에 따른 산화물 트랜지스터 제조 공정을 도시한 도면이다. 본 명세서에서는 상부 전극 하부 게이트(top-contact bottom-gate) 구조의 산화물 트랜지스터에 대하여 예로 들어 설명하였다.Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 is a diagram illustrating an oxide transistor according to an embodiment of the present invention, and FIG. 2 is a diagram illustrating an oxide transistor manufacturing process according to an embodiment of the present invention. In the present specification, an oxide transistor having a top-contact bottom-gate structure has been described as an example.
도 1에 도시된 바와 같이, 본 발명의 실시예에 따른 산화물 트랜지스터(10)는 기판(110), 게이트절연막(120), IZO 박막(130), 소스 및 드레인 전극(141, 142)을 포함한다.As illustrated in FIG. 1, an oxide transistor 10 according to an exemplary embodiment of the present invention includes a substrate 110, a gate insulating layer 120, an IZO thin film 130, and source and drain electrodes 141 and 142. .
기판(110)은 600um의 heavy Doped n-타입 실리콘(n-type Si) 웨이퍼를 이용하여 제조되며, 게이트 전극으로 사용된다.The substrate 110 is manufactured using a 600um heavy doped n-type Si wafer, and is used as a gate electrode.
게이트절연막(120)은 기판(110) 상에 형성되며, 노(furnace)에서 열산화(thermal oxidation) 공정을 통해 100nm 두께로 이산화규소(SiO2)를 성장시킴에 따라 형성된다.The gate insulating layer 120 is formed on the substrate 110 and is formed by growing silicon dioxide (SiO 2 ) to a thickness of 100 nm through a thermal oxidation process in a furnace.
이때, 게이트절연막(120)이 생성된 기판(110)은 예컨대, 피라냐 클리닝(piranha cleaning)에 의해 표준 세정된 후 IZO 박막(130)의 형성에 사용될 수 있다.In this case, the substrate 110 on which the gate insulating film 120 is formed may be used to form the IZO thin film 130 after standard cleaning by, for example, piranha cleaning.
IZO 박막(130)은 인듐-아연 용액을 기판(110)에 스핀공정하면서 자외선을 조사하여 형성된 산화물 활성층을 어닐링(anealing)하여 남은 용매를 증발시킴에 따라 형성된다.The IZO thin film 130 is formed by annealing the oxide active layer formed by irradiating ultraviolet rays while spin-processing an indium-zinc solution onto the substrate 110 to evaporate the remaining solvent.
여기서, 인듐-아연 용액은 다음과 같은 과정을 통해 제작될 수 있다. 구체적으로, 0.1M의 인듐과 아연(indium, zinc) 용액을 제작하기 위한 용매로써 2-메톡시에탄올(methoxyethanol)이 사용된다. 인듐 용액에는 시약을 용해시키기 위한 안정제로 아세틸아세톤(acetylacetone)을 첨가하고 빠른 반응을 위한 촉매로 NH3를 첨가하며, 아연 용액에는 안정제인 acetylacetone만 첨가하여 각각을 1시간 동안 60℃에서 스티어링(stirring)을 진행하였다. 이때, 시약은 질산인듐 수화물(indium nitrate hydrate)[In(NO3)32O], 아연 아세테이트 이수화물(zinc acetate dihydrate)[Zn(CH3COO)22O]이 사용된다. 이후, In 용액과 Zn 용액을 7:3의 비율로 혼합하여 상온에서 2시간 동안 스티어링(stirring)을 진행하였다.Here, the indium zinc solution may be prepared through the following process. Specifically, 2-methoxyethanol is used as a solvent for preparing a 0.1 M indium and zinc solution. To the indium solution, acetylacetone is added as a stabilizer for dissolving reagents, NH 3 is added as a catalyst for rapid reaction, and zinc solution is added with only acetylacetone, which is stabilized at 60 ° C. for 1 hour. ). In this case, indium nitrate hydrate [In (NO 3 ) 32 O], zinc acetate dihydrate [Zn (CH 3 COO) 22 O] is used as the reagent. Thereafter, the In solution and the Zn solution were mixed at a ratio of 7: 3, and steering was performed at room temperature for 2 hours.
전술한 인듐-아연 용액은 밴드갭(Gap)이 기설정된 기준치 이상인 다른 반도체 물질의 혼합 용액으로 대체될 수 있다. 여기서, 기설정된 기준치는 IZO 반도체 박막의 밴드갭인 3.5일 수 있다. 또한, 대체 가능한 다른 반도체 물질의 혼합 용액은 산화물 계열의 반도체 IYO(Indium gallium zinc oxide), IGZO(Zinc tin oxide), ZTO(Indium yttrium oxide) 등일 수 있다.The indium-zinc solution described above may be replaced with a mixed solution of other semiconductor materials having a band gap of more than a predetermined reference value. Here, the predetermined reference value may be 3.5, which is a band gap of the IZO semiconductor thin film. In addition, the mixed solution of another semiconductor material may be an oxide-based semiconductor indium gallium zinc oxide (IYO), zinc tin oxide (IGZO), indium yttrium oxide (ZTO), or the like.
도 2의 S220단계를 참조하면, 산화물 활성층은 기설정된 속도로 기판(110)을 회전시키며, 인듐-아연 용액을 20~30nm의 두께로 코팅하면서, 게이트절연막(120)의 상부에 기설정된 자외선을 기설정된 시간동안 조사함에 따라 형성될 수 있다. Referring to step S220 of FIG. 2, the oxide active layer rotates the substrate 110 at a predetermined speed, and coats an indium-zinc solution with a thickness of 20 to 30 nm, while applying predetermined ultraviolet rays to the upper portion of the gate insulating film 120. It may be formed by irradiation for a predetermined time.
여기서, 스핀코팅시 기판(110)의 회전속도는 1500rpm이며, 기설정된 자외선은 300nm~450nm 파장을 가질 수 있다. 또한, 자외선의 강도가 1200mW/cm2인 경우 자외선의 조사시간 60초 이상이면서 90초 이하인 시간일 수 있다. 이는 하나의 실시예에 지나지 않으며, 기설정된 자외선의 강도와 조사시간은 온/오프비와 모빌리티 특성을 고려하여 결정될 수 있음은 물론이다. 예를 들어, 스핀코팅시의 자외선 조사시간은 자외선의 강도가 증가할수록 짧아지되, 시험 결과 본 발명의 실시예에 따른 산화물 트랜지스터(10)의 온/오프비와 모빌리티가 각기 일정값 이상으로 유지할 수 있도록 설정될 수 있다. 여기서, 온/오프비와 모빌리티의 일정값은 각기 104 및 3cm2/Vs일 수 있다.Here, the spin speed of the substrate 110 during the spin coating is 1500rpm, the predetermined ultraviolet light may have a wavelength of 300nm ~ 450nm. In addition, when the intensity of the ultraviolet ray is 1200mW / cm 2 It may be a time of 60 seconds or more while the irradiation time of the ultraviolet ray is 90 seconds or less. This is only an example, and the predetermined intensity and irradiation time of ultraviolet rays may be determined in consideration of the on / off ratio and mobility characteristics. For example, UV irradiation time during spin coating becomes shorter as the intensity of ultraviolet light increases, but as a result of the test, the on / off ratio and mobility of the oxide transistor 10 according to the embodiment of the present invention can be maintained above a predetermined value. It can be set to. Here, the constant values of the on / off ratio and mobility may be 10 4 and 3 cm 2 / Vs, respectively.
이 같이, 본 발명에서는 스핀코팅과 자외선 조사를 동시에 진행함에 따라 전체 공정 시간을 단축할 수 있을 뿐만 아니라, 용액 공정의 온도를 낮춰 유연한(Flexible) 소자를 제작할 수 있다.As described above, according to the present invention, as the spin coating and the ultraviolet irradiation are simultaneously performed, the overall process time can be shortened, and the temperature of the solution process can be lowered to fabricate a flexible device.
이후, 도 2b를 참조하면, IZO 박막(130)은 산화물 활성층이 코팅된 기판(110)을 노(furnace)에서 350℃의 온도에서 4시간 동안 어닐링함에 따라 형성될 수 있다. 이 같이, 본 발명에서는 노를 이용한 어닐링을 수행함에 따라 소자별 성능 비균등화를 방지할 수 있고, UV 조사 및 스핀 공정 후에 노를 이용한 어닐링을 수행함에 따라 어닐링에 따른 소자의 특성 저하 현상을 방지할 수 있다. Thereafter, referring to FIG. 2B, the IZO thin film 130 may be formed by annealing the substrate 110 coated with the oxide active layer at a temperature of 350 ° C. in a furnace for 4 hours. As described above, according to the present invention, annealing using the furnace may prevent performance unevenness for each device, and an annealing using the furnace after UV irradiation and spin may prevent the device from deteriorating characteristics due to the annealing. Can be.
도 2c를 참조하면, 소스 및 드레인 전극(141, 142)은 IZO 박막(130)의 상부 각기 소스 전극과 드레인 전극이 형성될 위치에 메탈 증발기(metal evaporator)를 이용하여 100nm 두께로 알루미늄 소스를 증착함에 따라 형성된다.Referring to FIG. 2C, the source and drain electrodes 141 and 142 may deposit an aluminum source having a thickness of 100 nm by using a metal evaporator at positions where the source and drain electrodes of the IZO thin film 130 will be formed. It is formed as.
이와 같이, 본 발명의 실시예는 용액 공정을 이용한 공정 단계를 축소할 수 있으면서 UV 조사와 용액 공정의 동시 진행에 의해 공정 시간을 단축할 수 있고, 용액 공정의 온도를 낮춰 유연한(Flexible) 소자를 제작할 수 있다.As described above, the embodiment of the present invention can shorten the process step by using the solution process, and can shorten the process time by simultaneously proceeding the UV irradiation and the solution process, and lower the temperature of the solution process to provide a flexible device. I can make it.
뿐만 아니라, 본 발명의 실시예는 소자별 성능을 어느 정도 균등하게 유지할 수 있고, 어닐링에 따른 소자의 특성 저하 현상을 방지할 수 있다. In addition, the embodiment of the present invention can maintain the device-specific performance to some extent, and can prevent the deterioration of the characteristics of the device due to the annealing.
또한, 본 발명의 실시예는 밴드갭(Band GAP)이 큰 인듐-아연 산화물 반도체 트랜지스터를 제작함에 따라 투명 전자소자로 응용될 수 있다.In addition, the embodiment of the present invention can be applied to a transparent electronic device by fabricating an indium-zinc oxide semiconductor transistor having a large band gap.
더 나아가, 본 발명의 실시예는 산화물 트랜지스터, 디스플레이 백플레인 소자, 유연한 전자소자, 투명 전자소자 등의 다양한 분야의 특성을 향상시킬 수 있다.Furthermore, embodiments of the present invention may improve characteristics of various fields such as oxide transistors, display backplane devices, flexible electronic devices, and transparent electronic devices.
이하, 도 3a 및 3b를 참조하여 본 발명의 실시예에 따른 산화물 트랜지스터의 성능에 대하여 설명한다. 도 3a 및 도 3b는 각기 본 발명의 실시예에 따른 스핀코팅시에 자외선 조사시간을 달리하여 제조된 산화물 트랜지스터의 출력 커브(드레인 전류)와 전달 커브를 도시한 그래프이다. 해당 실험에서 산화물 트랜지스터의 소스 전극은 접지되고, 드레인 전극과 게이트 전극에는 전압이 인가되었다.Hereinafter, the performance of the oxide transistor according to the embodiment of the present invention will be described with reference to FIGS. 3A and 3B. 3A and 3B are graphs illustrating output curves (drain currents) and transfer curves of oxide transistors manufactured by varying ultraviolet irradiation time during spin coating, respectively, according to an embodiment of the present invention. In this experiment, the source electrode of the oxide transistor was grounded, and a voltage was applied to the drain electrode and the gate electrode.
도 3a 및 도 3b의 (a)는 스핀코팅시에 자외선을 조사하지 않은 경우, (b)는 스핀코팅시에 자외선을 30초 조사한 경우, (c)는 스핀코팅시에 자외선을 60초 조사한 경우, (d)는 스핀코팅시에 자외선을 90초 조사한 경우의 그래프이다.3a and 3b (a) is not irradiated with ultraviolet light during spin coating, (b) is irradiated with ultraviolet light for 30 seconds during spin coating, (c) is 60 seconds irradiated with ultraviolet light during spin coating and (d) are graphs when 90 seconds of ultraviolet radiation was applied during spin coating.
게이트 전극(110)과 드레인 전극(142)에 0, 10V, 20V, 30V의 전압을 각기 인가하며 드레인 전류를 측정한 결과, 도 3a 및 도 3b와 같이, 스핀코팅시에 60초 이상 기설정된 자외선을 조사한 경우에 산화물 트랜지스터가 제대로 동작함을 알 수 있다.As a result of measuring the drain current while applying voltages of 0, 10V, 20V, and 30V to the gate electrode 110 and the drain electrode 142, respectively, as shown in FIGS. 3A and 3B, ultraviolet rays preset for 60 seconds or more during spin coating In this case, it can be seen that the oxide transistor works properly.
또한, 본 발명의 실시예에 따른 스핀코팅시에 자외선을 90초 이상 조사하여 제작된 산화물 트랜지스터의 경우, 온/오프비가 107으로 가장 높고 모빌리티도 3cm2/Vs 이상이 되는 것을 확인할 수 있다. In addition, in the case of the oxide transistor manufactured by irradiating UV light for 90 seconds or more during spin coating according to an embodiment of the present invention, it can be seen that the on / off ratio is 10 7 , and the mobility is 3 cm 2 / Vs or more.
반면, 본 발명의 실시예에 따른 스핀코팅시에 자외선을 60초 조사하여 제작된 산화물 트랜지스터의 경우, 모빌리티는 5cm2/Vs 이상으로 뛰어나지만, 온/오프비가 104으로 낮은 것을 알 수 있다. On the other hand, in the case of the oxide transistor produced by irradiating ultraviolet light for 60 seconds during spin coating according to an embodiment of the present invention, the mobility is excellent in more than 5cm 2 / Vs, it can be seen that the on / off ratio is low as 10 4 .
이와 같이, 본 발명에서는 스핀코팅 공정중에 UV 조사시간을 조정함에 따라 온/오프비와 모빌리티를 어느 정도 이상으로 보장할 수 있는 산화물 트랜지스터를 제조하도록 지원할 수 있다.As described above, according to the present invention, it is possible to assist in manufacturing an oxide transistor capable of guaranteeing an on / off ratio and mobility to some extent as the UV irradiation time is adjusted during the spin coating process.
이상, 본 발명의 구성에 대하여 첨부 도면을 참조하여 상세히 설명하였으나, 이는 예시에 불과한 것으로서, 본 발명이 속하는 기술분야에 통상의 지식을 가진자라면 본 발명의 기술적 사상의 범위 내에서 다양한 변형과 변경이 가능함은 물론이다. 따라서 본 발명의 보호 범위는 전술한 실시예에 국한되어서는 아니되며 이하의 특허청구범위의 기재에 의하여 정해져야 할 것이다.In the above, the configuration of the present invention has been described in detail with reference to the accompanying drawings, which are merely examples, and those skilled in the art to which the present invention pertains various modifications and changes within the scope of the technical idea of the present invention. Of course this is possible. Therefore, the protection scope of the present invention should not be limited to the above-described embodiment but should be defined by the following claims.
Claims (12)
- 게이트 전극으로 사용되는 기판;A substrate used as a gate electrode;상기 기판 상에 형성된 게이트절연막;A gate insulating film formed on the substrate;상기 실리콘 절연막의 상부에 밴드갭(Gap)이 기설정된 기준치 이상인 반도체 물질의 혼합 용액을 스핀코팅(Spin Coating)하는 공정중에 기설정된 자외선을 기설정된 시간동안 조사하여 산화물 활성층을 형성한 후 어닐링(annealing)함에 따라 형성된 산화물 박막; 및In the process of spin coating a mixed solution of a semiconductor material having a band gap greater than or equal to a predetermined reference value on the silicon insulating film for a predetermined time to form an oxide active layer and then annealing Oxide thin film formed according to; And상기 산화물 박막의 상부에 알루미늄을 증착하여 형성된 소스 및 드레인 전극Source and drain electrodes formed by depositing aluminum on top of the oxide thin film을 포함하는 산화물 트랜지스터.Oxide transistor comprising a.
- 제1항에서, 상기 스핀코팅시에 상기 기판은,The method of claim 1, wherein the substrate during the spin coating,1500rpm의 속도로 회전되는 것인 산화물 트랜지스터.An oxide transistor that is rotated at a speed of 1500 rpm.
- 제1항에서, 상기 자외선은,The method of claim 1, wherein the ultraviolet light,300 내지 450nm 파장의 자외선인 산화물 트랜지스터.An oxide transistor that is an ultraviolet ray of 300 to 450nm wavelength.
- 제1항에서, 상기 자외선이 1200mW/cm2 강도의 일 자외선인 경우,The method of claim 1, wherein when the ultraviolet light is one ultraviolet light of 1200mW / cm 2 intensity,상기 스핀코팅의 공정중에 60초 이상, 90초 이하의 시간동안 상기 일 자외선이 조사되는 것인 산화물 트랜지스터.And the ultraviolet light is irradiated for 60 seconds or more and 90 seconds or less during the spin coating process.
- 제1항에서, 상기 산화물 박막은,The method of claim 1, wherein the oxide thin film,상기 산화물 활성층이 형성된 상기 기판을 노(Furnace)에서 350도의 온도에서 4시간 동안 어닐링하여 형성되는 것인 산화물 트랜지스터.And the substrate on which the oxide active layer is formed is annealed at a temperature of 350 degrees in a furnace for 4 hours.
- 제1항에서, 상기 혼합 용액은,The method of claim 1, wherein the mixed solution,인듐-아연용액, IYO(Indium gallium zinc oxide), IGZO(Zinc tin oxide), ZTO(Indium yttrium oxide)를 포함하는 밴드갭인 3.5인 산화물 계열의 반도체 물질의 혼합용액인 산화물 트랜지스터.An oxide transistor that is a mixed solution of an oxide-based semiconductor material having a bandgap of 3.5, including an indium zinc solution, indium gallium zinc oxide (IYO), zinc tin oxide (IGZO), and indium yttrium oxide (ZTO).
- 제1항에서,In claim 1,상기 산화물 박막은 인듐-아연 산화물(IZO) 박막인 산화물 트랜지스터.And the oxide thin film is an indium zinc oxide (IZO) thin film.
- 실리콘 게이트절연막이 형성된 기판에 밴드갭(Gap)이 기설정된 기준치 이상인 반도체 물질의 혼합 용액을 회전코팅(Spin Coating)하는 공정 중에 자외선을 조사하여 산화물 활성층을 형성하는 단계;Forming an oxide active layer by irradiating ultraviolet rays in a process of spin coating a mixed solution of a semiconductor material having a band gap greater than or equal to a predetermined reference value on a substrate on which a silicon gate insulating film is formed;상기 산화물 활성층이 형성된 상기 기판을 어닐링(annealing)함에 따라 산화물 박막을 형성하는 단계; 및Forming an oxide thin film by annealing the substrate on which the oxide active layer is formed; And상기 산화물 박막의 상부에 알루미늄을 증착하여 소스 및 드레인 전극을 형성하는 단계Depositing aluminum on the oxide thin film to form source and drain electrodes를 포함하는 산화물 트랜지스터 제조 방법.Oxide transistor manufacturing method comprising a.
- 제8항에서, 상기 산화물 활성층을 형성하는 단계는,The method of claim 8, wherein the forming of the oxide active layer,1500rpm의 속도로 회전하는 기판 상에 상기 혼합 용액을 코팅하는 단계; 및Coating the mixed solution on a substrate rotating at a speed of 1500 rpm; And상기 혼합 용액의 코팅 면의 상부에서 1200mW/cm2 강도의 자외선을 60초 이상, 90초 이하의 시간동안 조사하는 단계Irradiating 1200 mW / cm 2 intensity ultraviolet rays at the top of the coating surface of the mixed solution for a time of 60 seconds or more and 90 seconds or less를 포함하는 것인 산화물 트랜지스터 제조 방법.Oxide transistor manufacturing method comprising a.
- 제8항에서, In claim 8,상기 혼합 용액은 인듐 용액과 아연 용액을 7:3 비율로 혼합한 용액이며,The mixed solution is a solution in which the indium solution and the zinc solution are mixed in a 7: 3 ratio,상기 산화물 박막은 인듐-아연 산화물 박막인 산화물 트랜지스터 제조 방법.And the oxide thin film is an indium zinc oxide thin film.
- 제8항에서, 상기 산화물 박막을 형성하는 단계는,The method of claim 8, wherein the forming of the oxide thin film,상기 산화물 활성층이 형성된 상기 기판을 노(Furnace)에서 350도의 온도에서 4시간 동안 어닐링하는 단계를 포함하는 것인 산화물 트랜지스터 제조 방법.And annealing the substrate on which the oxide active layer is formed at a temperature of 350 degrees in a furnace for 4 hours.
- 제8항에서, 상기 자외선의 조사시간은 그 강도에 따라 결정되되,The method of claim 8, wherein the irradiation time of the ultraviolet light is determined according to the intensity,온/오프비가 104이상 및 모빌리티가 3cm2/Vs이상인 산화물 트랜지스터를 제조 가능하도록 설정되는 것인 산화물 트랜지스터 제조 방법.An oxide transistor manufacturing method in which the on / off ratio is set to be capable of manufacturing an oxide transistor having 10 4 or more and mobility of 3 cm 2 / Vs or more.
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| KR102431923B1 (en) * | 2020-11-30 | 2022-08-11 | 김성진 | Method for manufacturing thin film transistor |
| KR102564866B1 (en) * | 2021-07-27 | 2023-08-07 | 충북대학교 산학협력단 | Double-oxide based IGZO memtransistor and manufacturing method thereof |
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